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From: Andrii Anisov <andrii_anisov@epam.com>
To: Meng Xu <xumengpanda@gmail.com>, Dario Faggioli <dfaggioli@suse.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: RTDS with extra time issue
Date: Mon, 12 Feb 2018 12:38:34 +0200	[thread overview]
Message-ID: <bf737675-54b3-6d84-7e18-2a01be604952@epam.com> (raw)
In-Reply-To: <CAENZ-+k63FbKdfvaxxEb9UD0F=BQ-g=f1d=uR_VEEOBHr262Dg@mail.gmail.com>

Hello Meng,


On 10.02.18 06:53, Meng Xu wrote:
> If the RT VCPU has only one RT task on it, we can synchronize the
> release time of the VCPU and that of the RT task. In other words, the
> release offset of both the VCPU and the RT task are the same in terms
> of the wall clock. Then we can assign the task's parameter to the VCPU
> and guarantee the task has no deadline miss if the VCPU has no
> deadline miss.
IMO, such configuration could be useful for VCPU scheduling overhead 
estimations. Though it seems to be not realistic, because we need some 
instruments in that domain to measure if the task meets its deadline.

> Andrii and Dario,
> Do you think the assumption that one VCPU runs only one RT task is
> reasonable in practice?
> If it is, is there some use cases for this assumption?
No, I doubt real life use-cases would fit this scheme.

-- 

*Andrii Anisov*



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  parent reply	other threads:[~2018-02-12 10:38 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-09 12:20 RTDS with extra time issue Andrii Anisov
2018-02-09 12:25 ` Andrii Anisov
2018-02-09 13:18 ` Dario Faggioli
2018-02-09 15:03   ` Andrii Anisov
2018-02-09 15:18     ` Dario Faggioli
2018-02-09 15:36       ` Meng Xu
2018-02-09 15:56         ` Andrii Anisov
2018-02-09 17:51           ` Meng Xu
2018-02-10  0:14             ` Dario Faggioli
2018-02-10  4:53               ` Meng Xu
2018-02-12 10:17                 ` Dario Faggioli
2018-02-12 11:08                   ` Andrii Anisov
2018-02-12 14:52                     ` Meng Xu
2018-02-12 10:38                 ` Andrii Anisov [this message]
2018-02-12 10:20       ` Andrii Anisov
2018-02-12 18:44         ` Andrii Anisov
2018-02-16 18:37           ` Dario Faggioli
2018-02-20 11:34             ` Andrii Anisov
2018-02-22 17:53               ` Dario Faggioli
2018-02-26 12:00                 ` Andrii Anisov
2018-02-09 15:34 ` Meng Xu
2018-02-09 15:53   ` Andrii Anisov
2018-02-09 16:04   ` Andrii Anisov
2018-02-09 17:53     ` Meng Xu
2018-02-09 18:07       ` Andrii Anisov

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