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From: Meng Xu <xumengpanda@gmail.com>
To: Andrii Anisov <andrii_anisov@epam.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>,
	Dario Faggioli <dfaggioli@suse.com>
Subject: Re: RTDS with extra time issue
Date: Fri, 9 Feb 2018 10:34:26 -0500	[thread overview]
Message-ID: <CAENZ-+=O5Xb=sZ2mwvihryWWx6fOVU=0pcSe0j8JAMaK3sXjRQ@mail.gmail.com> (raw)
In-Reply-To: <762ccb02-b758-1636-fddc-f4e6a3ca19d0@epam.com>


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On Fri, Feb 9, 2018 at 7:20 AM, Andrii Anisov <andrii_anisov@epam.com>
wrote:

> Dear Dario,
>
> Now I'm experimenting with RTDS, in particular with "extra time"
> functionality.
>
> My experimental setup is built on Salvator-X board with H3 SOC (running
> only big cores cluster, 4xA57).
> Domains up and running, and their VCPU are as following:
>
> root@generic-armv8-xt-dom0:/xt/dom.cfg# xl sched-rtds -v all
> Cpupool Pool-0: sched=RTDS
> Name                                ID VCPU    Period    Budget Extratime
> (XEN) FLASK: Allowing unknown domctl_scheduler_op: 3.
> Domain-0                             0    0     10000 1000        yes
> Domain-0                             0    1     10000 1000        yes
> Domain-0                             0    2     10000 1000        yes
> Domain-0                             0    3     10000 1000        yes
> (XEN) FLASK: Allowing unknown domctl_scheduler_op: 3.
> DomR                                 3    0     10000 5000         no
>

To make sure no deadline miss of a task on a VCPU, we must guarantee:
1) The VCPU gets its configured time, which is shown in your following
emails that it does;
2) When the VCPU ​gets its configured time, the task on the VCPU can be
scheduled. <-- This can be achieved by configuring the VCPU's parameters
correctly.

The deadline miss problem in the test case you presented here is likely
caused by the case (2).
Even if the DomR gets 5ms in every 10ms, the task (period  = 10ms, budget =
4ms) on the VCPU will still  ​miss deadline.
In theory, the domR  with period 10ms should be configured to have budget =
7ms. But here the budget's configured to be 5ms, which is less than the
required.

The foundamental reason is that the release time of RT task and the task's
VCPU is not synchronized.
Here I show why we cannot assign the same/similar parameter of a task to
its VCPU. If you change the VCPU's budget to 5ms, the starvation interval
is 2 * ( period - budget) = 10ms, still making the VCPU's task miss
deadline.

[Forgive me to attach a slide to explain this.]
[image: Inline image 1]

If you want to keep the same VCPU parameter, can you try to set task's
period = 100ms and exe time = 40ms?
By theory (I used CARTS to compute), a VCPU (10ms, 5ms) can schedule a task
(100ms, 40ms).
Note that the resource demand of two RT tasks with the same utilization is
different: the task with smaller period has larger demand.

​Best,

Meng​


-----------
Meng Xu
Ph.D. Candidate in Computer and Information Science
University of Pennsylvania
http://www.cis.upenn.edu/~mengxu/

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  parent reply	other threads:[~2018-02-09 15:35 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-09 12:20 RTDS with extra time issue Andrii Anisov
2018-02-09 12:25 ` Andrii Anisov
2018-02-09 13:18 ` Dario Faggioli
2018-02-09 15:03   ` Andrii Anisov
2018-02-09 15:18     ` Dario Faggioli
2018-02-09 15:36       ` Meng Xu
2018-02-09 15:56         ` Andrii Anisov
2018-02-09 17:51           ` Meng Xu
2018-02-10  0:14             ` Dario Faggioli
2018-02-10  4:53               ` Meng Xu
2018-02-12 10:17                 ` Dario Faggioli
2018-02-12 11:08                   ` Andrii Anisov
2018-02-12 14:52                     ` Meng Xu
2018-02-12 10:38                 ` Andrii Anisov
2018-02-12 10:20       ` Andrii Anisov
2018-02-12 18:44         ` Andrii Anisov
2018-02-16 18:37           ` Dario Faggioli
2018-02-20 11:34             ` Andrii Anisov
2018-02-22 17:53               ` Dario Faggioli
2018-02-26 12:00                 ` Andrii Anisov
2018-02-09 15:34 ` Meng Xu [this message]
2018-02-09 15:53   ` Andrii Anisov
2018-02-09 16:04   ` Andrii Anisov
2018-02-09 17:53     ` Meng Xu
2018-02-09 18:07       ` Andrii Anisov

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