* [Bug 110208] New GPU sysfs Power State Interface for custom pp_od_clk_voltage
@ 2019-03-20 11:48 bugzilla-daemon
2019-03-20 11:50 ` bugzilla-daemon
2019-11-19 9:17 ` bugzilla-daemon
0 siblings, 2 replies; 3+ messages in thread
From: bugzilla-daemon @ 2019-03-20 11:48 UTC (permalink / raw)
To: dri-devel
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https://bugs.freedesktop.org/show_bug.cgi?id=110208
Bug ID: 110208
Summary: New GPU sysfs Power State Interface for custom
pp_od_clk_voltage
Product: DRI
Version: unspecified
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority: medium
Component: DRM/AMDgpu
Assignee: dri-devel@lists.freedesktop.org
Reporter: richard.llom@gmail.com
In order to use a custom pp_od_clk_voltage one has to set
power_dpm_force_performance_level to manual.
However this way it is not possible to use custom pp_od_clk_voltage and force -
for instance - high or peak performance levels.
The forcing of different performance levels doesn't (and shouldn't) relate to
custom clocks/voltages. Putting this setting in the same interface is a poor
choice and (unnecessarily) restricts the possibilities.
Please add a new sysfs interface for *solely* choosing between default and
custom pp_od_clk_voltage.
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* [Bug 110208] New GPU sysfs Power State Interface for custom pp_od_clk_voltage
2019-03-20 11:48 [Bug 110208] New GPU sysfs Power State Interface for custom pp_od_clk_voltage bugzilla-daemon
@ 2019-03-20 11:50 ` bugzilla-daemon
2019-11-19 9:17 ` bugzilla-daemon
1 sibling, 0 replies; 3+ messages in thread
From: bugzilla-daemon @ 2019-03-20 11:50 UTC (permalink / raw)
To: dri-devel
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https://bugs.freedesktop.org/show_bug.cgi?id=110208
--- Comment #1 from famo <richard.llom@gmail.com> ---
Link to documentation:
https://dri.freedesktop.org/docs/drm/gpu/amdgpu.html#power-dpm-force-performance-level
Quote:
pp_od_clk_voltage
The amdgpu driver provides a sysfs API for adjusting the clocks and voltages in
each power level within a power state. The pp_od_clk_voltage is used for this.
< For Vega10 and previous ASICs >
Reading the file will display:
a list of engine clock levels and voltages labeled OD_SCLK
a list of memory clock levels and voltages labeled OD_MCLK
a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
To manually adjust these settings, first select manual using
power_dpm_force_performance_level. ...
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* [Bug 110208] New GPU sysfs Power State Interface for custom pp_od_clk_voltage
2019-03-20 11:48 [Bug 110208] New GPU sysfs Power State Interface for custom pp_od_clk_voltage bugzilla-daemon
2019-03-20 11:50 ` bugzilla-daemon
@ 2019-11-19 9:17 ` bugzilla-daemon
1 sibling, 0 replies; 3+ messages in thread
From: bugzilla-daemon @ 2019-11-19 9:17 UTC (permalink / raw)
To: dri-devel
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https://bugs.freedesktop.org/show_bug.cgi?id=110208
Martin Peres <martin.peres@free.fr> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
Resolution|--- |MOVED
--- Comment #2 from Martin Peres <martin.peres@free.fr> ---
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This bug has been migrated to freedesktop.org's GitLab instance and has been
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You can subscribe and participate further through the new bug through this link
to our GitLab instance: https://gitlab.freedesktop.org/drm/amd/issues/731.
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