From: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Cc: Mesih Kilinc
<mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>,
Daniel Lezcano
<daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Julian Calaby
<julian.calaby-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: [RFC PATCH v4 12/17] dt-bindings: clock: Add Allwinner suniv F1C100s CCU
Date: Sun, 25 Nov 2018 10:43:15 +0300 [thread overview]
Message-ID: <c2e6e3f510d5663ecf25262126dcff1df112af15.1543131714.git.mesihkilinc@gmail.com> (raw)
In-Reply-To: <cover.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Add compatiple string for Allwinner suniv F1C100s CCU.
Add clock and reset definitions.
Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
---
.../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
include/dt-bindings/clock/suniv-ccu-f1c100s.h | 69 ++++++++++++++++++++++
include/dt-bindings/reset/suniv-ccu-f1c100s.h | 37 ++++++++++++
3 files changed, 107 insertions(+)
create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 47d2e90..e3bd88a 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -22,6 +22,7 @@ Required properties :
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
- "allwinner,sun50i-h6-r-ccu"
+ - "allwinner,suniv-f1c100s-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
new file mode 100644
index 0000000..56f6d0d
--- /dev/null
+++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
+
+#define CLK_CPU 11
+
+#define CLK_BUS_MMC0 14
+#define CLK_BUS_MMC1 15
+#define CLK_BUS_DRAM 16
+#define CLK_BUS_SPI0 17
+#define CLK_BUS_SPI1 18
+#define CLK_BUS_OTG 19
+#define CLK_BUS_VE 20
+#define CLK_BUS_LCD 21
+#define CLK_BUS_DEINTERLACE 22
+#define CLK_BUS_CSI 23
+#define CLK_BUS_TVD 24
+#define CLK_BUS_TVE 25
+#define CLK_BUS_DE_BE 26
+#define CLK_BUS_DE_FE 27
+#define CLK_BUS_CODEC 28
+#define CLK_BUS_SPDIF 29
+#define CLK_BUS_IR 30
+#define CLK_BUS_RSB 31
+#define CLK_BUS_I2S0 32
+#define CLK_BUS_I2C0 33
+#define CLK_BUS_I2C1 34
+#define CLK_BUS_I2C2 35
+#define CLK_BUS_PIO 36
+#define CLK_BUS_UART0 37
+#define CLK_BUS_UART1 38
+#define CLK_BUS_UART2 39
+
+#define CLK_MMC0 40
+#define CLK_MMC0_SAMPLE 41
+#define CLK_MMC0_OUTPUT 42
+#define CLK_MMC1 43
+#define CLK_MMC1_SAMPLE 44
+#define CLK_MMC1_OUTPUT 45
+#define CLK_I2S 46
+#define CLK_SPDIF 47
+
+#define CLK_USB_PHY0 48
+
+#define CLK_DRAM_VE 49
+#define CLK_DRAM_CSI 50
+#define CLK_DRAM_DEINTERLACE 51
+#define CLK_DRAM_TVD 52
+#define CLK_DRAM_DE_FE 53
+#define CLK_DRAM_DE_BE 54
+
+#define CLK_DE_BE 55
+#define CLK_DE_FE 56
+#define CLK_TCON 57
+#define CLK_DEINTERLACE 58
+#define CLK_TVE2_CLK 59
+#define CLK_TVE1_CLK 60
+#define CLK_TVD 61
+#define CLK_CSI 62
+#define CLK_VE 63
+#define CLK_CODEC 64
+#define CLK_AVS 65
+
+#endif
diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h
new file mode 100644
index 0000000..95f1ed0
--- /dev/null
+++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2018 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+
+#define RST_USB_PHY0 0
+#define RST_BUS_MMC0 1
+#define RST_BUS_MMC1 2
+#define RST_BUS_DRAM 3
+#define RST_BUS_SPI0 4
+#define RST_BUS_SPI1 5
+#define RST_BUS_OTG 6
+#define RST_BUS_VE 7
+#define RST_BUS_LCD 8
+#define RST_BUS_DEINTERLACE 9
+#define RST_BUS_CSI 10
+#define RST_BUS_TVD 11
+#define RST_BUS_TVE 12
+#define RST_BUS_DE_BE 13
+#define RST_BUS_DE_FE 14
+#define RST_BUS_CODEC 15
+#define RST_BUS_SPDIF 16
+#define RST_BUS_IR 17
+#define RST_BUS_RSB 18
+#define RST_BUS_I2S0 19
+#define RST_BUS_I2C0 20
+#define RST_BUS_I2C1 21
+#define RST_BUS_I2C2 22
+#define RST_BUS_UART0 23
+#define RST_BUS_UART1 24
+#define RST_BUS_UART2 25
+
+#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Mesih Kilinc <mesihkilinc@gmail.com>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Chen-Yu Tsai <wens@csie.org>,
Russell King <linux@armlinux.org.uk>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Marc Zyngier <marc.zyngier@arm.com>,
Linus Walleij <linus.walleij@linaro.org>,
Icenowy Zheng <icenowy@aosc.io>, Rob Herring <robh+dt@kernel.org>,
Julian Calaby <julian.calaby@gmail.com>
Subject: [RFC PATCH v4 12/17] dt-bindings: clock: Add Allwinner suniv F1C100s CCU
Date: Sun, 25 Nov 2018 10:43:15 +0300 [thread overview]
Message-ID: <c2e6e3f510d5663ecf25262126dcff1df112af15.1543131714.git.mesihkilinc@gmail.com> (raw)
In-Reply-To: <cover.1543131714.git.mesihkilinc@gmail.com>
Add compatiple string for Allwinner suniv F1C100s CCU.
Add clock and reset definitions.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
.../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
include/dt-bindings/clock/suniv-ccu-f1c100s.h | 69 ++++++++++++++++++++++
include/dt-bindings/reset/suniv-ccu-f1c100s.h | 37 ++++++++++++
3 files changed, 107 insertions(+)
create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 47d2e90..e3bd88a 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -22,6 +22,7 @@ Required properties :
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
- "allwinner,sun50i-h6-r-ccu"
+ - "allwinner,suniv-f1c100s-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
new file mode 100644
index 0000000..56f6d0d
--- /dev/null
+++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
+
+#define CLK_CPU 11
+
+#define CLK_BUS_MMC0 14
+#define CLK_BUS_MMC1 15
+#define CLK_BUS_DRAM 16
+#define CLK_BUS_SPI0 17
+#define CLK_BUS_SPI1 18
+#define CLK_BUS_OTG 19
+#define CLK_BUS_VE 20
+#define CLK_BUS_LCD 21
+#define CLK_BUS_DEINTERLACE 22
+#define CLK_BUS_CSI 23
+#define CLK_BUS_TVD 24
+#define CLK_BUS_TVE 25
+#define CLK_BUS_DE_BE 26
+#define CLK_BUS_DE_FE 27
+#define CLK_BUS_CODEC 28
+#define CLK_BUS_SPDIF 29
+#define CLK_BUS_IR 30
+#define CLK_BUS_RSB 31
+#define CLK_BUS_I2S0 32
+#define CLK_BUS_I2C0 33
+#define CLK_BUS_I2C1 34
+#define CLK_BUS_I2C2 35
+#define CLK_BUS_PIO 36
+#define CLK_BUS_UART0 37
+#define CLK_BUS_UART1 38
+#define CLK_BUS_UART2 39
+
+#define CLK_MMC0 40
+#define CLK_MMC0_SAMPLE 41
+#define CLK_MMC0_OUTPUT 42
+#define CLK_MMC1 43
+#define CLK_MMC1_SAMPLE 44
+#define CLK_MMC1_OUTPUT 45
+#define CLK_I2S 46
+#define CLK_SPDIF 47
+
+#define CLK_USB_PHY0 48
+
+#define CLK_DRAM_VE 49
+#define CLK_DRAM_CSI 50
+#define CLK_DRAM_DEINTERLACE 51
+#define CLK_DRAM_TVD 52
+#define CLK_DRAM_DE_FE 53
+#define CLK_DRAM_DE_BE 54
+
+#define CLK_DE_BE 55
+#define CLK_DE_FE 56
+#define CLK_TCON 57
+#define CLK_DEINTERLACE 58
+#define CLK_TVE2_CLK 59
+#define CLK_TVE1_CLK 60
+#define CLK_TVD 61
+#define CLK_CSI 62
+#define CLK_VE 63
+#define CLK_CODEC 64
+#define CLK_AVS 65
+
+#endif
diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h
new file mode 100644
index 0000000..95f1ed0
--- /dev/null
+++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+
+#define RST_USB_PHY0 0
+#define RST_BUS_MMC0 1
+#define RST_BUS_MMC1 2
+#define RST_BUS_DRAM 3
+#define RST_BUS_SPI0 4
+#define RST_BUS_SPI1 5
+#define RST_BUS_OTG 6
+#define RST_BUS_VE 7
+#define RST_BUS_LCD 8
+#define RST_BUS_DEINTERLACE 9
+#define RST_BUS_CSI 10
+#define RST_BUS_TVD 11
+#define RST_BUS_TVE 12
+#define RST_BUS_DE_BE 13
+#define RST_BUS_DE_FE 14
+#define RST_BUS_CODEC 15
+#define RST_BUS_SPDIF 16
+#define RST_BUS_IR 17
+#define RST_BUS_RSB 18
+#define RST_BUS_I2S0 19
+#define RST_BUS_I2C0 20
+#define RST_BUS_I2C1 21
+#define RST_BUS_I2C2 22
+#define RST_BUS_UART0 23
+#define RST_BUS_UART1 24
+#define RST_BUS_UART2 25
+
+#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: mesihkilinc@gmail.com (Mesih Kilinc)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH v4 12/17] dt-bindings: clock: Add Allwinner suniv F1C100s CCU
Date: Sun, 25 Nov 2018 10:43:15 +0300 [thread overview]
Message-ID: <c2e6e3f510d5663ecf25262126dcff1df112af15.1543131714.git.mesihkilinc@gmail.com> (raw)
In-Reply-To: <cover.1543131714.git.mesihkilinc@gmail.com>
Add compatiple string for Allwinner suniv F1C100s CCU.
Add clock and reset definitions.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
.../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
include/dt-bindings/clock/suniv-ccu-f1c100s.h | 69 ++++++++++++++++++++++
include/dt-bindings/reset/suniv-ccu-f1c100s.h | 37 ++++++++++++
3 files changed, 107 insertions(+)
create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 47d2e90..e3bd88a 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -22,6 +22,7 @@ Required properties :
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
- "allwinner,sun50i-h6-r-ccu"
+ - "allwinner,suniv-f1c100s-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
new file mode 100644
index 0000000..56f6d0d
--- /dev/null
+++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
+
+#define CLK_CPU 11
+
+#define CLK_BUS_MMC0 14
+#define CLK_BUS_MMC1 15
+#define CLK_BUS_DRAM 16
+#define CLK_BUS_SPI0 17
+#define CLK_BUS_SPI1 18
+#define CLK_BUS_OTG 19
+#define CLK_BUS_VE 20
+#define CLK_BUS_LCD 21
+#define CLK_BUS_DEINTERLACE 22
+#define CLK_BUS_CSI 23
+#define CLK_BUS_TVD 24
+#define CLK_BUS_TVE 25
+#define CLK_BUS_DE_BE 26
+#define CLK_BUS_DE_FE 27
+#define CLK_BUS_CODEC 28
+#define CLK_BUS_SPDIF 29
+#define CLK_BUS_IR 30
+#define CLK_BUS_RSB 31
+#define CLK_BUS_I2S0 32
+#define CLK_BUS_I2C0 33
+#define CLK_BUS_I2C1 34
+#define CLK_BUS_I2C2 35
+#define CLK_BUS_PIO 36
+#define CLK_BUS_UART0 37
+#define CLK_BUS_UART1 38
+#define CLK_BUS_UART2 39
+
+#define CLK_MMC0 40
+#define CLK_MMC0_SAMPLE 41
+#define CLK_MMC0_OUTPUT 42
+#define CLK_MMC1 43
+#define CLK_MMC1_SAMPLE 44
+#define CLK_MMC1_OUTPUT 45
+#define CLK_I2S 46
+#define CLK_SPDIF 47
+
+#define CLK_USB_PHY0 48
+
+#define CLK_DRAM_VE 49
+#define CLK_DRAM_CSI 50
+#define CLK_DRAM_DEINTERLACE 51
+#define CLK_DRAM_TVD 52
+#define CLK_DRAM_DE_FE 53
+#define CLK_DRAM_DE_BE 54
+
+#define CLK_DE_BE 55
+#define CLK_DE_FE 56
+#define CLK_TCON 57
+#define CLK_DEINTERLACE 58
+#define CLK_TVE2_CLK 59
+#define CLK_TVE1_CLK 60
+#define CLK_TVD 61
+#define CLK_CSI 62
+#define CLK_VE 63
+#define CLK_CODEC 64
+#define CLK_AVS 65
+
+#endif
diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h
new file mode 100644
index 0000000..95f1ed0
--- /dev/null
+++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+
+#define RST_USB_PHY0 0
+#define RST_BUS_MMC0 1
+#define RST_BUS_MMC1 2
+#define RST_BUS_DRAM 3
+#define RST_BUS_SPI0 4
+#define RST_BUS_SPI1 5
+#define RST_BUS_OTG 6
+#define RST_BUS_VE 7
+#define RST_BUS_LCD 8
+#define RST_BUS_DEINTERLACE 9
+#define RST_BUS_CSI 10
+#define RST_BUS_TVD 11
+#define RST_BUS_TVE 12
+#define RST_BUS_DE_BE 13
+#define RST_BUS_DE_FE 14
+#define RST_BUS_CODEC 15
+#define RST_BUS_SPDIF 16
+#define RST_BUS_IR 17
+#define RST_BUS_RSB 18
+#define RST_BUS_I2S0 19
+#define RST_BUS_I2C0 20
+#define RST_BUS_I2C1 21
+#define RST_BUS_I2C2 22
+#define RST_BUS_UART0 23
+#define RST_BUS_UART1 24
+#define RST_BUS_UART2 25
+
+#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */
--
2.7.4
next prev parent reply other threads:[~2018-11-25 7:43 UTC|newest]
Thread overview: 93+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-25 7:43 [RFC PATCH v4 00/17] initial support for "suniv" Allwinner new ARM9 SoC Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <cover.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-25 7:43 ` [RFC PATCH v4 01/17] ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` [RFC PATCH v4 02/17] dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <a038c5ba853cc2534a8ee9b51de3cab5539726cd.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-26 22:48 ` Rob Herring
2018-11-26 22:48 ` Rob Herring
2018-11-26 22:48 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 03/17] ARM: sunxi: add Allwinner ARMv5 SoCs Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` [RFC PATCH v4 04/17] dt-bindings: interrupt-controller: Add suniv interrupt-controller Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <ea00e2cc4dadb4a661e694dd022d8ca06470d3e8.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-26 22:49 ` Rob Herring
2018-11-26 22:49 ` Rob Herring
2018-11-26 22:49 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 05/17] irqchip/sun4i: Add a struct to hold global variables Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <2904a51d360af76765eccfb3b963a867a06a14ee.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-27 9:48 ` Maxime Ripard
2018-11-27 9:48 ` Maxime Ripard
2018-11-27 9:48 ` Maxime Ripard
2018-11-25 7:43 ` [RFC PATCH v4 06/17] irqchip/sun4i: Move IC specific register offsets to struct Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <0242923026be282e26fe9e50d9bb0ec3d5ae355f.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-27 9:49 ` Maxime Ripard
2018-11-27 9:49 ` Maxime Ripard
2018-11-27 9:49 ` Maxime Ripard
2018-11-25 7:43 ` [RFC PATCH v4 07/17] irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <1f3cce09623052eaa90093f13ea9d13047a2b250.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-27 9:49 ` Maxime Ripard
2018-11-27 9:49 ` Maxime Ripard
2018-11-27 9:49 ` Maxime Ripard
2018-11-25 7:43 ` [RFC PATCH v4 08/17] dt-bindings: timer: Add Allwinner suniv timer Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <48e7ce4d5e4c87a857cacbd01c427540c6bec002.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-27 1:37 ` Rob Herring
2018-11-27 1:37 ` Rob Herring
2018-11-27 1:37 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 09/17] clocksource: sun4i: add a compatible for suniv Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` [RFC PATCH v4 10/17] dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <ac8d900789e967650e0ab16eeadc04ec456fcf34.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-25 12:48 ` Linus Walleij
2018-11-25 12:48 ` Linus Walleij
2018-11-25 12:48 ` Linus Walleij
2018-11-25 7:43 ` [RFC PATCH v4 11/17] pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs) Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <233099b6384217ddaf5147e54859359acd56be0e.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-25 12:49 ` Linus Walleij
2018-11-25 12:49 ` Linus Walleij
2018-11-25 12:49 ` Linus Walleij
2018-11-25 7:43 ` Mesih Kilinc [this message]
2018-11-25 7:43 ` [RFC PATCH v4 12/17] dt-bindings: clock: Add Allwinner suniv F1C100s CCU Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <c2e6e3f510d5663ecf25262126dcff1df112af15.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-27 1:39 ` Rob Herring
2018-11-27 1:39 ` Rob Herring
2018-11-27 1:39 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 13/17] clk: sunxi-ng: add support for suniv F1C100s SoC Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-28 21:53 ` Stephen Boyd
2018-11-28 21:53 ` Stephen Boyd
2018-11-28 21:53 ` Stephen Boyd
2018-11-25 7:43 ` [RFC PATCH v4 14/17] dt-bindings: sram: Add Allwinner suniv F1C100s Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <f80ca2de497c44c9415b02ac9aba93721d723730.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-27 1:39 ` Rob Herring
2018-11-27 1:39 ` Rob Herring
2018-11-27 1:39 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 15/17] dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <29723ab4d09399185b8807a3f20bb2551b940f2f.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-27 1:40 ` Rob Herring
2018-11-27 1:40 ` Rob Herring
2018-11-27 1:40 ` Rob Herring
2018-11-25 7:43 ` [RFC PATCH v4 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
[not found] ` <3a0db6052d58eb440ea29772fc7ad2502a1dfa3b.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-11-27 9:59 ` Maxime Ripard
2018-11-27 9:59 ` Maxime Ripard
2018-11-27 9:59 ` Maxime Ripard
2018-11-25 7:43 ` [RFC PATCH v4 17/17] ARM: suniv: f1c100s: add device tree for Lichee Pi Nano Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
2018-11-25 7:43 ` Mesih Kilinc
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