Re: [PATCH 3/8] x86emul: support BMI1 insns

[Andrew Cooper <andrew.cooper3@citrix.com>]

On 16/01/17 13:58, Jan Beulich wrote:
>>>> On 16.01.17 at 14:51, <andrew.cooper3@citrix.com> wrote:
>> Right.  What happens in reality is this:
>>
>> --- Xen Test Framework ---
>> Environment: HVM 32bit (No paging)
>> Test VEX.W matching mode:
>>   andn cccca5a5, ff00ff00 = 00cc00a5
>> Test VEX.W opposite to mode:
>>   andn cccca5a5, ff00ff00 = 00cc00a5
>> Test result: SUCCESS
>>
>> --- Xen Test Framework ---
>> Environment: HVM 64bit (Long mode 4 levels)
>> Test VEX.W matching mode:
>>   andn cccca5a5cccca5a5, ff00ff00ff00ff00 = 00cc00a500cc00a5
>> Test VEX.W opposite to mode:
>>   andn cccca5a5cccca5a5, ff00ff00ff00ff00 = 0000000000cc00a5
>> Test result: SUCCESS
>>
>> So VEX.W is ignored in 32bit (i.e. doesn't raise #UD), and *does* cause
>> 64bit mode to operate on 32bit operands, contrary to the manual.
> Doesn't look so to me: The first result is a 64-bit one, and I'd expect
> VEX.W=1 to be "matching mode".

"matching mode" means "what the assembler generated when using the
mnemonic".  I didn't try hand-coding andn it to start with.

Here it is spelt out more clearly.

--- Xen Test Framework ---
Environment: HVM 32bit (No paging)
Test andn
Test VEX.W=0:
  andn cccca5a5, ff00ff00 = 00cc00a5
Test VEX.W=1:
  andn cccca5a5, ff00ff00 = 00cc00a5
Test result: SUCCESS

--- Xen Test Framework ---
Environment: HVM 64bit (Long mode 4 levels)
Test andn
Test VEX.W=1:
  andn cccca5a5cccca5a5, ff00ff00ff00ff00 = 00cc00a500cc00a5
Test VEX.W=0:
  andn cccca5a5cccca5a5, ff00ff00ff00ff00 = 0000000000cc00a5
Test result: SUCCESS

My conclusions still stand.

~Andrew

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel