* ppc4xx: u-boot sees PCIe endpoint, linux does not.
@ 2008-11-28 12:50 ` Leon Woestenberg
0 siblings, 0 replies; 10+ messages in thread
From: Leon Woestenberg @ 2008-11-28 12:50 UTC (permalink / raw)
To: u-boot, Linux PPC
Hello,
AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
u-boot sees the end point, but Linux does not:
U-Boot 1.3.3-00249-ga524e11 (Jun 30 2008 - 16:05:51)
CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
<...>
Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
<...>
PCIE1: successfully set as root-complex
02 00 2071 2071 00ff 00
Now, if I re-program the end-point FPGA during the u-boot boot
time-out, Linux will recognize the end-point.
Any takers on what I should start looking for?
Regards,
--
Leon
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] ppc4xx: u-boot sees PCIe endpoint, linux does not.
@ 2008-11-28 12:50 ` Leon Woestenberg
0 siblings, 0 replies; 10+ messages in thread
From: Leon Woestenberg @ 2008-11-28 12:50 UTC (permalink / raw)
To: u-boot
Hello,
AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
u-boot sees the end point, but Linux does not:
U-Boot 1.3.3-00249-ga524e11 (Jun 30 2008 - 16:05:51)
CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
<...>
Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
<...>
PCIE1: successfully set as root-complex
02 00 2071 2071 00ff 00
Now, if I re-program the end-point FPGA during the u-boot boot
time-out, Linux will recognize the end-point.
Any takers on what I should start looking for?
Regards,
--
Leon
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ppc4xx: u-boot sees PCIe endpoint, linux does not.
2008-11-28 12:50 ` [U-Boot] " Leon Woestenberg
@ 2008-12-01 8:12 ` Benjamin Herrenschmidt
-1 siblings, 0 replies; 10+ messages in thread
From: Benjamin Herrenschmidt @ 2008-12-01 8:12 UTC (permalink / raw)
To: Leon Woestenberg; +Cc: u-boot, Linux PPC
On Fri, 2008-11-28 at 13:50 +0100, Leon Woestenberg wrote:
> Hello,
>
> AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
>
> u-boot sees the end point, but Linux does not:
>
> U-Boot 1.3.3-00249-ga524e11 (Jun 30 2008 - 16:05:51)
> CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
> <...>
> Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
> <...>
> PCIE1: successfully set as root-complex
> 02 00 2071 2071 00ff 00
>
>
> Now, if I re-program the end-point FPGA during the u-boot boot
> time-out, Linux will recognize the end-point.
>
> Any takers on what I should start looking for?
It's possible that either the reset in between goes bonkers or something
else causes your FPGA to stop responding. It looks like a programming
problem with the FPGA to me.
Ben.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] ppc4xx: u-boot sees PCIe endpoint, linux does not.
@ 2008-12-01 8:12 ` Benjamin Herrenschmidt
0 siblings, 0 replies; 10+ messages in thread
From: Benjamin Herrenschmidt @ 2008-12-01 8:12 UTC (permalink / raw)
To: u-boot
On Fri, 2008-11-28 at 13:50 +0100, Leon Woestenberg wrote:
> Hello,
>
> AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
>
> u-boot sees the end point, but Linux does not:
>
> U-Boot 1.3.3-00249-ga524e11 (Jun 30 2008 - 16:05:51)
> CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
> <...>
> Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
> <...>
> PCIE1: successfully set as root-complex
> 02 00 2071 2071 00ff 00
>
>
> Now, if I re-program the end-point FPGA during the u-boot boot
> time-out, Linux will recognize the end-point.
>
> Any takers on what I should start looking for?
It's possible that either the reset in between goes bonkers or something
else causes your FPGA to stop responding. It looks like a programming
problem with the FPGA to me.
Ben.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ppc4xx: u-boot sees PCIe endpoint, linux does not.
2008-12-01 8:12 ` [U-Boot] " Benjamin Herrenschmidt
@ 2008-12-01 19:19 ` Leon Woestenberg
-1 siblings, 0 replies; 10+ messages in thread
From: Leon Woestenberg @ 2008-12-01 19:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: u-boot, Linux PPC
Hello all,
On Mon, Dec 1, 2008 at 9:12 AM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Fri, 2008-11-28 at 13:50 +0100, Leon Woestenberg wrote:
>>
>> AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
>>
>> u-boot sees the end point, but Linux does not:
>>
>> U-Boot 1.3.3-00249-ga524e11 (Jun 30 2008 - 16:05:51)
>> CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
>> <...>
>> Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
>> <...>
>> PCIE1: successfully set as root-complex
>> 02 00 2071 2071 00ff 00
>>
>> Now, if I re-program the end-point FPGA during the u-boot boot
>> time-out, Linux will recognize the end-point.
>>
> It's possible that either the reset in between goes bonkers or something
> else causes your FPGA to stop responding. It looks like a programming
> problem with the FPGA to me.
>
I have verified that the end point does not receive any kind of reset.
Also, this problem only happens on the Canyonlands board; on x86 and
powerpc MPC8315E it remains properly working after soft/hard resets,
u-boot init etc.
Could it be u-boot overwrites a too large payload into the config
space or something similar, which makes subsequent accesses fail?
Regards,
--
Leon
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] ppc4xx: u-boot sees PCIe endpoint, linux does not.
@ 2008-12-01 19:19 ` Leon Woestenberg
0 siblings, 0 replies; 10+ messages in thread
From: Leon Woestenberg @ 2008-12-01 19:19 UTC (permalink / raw)
To: u-boot
Hello all,
On Mon, Dec 1, 2008 at 9:12 AM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Fri, 2008-11-28 at 13:50 +0100, Leon Woestenberg wrote:
>>
>> AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
>>
>> u-boot sees the end point, but Linux does not:
>>
>> U-Boot 1.3.3-00249-ga524e11 (Jun 30 2008 - 16:05:51)
>> CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
>> <...>
>> Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
>> <...>
>> PCIE1: successfully set as root-complex
>> 02 00 2071 2071 00ff 00
>>
>> Now, if I re-program the end-point FPGA during the u-boot boot
>> time-out, Linux will recognize the end-point.
>>
> It's possible that either the reset in between goes bonkers or something
> else causes your FPGA to stop responding. It looks like a programming
> problem with the FPGA to me.
>
I have verified that the end point does not receive any kind of reset.
Also, this problem only happens on the Canyonlands board; on x86 and
powerpc MPC8315E it remains properly working after soft/hard resets,
u-boot init etc.
Could it be u-boot overwrites a too large payload into the config
space or something similar, which makes subsequent accesses fail?
Regards,
--
Leon
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [U-Boot] ppc4xx: u-boot sees PCIe endpoint, linux does not.
2008-12-01 19:19 ` [U-Boot] " Leon Woestenberg
@ 2008-12-01 19:46 ` Stefan Roese
-1 siblings, 0 replies; 10+ messages in thread
From: Stefan Roese @ 2008-12-01 19:46 UTC (permalink / raw)
To: u-boot; +Cc: Linux PPC
On Monday 01 December 2008, Leon Woestenberg wrote:
> >> Now, if I re-program the end-point FPGA during the u-boot boot
> >> time-out, Linux will recognize the end-point.
> >
> > It's possible that either the reset in between goes bonkers or something
> > else causes your FPGA to stop responding. It looks like a programming
> > problem with the FPGA to me.
>
> I have verified that the end point does not receive any kind of reset.
>
> Also, this problem only happens on the Canyonlands board; on x86 and
> powerpc MPC8315E it remains properly working after soft/hard resets,
> u-boot init etc.
This could be because only the 4xx Linux PCI(e) driver really resets the
endpoint (PHY reset). But you seem to have analyzed this already.
> Could it be u-boot overwrites a too large payload into the config
> space or something similar, which makes subsequent accesses fail?
Not sure. I suggest that you disable the PCI(e) support in U-Boot to see if
Linux behaves differently on a non-pre-initialized endpoint.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] ppc4xx: u-boot sees PCIe endpoint, linux does not.
@ 2008-12-01 19:46 ` Stefan Roese
0 siblings, 0 replies; 10+ messages in thread
From: Stefan Roese @ 2008-12-01 19:46 UTC (permalink / raw)
To: u-boot
On Monday 01 December 2008, Leon Woestenberg wrote:
> >> Now, if I re-program the end-point FPGA during the u-boot boot
> >> time-out, Linux will recognize the end-point.
> >
> > It's possible that either the reset in between goes bonkers or something
> > else causes your FPGA to stop responding. It looks like a programming
> > problem with the FPGA to me.
>
> I have verified that the end point does not receive any kind of reset.
>
> Also, this problem only happens on the Canyonlands board; on x86 and
> powerpc MPC8315E it remains properly working after soft/hard resets,
> u-boot init etc.
This could be because only the 4xx Linux PCI(e) driver really resets the
endpoint (PHY reset). But you seem to have analyzed this already.
> Could it be u-boot overwrites a too large payload into the config
> space or something similar, which makes subsequent accesses fail?
Not sure. I suggest that you disable the PCI(e) support in U-Boot to see if
Linux behaves differently on a non-pre-initialized endpoint.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [U-Boot] ppc4xx: u-boot sees PCIe endpoint, linux does not.
2008-12-01 19:46 ` Stefan Roese
@ 2009-03-09 14:23 ` Leon Woestenberg
-1 siblings, 0 replies; 10+ messages in thread
From: Leon Woestenberg @ 2009-03-09 14:23 UTC (permalink / raw)
To: Stefan Roese; +Cc: Linux PPC, u-boot
Hello Stefan,
On Mon, Dec 1, 2008 at 8:46 PM, Stefan Roese <sr@denx.de> wrote:
> On Monday 01 December 2008, Leon Woestenberg wrote:
>> >> Now, if I re-program the end-point FPGA during the u-boot boot
>> >> time-out, Linux will recognize the end-point.
>> >
>> > It's possible that either the reset in between goes bonkers or something
>> > else causes your FPGA to stop responding. It looks like a programming
>> > problem with the FPGA to me.
>>
>> I have verified that the end point does not receive any kind of reset.
>>
>> Also, this problem only happens on the Canyonlands board; on x86 and
>> powerpc MPC8315E it remains properly working after soft/hard resets,
>> u-boot init etc.
>
> This could be because only the 4xx Linux PCI(e) driver really resets the
> endpoint (PHY reset). But you seem to have analyzed this already.
>
Some progress:
Using au-boot GIT checkout of 9-2-2009 (one month old) I now have
different behaviour:
u-boot does report a link, but no longer the PCIe vendor id:
CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
Security/Kasumi support
Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
Internal PCI arbiter disabled
32 kB I-Cache 32 kB D-Cache
Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
I2C: ready
DTT: 1 is 44 C
DRAM: 512 MB (ECC not enabled, 400 MHz, CL3)
FLASH: 64 MB
NAND: 128 MiB
PCI: Bus Dev VenId DevId Class Int
PCIE0: link is not up.
PCIE0: initialization as root-complex failed
PCIE1: successfully set as root-complex
Linux now correctly recognizes the device.
The FPGA with PCIe end point now also survives both a hard reset
(reset button) and soft reset (shutdown -r now in Linux).
Regards,
--
Leon
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] ppc4xx: u-boot sees PCIe endpoint, linux does not.
@ 2009-03-09 14:23 ` Leon Woestenberg
0 siblings, 0 replies; 10+ messages in thread
From: Leon Woestenberg @ 2009-03-09 14:23 UTC (permalink / raw)
To: u-boot
Hello Stefan,
On Mon, Dec 1, 2008 at 8:46 PM, Stefan Roese <sr@denx.de> wrote:
> On Monday 01 December 2008, Leon Woestenberg wrote:
>> >> Now, if I re-program the end-point FPGA during the u-boot boot
>> >> time-out, Linux will recognize the end-point.
>> >
>> > It's possible that either the reset in between goes bonkers or something
>> > else causes your FPGA to stop responding. It looks like a programming
>> > problem with the FPGA to me.
>>
>> I have verified that the end point does not receive any kind of reset.
>>
>> Also, this problem only happens on the Canyonlands board; on x86 and
>> powerpc MPC8315E it remains properly working after soft/hard resets,
>> u-boot init etc.
>
> This could be because only the 4xx Linux PCI(e) driver really resets the
> endpoint (PHY reset). But you seem to have analyzed this already.
>
Some progress:
Using au-boot GIT checkout of 9-2-2009 (one month old) I now have
different behaviour:
u-boot does report a link, but no longer the PCIe vendor id:
CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
Security/Kasumi support
Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
Internal PCI arbiter disabled
32 kB I-Cache 32 kB D-Cache
Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
I2C: ready
DTT: 1 is 44 C
DRAM: 512 MB (ECC not enabled, 400 MHz, CL3)
FLASH: 64 MB
NAND: 128 MiB
PCI: Bus Dev VenId DevId Class Int
PCIE0: link is not up.
PCIE0: initialization as root-complex failed
PCIE1: successfully set as root-complex
Linux now correctly recognizes the device.
The FPGA with PCIe end point now also survives both a hard reset
(reset button) and soft reset (shutdown -r now in Linux).
Regards,
--
Leon
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2009-03-09 14:50 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2008-11-28 12:50 ppc4xx: u-boot sees PCIe endpoint, linux does not Leon Woestenberg
2008-11-28 12:50 ` [U-Boot] " Leon Woestenberg
2008-12-01 8:12 ` Benjamin Herrenschmidt
2008-12-01 8:12 ` [U-Boot] " Benjamin Herrenschmidt
2008-12-01 19:19 ` Leon Woestenberg
2008-12-01 19:19 ` [U-Boot] " Leon Woestenberg
2008-12-01 19:46 ` Stefan Roese
2008-12-01 19:46 ` Stefan Roese
2009-03-09 14:23 ` Leon Woestenberg
2009-03-09 14:23 ` Leon Woestenberg
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