* [PATCH] drm/amdgpu: Add CM_TEST_DEBUG regs for DCN
@ 2018-03-19 17:45 Harry Wentland
[not found] ` <20180319174522.6691-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Harry Wentland @ 2018-03-19 17:45 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
We'd like to use them for reading DCN debug status.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
---
See patch for where we use them http://git.amd.com:8080/#/c/137151/1
Tony can comment on details.
Harry
.../gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h | 19 ++++++++++++++++---
.../drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h | 8 ++++++++
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
index 4ccf9681c45d..721c61171045 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
@@ -3895,6 +3895,10 @@
#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_STATUS 0x0d33
#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35
+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36
+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
@@ -4367,7 +4371,10 @@
#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
-
+#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50
+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51
+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x399c
@@ -4839,7 +4846,10 @@
#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_STATUS 0x0f69
#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
-
+#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b
+#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c
+#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3e08
@@ -5311,7 +5321,10 @@
#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_STATUS 0x1084
#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
-
+#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086
+#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM3_CM_TEST_DEBUG_DATA 0x1087
+#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x4274
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
index e2a2f114bd8e..e7c0cad41081 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
@@ -14049,6 +14049,14 @@
#define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2
#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
#define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL
+//CM0_CM_TEST_DEBUG_INDEX
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//CM0_CM_TEST_DEBUG_DATA
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
--
2.14.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: Add CM_TEST_DEBUG regs for DCN
[not found] ` <20180319174522.6691-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-19 18:22 ` Harry Wentland
2018-03-22 19:53 ` Harry Wentland
1 sibling, 0 replies; 4+ messages in thread
From: Harry Wentland @ 2018-03-19 18:22 UTC (permalink / raw)
To: amd-gfx mailing list
On 2018-03-19 01:45 PM, Harry Wentland wrote:
> We'd like to use them for reading DCN debug status.
>
> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
> ---
>
> See patch for where we use them http://git.amd.com:8080/#/c/137151/1
>
> Tony can comment on details.
>
Whoops, didn't mean to include this message. Patch that uses these is coming shortly.
Harry
> Harry
>
> .../gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h | 19 ++++++++++++++++---
> .../drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h | 8 ++++++++
> 2 files changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> index 4ccf9681c45d..721c61171045 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> @@ -3895,6 +3895,10 @@
> #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM0_CM_MEM_PWR_STATUS 0x0d33
> #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
> +#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35
> +#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36
> +#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
>
> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> @@ -4367,7 +4371,10 @@
> #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
> #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50
> +#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51
> +#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x399c
> @@ -4839,7 +4846,10 @@
> #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM2_CM_MEM_PWR_STATUS 0x0f69
> #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b
> +#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c
> +#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x3e08
> @@ -5311,7 +5321,10 @@
> #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM3_CM_MEM_PWR_STATUS 0x1084
> #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086
> +#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM3_CM_TEST_DEBUG_DATA 0x1087
> +#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x4274
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> index e2a2f114bd8e..e7c0cad41081 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> @@ -14049,6 +14049,14 @@
> #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2
> #define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
> #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL
> +//CM0_CM_TEST_DEBUG_INDEX
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
> +//CM0_CM_TEST_DEBUG_DATA
> +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
> +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
>
>
> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: Add CM_TEST_DEBUG regs for DCN
[not found] ` <20180319174522.6691-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-19 18:22 ` Harry Wentland
@ 2018-03-22 19:53 ` Harry Wentland
[not found] ` <b1e3006c-33db-04d0-544d-74c585de9f19-5C7GfCeVMHo@public.gmane.org>
1 sibling, 1 reply; 4+ messages in thread
From: Harry Wentland @ 2018-03-22 19:53 UTC (permalink / raw)
To: amd-gfx mailing list; +Cc: Deucher, Alexander, Cheng, Tony
Ping.
Wonder if I can get an RB or AB for this.
Harry
On 2018-03-19 01:45 PM, Harry Wentland wrote:
> We'd like to use them for reading DCN debug status.
>
> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
> ---
>
> See patch for where we use them http://git.amd.com:8080/#/c/137151/1
>
> Tony can comment on details.
>
> Harry
>
> .../gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h | 19 ++++++++++++++++---
> .../drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h | 8 ++++++++
> 2 files changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> index 4ccf9681c45d..721c61171045 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> @@ -3895,6 +3895,10 @@
> #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM0_CM_MEM_PWR_STATUS 0x0d33
> #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
> +#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35
> +#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36
> +#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
>
> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> @@ -4367,7 +4371,10 @@
> #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
> #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50
> +#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51
> +#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x399c
> @@ -4839,7 +4846,10 @@
> #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM2_CM_MEM_PWR_STATUS 0x0f69
> #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b
> +#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c
> +#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x3e08
> @@ -5311,7 +5321,10 @@
> #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM3_CM_MEM_PWR_STATUS 0x1084
> #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086
> +#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM3_CM_TEST_DEBUG_DATA 0x1087
> +#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x4274
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> index e2a2f114bd8e..e7c0cad41081 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> @@ -14049,6 +14049,14 @@
> #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2
> #define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
> #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL
> +//CM0_CM_TEST_DEBUG_INDEX
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
> +//CM0_CM_TEST_DEBUG_DATA
> +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
> +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
>
>
> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: Add CM_TEST_DEBUG regs for DCN
[not found] ` <b1e3006c-33db-04d0-544d-74c585de9f19-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-22 20:03 ` Deucher, Alexander
0 siblings, 0 replies; 4+ messages in thread
From: Deucher, Alexander @ 2018-03-22 20:03 UTC (permalink / raw)
To: Wentland, Harry, amd-gfx mailing list; +Cc: Cheng, Tony
[-- Attachment #1.1: Type: text/plain, Size: 6420 bytes --]
Acked-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
________________________________
From: Wentland, Harry
Sent: Thursday, March 22, 2018 3:53:57 PM
To: amd-gfx mailing list
Cc: Cheng, Tony; Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: Add CM_TEST_DEBUG regs for DCN
Ping.
Wonder if I can get an RB or AB for this.
Harry
On 2018-03-19 01:45 PM, Harry Wentland wrote:
> We'd like to use them for reading DCN debug status.
>
> Signed-off-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
> ---
>
> See patch for where we use them http://git.amd.com:8080/#/c/137151/1
>
> Tony can comment on details.
>
> Harry
>
> .../gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h | 19 ++++++++++++++++---
> .../drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h | 8 ++++++++
> 2 files changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> index 4ccf9681c45d..721c61171045 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
> @@ -3895,6 +3895,10 @@
> #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM0_CM_MEM_PWR_STATUS 0x0d33
> #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
> +#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35
> +#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36
> +#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
>
> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> @@ -4367,7 +4371,10 @@
> #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
> #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50
> +#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51
> +#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x399c
> @@ -4839,7 +4846,10 @@
> #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM2_CM_MEM_PWR_STATUS 0x0f69
> #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b
> +#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c
> +#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x3e08
> @@ -5311,7 +5321,10 @@
> #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
> #define mmCM3_CM_MEM_PWR_STATUS 0x1084
> #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
> -
> +#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086
> +#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
> +#define mmCM3_CM_TEST_DEBUG_DATA 0x1087
> +#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
>
> // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
> // base address: 0x4274
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> index e2a2f114bd8e..e7c0cad41081 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
> @@ -14049,6 +14049,14 @@
> #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2
> #define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
> #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL
> +//CM0_CM_TEST_DEBUG_INDEX
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
> +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
> +//CM0_CM_TEST_DEBUG_DATA
> +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
> +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
>
>
> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>
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2018-03-19 17:45 [PATCH] drm/amdgpu: Add CM_TEST_DEBUG regs for DCN Harry Wentland
[not found] ` <20180319174522.6691-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-19 18:22 ` Harry Wentland
2018-03-22 19:53 ` Harry Wentland
[not found] ` <b1e3006c-33db-04d0-544d-74c585de9f19-5C7GfCeVMHo@public.gmane.org>
2018-03-22 20:03 ` Deucher, Alexander
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