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From: Stefan Wahren <stefan.wahren@i2se.com>
To: Richard Schleich <rs@noreya.tech>,
	robh+dt@kernel.org, nsaenz@kernel.org,  f.fainelli@gmail.com,
	bcm-kernel-feedback-list@broadcom.com,
	devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: dts: bcm2711: Fix comment
Date: Sun, 6 Feb 2022 13:55:46 +0100	[thread overview]
Message-ID: <c4e11d53-67af-1a51-9765-2ae16dc1372f@i2se.com> (raw)
In-Reply-To: <20220205195802.52449-1-rs@noreya.tech>

Hi Richard,

the subject of this patch is too general. Here is my suggestion:

ARM: dts: bcm2711: Fix comment about L2 cache set calculation

But maybe you have a better idea.

Am 05.02.22 um 20:58 schrieb Richard Schleich:
> No functional change.

Please write a simple sentence, explaining why this change is necessary.

Thanks

>
> Signed-off-by: Richard Schleich <rs@noreya.tech>
> ---
>  arch/arm/boot/dts/bcm2711.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
> index d9f31873e711..0f2f26dc5ec6 100644
> --- a/arch/arm/boot/dts/bcm2711.dtsi
> +++ b/arch/arm/boot/dts/bcm2711.dtsi
> @@ -536,7 +536,7 @@ l2: l2-cache0 {
>  			compatible = "cache";
>  			cache-size = <0x100000>;
>  			cache-line-size = <64>;
> -			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16000ways/16-way set
> +			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
>  			cache-level = <2>;
>  		};
>  	};

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WARNING: multiple messages have this Message-ID (diff)
From: Stefan Wahren <stefan.wahren@i2se.com>
To: Richard Schleich <rs@noreya.tech>,
	robh+dt@kernel.org, nsaenz@kernel.org, f.fainelli@gmail.com,
	bcm-kernel-feedback-list@broadcom.com,
	devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: dts: bcm2711: Fix comment
Date: Sun, 6 Feb 2022 13:55:46 +0100	[thread overview]
Message-ID: <c4e11d53-67af-1a51-9765-2ae16dc1372f@i2se.com> (raw)
In-Reply-To: <20220205195802.52449-1-rs@noreya.tech>

Hi Richard,

the subject of this patch is too general. Here is my suggestion:

ARM: dts: bcm2711: Fix comment about L2 cache set calculation

But maybe you have a better idea.

Am 05.02.22 um 20:58 schrieb Richard Schleich:
> No functional change.

Please write a simple sentence, explaining why this change is necessary.

Thanks

>
> Signed-off-by: Richard Schleich <rs@noreya.tech>
> ---
>  arch/arm/boot/dts/bcm2711.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
> index d9f31873e711..0f2f26dc5ec6 100644
> --- a/arch/arm/boot/dts/bcm2711.dtsi
> +++ b/arch/arm/boot/dts/bcm2711.dtsi
> @@ -536,7 +536,7 @@ l2: l2-cache0 {
>  			compatible = "cache";
>  			cache-size = <0x100000>;
>  			cache-line-size = <64>;
> -			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16000ways/16-way set
> +			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
>  			cache-level = <2>;
>  		};
>  	};

  reply	other threads:[~2022-02-06 12:57 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-05 19:58 [PATCH] ARM: dts: bcm2711: Fix comment Richard Schleich
2022-02-05 19:58 ` Richard Schleich
2022-02-06 12:55 ` Stefan Wahren [this message]
2022-02-06 12:55   ` Stefan Wahren
2022-02-11 22:23 ` Florian Fainelli
2022-02-11 22:23   ` Florian Fainelli
2022-02-11 22:24   ` Florian Fainelli
2022-02-11 22:24     ` Florian Fainelli

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