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From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] armv8: minor fix to comment for enabling SMPEN bit
Date: Thu, 27 Apr 2017 09:59:20 -0700	[thread overview]
Message-ID: <c51b3397-9a6c-414c-a015-27030b970c93@nxp.com> (raw)
In-Reply-To: <1493267763-10213-1-git-send-email-dinguyen@kernel.org>

On 04/26/2017 09:36 PM, Dinh Nguyen wrote:
> The SMPEN bit is located in the cpuectlr_el1 register and not the
> cpuactlr_el1 register. Adjust the comment accordingly and also fix
> a spelling error.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> CC: Mingkai Hu <mingkai.hu@nxp.com>
> CC: Gong Qianyu <Qianyu.Gong@nxp.com>
> CC: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> CC: York Sun <york.sun@nxp.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
> CC: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>  arch/arm/cpu/armv8/start.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index 62d97f7..354468b 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -86,12 +86,12 @@ save_boot_params_ret:
>  0:
>
>  	/*
> -	 * Enalbe SMPEN bit for coherency.
> +	 * Enable SMPEN bit for coherency.
>  	 * This register is not architectural but at the moment
>  	 * this bit should be set for A53/A57/A72.
>  	 */
>  #ifdef CONFIG_ARMV8_SET_SMPEN
> -	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
> +	mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
>  	orr     x0, x0, #0x40
>  	msr     S3_1_c15_c2_1, x0
>  #endif
>

Thanks for fixing this.

Reviewed-by: York Sun <york.sun@nxp.com>

  reply	other threads:[~2017-04-27 16:59 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-27  4:36 [U-Boot] [PATCH] armv8: minor fix to comment for enabling SMPEN bit Dinh Nguyen
2017-04-27 16:59 ` York Sun [this message]
2017-05-15 23:18 ` [U-Boot] " Tom Rini

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