[U-Boot] [PATCH] armv8: minor fix to comment for enabling SMPEN bit

[U-Boot] [PATCH] armv8: minor fix to comment for enabling SMPEN bit

[Dinh Nguyen]

The SMPEN bit is located in the cpuectlr_el1 register and not the
cpuactlr_el1 register. Adjust the comment accordingly and also fix
a spelling error.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
CC: Mingkai Hu <mingkai.hu@nxp.com>
CC: Gong Qianyu <Qianyu.Gong@nxp.com>
CC: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
CC: York Sun <york.sun@nxp.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/cpu/armv8/start.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 62d97f7..354468b 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -86,12 +86,12 @@ save_boot_params_ret:
 0:
 
 	/*
-	 * Enalbe SMPEN bit for coherency.
+	 * Enable SMPEN bit for coherency.
 	 * This register is not architectural but at the moment
 	 * this bit should be set for A53/A57/A72.
 	 */
 #ifdef CONFIG_ARMV8_SET_SMPEN
-	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
+	mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
 	orr     x0, x0, #0x40
 	msr     S3_1_c15_c2_1, x0
 #endif
-- 
2.7.4

[U-Boot] [PATCH] armv8: minor fix to comment for enabling SMPEN bit

[York Sun]

On 04/26/2017 09:36 PM, Dinh Nguyen wrote:
> The SMPEN bit is located in the cpuectlr_el1 register and not the
> cpuactlr_el1 register. Adjust the comment accordingly and also fix
> a spelling error.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> CC: Mingkai Hu <mingkai.hu@nxp.com>
> CC: Gong Qianyu <Qianyu.Gong@nxp.com>
> CC: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> CC: York Sun <york.sun@nxp.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
> CC: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>  arch/arm/cpu/armv8/start.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index 62d97f7..354468b 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -86,12 +86,12 @@ save_boot_params_ret:
>  0:
>
>  	/*
> -	 * Enalbe SMPEN bit for coherency.
> +	 * Enable SMPEN bit for coherency.
>  	 * This register is not architectural but at the moment
>  	 * this bit should be set for A53/A57/A72.
>  	 */
>  #ifdef CONFIG_ARMV8_SET_SMPEN
> -	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
> +	mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
>  	orr     x0, x0, #0x40
>  	msr     S3_1_c15_c2_1, x0
>  #endif
>

Thanks for fixing this.

Reviewed-by: York Sun <york.sun@nxp.com>

[U-Boot] armv8: minor fix to comment for enabling SMPEN bit

[Tom Rini]

On Wed, Apr 26, 2017 at 11:36:03PM -0500, Dinh Nguyen wrote:

> The SMPEN bit is located in the cpuectlr_el1 register and not the
> cpuactlr_el1 register. Adjust the comment accordingly and also fix
> a spelling error.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> CC: Mingkai Hu <mingkai.hu@nxp.com>
> CC: Gong Qianyu <Qianyu.Gong@nxp.com>
> CC: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> CC: York Sun <york.sun@nxp.com>
> CC: Albert Aribaud <albert.u.boot@aribaud.net>
> CC: Masahiro Yamada <yamada.masahiro@socionext.com>
> Reviewed-by: York Sun <york.sun@nxp.com>

Applied to u-boot/master, thanks!

-- 
Tom
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