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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Zhenyu Ye <yezhenyu2@huawei.com>,
	catalin.marinas@arm.com, peterz@infradead.org,
	mark.rutland@arm.com, will@kernel.org,
	aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org,
	npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org,
	maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de,
	yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com,
	broonie@kernel.org, guohanjun@huawei.com
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-mm@kvack.org, arm@kernel.org, xiexiangyou@huawei.com,
	prime.zeng@hisilicon.com, zhangshaokun@hisilicon.com,
	kuhn.chenqun@huawei.com
Subject: Re: [PATCH v3 1/6] arm64: Detect the ARMv8.4 TTL feature
Date: Tue, 26 May 2020 08:09:03 +0530	[thread overview]
Message-ID: <c6b6eb07-2606-9fc0-280a-e53b81a6491c@arm.com> (raw)
In-Reply-To: <20200525125300.794-2-yezhenyu2@huawei.com>

Hello Zhenyu,

On 05/25/2020 06:22 PM, Zhenyu Ye wrote:
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c4ac0ac25a00..477d84ba1056 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -725,6 +725,7 @@
>  
>  /* id_aa64mmfr2 */
>  #define ID_AA64MMFR2_E0PD_SHIFT		60
> +#define ID_AA64MMFR2_TTL_SHIFT		48
>  #define ID_AA64MMFR2_FWB_SHIFT		40
>  #define ID_AA64MMFR2_AT_SHIFT		32
>  #define ID_AA64MMFR2_LVA_SHIFT		16
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 9fac745aa7bb..d993dc6dc7d5 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -244,6 +244,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
>  
>  static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
> @@ -1622,6 +1623,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.matches = has_cpuid_feature,
>  		.cpu_enable = cpu_has_fwb,
>  	},

This patch (https://patchwork.kernel.org/patch/11557359/) is adding some
more ID_AA64MMFR2 features including the TTL. I am going to respin parts
of the V4 series patches along with the above mentioned patch. So please
rebase this series accordingly, probably on latest next.

- Anshuman

WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Zhenyu Ye <yezhenyu2@huawei.com>,
	catalin.marinas@arm.com, peterz@infradead.org,
	mark.rutland@arm.com, will@kernel.org,
	aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org,
	npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org,
	maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de,
	yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com,
	broonie@kernel.org, guohanjun@huawei.com
Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org,
	xiexiangyou@huawei.com, zhangshaokun@hisilicon.com,
	linux-mm@kvack.org, arm@kernel.org, prime.zeng@hisilicon.com,
	kuhn.chenqun@huawei.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 1/6] arm64: Detect the ARMv8.4 TTL feature
Date: Tue, 26 May 2020 08:09:03 +0530	[thread overview]
Message-ID: <c6b6eb07-2606-9fc0-280a-e53b81a6491c@arm.com> (raw)
In-Reply-To: <20200525125300.794-2-yezhenyu2@huawei.com>

Hello Zhenyu,

On 05/25/2020 06:22 PM, Zhenyu Ye wrote:
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c4ac0ac25a00..477d84ba1056 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -725,6 +725,7 @@
>  
>  /* id_aa64mmfr2 */
>  #define ID_AA64MMFR2_E0PD_SHIFT		60
> +#define ID_AA64MMFR2_TTL_SHIFT		48
>  #define ID_AA64MMFR2_FWB_SHIFT		40
>  #define ID_AA64MMFR2_AT_SHIFT		32
>  #define ID_AA64MMFR2_LVA_SHIFT		16
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 9fac745aa7bb..d993dc6dc7d5 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -244,6 +244,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
>  
>  static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
> @@ -1622,6 +1623,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.matches = has_cpuid_feature,
>  		.cpu_enable = cpu_has_fwb,
>  	},

This patch (https://patchwork.kernel.org/patch/11557359/) is adding some
more ID_AA64MMFR2 features including the TTL. I am going to respin parts
of the V4 series patches along with the above mentioned patch. So please
rebase this series accordingly, probably on latest next.

- Anshuman

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-05-26  2:39 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-25 12:52 [PATCH v3 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-05-25 12:52 ` Zhenyu Ye
2020-05-25 12:52 ` Zhenyu Ye
2020-05-25 12:52 ` [PATCH v3 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-26  2:39   ` Anshuman Khandual [this message]
2020-05-26  2:39     ` Anshuman Khandual
2020-05-26  6:40     ` Zhenyu Ye
2020-05-26  6:40       ` Zhenyu Ye
2020-05-26  6:40       ` Zhenyu Ye
2020-05-26 10:06       ` Marc Zyngier
2020-05-26 10:06         ` Marc Zyngier
2020-05-25 12:52 ` [PATCH v3 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:52 ` [PATCH v3 3/6] arm64: Add tlbi_user_level " Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:52 ` [PATCH v3 4/6] tlb: mmu_gather: add tlb_flush_*_range APIs Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:52 ` [PATCH v3 5/6] mm: tlb: Provide flush_*_tlb_range wrappers Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:52   ` Zhenyu Ye
2020-05-25 12:53 ` [PATCH v3 6/6] arm64: tlb: Set the TTL field in flush_tlb_range Zhenyu Ye
2020-05-25 12:53   ` Zhenyu Ye
2020-05-25 12:53   ` Zhenyu Ye

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