From: Geert Uytterhoeven <geert+renesas@glider.be> To: Tony Lindgren <tony@atomide.com>, Russell King <linux@armlinux.org.uk>, Rajendra Nayak <rnayak@codeaurora.org>, Paul Walmsley <paul@pwsan.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Nicolas Ferre <nicolas.ferre@microchip.com>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Ludovic Desroches <ludovic.desroches@microchip.com>, Tero Kristo <kristo@kernel.org>, Jonathan Cameron <jic23@kernel.org>, Lars-Peter Clausen <lars@metafoo.de>, Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>, Benoit Parrot <bparrot@ti.com>, Mauro Carvalho Chehab <mchehab@kernel.org>, Adrian Hunter <adrian.hunter@intel.com>, Andrew Jeffery <andrew@aj.id.au>, Ulf Hansson <ulf.hansson@linaro.org>, Joel Stanley <joel@jms.id.au>, Ping-Ke Shih <pkshih@realtek.com>, Kalle Valo <kvalo@codeaurora.org>, "David S . Miller" <davem@davemloft.net>, Jakub Kicinski <kuba@kernel.org>, Linus Walleij <linus.walleij@linaro.org>, Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>, Magnus Damm <magnus.damm@gmail.com>, Eduardo Valentin <edubezval@gmail.com>, Keerthy <j-keerthy@ti.com>, "Rafael J . Wysocki" <rafael@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Amit Kucheria <amitk@kernel.org>, Zhang Rui <rui.zhang@intel.com>, Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com> Cc: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-iio@vger.kernel.org, linux-media@vger.kernel.org, linux-mmc@vger.kernel.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-wireless@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, alsa-devel@alsa-project.org, Geert Uytterhoeven <geert+renesas@glider.be> Subject: [PATCH 02/17] clk: renesas: Use bitfield helpers Date: Mon, 22 Nov 2021 16:53:55 +0100 [thread overview] Message-ID: <c6e4bfbf798a8fcb4d8c02861a0c1b029f2f5cb1.1637592133.git.geert+renesas@glider.be> (raw) In-Reply-To: <cover.1637592133.git.geert+renesas@glider.be> Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const respective non-const bitfields, instead of open-coding the same operations. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- drivers/clk/renesas/clk-div6.c | 6 +++--- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 9 +++------ drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++++---------- 3 files changed, 11 insertions(+), 19 deletions(-) diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c index 3abd6e5400aded6a..f7b827b5e9b2dd32 100644 --- a/drivers/clk/renesas/clk-div6.c +++ b/drivers/clk/renesas/clk-div6.c @@ -7,6 +7,7 @@ * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> */ +#include <linux/bitfield.h> #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/io.h> @@ -171,8 +172,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) if (clock->src_mask == 0) return 0; - hw_index = (readl(clock->reg) & clock->src_mask) >> - __ffs(clock->src_mask); + hw_index = field_get(clock->src_mask, readl(clock->reg)); for (i = 0; i < clk_hw_get_num_parents(hw); i++) { if (clock->parents[i] == hw_index) return i; @@ -191,7 +191,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) if (index >= clk_hw_get_num_parents(hw)) return -EINVAL; - src = clock->parents[index] << __ffs(clock->src_mask); + src = field_prep(clock->src_mask, clock->parents[index]); writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); return 0; } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 7df86743c5491292..f716e739d138b722 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -302,11 +302,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); - unsigned int mult; - u32 val; - - val = readl(zclk->reg) & zclk->mask; - mult = 32 - (val >> __ffs(zclk->mask)); + unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * zclk->fixed_div); @@ -357,7 +353,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; - cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); + cpg_reg_modify(zclk->reg, zclk->mask, + field_prep(zclk->mask, 32 - mult)); /* * Set KICK bit in FRQCRB to update hardware setting and wait for diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index a9816b1beabb2582..30bbe8418e018153 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -54,10 +54,8 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); unsigned int mult; - u32 val; - val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; - mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; + mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1; return parent_rate * mult * pll_clk->fixed_mult; } @@ -94,7 +92,7 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, val = readl(pll_clk->pllcr_reg); val &= ~CPG_PLLnCR_STC_MASK; - val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); + val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1); writel(val, pll_clk->pllcr_reg); for (i = 1000; i; i--) { @@ -176,11 +174,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); - unsigned int mult; - u32 val; - - val = readl(zclk->reg) & zclk->mask; - mult = 32 - (val >> __ffs(zclk->mask)); + unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * zclk->fixed_div); @@ -231,7 +225,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; - cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); + cpg_reg_modify(zclk->reg, zclk->mask, + field_prep(zclk->mask, 32 - mult)); /* * Set KICK bit in FRQCRB to update hardware setting and wait for -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert+renesas@glider.be> To: Tony Lindgren <tony@atomide.com>, Russell King <linux@armlinux.org.uk>, Rajendra Nayak <rnayak@codeaurora.org>, Paul Walmsley <paul@pwsan.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Nicolas Ferre <nicolas.ferre@microchip.com>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Ludovic Desroches <ludovic.desroches@microchip.com>, Tero Kristo <kristo@kernel.org>, Jonathan Cameron <jic23@kernel.org>, Lars-Peter Clausen <lars@metafoo.de>, Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>, Benoit Parrot <bparrot@ti.com>, Mauro Carvalho Chehab <mchehab@kernel.org>, Adrian Hunter <adrian.hunter@intel.com>, Andrew Jeffery <andrew@aj.id.au>, Ulf Hansson <ulf.hansson@linaro.org>, Joel Stanley <joel@jms.id.au>, Ping-Ke Shih <pkshih@realtek.com>, Kalle Valo <kvalo@codeaurora.org>, "David S . Miller" <davem@davemloft.net>, Jakub Kicinski <kuba@kernel.org>, Linus Walleij <linus.walleij@linaro.org>, Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>, Magnus Damm <magnus.damm@gmail.com>, Eduardo Valentin <edubezval@gmail.com>, Keerthy <j-keerthy@ti.com>, "Rafael J . Wysocki" <rafael@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Amit Kucheria <amitk@kernel.org>, Zhang Rui <rui.zhang@intel.com>, Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com> Cc: alsa-devel@alsa-project.org, Geert Uytterhoeven <geert+renesas@glider.be>, linux-aspeed@lists.ozlabs.org, linux-pm@vger.kernel.org, linux-iio@vger.kernel.org, linux-wireless@vger.kernel.org, openbmc@lists.ozlabs.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Subject: [PATCH 02/17] clk: renesas: Use bitfield helpers Date: Mon, 22 Nov 2021 16:53:55 +0100 [thread overview] Message-ID: <c6e4bfbf798a8fcb4d8c02861a0c1b029f2f5cb1.1637592133.git.geert+renesas@glider.be> (raw) In-Reply-To: <cover.1637592133.git.geert+renesas@glider.be> Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const respective non-const bitfields, instead of open-coding the same operations. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- drivers/clk/renesas/clk-div6.c | 6 +++--- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 9 +++------ drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++++---------- 3 files changed, 11 insertions(+), 19 deletions(-) diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c index 3abd6e5400aded6a..f7b827b5e9b2dd32 100644 --- a/drivers/clk/renesas/clk-div6.c +++ b/drivers/clk/renesas/clk-div6.c @@ -7,6 +7,7 @@ * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> */ +#include <linux/bitfield.h> #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/io.h> @@ -171,8 +172,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) if (clock->src_mask == 0) return 0; - hw_index = (readl(clock->reg) & clock->src_mask) >> - __ffs(clock->src_mask); + hw_index = field_get(clock->src_mask, readl(clock->reg)); for (i = 0; i < clk_hw_get_num_parents(hw); i++) { if (clock->parents[i] == hw_index) return i; @@ -191,7 +191,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) if (index >= clk_hw_get_num_parents(hw)) return -EINVAL; - src = clock->parents[index] << __ffs(clock->src_mask); + src = field_prep(clock->src_mask, clock->parents[index]); writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); return 0; } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 7df86743c5491292..f716e739d138b722 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -302,11 +302,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); - unsigned int mult; - u32 val; - - val = readl(zclk->reg) & zclk->mask; - mult = 32 - (val >> __ffs(zclk->mask)); + unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * zclk->fixed_div); @@ -357,7 +353,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; - cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); + cpg_reg_modify(zclk->reg, zclk->mask, + field_prep(zclk->mask, 32 - mult)); /* * Set KICK bit in FRQCRB to update hardware setting and wait for diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index a9816b1beabb2582..30bbe8418e018153 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -54,10 +54,8 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); unsigned int mult; - u32 val; - val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; - mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; + mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1; return parent_rate * mult * pll_clk->fixed_mult; } @@ -94,7 +92,7 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, val = readl(pll_clk->pllcr_reg); val &= ~CPG_PLLnCR_STC_MASK; - val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); + val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1); writel(val, pll_clk->pllcr_reg); for (i = 1000; i; i--) { @@ -176,11 +174,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); - unsigned int mult; - u32 val; - - val = readl(zclk->reg) & zclk->mask; - mult = 32 - (val >> __ffs(zclk->mask)); + unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * zclk->fixed_div); @@ -231,7 +225,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; - cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); + cpg_reg_modify(zclk->reg, zclk->mask, + field_prep(zclk->mask, 32 - mult)); /* * Set KICK bit in FRQCRB to update hardware setting and wait for -- 2.25.1
next prev parent reply other threads:[~2021-11-22 15:57 UTC|newest] Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-22 15:53 [PATCH 00/17] Non-const bitfield helper conversions Geert Uytterhoeven 2021-11-22 15:53 ` Geert Uytterhoeven 2021-11-22 15:53 ` [PATCH 01/17] bitfield: Add non-constant field_{prep,get}() helpers Geert Uytterhoeven 2021-11-22 15:53 ` Geert Uytterhoeven 2021-11-22 16:32 ` Johannes Berg 2021-11-22 16:32 ` Johannes Berg 2021-11-23 1:17 ` Jakub Kicinski 2021-11-23 1:17 ` Jakub Kicinski 2021-11-23 8:36 ` Geert Uytterhoeven 2021-11-23 8:36 ` [PATCH 01/17] bitfield: Add non-constant field_{prep, get}() helpers Geert Uytterhoeven 2021-11-23 16:24 ` [PATCH 01/17] bitfield: Add non-constant field_{prep,get}() helpers Johannes Berg 2021-11-23 16:24 ` Johannes Berg 2021-11-23 23:49 ` Jakub Kicinski 2021-11-23 23:49 ` Jakub Kicinski 2021-11-24 8:03 ` Johannes Berg 2021-11-24 13:59 ` Jakub Kicinski 2021-11-24 14:07 ` Johannes Berg 2021-11-23 23:39 ` Jakub Kicinski 2021-11-23 23:39 ` Jakub Kicinski 2021-11-23 1:52 ` Alex Elder 2021-11-23 1:52 ` Alex Elder 2021-11-23 8:38 ` Geert Uytterhoeven 2021-11-23 8:38 ` [PATCH 01/17] bitfield: Add non-constant field_{prep, get}() helpers Geert Uytterhoeven 2021-11-23 8:30 ` [PATCH 01/17] bitfield: Add non-constant field_{prep,get}() helpers Geert Uytterhoeven 2021-11-23 8:30 ` [PATCH 01/17] bitfield: Add non-constant field_{prep, get}() helpers Geert Uytterhoeven 2021-11-23 16:21 ` [PATCH 01/17] bitfield: Add non-constant field_{prep,get}() helpers Johannes Berg 2021-11-23 16:21 ` Johannes Berg 2021-11-23 16:31 ` Geert Uytterhoeven 2021-11-23 16:31 ` [PATCH 01/17] bitfield: Add non-constant field_{prep, get}() helpers Geert Uytterhoeven 2021-11-24 8:24 ` [PATCH 01/17] bitfield: Add non-constant field_{prep,get}() helpers Kalle Valo 2021-11-22 15:53 ` Geert Uytterhoeven [this message] 2021-11-22 15:53 ` [PATCH 02/17] clk: renesas: Use bitfield helpers Geert Uytterhoeven 2021-11-22 15:53 ` [PATCH/RFC 03/17] soc: " Geert Uytterhoeven 2021-11-22 15:53 ` Geert Uytterhoeven 2021-11-22 15:53 ` [PATCH/RFC 04/17] ARM: OMAP2+: " Geert Uytterhoeven 2021-11-22 15:53 ` Geert Uytterhoeven 2021-11-22 15:53 ` [PATCH/RFC 05/17] bus: omap_l3_noc: " Geert Uytterhoeven 2021-11-22 15:53 ` Geert Uytterhoeven 2021-11-22 15:53 ` [PATCH/RFC 06/17] clk: ti: " Geert Uytterhoeven 2021-11-22 15:53 ` Geert Uytterhoeven 2021-11-22 15:54 ` [PATCH/RFC 07/17] iio: st_sensors: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-23 23:35 ` Linus Walleij 2021-11-23 23:35 ` Linus Walleij 2021-11-22 15:54 ` [PATCH/RFC 08/17] iio: humidity: hts221: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-24 15:21 ` Jonathan Cameron 2021-11-22 15:54 ` [PATCH/RFC 09/17] iio: imu: st_lsm6dsx: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-22 15:54 ` [PATCH/RFC 10/17] media: ti-vpe: cal: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-22 15:54 ` [PATCH/RFC 11/17] mmc: sdhci-of-aspeed: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-22 15:54 ` [PATCH/RFC 12/17] pinctrl: aspeed: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-22 15:54 ` [PATCH/RFC 13/17] pinctl: ti: iodelay: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-22 17:52 ` Alexandre Belloni 2021-11-22 17:52 ` Alexandre Belloni 2021-11-22 15:54 ` [PATCH/RFC 14/17] regulator: ti-abb: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-22 16:31 ` Mark Brown 2021-11-22 16:31 ` Mark Brown 2021-11-22 15:54 ` [PATCH/RFC 15/17] thermal/ti-soc-thermal: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-22 15:54 ` [PATCH/RFC 16/17] ALSA: ice1724: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-23 11:24 ` Takashi Iwai 2021-11-23 11:24 ` Takashi Iwai 2021-11-22 15:54 ` [PATCH/RFC 17/17] rtw89: " Geert Uytterhoeven 2021-11-22 15:54 ` Geert Uytterhoeven 2021-11-22 18:38 ` Larry Finger 2021-11-22 18:38 ` Larry Finger 2021-11-22 17:50 ` [PATCH 00/17] Non-const bitfield helper conversions Alexandre Belloni 2021-11-22 17:50 ` Alexandre Belloni 2021-11-23 8:20 ` Geert Uytterhoeven 2021-11-23 8:20 ` Geert Uytterhoeven
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