* [PATCH v2 00/27] drm/msm/dpu: wide planes support
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
It took me a way longer to finish than I expected. And more patches that
I previously hoped (despite having several patches already being merged
from v1).
This patchset brings in multirect usage to support using two SSPP
rectangles for a single plane. Full virtual planes support is omitted
from this pull request, it will come later.
Abhinav, could you please pick up patch 1 for the -fixes? Otherwise QoS
is not programmed correcly.
Changes since v1 (which was ages ago):
- Rebased on top of 6.2-rc1
- Dropped the controversial _dpu_crtc_blend_setup() split patch
- Renamed dpu_hw_pipe to dpu_hw_sspp
- Other misc changes
Dmitry Baryshkov (27):
drm/msm/dpu: set pdpu->is_rt_pipe early in
dpu_plane_sspp_atomic_update()
drm/msm/dpu: rename struct dpu_hw_pipe to dpu_hw_sspp
drm/msm/dpu: move SSPP allocation to the RM
drm/msm/dpu: move SSPP debugfs creation to dpu_kms.c
drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
drm/msm/dpu: move pipe_hw to dpu_plane_state
drm/msm/dpu: drop dpu_plane_pipe function
drm/msm/dpu: introduce struct dpu_sw_pipe
drm/msm/dpu: use dpu_sw_pipe for dpu_hw_sspp callbacks
drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
drm/msm/dpu: move stride programming to
dpu_hw_sspp_setup_sourceaddress
drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
drm/msm/dpu: drop src_split and multirect check from
dpu_crtc_atomic_check
drm/msm/dpu: don't use unsupported blend stages
drm/msm/dpu: move the rest of plane checks to dpu_plane_atomic_check()
drm/msm/dpu: drop redundant plane dst check from
dpu_crtc_atomic_check()
drm/msm/dpu: add dpu_hw_pipe_cfg to dpu_plane_state
drm/msm/dpu: simplify dpu_plane_validate_src()
drm/msm/dpu: rewrite plane's QoS-related functions to take dpu_sw_pipe
and dpu_format
drm/msm/dpu: populate SmartDMA features in hw catalog
drm/msm/dpu: make _dpu_plane_calc_clk accept mode directly
drm/msm/dpu: rework dpu_plane_sspp_atomic_update()
drm/msm/dpu: rework dpu_plane_atomic_check()
drm/msm/dpu: rework plane CSC setting
drm/msm/dpu: rework static color fill code
drm/msm/dpu: split pipe handling from _dpu_crtc_blend_setup_mixer
drm/msm/dpu: add support for wide planes
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 283 ++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 163 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 104 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 +
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 735 ++++++++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 20 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 +
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 25 +-
11 files changed, 685 insertions(+), 717 deletions(-)
--
2.39.0
^ permalink raw reply [flat|nested] 110+ messages in thread* [PATCH v2 01/27] drm/msm/dpu: set pdpu->is_rt_pipe early in dpu_plane_sspp_atomic_update()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
The function dpu_plane_sspp_atomic_update() updates pdpu->is_rt_pipe
flag, but after the commit 854f6f1c653b ("drm/msm/dpu: update the qos
remap only if the client type changes") it sets the flag late, after all
the qos functions have updated QoS programming. Move the flag update
back to the place where it happended before the mentioned commit to let
the pipe be programmed according to its current RT/non-RT state.
Fixes: 854f6f1c653b ("drm/msm/dpu: update the qos remap only if the client type changes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 86719020afe2..bfd5be89e8b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1126,7 +1126,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
- bool is_rt_pipe, update_qos_remap;
+ bool is_rt_pipe;
const struct dpu_format *fmt =
to_dpu_format(msm_framebuffer_format(fb));
struct dpu_hw_pipe_cfg pipe_cfg;
@@ -1138,6 +1138,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
pstate->pending = true;
is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
+ pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
+ pdpu->is_rt_pipe = is_rt_pipe;
+
_dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
@@ -1219,14 +1222,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
_dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
}
- update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) ||
- pstate->needs_qos_remap;
-
- if (update_qos_remap) {
- if (is_rt_pipe != pdpu->is_rt_pipe)
- pdpu->is_rt_pipe = is_rt_pipe;
- else if (pstate->needs_qos_remap)
- pstate->needs_qos_remap = false;
+ if (pstate->needs_qos_remap) {
+ pstate->needs_qos_remap = false;
_dpu_plane_set_qos_remap(plane);
}
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 01/27] drm/msm/dpu: set pdpu->is_rt_pipe early in dpu_plane_sspp_atomic_update()
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
The function dpu_plane_sspp_atomic_update() updates pdpu->is_rt_pipe
flag, but after the commit 854f6f1c653b ("drm/msm/dpu: update the qos
remap only if the client type changes") it sets the flag late, after all
the qos functions have updated QoS programming. Move the flag update
back to the place where it happended before the mentioned commit to let
the pipe be programmed according to its current RT/non-RT state.
Fixes: 854f6f1c653b ("drm/msm/dpu: update the qos remap only if the client type changes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 86719020afe2..bfd5be89e8b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1126,7 +1126,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
- bool is_rt_pipe, update_qos_remap;
+ bool is_rt_pipe;
const struct dpu_format *fmt =
to_dpu_format(msm_framebuffer_format(fb));
struct dpu_hw_pipe_cfg pipe_cfg;
@@ -1138,6 +1138,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
pstate->pending = true;
is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
+ pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
+ pdpu->is_rt_pipe = is_rt_pipe;
+
_dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
@@ -1219,14 +1222,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
_dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
}
- update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) ||
- pstate->needs_qos_remap;
-
- if (update_qos_remap) {
- if (is_rt_pipe != pdpu->is_rt_pipe)
- pdpu->is_rt_pipe = is_rt_pipe;
- else if (pstate->needs_qos_remap)
- pstate->needs_qos_remap = false;
+ if (pstate->needs_qos_remap) {
+ pstate->needs_qos_remap = false;
_dpu_plane_set_qos_remap(plane);
}
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [PATCH v2 01/27] drm/msm/dpu: set pdpu->is_rt_pipe early in dpu_plane_sspp_atomic_update()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2023-01-26 19:26 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-26 19:26 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> The function dpu_plane_sspp_atomic_update() updates pdpu->is_rt_pipe
> flag, but after the commit 854f6f1c653b ("drm/msm/dpu: update the qos
> remap only if the client type changes") it sets the flag late, after all
> the qos functions have updated QoS programming. Move the flag update
> back to the place where it happended before the mentioned commit to let
happended ---> happened
> the pipe be programmed according to its current RT/non-RT state.
>
> Fixes: 854f6f1c653b ("drm/msm/dpu: update the qos remap only if the client type changes")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
With that nit fixed,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Looks much cleaner now, thanks !
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 86719020afe2..bfd5be89e8b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -1126,7 +1126,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> struct drm_crtc *crtc = state->crtc;
> struct drm_framebuffer *fb = state->fb;
> - bool is_rt_pipe, update_qos_remap;
> + bool is_rt_pipe;
> const struct dpu_format *fmt =
> to_dpu_format(msm_framebuffer_format(fb));
> struct dpu_hw_pipe_cfg pipe_cfg;
> @@ -1138,6 +1138,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> pstate->pending = true;
>
> is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
> + pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
> + pdpu->is_rt_pipe = is_rt_pipe;
> +
> _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
>
> DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
> @@ -1219,14 +1222,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
> }
>
> - update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) ||
> - pstate->needs_qos_remap;
> -
> - if (update_qos_remap) {
> - if (is_rt_pipe != pdpu->is_rt_pipe)
> - pdpu->is_rt_pipe = is_rt_pipe;
> - else if (pstate->needs_qos_remap)
> - pstate->needs_qos_remap = false;
> + if (pstate->needs_qos_remap) {
> + pstate->needs_qos_remap = false;
> _dpu_plane_set_qos_remap(plane);
> }
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 01/27] drm/msm/dpu: set pdpu->is_rt_pipe early in dpu_plane_sspp_atomic_update()
@ 2023-01-26 19:26 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-26 19:26 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> The function dpu_plane_sspp_atomic_update() updates pdpu->is_rt_pipe
> flag, but after the commit 854f6f1c653b ("drm/msm/dpu: update the qos
> remap only if the client type changes") it sets the flag late, after all
> the qos functions have updated QoS programming. Move the flag update
> back to the place where it happended before the mentioned commit to let
happended ---> happened
> the pipe be programmed according to its current RT/non-RT state.
>
> Fixes: 854f6f1c653b ("drm/msm/dpu: update the qos remap only if the client type changes")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
With that nit fixed,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Looks much cleaner now, thanks !
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 86719020afe2..bfd5be89e8b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -1126,7 +1126,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> struct drm_crtc *crtc = state->crtc;
> struct drm_framebuffer *fb = state->fb;
> - bool is_rt_pipe, update_qos_remap;
> + bool is_rt_pipe;
> const struct dpu_format *fmt =
> to_dpu_format(msm_framebuffer_format(fb));
> struct dpu_hw_pipe_cfg pipe_cfg;
> @@ -1138,6 +1138,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> pstate->pending = true;
>
> is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
> + pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
> + pdpu->is_rt_pipe = is_rt_pipe;
> +
> _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
>
> DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
> @@ -1219,14 +1222,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
> }
>
> - update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) ||
> - pstate->needs_qos_remap;
> -
> - if (update_qos_remap) {
> - if (is_rt_pipe != pdpu->is_rt_pipe)
> - pdpu->is_rt_pipe = is_rt_pipe;
> - else if (pstate->needs_qos_remap)
> - pstate->needs_qos_remap = false;
> + if (pstate->needs_qos_remap) {
> + pstate->needs_qos_remap = false;
> _dpu_plane_set_qos_remap(plane);
> }
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 02/27] drm/msm/dpu: rename struct dpu_hw_pipe to dpu_hw_sspp
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
For all hardware blocks except SSPP the corresponding struct is named
after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 42 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 42 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
3 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 691c471b08c2..93f01f767fd8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -136,7 +136,7 @@
#define TS_CLK 19200000
-static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
+static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
int s_id,
u32 *idx)
{
@@ -168,7 +168,7 @@ static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
return rc;
}
-static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
enum dpu_sspp_multirect_index index,
enum dpu_sspp_multirect_mode mode)
{
@@ -197,7 +197,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
}
-static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
+static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en)
{
u32 idx;
@@ -218,7 +218,7 @@ static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
}
-static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
+static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en)
{
u32 idx;
@@ -239,7 +239,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
/*
* Setup source pixel format, flip,
*/
-static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
const struct dpu_format *fmt, u32 flags,
enum dpu_sspp_multirect_index rect_mode)
{
@@ -356,7 +356,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
}
-static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
struct dpu_hw_pixel_ext *pe_ext)
{
struct dpu_hw_blk_reg_map *c;
@@ -414,7 +414,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
tot_req_pixels[3]);
}
-static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
+static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *sspp,
void *scaler_cfg)
{
@@ -430,7 +430,7 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
sspp->layout.format);
}
-static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
+static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
{
u32 idx;
@@ -443,7 +443,7 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
/*
* dpu_hw_sspp_setup_rects()
*/
-static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *cfg,
enum dpu_sspp_multirect_index rect_index)
{
@@ -512,7 +512,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
-static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *cfg,
enum dpu_sspp_multirect_index rect_mode)
{
@@ -539,7 +539,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
}
}
-static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
const struct dpu_csc_cfg *data)
{
u32 idx;
@@ -556,7 +556,7 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
}
-static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
+static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32 color, enum
dpu_sspp_multirect_index rect_index)
{
u32 idx;
@@ -571,7 +571,7 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
color);
}
-static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx,
u32 danger_lut,
u32 safe_lut)
{
@@ -584,7 +584,7 @@ static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
}
-static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,
u64 creq_lut)
{
u32 idx;
@@ -601,7 +601,7 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
}
}
-static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_qos_cfg *cfg)
{
u32 idx;
@@ -626,7 +626,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
}
-static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
struct dpu_hw_cdp_cfg *cfg,
enum dpu_sspp_multirect_index index)
{
@@ -657,7 +657,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
}
-static void _setup_layer_ops(struct dpu_hw_pipe *c,
+static void _setup_layer_ops(struct dpu_hw_sspp *c,
unsigned long features)
{
if (test_bit(DPU_SSPP_SRC, &features)) {
@@ -695,7 +695,7 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
}
#ifdef CONFIG_DEBUG_FS
-int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
+int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
{
const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
@@ -779,10 +779,10 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
return ERR_PTR(-ENOMEM);
}
-struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
+struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
void __iomem *addr, const struct dpu_mdss_cfg *catalog)
{
- struct dpu_hw_pipe *hw_pipe;
+ struct dpu_hw_sspp *hw_pipe;
const struct dpu_sspp_cfg *cfg;
if (!addr || !catalog)
@@ -808,7 +808,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
return hw_pipe;
}
-void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
+void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx)
{
kfree(ctx);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 0c95b7e64f6c..651621b9794f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -10,7 +10,7 @@
#include "dpu_hw_util.h"
#include "dpu_formats.h"
-struct dpu_hw_pipe;
+struct dpu_hw_sspp;
/**
* Flags
@@ -214,7 +214,7 @@ struct dpu_hw_sspp_ops {
* @flags: Extra flags for format config
* @index: rectangle index in multirect
*/
- void (*setup_format)(struct dpu_hw_pipe *ctx,
+ void (*setup_format)(struct dpu_hw_sspp *ctx,
const struct dpu_format *fmt, u32 flags,
enum dpu_sspp_multirect_index index);
@@ -224,7 +224,7 @@ struct dpu_hw_sspp_ops {
* @cfg: Pointer to pipe config structure
* @index: rectangle index in multirect
*/
- void (*setup_rects)(struct dpu_hw_pipe *ctx,
+ void (*setup_rects)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *cfg,
enum dpu_sspp_multirect_index index);
@@ -233,7 +233,7 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @pe_ext: Pointer to pixel ext settings
*/
- void (*setup_pe)(struct dpu_hw_pipe *ctx,
+ void (*setup_pe)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pixel_ext *pe_ext);
/**
@@ -242,7 +242,7 @@ struct dpu_hw_sspp_ops {
* @cfg: Pointer to pipe config structure
* @index: rectangle index in multirect
*/
- void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
+ void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *cfg,
enum dpu_sspp_multirect_index index);
@@ -251,7 +251,7 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @data: Pointer to config structure
*/
- void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data);
+ void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data);
/**
* setup_solidfill - enable/disable colorfill
@@ -260,7 +260,7 @@ struct dpu_hw_sspp_ops {
* @flags: Pipe flags
* @index: rectangle index in multirect
*/
- void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
+ void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color,
enum dpu_sspp_multirect_index index);
/**
@@ -270,7 +270,7 @@ struct dpu_hw_sspp_ops {
* @mode: parallel fetch / time multiplex multirect mode
*/
- void (*setup_multirect)(struct dpu_hw_pipe *ctx,
+ void (*setup_multirect)(struct dpu_hw_sspp *ctx,
enum dpu_sspp_multirect_index index,
enum dpu_sspp_multirect_mode mode);
@@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @cfg: Pointer to config structure
*/
- void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
+ void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
struct dpu_hw_sharp_cfg *cfg);
/**
@@ -289,7 +289,7 @@ struct dpu_hw_sspp_ops {
* @safe_lut: LUT for generate safe level based on fill level
*
*/
- void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
+ void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx,
u32 danger_lut,
u32 safe_lut);
@@ -299,7 +299,7 @@ struct dpu_hw_sspp_ops {
* @creq_lut: LUT for generate creq level based on fill level
*
*/
- void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
+ void (*setup_creq_lut)(struct dpu_hw_sspp *ctx,
u64 creq_lut);
/**
@@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops {
* @cfg: Pointer to pipe QoS configuration
*
*/
- void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
+ void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_qos_cfg *cfg);
/**
@@ -316,7 +316,7 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @cfg: Pointer to histogram configuration
*/
- void (*setup_histogram)(struct dpu_hw_pipe *ctx,
+ void (*setup_histogram)(struct dpu_hw_sspp *ctx,
void *cfg);
/**
@@ -325,7 +325,7 @@ struct dpu_hw_sspp_ops {
* @pipe_cfg: Pointer to pipe configuration
* @scaler_cfg: Pointer to scaler configuration
*/
- void (*setup_scaler)(struct dpu_hw_pipe *ctx,
+ void (*setup_scaler)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *pipe_cfg,
void *scaler_cfg);
@@ -333,7 +333,7 @@ struct dpu_hw_sspp_ops {
* get_scaler_ver - get scaler h/w version
* @ctx: Pointer to pipe context
*/
- u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
+ u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx);
/**
* setup_cdp - setup client driven prefetch
@@ -341,13 +341,13 @@ struct dpu_hw_sspp_ops {
* @cfg: Pointer to cdp configuration
* @index: rectangle index in multirect
*/
- void (*setup_cdp)(struct dpu_hw_pipe *ctx,
+ void (*setup_cdp)(struct dpu_hw_sspp *ctx,
struct dpu_hw_cdp_cfg *cfg,
enum dpu_sspp_multirect_index index);
};
/**
- * struct dpu_hw_pipe - pipe description
+ * struct dpu_hw_sspp - pipe description
* @base: hardware block base structure
* @hw: block hardware details
* @catalog: back pointer to catalog
@@ -356,7 +356,7 @@ struct dpu_hw_sspp_ops {
* @cap: pointer to layer_cfg
* @ops: pointer to operations possible for this pipe
*/
-struct dpu_hw_pipe {
+struct dpu_hw_sspp {
struct dpu_hw_blk base;
struct dpu_hw_blk_reg_map hw;
const struct dpu_mdss_cfg *catalog;
@@ -378,7 +378,7 @@ struct dpu_kms;
* @addr: Mapped register io address of MDP
* @catalog : Pointer to mdss catalog data
*/
-struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
+struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
void __iomem *addr, const struct dpu_mdss_cfg *catalog);
/**
@@ -386,10 +386,10 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
* should be called during Hw pipe cleanup.
* @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
*/
-void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
+void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);
-int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
+int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
#endif /*_DPU_HW_SSPP_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index bfd5be89e8b8..e1cdd71716f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -104,7 +104,7 @@ struct dpu_plane {
enum dpu_sspp pipe;
- struct dpu_hw_pipe *pipe_hw;
+ struct dpu_hw_sspp *pipe_hw;
uint32_t color_fill;
bool is_error;
bool is_rt_pipe;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 02/27] drm/msm/dpu: rename struct dpu_hw_pipe to dpu_hw_sspp
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
For all hardware blocks except SSPP the corresponding struct is named
after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 42 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 42 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
3 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 691c471b08c2..93f01f767fd8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -136,7 +136,7 @@
#define TS_CLK 19200000
-static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
+static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
int s_id,
u32 *idx)
{
@@ -168,7 +168,7 @@ static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
return rc;
}
-static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
enum dpu_sspp_multirect_index index,
enum dpu_sspp_multirect_mode mode)
{
@@ -197,7 +197,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
}
-static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
+static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en)
{
u32 idx;
@@ -218,7 +218,7 @@ static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
}
-static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
+static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en)
{
u32 idx;
@@ -239,7 +239,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
/*
* Setup source pixel format, flip,
*/
-static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
const struct dpu_format *fmt, u32 flags,
enum dpu_sspp_multirect_index rect_mode)
{
@@ -356,7 +356,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
}
-static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
struct dpu_hw_pixel_ext *pe_ext)
{
struct dpu_hw_blk_reg_map *c;
@@ -414,7 +414,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
tot_req_pixels[3]);
}
-static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
+static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *sspp,
void *scaler_cfg)
{
@@ -430,7 +430,7 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
sspp->layout.format);
}
-static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
+static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
{
u32 idx;
@@ -443,7 +443,7 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
/*
* dpu_hw_sspp_setup_rects()
*/
-static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *cfg,
enum dpu_sspp_multirect_index rect_index)
{
@@ -512,7 +512,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
-static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *cfg,
enum dpu_sspp_multirect_index rect_mode)
{
@@ -539,7 +539,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
}
}
-static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
const struct dpu_csc_cfg *data)
{
u32 idx;
@@ -556,7 +556,7 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
}
-static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
+static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32 color, enum
dpu_sspp_multirect_index rect_index)
{
u32 idx;
@@ -571,7 +571,7 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
color);
}
-static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx,
u32 danger_lut,
u32 safe_lut)
{
@@ -584,7 +584,7 @@ static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
}
-static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,
u64 creq_lut)
{
u32 idx;
@@ -601,7 +601,7 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
}
}
-static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_qos_cfg *cfg)
{
u32 idx;
@@ -626,7 +626,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
}
-static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
+static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
struct dpu_hw_cdp_cfg *cfg,
enum dpu_sspp_multirect_index index)
{
@@ -657,7 +657,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
}
-static void _setup_layer_ops(struct dpu_hw_pipe *c,
+static void _setup_layer_ops(struct dpu_hw_sspp *c,
unsigned long features)
{
if (test_bit(DPU_SSPP_SRC, &features)) {
@@ -695,7 +695,7 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
}
#ifdef CONFIG_DEBUG_FS
-int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
+int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
{
const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
@@ -779,10 +779,10 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
return ERR_PTR(-ENOMEM);
}
-struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
+struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
void __iomem *addr, const struct dpu_mdss_cfg *catalog)
{
- struct dpu_hw_pipe *hw_pipe;
+ struct dpu_hw_sspp *hw_pipe;
const struct dpu_sspp_cfg *cfg;
if (!addr || !catalog)
@@ -808,7 +808,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
return hw_pipe;
}
-void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
+void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx)
{
kfree(ctx);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 0c95b7e64f6c..651621b9794f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -10,7 +10,7 @@
#include "dpu_hw_util.h"
#include "dpu_formats.h"
-struct dpu_hw_pipe;
+struct dpu_hw_sspp;
/**
* Flags
@@ -214,7 +214,7 @@ struct dpu_hw_sspp_ops {
* @flags: Extra flags for format config
* @index: rectangle index in multirect
*/
- void (*setup_format)(struct dpu_hw_pipe *ctx,
+ void (*setup_format)(struct dpu_hw_sspp *ctx,
const struct dpu_format *fmt, u32 flags,
enum dpu_sspp_multirect_index index);
@@ -224,7 +224,7 @@ struct dpu_hw_sspp_ops {
* @cfg: Pointer to pipe config structure
* @index: rectangle index in multirect
*/
- void (*setup_rects)(struct dpu_hw_pipe *ctx,
+ void (*setup_rects)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *cfg,
enum dpu_sspp_multirect_index index);
@@ -233,7 +233,7 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @pe_ext: Pointer to pixel ext settings
*/
- void (*setup_pe)(struct dpu_hw_pipe *ctx,
+ void (*setup_pe)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pixel_ext *pe_ext);
/**
@@ -242,7 +242,7 @@ struct dpu_hw_sspp_ops {
* @cfg: Pointer to pipe config structure
* @index: rectangle index in multirect
*/
- void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
+ void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *cfg,
enum dpu_sspp_multirect_index index);
@@ -251,7 +251,7 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @data: Pointer to config structure
*/
- void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data);
+ void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data);
/**
* setup_solidfill - enable/disable colorfill
@@ -260,7 +260,7 @@ struct dpu_hw_sspp_ops {
* @flags: Pipe flags
* @index: rectangle index in multirect
*/
- void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
+ void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color,
enum dpu_sspp_multirect_index index);
/**
@@ -270,7 +270,7 @@ struct dpu_hw_sspp_ops {
* @mode: parallel fetch / time multiplex multirect mode
*/
- void (*setup_multirect)(struct dpu_hw_pipe *ctx,
+ void (*setup_multirect)(struct dpu_hw_sspp *ctx,
enum dpu_sspp_multirect_index index,
enum dpu_sspp_multirect_mode mode);
@@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @cfg: Pointer to config structure
*/
- void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
+ void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
struct dpu_hw_sharp_cfg *cfg);
/**
@@ -289,7 +289,7 @@ struct dpu_hw_sspp_ops {
* @safe_lut: LUT for generate safe level based on fill level
*
*/
- void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
+ void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx,
u32 danger_lut,
u32 safe_lut);
@@ -299,7 +299,7 @@ struct dpu_hw_sspp_ops {
* @creq_lut: LUT for generate creq level based on fill level
*
*/
- void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
+ void (*setup_creq_lut)(struct dpu_hw_sspp *ctx,
u64 creq_lut);
/**
@@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops {
* @cfg: Pointer to pipe QoS configuration
*
*/
- void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
+ void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_qos_cfg *cfg);
/**
@@ -316,7 +316,7 @@ struct dpu_hw_sspp_ops {
* @ctx: Pointer to pipe context
* @cfg: Pointer to histogram configuration
*/
- void (*setup_histogram)(struct dpu_hw_pipe *ctx,
+ void (*setup_histogram)(struct dpu_hw_sspp *ctx,
void *cfg);
/**
@@ -325,7 +325,7 @@ struct dpu_hw_sspp_ops {
* @pipe_cfg: Pointer to pipe configuration
* @scaler_cfg: Pointer to scaler configuration
*/
- void (*setup_scaler)(struct dpu_hw_pipe *ctx,
+ void (*setup_scaler)(struct dpu_hw_sspp *ctx,
struct dpu_hw_pipe_cfg *pipe_cfg,
void *scaler_cfg);
@@ -333,7 +333,7 @@ struct dpu_hw_sspp_ops {
* get_scaler_ver - get scaler h/w version
* @ctx: Pointer to pipe context
*/
- u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
+ u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx);
/**
* setup_cdp - setup client driven prefetch
@@ -341,13 +341,13 @@ struct dpu_hw_sspp_ops {
* @cfg: Pointer to cdp configuration
* @index: rectangle index in multirect
*/
- void (*setup_cdp)(struct dpu_hw_pipe *ctx,
+ void (*setup_cdp)(struct dpu_hw_sspp *ctx,
struct dpu_hw_cdp_cfg *cfg,
enum dpu_sspp_multirect_index index);
};
/**
- * struct dpu_hw_pipe - pipe description
+ * struct dpu_hw_sspp - pipe description
* @base: hardware block base structure
* @hw: block hardware details
* @catalog: back pointer to catalog
@@ -356,7 +356,7 @@ struct dpu_hw_sspp_ops {
* @cap: pointer to layer_cfg
* @ops: pointer to operations possible for this pipe
*/
-struct dpu_hw_pipe {
+struct dpu_hw_sspp {
struct dpu_hw_blk base;
struct dpu_hw_blk_reg_map hw;
const struct dpu_mdss_cfg *catalog;
@@ -378,7 +378,7 @@ struct dpu_kms;
* @addr: Mapped register io address of MDP
* @catalog : Pointer to mdss catalog data
*/
-struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
+struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
void __iomem *addr, const struct dpu_mdss_cfg *catalog);
/**
@@ -386,10 +386,10 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
* should be called during Hw pipe cleanup.
* @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
*/
-void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
+void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);
-int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
+int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
#endif /*_DPU_HW_SSPP_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index bfd5be89e8b8..e1cdd71716f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -104,7 +104,7 @@ struct dpu_plane {
enum dpu_sspp pipe;
- struct dpu_hw_pipe *pipe_hw;
+ struct dpu_hw_sspp *pipe_hw;
uint32_t color_fill;
bool is_error;
bool is_rt_pipe;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [PATCH v2 02/27] drm/msm/dpu: rename struct dpu_hw_pipe to dpu_hw_sspp
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2023-01-26 22:55 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-26 22:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> For all hardware blocks except SSPP the corresponding struct is named
> after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Idea seems okay but then we should also rename dpu_hw_pipe_cfg to
dpu_hw_sspp_cfg.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 42 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 42 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
> 3 files changed, 43 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 691c471b08c2..93f01f767fd8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -136,7 +136,7 @@
> #define TS_CLK 19200000
>
>
> -static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
> +static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
> int s_id,
> u32 *idx)
> {
> @@ -168,7 +168,7 @@ static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
> return rc;
> }
>
> -static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
> enum dpu_sspp_multirect_index index,
> enum dpu_sspp_multirect_mode mode)
> {
> @@ -197,7 +197,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
> }
>
> -static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
> +static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
> u32 mask, u8 en)
> {
> u32 idx;
> @@ -218,7 +218,7 @@ static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
> }
>
> -static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
> +static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
> u32 mask, u8 en)
> {
> u32 idx;
> @@ -239,7 +239,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
> /*
> * Setup source pixel format, flip,
> */
> -static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
> const struct dpu_format *fmt, u32 flags,
> enum dpu_sspp_multirect_index rect_mode)
> {
> @@ -356,7 +356,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
> }
>
> -static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pixel_ext *pe_ext)
> {
> struct dpu_hw_blk_reg_map *c;
> @@ -414,7 +414,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
> tot_req_pixels[3]);
> }
>
> -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
> +static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *sspp,
> void *scaler_cfg)
> {
> @@ -430,7 +430,7 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
> sspp->layout.format);
> }
>
> -static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
> +static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
> {
> u32 idx;
>
> @@ -443,7 +443,7 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
> /*
> * dpu_hw_sspp_setup_rects()
> */
> -static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *cfg,
> enum dpu_sspp_multirect_index rect_index)
> {
> @@ -512,7 +512,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> }
>
> -static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *cfg,
> enum dpu_sspp_multirect_index rect_mode)
> {
> @@ -539,7 +539,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
> }
> }
>
> -static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
> const struct dpu_csc_cfg *data)
> {
> u32 idx;
> @@ -556,7 +556,7 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
> dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
> }
>
> -static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
> +static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32 color, enum
> dpu_sspp_multirect_index rect_index)
> {
> u32 idx;
> @@ -571,7 +571,7 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
> color);
> }
>
> -static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx,
> u32 danger_lut,
> u32 safe_lut)
> {
> @@ -584,7 +584,7 @@ static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
> }
>
> -static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,
> u64 creq_lut)
> {
> u32 idx;
> @@ -601,7 +601,7 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
> }
> }
>
> -static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_qos_cfg *cfg)
> {
> u32 idx;
> @@ -626,7 +626,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
> }
>
> -static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
> struct dpu_hw_cdp_cfg *cfg,
> enum dpu_sspp_multirect_index index)
> {
> @@ -657,7 +657,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
> }
>
> -static void _setup_layer_ops(struct dpu_hw_pipe *c,
> +static void _setup_layer_ops(struct dpu_hw_sspp *c,
> unsigned long features)
> {
> if (test_bit(DPU_SSPP_SRC, &features)) {
> @@ -695,7 +695,7 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
> }
>
> #ifdef CONFIG_DEBUG_FS
> -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
> +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
> {
> const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
> const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
> @@ -779,10 +779,10 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
> return ERR_PTR(-ENOMEM);
> }
>
> -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
> +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
> void __iomem *addr, const struct dpu_mdss_cfg *catalog)
> {
> - struct dpu_hw_pipe *hw_pipe;
> + struct dpu_hw_sspp *hw_pipe;
> const struct dpu_sspp_cfg *cfg;
>
> if (!addr || !catalog)
> @@ -808,7 +808,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
> return hw_pipe;
> }
>
> -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
> +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx)
> {
> kfree(ctx);
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index 0c95b7e64f6c..651621b9794f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -10,7 +10,7 @@
> #include "dpu_hw_util.h"
> #include "dpu_formats.h"
>
> -struct dpu_hw_pipe;
> +struct dpu_hw_sspp;
>
> /**
> * Flags
> @@ -214,7 +214,7 @@ struct dpu_hw_sspp_ops {
> * @flags: Extra flags for format config
> * @index: rectangle index in multirect
> */
> - void (*setup_format)(struct dpu_hw_pipe *ctx,
> + void (*setup_format)(struct dpu_hw_sspp *ctx,
> const struct dpu_format *fmt, u32 flags,
> enum dpu_sspp_multirect_index index);
>
> @@ -224,7 +224,7 @@ struct dpu_hw_sspp_ops {
> * @cfg: Pointer to pipe config structure
> * @index: rectangle index in multirect
> */
> - void (*setup_rects)(struct dpu_hw_pipe *ctx,
> + void (*setup_rects)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *cfg,
> enum dpu_sspp_multirect_index index);
>
> @@ -233,7 +233,7 @@ struct dpu_hw_sspp_ops {
> * @ctx: Pointer to pipe context
> * @pe_ext: Pointer to pixel ext settings
> */
> - void (*setup_pe)(struct dpu_hw_pipe *ctx,
> + void (*setup_pe)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pixel_ext *pe_ext);
>
> /**
> @@ -242,7 +242,7 @@ struct dpu_hw_sspp_ops {
> * @cfg: Pointer to pipe config structure
> * @index: rectangle index in multirect
> */
> - void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
> + void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *cfg,
> enum dpu_sspp_multirect_index index);
>
> @@ -251,7 +251,7 @@ struct dpu_hw_sspp_ops {
> * @ctx: Pointer to pipe context
> * @data: Pointer to config structure
> */
> - void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data);
> + void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data);
>
> /**
> * setup_solidfill - enable/disable colorfill
> @@ -260,7 +260,7 @@ struct dpu_hw_sspp_ops {
> * @flags: Pipe flags
> * @index: rectangle index in multirect
> */
> - void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
> + void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color,
> enum dpu_sspp_multirect_index index);
>
> /**
> @@ -270,7 +270,7 @@ struct dpu_hw_sspp_ops {
> * @mode: parallel fetch / time multiplex multirect mode
> */
>
> - void (*setup_multirect)(struct dpu_hw_pipe *ctx,
> + void (*setup_multirect)(struct dpu_hw_sspp *ctx,
> enum dpu_sspp_multirect_index index,
> enum dpu_sspp_multirect_mode mode);
>
> @@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
> * @ctx: Pointer to pipe context
> * @cfg: Pointer to config structure
> */
> - void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
> + void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_sharp_cfg *cfg);
>
> /**
> @@ -289,7 +289,7 @@ struct dpu_hw_sspp_ops {
> * @safe_lut: LUT for generate safe level based on fill level
> *
> */
> - void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
> + void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx,
> u32 danger_lut,
> u32 safe_lut);
>
> @@ -299,7 +299,7 @@ struct dpu_hw_sspp_ops {
> * @creq_lut: LUT for generate creq level based on fill level
> *
> */
> - void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
> + void (*setup_creq_lut)(struct dpu_hw_sspp *ctx,
> u64 creq_lut);
>
> /**
> @@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops {
> * @cfg: Pointer to pipe QoS configuration
> *
> */
> - void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
> + void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_qos_cfg *cfg);
>
> /**
> @@ -316,7 +316,7 @@ struct dpu_hw_sspp_ops {
> * @ctx: Pointer to pipe context
> * @cfg: Pointer to histogram configuration
> */
> - void (*setup_histogram)(struct dpu_hw_pipe *ctx,
> + void (*setup_histogram)(struct dpu_hw_sspp *ctx,
> void *cfg);
>
> /**
> @@ -325,7 +325,7 @@ struct dpu_hw_sspp_ops {
> * @pipe_cfg: Pointer to pipe configuration
> * @scaler_cfg: Pointer to scaler configuration
> */
> - void (*setup_scaler)(struct dpu_hw_pipe *ctx,
> + void (*setup_scaler)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *pipe_cfg,
> void *scaler_cfg);
>
> @@ -333,7 +333,7 @@ struct dpu_hw_sspp_ops {
> * get_scaler_ver - get scaler h/w version
> * @ctx: Pointer to pipe context
> */
> - u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
> + u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx);
>
> /**
> * setup_cdp - setup client driven prefetch
> @@ -341,13 +341,13 @@ struct dpu_hw_sspp_ops {
> * @cfg: Pointer to cdp configuration
> * @index: rectangle index in multirect
> */
> - void (*setup_cdp)(struct dpu_hw_pipe *ctx,
> + void (*setup_cdp)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_cdp_cfg *cfg,
> enum dpu_sspp_multirect_index index);
> };
>
> /**
> - * struct dpu_hw_pipe - pipe description
> + * struct dpu_hw_sspp - pipe description
> * @base: hardware block base structure
> * @hw: block hardware details
> * @catalog: back pointer to catalog
> @@ -356,7 +356,7 @@ struct dpu_hw_sspp_ops {
> * @cap: pointer to layer_cfg
> * @ops: pointer to operations possible for this pipe
> */
> -struct dpu_hw_pipe {
> +struct dpu_hw_sspp {
> struct dpu_hw_blk base;
> struct dpu_hw_blk_reg_map hw;
> const struct dpu_mdss_cfg *catalog;
> @@ -378,7 +378,7 @@ struct dpu_kms;
> * @addr: Mapped register io address of MDP
> * @catalog : Pointer to mdss catalog data
> */
> -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
> +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
> void __iomem *addr, const struct dpu_mdss_cfg *catalog);
>
> /**
> @@ -386,10 +386,10 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
> * should be called during Hw pipe cleanup.
> * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
> */
> -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
> +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
>
> void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);
> -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
> +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
>
> #endif /*_DPU_HW_SSPP_H */
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index bfd5be89e8b8..e1cdd71716f0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -104,7 +104,7 @@ struct dpu_plane {
>
> enum dpu_sspp pipe;
>
> - struct dpu_hw_pipe *pipe_hw;
> + struct dpu_hw_sspp *pipe_hw;
> uint32_t color_fill;
> bool is_error;
> bool is_rt_pipe;
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 02/27] drm/msm/dpu: rename struct dpu_hw_pipe to dpu_hw_sspp
@ 2023-01-26 22:55 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-26 22:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> For all hardware blocks except SSPP the corresponding struct is named
> after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Idea seems okay but then we should also rename dpu_hw_pipe_cfg to
dpu_hw_sspp_cfg.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 42 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 42 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
> 3 files changed, 43 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 691c471b08c2..93f01f767fd8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -136,7 +136,7 @@
> #define TS_CLK 19200000
>
>
> -static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
> +static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
> int s_id,
> u32 *idx)
> {
> @@ -168,7 +168,7 @@ static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
> return rc;
> }
>
> -static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
> enum dpu_sspp_multirect_index index,
> enum dpu_sspp_multirect_mode mode)
> {
> @@ -197,7 +197,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
> }
>
> -static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
> +static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
> u32 mask, u8 en)
> {
> u32 idx;
> @@ -218,7 +218,7 @@ static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
> }
>
> -static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
> +static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
> u32 mask, u8 en)
> {
> u32 idx;
> @@ -239,7 +239,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
> /*
> * Setup source pixel format, flip,
> */
> -static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
> const struct dpu_format *fmt, u32 flags,
> enum dpu_sspp_multirect_index rect_mode)
> {
> @@ -356,7 +356,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
> }
>
> -static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pixel_ext *pe_ext)
> {
> struct dpu_hw_blk_reg_map *c;
> @@ -414,7 +414,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
> tot_req_pixels[3]);
> }
>
> -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
> +static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *sspp,
> void *scaler_cfg)
> {
> @@ -430,7 +430,7 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
> sspp->layout.format);
> }
>
> -static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
> +static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
> {
> u32 idx;
>
> @@ -443,7 +443,7 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
> /*
> * dpu_hw_sspp_setup_rects()
> */
> -static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *cfg,
> enum dpu_sspp_multirect_index rect_index)
> {
> @@ -512,7 +512,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> }
>
> -static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *cfg,
> enum dpu_sspp_multirect_index rect_mode)
> {
> @@ -539,7 +539,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
> }
> }
>
> -static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
> const struct dpu_csc_cfg *data)
> {
> u32 idx;
> @@ -556,7 +556,7 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
> dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
> }
>
> -static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
> +static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32 color, enum
> dpu_sspp_multirect_index rect_index)
> {
> u32 idx;
> @@ -571,7 +571,7 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
> color);
> }
>
> -static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx,
> u32 danger_lut,
> u32 safe_lut)
> {
> @@ -584,7 +584,7 @@ static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
> }
>
> -static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,
> u64 creq_lut)
> {
> u32 idx;
> @@ -601,7 +601,7 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
> }
> }
>
> -static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_qos_cfg *cfg)
> {
> u32 idx;
> @@ -626,7 +626,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
> }
>
> -static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
> +static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
> struct dpu_hw_cdp_cfg *cfg,
> enum dpu_sspp_multirect_index index)
> {
> @@ -657,7 +657,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
> }
>
> -static void _setup_layer_ops(struct dpu_hw_pipe *c,
> +static void _setup_layer_ops(struct dpu_hw_sspp *c,
> unsigned long features)
> {
> if (test_bit(DPU_SSPP_SRC, &features)) {
> @@ -695,7 +695,7 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
> }
>
> #ifdef CONFIG_DEBUG_FS
> -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
> +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
> {
> const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
> const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
> @@ -779,10 +779,10 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
> return ERR_PTR(-ENOMEM);
> }
>
> -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
> +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
> void __iomem *addr, const struct dpu_mdss_cfg *catalog)
> {
> - struct dpu_hw_pipe *hw_pipe;
> + struct dpu_hw_sspp *hw_pipe;
> const struct dpu_sspp_cfg *cfg;
>
> if (!addr || !catalog)
> @@ -808,7 +808,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
> return hw_pipe;
> }
>
> -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
> +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx)
> {
> kfree(ctx);
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index 0c95b7e64f6c..651621b9794f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -10,7 +10,7 @@
> #include "dpu_hw_util.h"
> #include "dpu_formats.h"
>
> -struct dpu_hw_pipe;
> +struct dpu_hw_sspp;
>
> /**
> * Flags
> @@ -214,7 +214,7 @@ struct dpu_hw_sspp_ops {
> * @flags: Extra flags for format config
> * @index: rectangle index in multirect
> */
> - void (*setup_format)(struct dpu_hw_pipe *ctx,
> + void (*setup_format)(struct dpu_hw_sspp *ctx,
> const struct dpu_format *fmt, u32 flags,
> enum dpu_sspp_multirect_index index);
>
> @@ -224,7 +224,7 @@ struct dpu_hw_sspp_ops {
> * @cfg: Pointer to pipe config structure
> * @index: rectangle index in multirect
> */
> - void (*setup_rects)(struct dpu_hw_pipe *ctx,
> + void (*setup_rects)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *cfg,
> enum dpu_sspp_multirect_index index);
>
> @@ -233,7 +233,7 @@ struct dpu_hw_sspp_ops {
> * @ctx: Pointer to pipe context
> * @pe_ext: Pointer to pixel ext settings
> */
> - void (*setup_pe)(struct dpu_hw_pipe *ctx,
> + void (*setup_pe)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pixel_ext *pe_ext);
>
> /**
> @@ -242,7 +242,7 @@ struct dpu_hw_sspp_ops {
> * @cfg: Pointer to pipe config structure
> * @index: rectangle index in multirect
> */
> - void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
> + void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *cfg,
> enum dpu_sspp_multirect_index index);
>
> @@ -251,7 +251,7 @@ struct dpu_hw_sspp_ops {
> * @ctx: Pointer to pipe context
> * @data: Pointer to config structure
> */
> - void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data);
> + void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data);
>
> /**
> * setup_solidfill - enable/disable colorfill
> @@ -260,7 +260,7 @@ struct dpu_hw_sspp_ops {
> * @flags: Pipe flags
> * @index: rectangle index in multirect
> */
> - void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
> + void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color,
> enum dpu_sspp_multirect_index index);
>
> /**
> @@ -270,7 +270,7 @@ struct dpu_hw_sspp_ops {
> * @mode: parallel fetch / time multiplex multirect mode
> */
>
> - void (*setup_multirect)(struct dpu_hw_pipe *ctx,
> + void (*setup_multirect)(struct dpu_hw_sspp *ctx,
> enum dpu_sspp_multirect_index index,
> enum dpu_sspp_multirect_mode mode);
>
> @@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
> * @ctx: Pointer to pipe context
> * @cfg: Pointer to config structure
> */
> - void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
> + void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_sharp_cfg *cfg);
>
> /**
> @@ -289,7 +289,7 @@ struct dpu_hw_sspp_ops {
> * @safe_lut: LUT for generate safe level based on fill level
> *
> */
> - void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
> + void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx,
> u32 danger_lut,
> u32 safe_lut);
>
> @@ -299,7 +299,7 @@ struct dpu_hw_sspp_ops {
> * @creq_lut: LUT for generate creq level based on fill level
> *
> */
> - void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
> + void (*setup_creq_lut)(struct dpu_hw_sspp *ctx,
> u64 creq_lut);
>
> /**
> @@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops {
> * @cfg: Pointer to pipe QoS configuration
> *
> */
> - void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
> + void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_qos_cfg *cfg);
>
> /**
> @@ -316,7 +316,7 @@ struct dpu_hw_sspp_ops {
> * @ctx: Pointer to pipe context
> * @cfg: Pointer to histogram configuration
> */
> - void (*setup_histogram)(struct dpu_hw_pipe *ctx,
> + void (*setup_histogram)(struct dpu_hw_sspp *ctx,
> void *cfg);
>
> /**
> @@ -325,7 +325,7 @@ struct dpu_hw_sspp_ops {
> * @pipe_cfg: Pointer to pipe configuration
> * @scaler_cfg: Pointer to scaler configuration
> */
> - void (*setup_scaler)(struct dpu_hw_pipe *ctx,
> + void (*setup_scaler)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_pipe_cfg *pipe_cfg,
> void *scaler_cfg);
>
> @@ -333,7 +333,7 @@ struct dpu_hw_sspp_ops {
> * get_scaler_ver - get scaler h/w version
> * @ctx: Pointer to pipe context
> */
> - u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
> + u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx);
>
> /**
> * setup_cdp - setup client driven prefetch
> @@ -341,13 +341,13 @@ struct dpu_hw_sspp_ops {
> * @cfg: Pointer to cdp configuration
> * @index: rectangle index in multirect
> */
> - void (*setup_cdp)(struct dpu_hw_pipe *ctx,
> + void (*setup_cdp)(struct dpu_hw_sspp *ctx,
> struct dpu_hw_cdp_cfg *cfg,
> enum dpu_sspp_multirect_index index);
> };
>
> /**
> - * struct dpu_hw_pipe - pipe description
> + * struct dpu_hw_sspp - pipe description
> * @base: hardware block base structure
> * @hw: block hardware details
> * @catalog: back pointer to catalog
> @@ -356,7 +356,7 @@ struct dpu_hw_sspp_ops {
> * @cap: pointer to layer_cfg
> * @ops: pointer to operations possible for this pipe
> */
> -struct dpu_hw_pipe {
> +struct dpu_hw_sspp {
> struct dpu_hw_blk base;
> struct dpu_hw_blk_reg_map hw;
> const struct dpu_mdss_cfg *catalog;
> @@ -378,7 +378,7 @@ struct dpu_kms;
> * @addr: Mapped register io address of MDP
> * @catalog : Pointer to mdss catalog data
> */
> -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
> +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
> void __iomem *addr, const struct dpu_mdss_cfg *catalog);
>
> /**
> @@ -386,10 +386,10 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
> * should be called during Hw pipe cleanup.
> * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
> */
> -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
> +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
>
> void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);
> -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
> +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
>
> #endif /*_DPU_HW_SSPP_H */
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index bfd5be89e8b8..e1cdd71716f0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -104,7 +104,7 @@ struct dpu_plane {
>
> enum dpu_sspp pipe;
>
> - struct dpu_hw_pipe *pipe_hw;
> + struct dpu_hw_sspp *pipe_hw;
> uint32_t color_fill;
> bool is_error;
> bool is_rt_pipe;
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 02/27] drm/msm/dpu: rename struct dpu_hw_pipe to dpu_hw_sspp
2023-01-26 22:55 ` Abhinav Kumar
@ 2023-01-31 11:19 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-31 11:19 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 27/01/2023 00:55, Abhinav Kumar wrote:
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>> For all hardware blocks except SSPP the corresponding struct is named
>> after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Idea seems okay but then we should also rename dpu_hw_pipe_cfg to
> dpu_hw_sspp_cfg.
I'll have to think about it. I ended up reusing the dpu_hw_pipe_cfg to
describe a single rectangle configuration (iow, one for rect0, one for
rect1). Let me check if I can make it more obvious.
>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 42 ++++++++++-----------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 42 ++++++++++-----------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
>> 3 files changed, 43 insertions(+), 43 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> index 691c471b08c2..93f01f767fd8 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> @@ -136,7 +136,7 @@
>> #define TS_CLK 19200000
>> -static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
>> +static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
>> int s_id,
>> u32 *idx)
>> {
>> @@ -168,7 +168,7 @@ static int _sspp_subblk_offset(struct dpu_hw_pipe
>> *ctx,
>> return rc;
>> }
>> -static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
>> enum dpu_sspp_multirect_index index,
>> enum dpu_sspp_multirect_mode mode)
>> {
>> @@ -197,7 +197,7 @@ static void dpu_hw_sspp_setup_multirect(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
>> }
>> -static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
>> +static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
>> u32 mask, u8 en)
>> {
>> u32 idx;
>> @@ -218,7 +218,7 @@ static void _sspp_setup_opmode(struct dpu_hw_pipe
>> *ctx,
>> DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
>> }
>> -static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
>> +static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
>> u32 mask, u8 en)
>> {
>> u32 idx;
>> @@ -239,7 +239,7 @@ static void _sspp_setup_csc10_opmode(struct
>> dpu_hw_pipe *ctx,
>> /*
>> * Setup source pixel format, flip,
>> */
>> -static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
>> const struct dpu_format *fmt, u32 flags,
>> enum dpu_sspp_multirect_index rect_mode)
>> {
>> @@ -356,7 +356,7 @@ static void dpu_hw_sspp_setup_format(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
>> }
>> -static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pixel_ext *pe_ext)
>> {
>> struct dpu_hw_blk_reg_map *c;
>> @@ -414,7 +414,7 @@ static void dpu_hw_sspp_setup_pe_config(struct
>> dpu_hw_pipe *ctx,
>> tot_req_pixels[3]);
>> }
>> -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
>> +static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *sspp,
>> void *scaler_cfg)
>> {
>> @@ -430,7 +430,7 @@ static void _dpu_hw_sspp_setup_scaler3(struct
>> dpu_hw_pipe *ctx,
>> sspp->layout.format);
>> }
>> -static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
>> +static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
>> {
>> u32 idx;
>> @@ -443,7 +443,7 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct
>> dpu_hw_pipe *ctx)
>> /*
>> * dpu_hw_sspp_setup_rects()
>> */
>> -static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *cfg,
>> enum dpu_sspp_multirect_index rect_index)
>> {
>> @@ -512,7 +512,7 @@ static void dpu_hw_sspp_setup_rects(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
>> }
>> -static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *cfg,
>> enum dpu_sspp_multirect_index rect_mode)
>> {
>> @@ -539,7 +539,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct
>> dpu_hw_pipe *ctx,
>> }
>> }
>> -static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
>> const struct dpu_csc_cfg *data)
>> {
>> u32 idx;
>> @@ -556,7 +556,7 @@ static void dpu_hw_sspp_setup_csc(struct
>> dpu_hw_pipe *ctx,
>> dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
>> }
>> -static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32
>> color, enum
>> +static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32
>> color, enum
>> dpu_sspp_multirect_index rect_index)
>> {
>> u32 idx;
>> @@ -571,7 +571,7 @@ static void dpu_hw_sspp_setup_solidfill(struct
>> dpu_hw_pipe *ctx, u32 color, enum
>> color);
>> }
>> -static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx,
>> u32 danger_lut,
>> u32 safe_lut)
>> {
>> @@ -584,7 +584,7 @@ static void
>> dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
>> }
>> -static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,
>> u64 creq_lut)
>> {
>> u32 idx;
>> @@ -601,7 +601,7 @@ static void dpu_hw_sspp_setup_creq_lut(struct
>> dpu_hw_pipe *ctx,
>> }
>> }
>> -static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_qos_cfg *cfg)
>> {
>> u32 idx;
>> @@ -626,7 +626,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
>> }
>> -static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_cdp_cfg *cfg,
>> enum dpu_sspp_multirect_index index)
>> {
>> @@ -657,7 +657,7 @@ static void dpu_hw_sspp_setup_cdp(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
>> }
>> -static void _setup_layer_ops(struct dpu_hw_pipe *c,
>> +static void _setup_layer_ops(struct dpu_hw_sspp *c,
>> unsigned long features)
>> {
>> if (test_bit(DPU_SSPP_SRC, &features)) {
>> @@ -695,7 +695,7 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
>> }
>> #ifdef CONFIG_DEBUG_FS
>> -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct
>> dpu_kms *kms, struct dentry *entry)
>> +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct
>> dpu_kms *kms, struct dentry *entry)
>> {
>> const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
>> const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
>> @@ -779,10 +779,10 @@ static const struct dpu_sspp_cfg
>> *_sspp_offset(enum dpu_sspp sspp,
>> return ERR_PTR(-ENOMEM);
>> }
>> -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
>> +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
>> void __iomem *addr, const struct dpu_mdss_cfg *catalog)
>> {
>> - struct dpu_hw_pipe *hw_pipe;
>> + struct dpu_hw_sspp *hw_pipe;
>> const struct dpu_sspp_cfg *cfg;
>> if (!addr || !catalog)
>> @@ -808,7 +808,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp
>> idx,
>> return hw_pipe;
>> }
>> -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
>> +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx)
>> {
>> kfree(ctx);
>> }
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> index 0c95b7e64f6c..651621b9794f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> @@ -10,7 +10,7 @@
>> #include "dpu_hw_util.h"
>> #include "dpu_formats.h"
>> -struct dpu_hw_pipe;
>> +struct dpu_hw_sspp;
>> /**
>> * Flags
>> @@ -214,7 +214,7 @@ struct dpu_hw_sspp_ops {
>> * @flags: Extra flags for format config
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_format)(struct dpu_hw_pipe *ctx,
>> + void (*setup_format)(struct dpu_hw_sspp *ctx,
>> const struct dpu_format *fmt, u32 flags,
>> enum dpu_sspp_multirect_index index);
>> @@ -224,7 +224,7 @@ struct dpu_hw_sspp_ops {
>> * @cfg: Pointer to pipe config structure
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_rects)(struct dpu_hw_pipe *ctx,
>> + void (*setup_rects)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *cfg,
>> enum dpu_sspp_multirect_index index);
>> @@ -233,7 +233,7 @@ struct dpu_hw_sspp_ops {
>> * @ctx: Pointer to pipe context
>> * @pe_ext: Pointer to pixel ext settings
>> */
>> - void (*setup_pe)(struct dpu_hw_pipe *ctx,
>> + void (*setup_pe)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pixel_ext *pe_ext);
>> /**
>> @@ -242,7 +242,7 @@ struct dpu_hw_sspp_ops {
>> * @cfg: Pointer to pipe config structure
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
>> + void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *cfg,
>> enum dpu_sspp_multirect_index index);
>> @@ -251,7 +251,7 @@ struct dpu_hw_sspp_ops {
>> * @ctx: Pointer to pipe context
>> * @data: Pointer to config structure
>> */
>> - void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct
>> dpu_csc_cfg *data);
>> + void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct
>> dpu_csc_cfg *data);
>> /**
>> * setup_solidfill - enable/disable colorfill
>> @@ -260,7 +260,7 @@ struct dpu_hw_sspp_ops {
>> * @flags: Pipe flags
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
>> + void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color,
>> enum dpu_sspp_multirect_index index);
>> /**
>> @@ -270,7 +270,7 @@ struct dpu_hw_sspp_ops {
>> * @mode: parallel fetch / time multiplex multirect mode
>> */
>> - void (*setup_multirect)(struct dpu_hw_pipe *ctx,
>> + void (*setup_multirect)(struct dpu_hw_sspp *ctx,
>> enum dpu_sspp_multirect_index index,
>> enum dpu_sspp_multirect_mode mode);
>> @@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
>> * @ctx: Pointer to pipe context
>> * @cfg: Pointer to config structure
>> */
>> - void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
>> + void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_sharp_cfg *cfg);
>> /**
>> @@ -289,7 +289,7 @@ struct dpu_hw_sspp_ops {
>> * @safe_lut: LUT for generate safe level based on fill level
>> *
>> */
>> - void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
>> + void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx,
>> u32 danger_lut,
>> u32 safe_lut);
>> @@ -299,7 +299,7 @@ struct dpu_hw_sspp_ops {
>> * @creq_lut: LUT for generate creq level based on fill level
>> *
>> */
>> - void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
>> + void (*setup_creq_lut)(struct dpu_hw_sspp *ctx,
>> u64 creq_lut);
>> /**
>> @@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops {
>> * @cfg: Pointer to pipe QoS configuration
>> *
>> */
>> - void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
>> + void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_qos_cfg *cfg);
>> /**
>> @@ -316,7 +316,7 @@ struct dpu_hw_sspp_ops {
>> * @ctx: Pointer to pipe context
>> * @cfg: Pointer to histogram configuration
>> */
>> - void (*setup_histogram)(struct dpu_hw_pipe *ctx,
>> + void (*setup_histogram)(struct dpu_hw_sspp *ctx,
>> void *cfg);
>> /**
>> @@ -325,7 +325,7 @@ struct dpu_hw_sspp_ops {
>> * @pipe_cfg: Pointer to pipe configuration
>> * @scaler_cfg: Pointer to scaler configuration
>> */
>> - void (*setup_scaler)(struct dpu_hw_pipe *ctx,
>> + void (*setup_scaler)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *pipe_cfg,
>> void *scaler_cfg);
>> @@ -333,7 +333,7 @@ struct dpu_hw_sspp_ops {
>> * get_scaler_ver - get scaler h/w version
>> * @ctx: Pointer to pipe context
>> */
>> - u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
>> + u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx);
>> /**
>> * setup_cdp - setup client driven prefetch
>> @@ -341,13 +341,13 @@ struct dpu_hw_sspp_ops {
>> * @cfg: Pointer to cdp configuration
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_cdp)(struct dpu_hw_pipe *ctx,
>> + void (*setup_cdp)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_cdp_cfg *cfg,
>> enum dpu_sspp_multirect_index index);
>> };
>> /**
>> - * struct dpu_hw_pipe - pipe description
>> + * struct dpu_hw_sspp - pipe description
>> * @base: hardware block base structure
>> * @hw: block hardware details
>> * @catalog: back pointer to catalog
>> @@ -356,7 +356,7 @@ struct dpu_hw_sspp_ops {
>> * @cap: pointer to layer_cfg
>> * @ops: pointer to operations possible for this pipe
>> */
>> -struct dpu_hw_pipe {
>> +struct dpu_hw_sspp {
>> struct dpu_hw_blk base;
>> struct dpu_hw_blk_reg_map hw;
>> const struct dpu_mdss_cfg *catalog;
>> @@ -378,7 +378,7 @@ struct dpu_kms;
>> * @addr: Mapped register io address of MDP
>> * @catalog : Pointer to mdss catalog data
>> */
>> -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
>> +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
>> void __iomem *addr, const struct dpu_mdss_cfg *catalog);
>> /**
>> @@ -386,10 +386,10 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum
>> dpu_sspp idx,
>> * should be called during Hw pipe cleanup.
>> * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
>> */
>> -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
>> +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
>> void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry
>> *debugfs_root);
>> -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct
>> dpu_kms *kms, struct dentry *entry);
>> +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct
>> dpu_kms *kms, struct dentry *entry);
>> #endif /*_DPU_HW_SSPP_H */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> index bfd5be89e8b8..e1cdd71716f0 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> @@ -104,7 +104,7 @@ struct dpu_plane {
>> enum dpu_sspp pipe;
>> - struct dpu_hw_pipe *pipe_hw;
>> + struct dpu_hw_sspp *pipe_hw;
>> uint32_t color_fill;
>> bool is_error;
>> bool is_rt_pipe;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 02/27] drm/msm/dpu: rename struct dpu_hw_pipe to dpu_hw_sspp
@ 2023-01-31 11:19 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-31 11:19 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 27/01/2023 00:55, Abhinav Kumar wrote:
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>> For all hardware blocks except SSPP the corresponding struct is named
>> after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Idea seems okay but then we should also rename dpu_hw_pipe_cfg to
> dpu_hw_sspp_cfg.
I'll have to think about it. I ended up reusing the dpu_hw_pipe_cfg to
describe a single rectangle configuration (iow, one for rect0, one for
rect1). Let me check if I can make it more obvious.
>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 42 ++++++++++-----------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 42 ++++++++++-----------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
>> 3 files changed, 43 insertions(+), 43 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> index 691c471b08c2..93f01f767fd8 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> @@ -136,7 +136,7 @@
>> #define TS_CLK 19200000
>> -static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
>> +static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
>> int s_id,
>> u32 *idx)
>> {
>> @@ -168,7 +168,7 @@ static int _sspp_subblk_offset(struct dpu_hw_pipe
>> *ctx,
>> return rc;
>> }
>> -static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
>> enum dpu_sspp_multirect_index index,
>> enum dpu_sspp_multirect_mode mode)
>> {
>> @@ -197,7 +197,7 @@ static void dpu_hw_sspp_setup_multirect(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
>> }
>> -static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
>> +static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
>> u32 mask, u8 en)
>> {
>> u32 idx;
>> @@ -218,7 +218,7 @@ static void _sspp_setup_opmode(struct dpu_hw_pipe
>> *ctx,
>> DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
>> }
>> -static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
>> +static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
>> u32 mask, u8 en)
>> {
>> u32 idx;
>> @@ -239,7 +239,7 @@ static void _sspp_setup_csc10_opmode(struct
>> dpu_hw_pipe *ctx,
>> /*
>> * Setup source pixel format, flip,
>> */
>> -static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
>> const struct dpu_format *fmt, u32 flags,
>> enum dpu_sspp_multirect_index rect_mode)
>> {
>> @@ -356,7 +356,7 @@ static void dpu_hw_sspp_setup_format(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
>> }
>> -static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pixel_ext *pe_ext)
>> {
>> struct dpu_hw_blk_reg_map *c;
>> @@ -414,7 +414,7 @@ static void dpu_hw_sspp_setup_pe_config(struct
>> dpu_hw_pipe *ctx,
>> tot_req_pixels[3]);
>> }
>> -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
>> +static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *sspp,
>> void *scaler_cfg)
>> {
>> @@ -430,7 +430,7 @@ static void _dpu_hw_sspp_setup_scaler3(struct
>> dpu_hw_pipe *ctx,
>> sspp->layout.format);
>> }
>> -static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
>> +static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
>> {
>> u32 idx;
>> @@ -443,7 +443,7 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct
>> dpu_hw_pipe *ctx)
>> /*
>> * dpu_hw_sspp_setup_rects()
>> */
>> -static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *cfg,
>> enum dpu_sspp_multirect_index rect_index)
>> {
>> @@ -512,7 +512,7 @@ static void dpu_hw_sspp_setup_rects(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
>> }
>> -static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *cfg,
>> enum dpu_sspp_multirect_index rect_mode)
>> {
>> @@ -539,7 +539,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct
>> dpu_hw_pipe *ctx,
>> }
>> }
>> -static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
>> const struct dpu_csc_cfg *data)
>> {
>> u32 idx;
>> @@ -556,7 +556,7 @@ static void dpu_hw_sspp_setup_csc(struct
>> dpu_hw_pipe *ctx,
>> dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
>> }
>> -static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32
>> color, enum
>> +static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32
>> color, enum
>> dpu_sspp_multirect_index rect_index)
>> {
>> u32 idx;
>> @@ -571,7 +571,7 @@ static void dpu_hw_sspp_setup_solidfill(struct
>> dpu_hw_pipe *ctx, u32 color, enum
>> color);
>> }
>> -static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx,
>> u32 danger_lut,
>> u32 safe_lut)
>> {
>> @@ -584,7 +584,7 @@ static void
>> dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
>> }
>> -static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,
>> u64 creq_lut)
>> {
>> u32 idx;
>> @@ -601,7 +601,7 @@ static void dpu_hw_sspp_setup_creq_lut(struct
>> dpu_hw_pipe *ctx,
>> }
>> }
>> -static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_qos_cfg *cfg)
>> {
>> u32 idx;
>> @@ -626,7 +626,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
>> }
>> -static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
>> +static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_cdp_cfg *cfg,
>> enum dpu_sspp_multirect_index index)
>> {
>> @@ -657,7 +657,7 @@ static void dpu_hw_sspp_setup_cdp(struct
>> dpu_hw_pipe *ctx,
>> DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
>> }
>> -static void _setup_layer_ops(struct dpu_hw_pipe *c,
>> +static void _setup_layer_ops(struct dpu_hw_sspp *c,
>> unsigned long features)
>> {
>> if (test_bit(DPU_SSPP_SRC, &features)) {
>> @@ -695,7 +695,7 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
>> }
>> #ifdef CONFIG_DEBUG_FS
>> -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct
>> dpu_kms *kms, struct dentry *entry)
>> +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct
>> dpu_kms *kms, struct dentry *entry)
>> {
>> const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
>> const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
>> @@ -779,10 +779,10 @@ static const struct dpu_sspp_cfg
>> *_sspp_offset(enum dpu_sspp sspp,
>> return ERR_PTR(-ENOMEM);
>> }
>> -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
>> +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
>> void __iomem *addr, const struct dpu_mdss_cfg *catalog)
>> {
>> - struct dpu_hw_pipe *hw_pipe;
>> + struct dpu_hw_sspp *hw_pipe;
>> const struct dpu_sspp_cfg *cfg;
>> if (!addr || !catalog)
>> @@ -808,7 +808,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp
>> idx,
>> return hw_pipe;
>> }
>> -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
>> +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx)
>> {
>> kfree(ctx);
>> }
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> index 0c95b7e64f6c..651621b9794f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> @@ -10,7 +10,7 @@
>> #include "dpu_hw_util.h"
>> #include "dpu_formats.h"
>> -struct dpu_hw_pipe;
>> +struct dpu_hw_sspp;
>> /**
>> * Flags
>> @@ -214,7 +214,7 @@ struct dpu_hw_sspp_ops {
>> * @flags: Extra flags for format config
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_format)(struct dpu_hw_pipe *ctx,
>> + void (*setup_format)(struct dpu_hw_sspp *ctx,
>> const struct dpu_format *fmt, u32 flags,
>> enum dpu_sspp_multirect_index index);
>> @@ -224,7 +224,7 @@ struct dpu_hw_sspp_ops {
>> * @cfg: Pointer to pipe config structure
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_rects)(struct dpu_hw_pipe *ctx,
>> + void (*setup_rects)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *cfg,
>> enum dpu_sspp_multirect_index index);
>> @@ -233,7 +233,7 @@ struct dpu_hw_sspp_ops {
>> * @ctx: Pointer to pipe context
>> * @pe_ext: Pointer to pixel ext settings
>> */
>> - void (*setup_pe)(struct dpu_hw_pipe *ctx,
>> + void (*setup_pe)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pixel_ext *pe_ext);
>> /**
>> @@ -242,7 +242,7 @@ struct dpu_hw_sspp_ops {
>> * @cfg: Pointer to pipe config structure
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
>> + void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *cfg,
>> enum dpu_sspp_multirect_index index);
>> @@ -251,7 +251,7 @@ struct dpu_hw_sspp_ops {
>> * @ctx: Pointer to pipe context
>> * @data: Pointer to config structure
>> */
>> - void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct
>> dpu_csc_cfg *data);
>> + void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct
>> dpu_csc_cfg *data);
>> /**
>> * setup_solidfill - enable/disable colorfill
>> @@ -260,7 +260,7 @@ struct dpu_hw_sspp_ops {
>> * @flags: Pipe flags
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
>> + void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color,
>> enum dpu_sspp_multirect_index index);
>> /**
>> @@ -270,7 +270,7 @@ struct dpu_hw_sspp_ops {
>> * @mode: parallel fetch / time multiplex multirect mode
>> */
>> - void (*setup_multirect)(struct dpu_hw_pipe *ctx,
>> + void (*setup_multirect)(struct dpu_hw_sspp *ctx,
>> enum dpu_sspp_multirect_index index,
>> enum dpu_sspp_multirect_mode mode);
>> @@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
>> * @ctx: Pointer to pipe context
>> * @cfg: Pointer to config structure
>> */
>> - void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
>> + void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_sharp_cfg *cfg);
>> /**
>> @@ -289,7 +289,7 @@ struct dpu_hw_sspp_ops {
>> * @safe_lut: LUT for generate safe level based on fill level
>> *
>> */
>> - void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
>> + void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx,
>> u32 danger_lut,
>> u32 safe_lut);
>> @@ -299,7 +299,7 @@ struct dpu_hw_sspp_ops {
>> * @creq_lut: LUT for generate creq level based on fill level
>> *
>> */
>> - void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
>> + void (*setup_creq_lut)(struct dpu_hw_sspp *ctx,
>> u64 creq_lut);
>> /**
>> @@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops {
>> * @cfg: Pointer to pipe QoS configuration
>> *
>> */
>> - void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
>> + void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_qos_cfg *cfg);
>> /**
>> @@ -316,7 +316,7 @@ struct dpu_hw_sspp_ops {
>> * @ctx: Pointer to pipe context
>> * @cfg: Pointer to histogram configuration
>> */
>> - void (*setup_histogram)(struct dpu_hw_pipe *ctx,
>> + void (*setup_histogram)(struct dpu_hw_sspp *ctx,
>> void *cfg);
>> /**
>> @@ -325,7 +325,7 @@ struct dpu_hw_sspp_ops {
>> * @pipe_cfg: Pointer to pipe configuration
>> * @scaler_cfg: Pointer to scaler configuration
>> */
>> - void (*setup_scaler)(struct dpu_hw_pipe *ctx,
>> + void (*setup_scaler)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_pipe_cfg *pipe_cfg,
>> void *scaler_cfg);
>> @@ -333,7 +333,7 @@ struct dpu_hw_sspp_ops {
>> * get_scaler_ver - get scaler h/w version
>> * @ctx: Pointer to pipe context
>> */
>> - u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
>> + u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx);
>> /**
>> * setup_cdp - setup client driven prefetch
>> @@ -341,13 +341,13 @@ struct dpu_hw_sspp_ops {
>> * @cfg: Pointer to cdp configuration
>> * @index: rectangle index in multirect
>> */
>> - void (*setup_cdp)(struct dpu_hw_pipe *ctx,
>> + void (*setup_cdp)(struct dpu_hw_sspp *ctx,
>> struct dpu_hw_cdp_cfg *cfg,
>> enum dpu_sspp_multirect_index index);
>> };
>> /**
>> - * struct dpu_hw_pipe - pipe description
>> + * struct dpu_hw_sspp - pipe description
>> * @base: hardware block base structure
>> * @hw: block hardware details
>> * @catalog: back pointer to catalog
>> @@ -356,7 +356,7 @@ struct dpu_hw_sspp_ops {
>> * @cap: pointer to layer_cfg
>> * @ops: pointer to operations possible for this pipe
>> */
>> -struct dpu_hw_pipe {
>> +struct dpu_hw_sspp {
>> struct dpu_hw_blk base;
>> struct dpu_hw_blk_reg_map hw;
>> const struct dpu_mdss_cfg *catalog;
>> @@ -378,7 +378,7 @@ struct dpu_kms;
>> * @addr: Mapped register io address of MDP
>> * @catalog : Pointer to mdss catalog data
>> */
>> -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
>> +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
>> void __iomem *addr, const struct dpu_mdss_cfg *catalog);
>> /**
>> @@ -386,10 +386,10 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum
>> dpu_sspp idx,
>> * should be called during Hw pipe cleanup.
>> * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
>> */
>> -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
>> +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
>> void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry
>> *debugfs_root);
>> -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct
>> dpu_kms *kms, struct dentry *entry);
>> +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct
>> dpu_kms *kms, struct dentry *entry);
>> #endif /*_DPU_HW_SSPP_H */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> index bfd5be89e8b8..e1cdd71716f0 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> @@ -104,7 +104,7 @@ struct dpu_plane {
>> enum dpu_sspp pipe;
>> - struct dpu_hw_pipe *pipe_hw;
>> + struct dpu_hw_sspp *pipe_hw;
>> uint32_t color_fill;
>> bool is_error;
>> bool is_rt_pipe;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 03/27] drm/msm/dpu: move SSPP allocation to the RM
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Follow the example of all other hw blocks and initialize SSPP blocks in
Resource Manager.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++-------------
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++
3 files changed, 38 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index e1cdd71716f0..e443799de2c1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1275,8 +1275,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
/* this will destroy the states as well */
drm_plane_cleanup(plane);
- dpu_hw_sspp_destroy(pdpu->pipe_hw);
-
kfree(pdpu);
}
}
@@ -1482,14 +1480,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
pdpu->pipe = pipe;
/* initialize underlying h/w driver */
- pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
- if (IS_ERR(pdpu->pipe_hw)) {
- DPU_ERROR("[%u]SSPP init failed\n", pipe);
- ret = PTR_ERR(pdpu->pipe_hw);
+ pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
+ if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
+ DPU_ERROR("[%u]SSPP is invalid\n", pipe);
goto clean_plane;
- } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
- DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
- goto clean_sspp;
}
format_list = pdpu->pipe_hw->cap->sblk->format_list;
@@ -1499,7 +1493,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
format_list, num_formats,
supported_format_modifiers, type, NULL);
if (ret)
- goto clean_sspp;
+ goto clean_plane;
pdpu->catalog = kms->catalog;
@@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
pipe, plane->base.id);
return plane;
-clean_sspp:
- if (pdpu && pdpu->pipe_hw)
- dpu_hw_sspp_destroy(pdpu->pipe_hw);
clean_plane:
kfree(pdpu);
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 73b3442e7467..0668009cc9ed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -8,6 +8,7 @@
#include "dpu_hw_lm.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_pingpong.h"
+#include "dpu_hw_sspp.h"
#include "dpu_hw_intf.h"
#include "dpu_hw_wb.h"
#include "dpu_hw_dspp.h"
@@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
dpu_hw_wb_destroy(rm->hw_wb[i]);
+ for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++)
+ dpu_hw_sspp_destroy(rm->hw_sspp[i]);
+
return 0;
}
@@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm,
rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
}
+ for (i = 0; i < cat->sspp_count; i++) {
+ struct dpu_hw_sspp *hw;
+ const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
+
+ if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
+ DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
+ continue;
+ }
+
+ hw = dpu_hw_sspp_init(sspp->id, mmio, cat);
+ if (IS_ERR(hw)) {
+ rc = PTR_ERR(hw);
+ DPU_ERROR("failed sspp object creation: err %d\n", rc);
+ goto fail;
+ }
+ rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
+ }
+
return 0;
fail:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 59de72b381f9..d62c2edb2460 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -21,6 +21,7 @@ struct dpu_global_state;
* @hw_intf: array of intf hardware resources
* @hw_wb: array of wb hardware resources
* @dspp_blks: array of dspp hardware resources
+ * @hw_sspp: array of sspp hardware resources
*/
struct dpu_rm {
struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
@@ -31,6 +32,7 @@ struct dpu_rm {
struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
+ struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
};
/**
@@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_
return rm->hw_wb[wb_idx - WB_0];
}
+/**
+ * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
+ * @rm: DPU Resource Manager handle
+ * @sspp_idx: SSPP index
+ */
+static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
+{
+ return rm->hw_sspp[sspp_idx - SSPP_NONE];
+}
+
#endif /* __DPU_RM_H__ */
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 03/27] drm/msm/dpu: move SSPP allocation to the RM
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Follow the example of all other hw blocks and initialize SSPP blocks in
Resource Manager.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++-------------
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++
3 files changed, 38 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index e1cdd71716f0..e443799de2c1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1275,8 +1275,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
/* this will destroy the states as well */
drm_plane_cleanup(plane);
- dpu_hw_sspp_destroy(pdpu->pipe_hw);
-
kfree(pdpu);
}
}
@@ -1482,14 +1480,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
pdpu->pipe = pipe;
/* initialize underlying h/w driver */
- pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
- if (IS_ERR(pdpu->pipe_hw)) {
- DPU_ERROR("[%u]SSPP init failed\n", pipe);
- ret = PTR_ERR(pdpu->pipe_hw);
+ pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
+ if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
+ DPU_ERROR("[%u]SSPP is invalid\n", pipe);
goto clean_plane;
- } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
- DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
- goto clean_sspp;
}
format_list = pdpu->pipe_hw->cap->sblk->format_list;
@@ -1499,7 +1493,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
format_list, num_formats,
supported_format_modifiers, type, NULL);
if (ret)
- goto clean_sspp;
+ goto clean_plane;
pdpu->catalog = kms->catalog;
@@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
pipe, plane->base.id);
return plane;
-clean_sspp:
- if (pdpu && pdpu->pipe_hw)
- dpu_hw_sspp_destroy(pdpu->pipe_hw);
clean_plane:
kfree(pdpu);
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 73b3442e7467..0668009cc9ed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -8,6 +8,7 @@
#include "dpu_hw_lm.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_pingpong.h"
+#include "dpu_hw_sspp.h"
#include "dpu_hw_intf.h"
#include "dpu_hw_wb.h"
#include "dpu_hw_dspp.h"
@@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
dpu_hw_wb_destroy(rm->hw_wb[i]);
+ for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++)
+ dpu_hw_sspp_destroy(rm->hw_sspp[i]);
+
return 0;
}
@@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm,
rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
}
+ for (i = 0; i < cat->sspp_count; i++) {
+ struct dpu_hw_sspp *hw;
+ const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
+
+ if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
+ DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
+ continue;
+ }
+
+ hw = dpu_hw_sspp_init(sspp->id, mmio, cat);
+ if (IS_ERR(hw)) {
+ rc = PTR_ERR(hw);
+ DPU_ERROR("failed sspp object creation: err %d\n", rc);
+ goto fail;
+ }
+ rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
+ }
+
return 0;
fail:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 59de72b381f9..d62c2edb2460 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -21,6 +21,7 @@ struct dpu_global_state;
* @hw_intf: array of intf hardware resources
* @hw_wb: array of wb hardware resources
* @dspp_blks: array of dspp hardware resources
+ * @hw_sspp: array of sspp hardware resources
*/
struct dpu_rm {
struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
@@ -31,6 +32,7 @@ struct dpu_rm {
struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
+ struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
};
/**
@@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_
return rm->hw_wb[wb_idx - WB_0];
}
+/**
+ * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
+ * @rm: DPU Resource Manager handle
+ * @sspp_idx: SSPP index
+ */
+static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
+{
+ return rm->hw_sspp[sspp_idx - SSPP_NONE];
+}
+
#endif /* __DPU_RM_H__ */
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [PATCH v2 03/27] drm/msm/dpu: move SSPP allocation to the RM
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2023-01-26 23:29 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-26 23:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> Follow the example of all other hw blocks and initialize SSPP blocks in
> Resource Manager.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++-------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++
> 3 files changed, 38 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index e1cdd71716f0..e443799de2c1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -1275,8 +1275,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
> /* this will destroy the states as well */
> drm_plane_cleanup(plane);
>
> - dpu_hw_sspp_destroy(pdpu->pipe_hw);
> -
We removed from here so the flow will be msm_drm_uninit calls
drm_mode_config_cleanup() which will call kms->destroy() which shall
call dpu_rm_destroy() where this will be released now right?
> kfree(pdpu);
> }
> }
> @@ -1482,14 +1480,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> pdpu->pipe = pipe;
>
> /* initialize underlying h/w driver */
> - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
> - if (IS_ERR(pdpu->pipe_hw)) {
> - DPU_ERROR("[%u]SSPP init failed\n", pipe);
> - ret = PTR_ERR(pdpu->pipe_hw);
> + pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
> + if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> + DPU_ERROR("[%u]SSPP is invalid\n", pipe);
I know this was existing code but can there be a case where pipe_hw->cap
exists but pipe_hw->cap->sblk doesnt?
> goto clean_plane;
> - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
> - goto clean_sspp;
> }
>
> format_list = pdpu->pipe_hw->cap->sblk->format_list;
> @@ -1499,7 +1493,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> format_list, num_formats,
> supported_format_modifiers, type, NULL);
> if (ret)
> - goto clean_sspp;
> + goto clean_plane;
>
> pdpu->catalog = kms->catalog;
>
> @@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> pipe, plane->base.id);
> return plane;
>
> -clean_sspp:
> - if (pdpu && pdpu->pipe_hw)
> - dpu_hw_sspp_destroy(pdpu->pipe_hw);
> clean_plane:
> kfree(pdpu);
> return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 73b3442e7467..0668009cc9ed 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -8,6 +8,7 @@
> #include "dpu_hw_lm.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_pingpong.h"
> +#include "dpu_hw_sspp.h"
> #include "dpu_hw_intf.h"
> #include "dpu_hw_wb.h"
> #include "dpu_hw_dspp.h"
> @@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
> for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
> dpu_hw_wb_destroy(rm->hw_wb[i]);
>
> + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++)
> + dpu_hw_sspp_destroy(rm->hw_sspp[i]);
> +
> return 0;
> }
>
> @@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm,
> rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
> }
>
> + for (i = 0; i < cat->sspp_count; i++) {
> + struct dpu_hw_sspp *hw;
> + const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
> +
> + if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
> + DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
> + continue;
> + }
> +
> + hw = dpu_hw_sspp_init(sspp->id, mmio, cat);
> + if (IS_ERR(hw)) {
> + rc = PTR_ERR(hw);
> + DPU_ERROR("failed sspp object creation: err %d\n", rc);
> + goto fail;
> + }
> + rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
> + }
> +
> return 0;
>
> fail:
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 59de72b381f9..d62c2edb2460 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -21,6 +21,7 @@ struct dpu_global_state;
> * @hw_intf: array of intf hardware resources
> * @hw_wb: array of wb hardware resources
> * @dspp_blks: array of dspp hardware resources
> + * @hw_sspp: array of sspp hardware resources
> */
> struct dpu_rm {
> struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
> @@ -31,6 +32,7 @@ struct dpu_rm {
> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
> struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
> + struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
> };
>
> /**
> @@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_
> return rm->hw_wb[wb_idx - WB_0];
> }
>
> +/**
> + * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
> + * @rm: DPU Resource Manager handle
> + * @sspp_idx: SSPP index
> + */
> +static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
> +{
> + return rm->hw_sspp[sspp_idx - SSPP_NONE];
> +}
> +
> #endif /* __DPU_RM_H__ */
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 03/27] drm/msm/dpu: move SSPP allocation to the RM
@ 2023-01-26 23:29 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-26 23:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> Follow the example of all other hw blocks and initialize SSPP blocks in
> Resource Manager.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++-------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++
> 3 files changed, 38 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index e1cdd71716f0..e443799de2c1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -1275,8 +1275,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
> /* this will destroy the states as well */
> drm_plane_cleanup(plane);
>
> - dpu_hw_sspp_destroy(pdpu->pipe_hw);
> -
We removed from here so the flow will be msm_drm_uninit calls
drm_mode_config_cleanup() which will call kms->destroy() which shall
call dpu_rm_destroy() where this will be released now right?
> kfree(pdpu);
> }
> }
> @@ -1482,14 +1480,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> pdpu->pipe = pipe;
>
> /* initialize underlying h/w driver */
> - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
> - if (IS_ERR(pdpu->pipe_hw)) {
> - DPU_ERROR("[%u]SSPP init failed\n", pipe);
> - ret = PTR_ERR(pdpu->pipe_hw);
> + pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
> + if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> + DPU_ERROR("[%u]SSPP is invalid\n", pipe);
I know this was existing code but can there be a case where pipe_hw->cap
exists but pipe_hw->cap->sblk doesnt?
> goto clean_plane;
> - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
> - goto clean_sspp;
> }
>
> format_list = pdpu->pipe_hw->cap->sblk->format_list;
> @@ -1499,7 +1493,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> format_list, num_formats,
> supported_format_modifiers, type, NULL);
> if (ret)
> - goto clean_sspp;
> + goto clean_plane;
>
> pdpu->catalog = kms->catalog;
>
> @@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> pipe, plane->base.id);
> return plane;
>
> -clean_sspp:
> - if (pdpu && pdpu->pipe_hw)
> - dpu_hw_sspp_destroy(pdpu->pipe_hw);
> clean_plane:
> kfree(pdpu);
> return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 73b3442e7467..0668009cc9ed 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -8,6 +8,7 @@
> #include "dpu_hw_lm.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_pingpong.h"
> +#include "dpu_hw_sspp.h"
> #include "dpu_hw_intf.h"
> #include "dpu_hw_wb.h"
> #include "dpu_hw_dspp.h"
> @@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
> for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
> dpu_hw_wb_destroy(rm->hw_wb[i]);
>
> + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++)
> + dpu_hw_sspp_destroy(rm->hw_sspp[i]);
> +
> return 0;
> }
>
> @@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm,
> rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
> }
>
> + for (i = 0; i < cat->sspp_count; i++) {
> + struct dpu_hw_sspp *hw;
> + const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
> +
> + if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
> + DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
> + continue;
> + }
> +
> + hw = dpu_hw_sspp_init(sspp->id, mmio, cat);
> + if (IS_ERR(hw)) {
> + rc = PTR_ERR(hw);
> + DPU_ERROR("failed sspp object creation: err %d\n", rc);
> + goto fail;
> + }
> + rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
> + }
> +
> return 0;
>
> fail:
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 59de72b381f9..d62c2edb2460 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -21,6 +21,7 @@ struct dpu_global_state;
> * @hw_intf: array of intf hardware resources
> * @hw_wb: array of wb hardware resources
> * @dspp_blks: array of dspp hardware resources
> + * @hw_sspp: array of sspp hardware resources
> */
> struct dpu_rm {
> struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
> @@ -31,6 +32,7 @@ struct dpu_rm {
> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
> struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
> + struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
> };
>
> /**
> @@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_
> return rm->hw_wb[wb_idx - WB_0];
> }
>
> +/**
> + * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
> + * @rm: DPU Resource Manager handle
> + * @sspp_idx: SSPP index
> + */
> +static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
> +{
> + return rm->hw_sspp[sspp_idx - SSPP_NONE];
> +}
> +
> #endif /* __DPU_RM_H__ */
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 03/27] drm/msm/dpu: move SSPP allocation to the RM
2023-01-26 23:29 ` Abhinav Kumar
@ 2023-01-27 5:56 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-27 5:56 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On Fri, 27 Jan 2023 at 01:29, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> > Follow the example of all other hw blocks and initialize SSPP blocks in
> > Resource Manager.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++-------------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++
> > 3 files changed, 38 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index e1cdd71716f0..e443799de2c1 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -1275,8 +1275,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
> > /* this will destroy the states as well */
> > drm_plane_cleanup(plane);
> >
> > - dpu_hw_sspp_destroy(pdpu->pipe_hw);
> > -
> We removed from here so the flow will be msm_drm_uninit calls
> drm_mode_config_cleanup() which will call kms->destroy() which shall
> call dpu_rm_destroy() where this will be released now right?
Yes. _dpu_kms_hw_destroy() calls dpu_rm_destroy(), which destroys all
RM-allocated objects.
>
>
> > kfree(pdpu);
> > }
> > }
> > @@ -1482,14 +1480,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> > pdpu->pipe = pipe;
> >
> > /* initialize underlying h/w driver */
> > - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
> > - if (IS_ERR(pdpu->pipe_hw)) {
> > - DPU_ERROR("[%u]SSPP init failed\n", pipe);
> > - ret = PTR_ERR(pdpu->pipe_hw);
> > + pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
> > + if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> > + DPU_ERROR("[%u]SSPP is invalid\n", pipe);
>
> I know this was existing code but can there be a case where pipe_hw->cap
> exists but pipe_hw->cap->sblk doesnt?
There is none up to now, granted that SSPP has a lot of extra data in
sblk. However, as you said, it's an existing code. No need to change
it here. And it's good as a safety net.
Granted that SRC offset is always 0, we can safely drop the src_sblk
and always access it via main register space.
>
> > goto clean_plane;
> > - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> > - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
> > - goto clean_sspp;
> > }
> >
> > format_list = pdpu->pipe_hw->cap->sblk->format_list;
> > @@ -1499,7 +1493,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> > format_list, num_formats,
> > supported_format_modifiers, type, NULL);
> > if (ret)
> > - goto clean_sspp;
> > + goto clean_plane;
> >
> > pdpu->catalog = kms->catalog;
> >
> > @@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> > pipe, plane->base.id);
> > return plane;
> >
> > -clean_sspp:
> > - if (pdpu && pdpu->pipe_hw)
> > - dpu_hw_sspp_destroy(pdpu->pipe_hw);
> > clean_plane:
> > kfree(pdpu);
> > return ERR_PTR(ret);
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > index 73b3442e7467..0668009cc9ed 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > @@ -8,6 +8,7 @@
> > #include "dpu_hw_lm.h"
> > #include "dpu_hw_ctl.h"
> > #include "dpu_hw_pingpong.h"
> > +#include "dpu_hw_sspp.h"
> > #include "dpu_hw_intf.h"
> > #include "dpu_hw_wb.h"
> > #include "dpu_hw_dspp.h"
> > @@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
> > for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
> > dpu_hw_wb_destroy(rm->hw_wb[i]);
> >
> > + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++)
> > + dpu_hw_sspp_destroy(rm->hw_sspp[i]);
> > +
> > return 0;
> > }
> >
> > @@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm,
> > rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
> > }
> >
> > + for (i = 0; i < cat->sspp_count; i++) {
> > + struct dpu_hw_sspp *hw;
> > + const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
> > +
> > + if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
> > + DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
> > + continue;
> > + }
> > +
> > + hw = dpu_hw_sspp_init(sspp->id, mmio, cat);
> > + if (IS_ERR(hw)) {
> > + rc = PTR_ERR(hw);
> > + DPU_ERROR("failed sspp object creation: err %d\n", rc);
> > + goto fail;
> > + }
> > + rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
> > + }
> > +
> > return 0;
> >
> > fail:
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > index 59de72b381f9..d62c2edb2460 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > @@ -21,6 +21,7 @@ struct dpu_global_state;
> > * @hw_intf: array of intf hardware resources
> > * @hw_wb: array of wb hardware resources
> > * @dspp_blks: array of dspp hardware resources
> > + * @hw_sspp: array of sspp hardware resources
> > */
> > struct dpu_rm {
> > struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
> > @@ -31,6 +32,7 @@ struct dpu_rm {
> > struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
> > struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
> > struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
> > + struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
> > };
> >
> > /**
> > @@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_
> > return rm->hw_wb[wb_idx - WB_0];
> > }
> >
> > +/**
> > + * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
> > + * @rm: DPU Resource Manager handle
> > + * @sspp_idx: SSPP index
> > + */
> > +static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
> > +{
> > + return rm->hw_sspp[sspp_idx - SSPP_NONE];
> > +}
> > +
> > #endif /* __DPU_RM_H__ */
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 03/27] drm/msm/dpu: move SSPP allocation to the RM
@ 2023-01-27 5:56 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-27 5:56 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On Fri, 27 Jan 2023 at 01:29, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> > Follow the example of all other hw blocks and initialize SSPP blocks in
> > Resource Manager.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++-------------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++
> > 3 files changed, 38 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index e1cdd71716f0..e443799de2c1 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -1275,8 +1275,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
> > /* this will destroy the states as well */
> > drm_plane_cleanup(plane);
> >
> > - dpu_hw_sspp_destroy(pdpu->pipe_hw);
> > -
> We removed from here so the flow will be msm_drm_uninit calls
> drm_mode_config_cleanup() which will call kms->destroy() which shall
> call dpu_rm_destroy() where this will be released now right?
Yes. _dpu_kms_hw_destroy() calls dpu_rm_destroy(), which destroys all
RM-allocated objects.
>
>
> > kfree(pdpu);
> > }
> > }
> > @@ -1482,14 +1480,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> > pdpu->pipe = pipe;
> >
> > /* initialize underlying h/w driver */
> > - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
> > - if (IS_ERR(pdpu->pipe_hw)) {
> > - DPU_ERROR("[%u]SSPP init failed\n", pipe);
> > - ret = PTR_ERR(pdpu->pipe_hw);
> > + pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
> > + if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> > + DPU_ERROR("[%u]SSPP is invalid\n", pipe);
>
> I know this was existing code but can there be a case where pipe_hw->cap
> exists but pipe_hw->cap->sblk doesnt?
There is none up to now, granted that SSPP has a lot of extra data in
sblk. However, as you said, it's an existing code. No need to change
it here. And it's good as a safety net.
Granted that SRC offset is always 0, we can safely drop the src_sblk
and always access it via main register space.
>
> > goto clean_plane;
> > - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> > - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
> > - goto clean_sspp;
> > }
> >
> > format_list = pdpu->pipe_hw->cap->sblk->format_list;
> > @@ -1499,7 +1493,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> > format_list, num_formats,
> > supported_format_modifiers, type, NULL);
> > if (ret)
> > - goto clean_sspp;
> > + goto clean_plane;
> >
> > pdpu->catalog = kms->catalog;
> >
> > @@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> > pipe, plane->base.id);
> > return plane;
> >
> > -clean_sspp:
> > - if (pdpu && pdpu->pipe_hw)
> > - dpu_hw_sspp_destroy(pdpu->pipe_hw);
> > clean_plane:
> > kfree(pdpu);
> > return ERR_PTR(ret);
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > index 73b3442e7467..0668009cc9ed 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > @@ -8,6 +8,7 @@
> > #include "dpu_hw_lm.h"
> > #include "dpu_hw_ctl.h"
> > #include "dpu_hw_pingpong.h"
> > +#include "dpu_hw_sspp.h"
> > #include "dpu_hw_intf.h"
> > #include "dpu_hw_wb.h"
> > #include "dpu_hw_dspp.h"
> > @@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
> > for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
> > dpu_hw_wb_destroy(rm->hw_wb[i]);
> >
> > + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++)
> > + dpu_hw_sspp_destroy(rm->hw_sspp[i]);
> > +
> > return 0;
> > }
> >
> > @@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm,
> > rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
> > }
> >
> > + for (i = 0; i < cat->sspp_count; i++) {
> > + struct dpu_hw_sspp *hw;
> > + const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
> > +
> > + if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
> > + DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
> > + continue;
> > + }
> > +
> > + hw = dpu_hw_sspp_init(sspp->id, mmio, cat);
> > + if (IS_ERR(hw)) {
> > + rc = PTR_ERR(hw);
> > + DPU_ERROR("failed sspp object creation: err %d\n", rc);
> > + goto fail;
> > + }
> > + rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
> > + }
> > +
> > return 0;
> >
> > fail:
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > index 59de72b381f9..d62c2edb2460 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > @@ -21,6 +21,7 @@ struct dpu_global_state;
> > * @hw_intf: array of intf hardware resources
> > * @hw_wb: array of wb hardware resources
> > * @dspp_blks: array of dspp hardware resources
> > + * @hw_sspp: array of sspp hardware resources
> > */
> > struct dpu_rm {
> > struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
> > @@ -31,6 +32,7 @@ struct dpu_rm {
> > struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
> > struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
> > struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
> > + struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
> > };
> >
> > /**
> > @@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_
> > return rm->hw_wb[wb_idx - WB_0];
> > }
> >
> > +/**
> > + * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
> > + * @rm: DPU Resource Manager handle
> > + * @sspp_idx: SSPP index
> > + */
> > +static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
> > +{
> > + return rm->hw_sspp[sspp_idx - SSPP_NONE];
> > +}
> > +
> > #endif /* __DPU_RM_H__ */
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 03/27] drm/msm/dpu: move SSPP allocation to the RM
2023-01-27 5:56 ` Dmitry Baryshkov
@ 2023-01-27 22:59 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-27 22:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 1/26/2023 9:56 PM, Dmitry Baryshkov wrote:
> On Fri, 27 Jan 2023 at 01:29, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> Follow the example of all other hw blocks and initialize SSPP blocks in
>>> Resource Manager.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++-------------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++
>>> 3 files changed, 38 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> index e1cdd71716f0..e443799de2c1 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> @@ -1275,8 +1275,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
>>> /* this will destroy the states as well */
>>> drm_plane_cleanup(plane);
>>>
>>> - dpu_hw_sspp_destroy(pdpu->pipe_hw);
>>> -
>> We removed from here so the flow will be msm_drm_uninit calls
>> drm_mode_config_cleanup() which will call kms->destroy() which shall
>> call dpu_rm_destroy() where this will be released now right?
>
> Yes. _dpu_kms_hw_destroy() calls dpu_rm_destroy(), which destroys all
> RM-allocated objects.
>
Ack, thanks
>>
>>
>>> kfree(pdpu);
>>> }
>>> }
>>> @@ -1482,14 +1480,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>>> pdpu->pipe = pipe;
>>>
>>> /* initialize underlying h/w driver */
>>> - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
>>> - if (IS_ERR(pdpu->pipe_hw)) {
>>> - DPU_ERROR("[%u]SSPP init failed\n", pipe);
>>> - ret = PTR_ERR(pdpu->pipe_hw);
>>> + pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
>>> + if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
>>> + DPU_ERROR("[%u]SSPP is invalid\n", pipe);
>>
>> I know this was existing code but can there be a case where pipe_hw->cap
>> exists but pipe_hw->cap->sblk doesnt?
>
> There is none up to now, granted that SSPP has a lot of extra data in
> sblk. However, as you said, it's an existing code. No need to change
> it here. And it's good as a safety net.
> Granted that SRC offset is always 0, we can safely drop the src_sblk
> and always access it via main register space.
>
Alright, since this is existing code, lets have it as a separate change.
Hence,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>>> goto clean_plane;
>>> - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
>>> - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
>>> - goto clean_sspp;
>>> }
>>>
>>> format_list = pdpu->pipe_hw->cap->sblk->format_list;
>>> @@ -1499,7 +1493,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>>> format_list, num_formats,
>>> supported_format_modifiers, type, NULL);
>>> if (ret)
>>> - goto clean_sspp;
>>> + goto clean_plane;
>>>
>>> pdpu->catalog = kms->catalog;
>>>
>>> @@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>>> pipe, plane->base.id);
>>> return plane;
>>>
>>> -clean_sspp:
>>> - if (pdpu && pdpu->pipe_hw)
>>> - dpu_hw_sspp_destroy(pdpu->pipe_hw);
>>> clean_plane:
>>> kfree(pdpu);
>>> return ERR_PTR(ret);
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> index 73b3442e7467..0668009cc9ed 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> @@ -8,6 +8,7 @@
>>> #include "dpu_hw_lm.h"
>>> #include "dpu_hw_ctl.h"
>>> #include "dpu_hw_pingpong.h"
>>> +#include "dpu_hw_sspp.h"
>>> #include "dpu_hw_intf.h"
>>> #include "dpu_hw_wb.h"
>>> #include "dpu_hw_dspp.h"
>>> @@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
>>> for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
>>> dpu_hw_wb_destroy(rm->hw_wb[i]);
>>>
>>> + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++)
>>> + dpu_hw_sspp_destroy(rm->hw_sspp[i]);
>>> +
>>> return 0;
>>> }
>>>
>>> @@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm,
>>> rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
>>> }
>>>
>>> + for (i = 0; i < cat->sspp_count; i++) {
>>> + struct dpu_hw_sspp *hw;
>>> + const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
>>> +
>>> + if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
>>> + DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
>>> + continue;
>>> + }
>>> +
>>> + hw = dpu_hw_sspp_init(sspp->id, mmio, cat);
>>> + if (IS_ERR(hw)) {
>>> + rc = PTR_ERR(hw);
>>> + DPU_ERROR("failed sspp object creation: err %d\n", rc);
>>> + goto fail;
>>> + }
>>> + rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
>>> + }
>>> +
>>> return 0;
>>>
>>> fail:
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> index 59de72b381f9..d62c2edb2460 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> @@ -21,6 +21,7 @@ struct dpu_global_state;
>>> * @hw_intf: array of intf hardware resources
>>> * @hw_wb: array of wb hardware resources
>>> * @dspp_blks: array of dspp hardware resources
>>> + * @hw_sspp: array of sspp hardware resources
>>> */
>>> struct dpu_rm {
>>> struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
>>> @@ -31,6 +32,7 @@ struct dpu_rm {
>>> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
>>> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
>>> struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
>>> + struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
>>> };
>>>
>>> /**
>>> @@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_
>>> return rm->hw_wb[wb_idx - WB_0];
>>> }
>>>
>>> +/**
>>> + * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
>>> + * @rm: DPU Resource Manager handle
>>> + * @sspp_idx: SSPP index
>>> + */
>>> +static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
>>> +{
>>> + return rm->hw_sspp[sspp_idx - SSPP_NONE];
>>> +}
>>> +
>>> #endif /* __DPU_RM_H__ */
>>>
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 03/27] drm/msm/dpu: move SSPP allocation to the RM
@ 2023-01-27 22:59 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-27 22:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 1/26/2023 9:56 PM, Dmitry Baryshkov wrote:
> On Fri, 27 Jan 2023 at 01:29, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> Follow the example of all other hw blocks and initialize SSPP blocks in
>>> Resource Manager.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++-------------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++
>>> 3 files changed, 38 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> index e1cdd71716f0..e443799de2c1 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> @@ -1275,8 +1275,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
>>> /* this will destroy the states as well */
>>> drm_plane_cleanup(plane);
>>>
>>> - dpu_hw_sspp_destroy(pdpu->pipe_hw);
>>> -
>> We removed from here so the flow will be msm_drm_uninit calls
>> drm_mode_config_cleanup() which will call kms->destroy() which shall
>> call dpu_rm_destroy() where this will be released now right?
>
> Yes. _dpu_kms_hw_destroy() calls dpu_rm_destroy(), which destroys all
> RM-allocated objects.
>
Ack, thanks
>>
>>
>>> kfree(pdpu);
>>> }
>>> }
>>> @@ -1482,14 +1480,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>>> pdpu->pipe = pipe;
>>>
>>> /* initialize underlying h/w driver */
>>> - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog);
>>> - if (IS_ERR(pdpu->pipe_hw)) {
>>> - DPU_ERROR("[%u]SSPP init failed\n", pipe);
>>> - ret = PTR_ERR(pdpu->pipe_hw);
>>> + pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
>>> + if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
>>> + DPU_ERROR("[%u]SSPP is invalid\n", pipe);
>>
>> I know this was existing code but can there be a case where pipe_hw->cap
>> exists but pipe_hw->cap->sblk doesnt?
>
> There is none up to now, granted that SSPP has a lot of extra data in
> sblk. However, as you said, it's an existing code. No need to change
> it here. And it's good as a safety net.
> Granted that SRC offset is always 0, we can safely drop the src_sblk
> and always access it via main register space.
>
Alright, since this is existing code, lets have it as a separate change.
Hence,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>>> goto clean_plane;
>>> - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
>>> - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
>>> - goto clean_sspp;
>>> }
>>>
>>> format_list = pdpu->pipe_hw->cap->sblk->format_list;
>>> @@ -1499,7 +1493,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>>> format_list, num_formats,
>>> supported_format_modifiers, type, NULL);
>>> if (ret)
>>> - goto clean_sspp;
>>> + goto clean_plane;
>>>
>>> pdpu->catalog = kms->catalog;
>>>
>>> @@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>>> pipe, plane->base.id);
>>> return plane;
>>>
>>> -clean_sspp:
>>> - if (pdpu && pdpu->pipe_hw)
>>> - dpu_hw_sspp_destroy(pdpu->pipe_hw);
>>> clean_plane:
>>> kfree(pdpu);
>>> return ERR_PTR(ret);
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> index 73b3442e7467..0668009cc9ed 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> @@ -8,6 +8,7 @@
>>> #include "dpu_hw_lm.h"
>>> #include "dpu_hw_ctl.h"
>>> #include "dpu_hw_pingpong.h"
>>> +#include "dpu_hw_sspp.h"
>>> #include "dpu_hw_intf.h"
>>> #include "dpu_hw_wb.h"
>>> #include "dpu_hw_dspp.h"
>>> @@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
>>> for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
>>> dpu_hw_wb_destroy(rm->hw_wb[i]);
>>>
>>> + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++)
>>> + dpu_hw_sspp_destroy(rm->hw_sspp[i]);
>>> +
>>> return 0;
>>> }
>>>
>>> @@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm,
>>> rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
>>> }
>>>
>>> + for (i = 0; i < cat->sspp_count; i++) {
>>> + struct dpu_hw_sspp *hw;
>>> + const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
>>> +
>>> + if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
>>> + DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
>>> + continue;
>>> + }
>>> +
>>> + hw = dpu_hw_sspp_init(sspp->id, mmio, cat);
>>> + if (IS_ERR(hw)) {
>>> + rc = PTR_ERR(hw);
>>> + DPU_ERROR("failed sspp object creation: err %d\n", rc);
>>> + goto fail;
>>> + }
>>> + rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
>>> + }
>>> +
>>> return 0;
>>>
>>> fail:
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> index 59de72b381f9..d62c2edb2460 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>>> @@ -21,6 +21,7 @@ struct dpu_global_state;
>>> * @hw_intf: array of intf hardware resources
>>> * @hw_wb: array of wb hardware resources
>>> * @dspp_blks: array of dspp hardware resources
>>> + * @hw_sspp: array of sspp hardware resources
>>> */
>>> struct dpu_rm {
>>> struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
>>> @@ -31,6 +32,7 @@ struct dpu_rm {
>>> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
>>> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
>>> struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
>>> + struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
>>> };
>>>
>>> /**
>>> @@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_
>>> return rm->hw_wb[wb_idx - WB_0];
>>> }
>>>
>>> +/**
>>> + * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
>>> + * @rm: DPU Resource Manager handle
>>> + * @sspp_idx: SSPP index
>>> + */
>>> +static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
>>> +{
>>> + return rm->hw_sspp[sspp_idx - SSPP_NONE];
>>> +}
>>> +
>>> #endif /* __DPU_RM_H__ */
>>>
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 04/27] drm/msm/dpu: move SSPP debugfs creation to dpu_kms.c
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
As SSPP blocks are now visible through dpu_kms->rm.sspp_blocks, move
SSPP debugfs creation from dpu_plane to dpu_kms. We are going to break
the 1:1 correspondence between planes and SSPPs, so it makes no sense
anymore to create SSPP debugfs entries in dpu_plane.c
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 ++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 ----------------
3 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 651621b9794f..8c3e9090be4b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -388,7 +388,6 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
*/
void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
-void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
#endif /*_DPU_HW_SSPP_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index b71199511a52..2dfc4748a0e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -250,6 +250,24 @@ void dpu_debugfs_create_regset32(const char *name, umode_t mode,
debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops);
}
+static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
+{
+ struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
+ int i;
+
+ if (IS_ERR(entry))
+ return;
+
+ for (i = SSPP_NONE; i < SSPP_MAX; i++) {
+ struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i);
+
+ if (!hw)
+ continue;
+
+ _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry);
+ }
+}
+
static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
{
struct dpu_kms *dpu_kms = to_dpu_kms(kms);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index e443799de2c1..cdde7b9ec882 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1399,22 +1399,6 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
_dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
}
-
-/* SSPP live inside dpu_plane private data only. Enumerate them here. */
-void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
-{
- struct drm_plane *plane;
- struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
-
- if (IS_ERR(entry))
- return;
-
- drm_for_each_plane(plane, dpu_kms->dev) {
- struct dpu_plane *pdpu = to_dpu_plane(plane);
-
- _dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry);
- }
-}
#endif
static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 04/27] drm/msm/dpu: move SSPP debugfs creation to dpu_kms.c
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
As SSPP blocks are now visible through dpu_kms->rm.sspp_blocks, move
SSPP debugfs creation from dpu_plane to dpu_kms. We are going to break
the 1:1 correspondence between planes and SSPPs, so it makes no sense
anymore to create SSPP debugfs entries in dpu_plane.c
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 ++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 ----------------
3 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 651621b9794f..8c3e9090be4b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -388,7 +388,6 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
*/
void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);
-void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
#endif /*_DPU_HW_SSPP_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index b71199511a52..2dfc4748a0e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -250,6 +250,24 @@ void dpu_debugfs_create_regset32(const char *name, umode_t mode,
debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops);
}
+static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
+{
+ struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
+ int i;
+
+ if (IS_ERR(entry))
+ return;
+
+ for (i = SSPP_NONE; i < SSPP_MAX; i++) {
+ struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i);
+
+ if (!hw)
+ continue;
+
+ _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry);
+ }
+}
+
static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
{
struct dpu_kms *dpu_kms = to_dpu_kms(kms);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index e443799de2c1..cdde7b9ec882 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1399,22 +1399,6 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
_dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
}
-
-/* SSPP live inside dpu_plane private data only. Enumerate them here. */
-void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
-{
- struct drm_plane *plane;
- struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
-
- if (IS_ERR(entry))
- return;
-
- drm_for_each_plane(plane, dpu_kms->dev) {
- struct dpu_plane *pdpu = to_dpu_plane(plane);
-
- _dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry);
- }
-}
#endif
static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
The pipe's layout is not cached, corresponding data structure is zeroed
out each time in the dpu_plane_sspp_atomic_update(), right before the
call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
Drop plane_addr comparison against previous layout and corresponding
EAGAIN handling.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +---------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +---
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index d95540309d4d..ec1001e10f4f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -918,8 +918,7 @@ int dpu_format_populate_layout(
struct drm_framebuffer *fb,
struct dpu_hw_fmt_layout *layout)
{
- uint32_t plane_addr[DPU_MAX_PLANES];
- int i, ret;
+ int ret;
if (!fb || !layout) {
DRM_ERROR("invalid arguments\n");
@@ -940,9 +939,6 @@ int dpu_format_populate_layout(
if (ret)
return ret;
- for (i = 0; i < DPU_MAX_PLANES; ++i)
- plane_addr[i] = layout->plane_addr[i];
-
/* Populate the addresses given the fb */
if (DPU_FORMAT_IS_UBWC(layout->format) ||
DPU_FORMAT_IS_TILE(layout->format))
@@ -950,10 +946,6 @@ int dpu_format_populate_layout(
else
ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
- /* check if anything changed */
- if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
- ret = -EAGAIN;
-
return ret;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index cdde7b9ec882..43fb8e00ada6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
int ret;
ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
- if (ret == -EAGAIN)
- DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
- else if (ret)
+ if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
The pipe's layout is not cached, corresponding data structure is zeroed
out each time in the dpu_plane_sspp_atomic_update(), right before the
call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
Drop plane_addr comparison against previous layout and corresponding
EAGAIN handling.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +---------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +---
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index d95540309d4d..ec1001e10f4f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -918,8 +918,7 @@ int dpu_format_populate_layout(
struct drm_framebuffer *fb,
struct dpu_hw_fmt_layout *layout)
{
- uint32_t plane_addr[DPU_MAX_PLANES];
- int i, ret;
+ int ret;
if (!fb || !layout) {
DRM_ERROR("invalid arguments\n");
@@ -940,9 +939,6 @@ int dpu_format_populate_layout(
if (ret)
return ret;
- for (i = 0; i < DPU_MAX_PLANES; ++i)
- plane_addr[i] = layout->plane_addr[i];
-
/* Populate the addresses given the fb */
if (DPU_FORMAT_IS_UBWC(layout->format) ||
DPU_FORMAT_IS_TILE(layout->format))
@@ -950,10 +946,6 @@ int dpu_format_populate_layout(
else
ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
- /* check if anything changed */
- if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
- ret = -EAGAIN;
-
return ret;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index cdde7b9ec882..43fb8e00ada6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
int ret;
ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
- if (ret == -EAGAIN)
- DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
- else if (ret)
+ if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2023-01-27 0:52 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-27 0:52 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> The pipe's layout is not cached, corresponding data structure is zeroed
> out each time in the dpu_plane_sspp_atomic_update(), right before the
> call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
>
> Drop plane_addr comparison against previous layout and corresponding
> EAGAIN handling.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
The change itself LGTM, hence
But, shouldnt we add this EAGAIN validation or in other words fix this
rather than drop this?
Like I wrote in the review last time, this makes sure to fail the commit
if the same addr is being programmed.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +---------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +---
> 2 files changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> index d95540309d4d..ec1001e10f4f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> @@ -918,8 +918,7 @@ int dpu_format_populate_layout(
> struct drm_framebuffer *fb,
> struct dpu_hw_fmt_layout *layout)
> {
> - uint32_t plane_addr[DPU_MAX_PLANES];
> - int i, ret;
> + int ret;
>
> if (!fb || !layout) {
> DRM_ERROR("invalid arguments\n");
> @@ -940,9 +939,6 @@ int dpu_format_populate_layout(
> if (ret)
> return ret;
>
> - for (i = 0; i < DPU_MAX_PLANES; ++i)
> - plane_addr[i] = layout->plane_addr[i];
> -
> /* Populate the addresses given the fb */
> if (DPU_FORMAT_IS_UBWC(layout->format) ||
> DPU_FORMAT_IS_TILE(layout->format))
> @@ -950,10 +946,6 @@ int dpu_format_populate_layout(
> else
> ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
>
> - /* check if anything changed */
> - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
> - ret = -EAGAIN;
> -
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index cdde7b9ec882..43fb8e00ada6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
> int ret;
>
> ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> - if (ret == -EAGAIN)
> - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
> - else if (ret)
> + if (ret)
> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
> trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
@ 2023-01-27 0:52 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-27 0:52 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> The pipe's layout is not cached, corresponding data structure is zeroed
> out each time in the dpu_plane_sspp_atomic_update(), right before the
> call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
>
> Drop plane_addr comparison against previous layout and corresponding
> EAGAIN handling.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
The change itself LGTM, hence
But, shouldnt we add this EAGAIN validation or in other words fix this
rather than drop this?
Like I wrote in the review last time, this makes sure to fail the commit
if the same addr is being programmed.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +---------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +---
> 2 files changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> index d95540309d4d..ec1001e10f4f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> @@ -918,8 +918,7 @@ int dpu_format_populate_layout(
> struct drm_framebuffer *fb,
> struct dpu_hw_fmt_layout *layout)
> {
> - uint32_t plane_addr[DPU_MAX_PLANES];
> - int i, ret;
> + int ret;
>
> if (!fb || !layout) {
> DRM_ERROR("invalid arguments\n");
> @@ -940,9 +939,6 @@ int dpu_format_populate_layout(
> if (ret)
> return ret;
>
> - for (i = 0; i < DPU_MAX_PLANES; ++i)
> - plane_addr[i] = layout->plane_addr[i];
> -
> /* Populate the addresses given the fb */
> if (DPU_FORMAT_IS_UBWC(layout->format) ||
> DPU_FORMAT_IS_TILE(layout->format))
> @@ -950,10 +946,6 @@ int dpu_format_populate_layout(
> else
> ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
>
> - /* check if anything changed */
> - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
> - ret = -EAGAIN;
> -
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index cdde7b9ec882..43fb8e00ada6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
> int ret;
>
> ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> - if (ret == -EAGAIN)
> - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
> - else if (ret)
> + if (ret)
> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
> trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
2023-01-27 0:52 ` Abhinav Kumar
@ 2023-01-27 6:05 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-27 6:05 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On Fri, 27 Jan 2023 at 02:52, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> > The pipe's layout is not cached, corresponding data structure is zeroed
> > out each time in the dpu_plane_sspp_atomic_update(), right before the
> > call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
> >
> > Drop plane_addr comparison against previous layout and corresponding
> > EAGAIN handling.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> The change itself LGTM, hence
>
> But, shouldnt we add this EAGAIN validation or in other words fix this
> rather than drop this?
What for? Does it really save us anything? What's the price of
re-programming the SSPP_SRC0_ADDR registers?
>
> Like I wrote in the review last time, this makes sure to fail the commit
> if the same addr is being programmed.
First, there is nothing wrong with committing the same source addr.
For example setting the atomic property incurs an internal
drm_atomic_commit() with no change to addresses at all.
And then, this doesn't make atomic_commit fail. Instead it just
shortcuts a call to SSPP->setup_sourceaddress.
>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +---------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +---
> > 2 files changed, 2 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > index d95540309d4d..ec1001e10f4f 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > @@ -918,8 +918,7 @@ int dpu_format_populate_layout(
> > struct drm_framebuffer *fb,
> > struct dpu_hw_fmt_layout *layout)
> > {
> > - uint32_t plane_addr[DPU_MAX_PLANES];
> > - int i, ret;
> > + int ret;
> >
> > if (!fb || !layout) {
> > DRM_ERROR("invalid arguments\n");
> > @@ -940,9 +939,6 @@ int dpu_format_populate_layout(
> > if (ret)
> > return ret;
> >
> > - for (i = 0; i < DPU_MAX_PLANES; ++i)
> > - plane_addr[i] = layout->plane_addr[i];
> > -
> > /* Populate the addresses given the fb */
> > if (DPU_FORMAT_IS_UBWC(layout->format) ||
> > DPU_FORMAT_IS_TILE(layout->format))
> > @@ -950,10 +946,6 @@ int dpu_format_populate_layout(
> > else
> > ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
> >
> > - /* check if anything changed */
> > - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
> > - ret = -EAGAIN;
> > -
> > return ret;
> > }
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index cdde7b9ec882..43fb8e00ada6 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
> > int ret;
> >
> > ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> > - if (ret == -EAGAIN)
> > - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
> > - else if (ret)
> > + if (ret)
> > DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> > else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
> > trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
@ 2023-01-27 6:05 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-27 6:05 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On Fri, 27 Jan 2023 at 02:52, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> > The pipe's layout is not cached, corresponding data structure is zeroed
> > out each time in the dpu_plane_sspp_atomic_update(), right before the
> > call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
> >
> > Drop plane_addr comparison against previous layout and corresponding
> > EAGAIN handling.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> The change itself LGTM, hence
>
> But, shouldnt we add this EAGAIN validation or in other words fix this
> rather than drop this?
What for? Does it really save us anything? What's the price of
re-programming the SSPP_SRC0_ADDR registers?
>
> Like I wrote in the review last time, this makes sure to fail the commit
> if the same addr is being programmed.
First, there is nothing wrong with committing the same source addr.
For example setting the atomic property incurs an internal
drm_atomic_commit() with no change to addresses at all.
And then, this doesn't make atomic_commit fail. Instead it just
shortcuts a call to SSPP->setup_sourceaddress.
>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +---------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +---
> > 2 files changed, 2 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > index d95540309d4d..ec1001e10f4f 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > @@ -918,8 +918,7 @@ int dpu_format_populate_layout(
> > struct drm_framebuffer *fb,
> > struct dpu_hw_fmt_layout *layout)
> > {
> > - uint32_t plane_addr[DPU_MAX_PLANES];
> > - int i, ret;
> > + int ret;
> >
> > if (!fb || !layout) {
> > DRM_ERROR("invalid arguments\n");
> > @@ -940,9 +939,6 @@ int dpu_format_populate_layout(
> > if (ret)
> > return ret;
> >
> > - for (i = 0; i < DPU_MAX_PLANES; ++i)
> > - plane_addr[i] = layout->plane_addr[i];
> > -
> > /* Populate the addresses given the fb */
> > if (DPU_FORMAT_IS_UBWC(layout->format) ||
> > DPU_FORMAT_IS_TILE(layout->format))
> > @@ -950,10 +946,6 @@ int dpu_format_populate_layout(
> > else
> > ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
> >
> > - /* check if anything changed */
> > - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
> > - ret = -EAGAIN;
> > -
> > return ret;
> > }
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index cdde7b9ec882..43fb8e00ada6 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
> > int ret;
> >
> > ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> > - if (ret == -EAGAIN)
> > - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
> > - else if (ret)
> > + if (ret)
> > DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> > else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
> > trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
2023-01-27 6:05 ` Dmitry Baryshkov
@ 2023-01-27 23:59 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-27 23:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 1/26/2023 10:05 PM, Dmitry Baryshkov wrote:
> On Fri, 27 Jan 2023 at 02:52, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> The pipe's layout is not cached, corresponding data structure is zeroed
>>> out each time in the dpu_plane_sspp_atomic_update(), right before the
>>> call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
>>>
>>> Drop plane_addr comparison against previous layout and corresponding
>>> EAGAIN handling.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>
>> The change itself LGTM, hence
>>
>> But, shouldnt we add this EAGAIN validation or in other words fix this
>> rather than drop this?
>
> What for? Does it really save us anything? What's the price of
> re-programming the SSPP_SRC0_ADDR registers?
>
There are 4 Src registers being programmed per sspp.
With number of layers going up this will be 4x.
So lets say there are 5 layers and only one of their address has
changed, we need to reprogram only 4 regs but now will reprogram 20.
Thats why i thought this is a good optimization.
But still, that is a separate change so I am fine if this goes in first
as its just removing dead code anyway.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>> Like I wrote in the review last time, this makes sure to fail the commit
>> if the same addr is being programmed.
>
> First, there is nothing wrong with committing the same source addr.
> For example setting the atomic property incurs an internal
> drm_atomic_commit() with no change to addresses at all.
> And then, this doesn't make atomic_commit fail. Instead it just
> shortcuts a call to SSPP->setup_sourceaddress.
>
Ack, yes it wont fail the commit but will skip programming the new address.
>>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +---------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +---
>>> 2 files changed, 2 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
>>> index d95540309d4d..ec1001e10f4f 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
>>> @@ -918,8 +918,7 @@ int dpu_format_populate_layout(
>>> struct drm_framebuffer *fb,
>>> struct dpu_hw_fmt_layout *layout)
>>> {
>>> - uint32_t plane_addr[DPU_MAX_PLANES];
>>> - int i, ret;
>>> + int ret;
>>>
>>> if (!fb || !layout) {
>>> DRM_ERROR("invalid arguments\n");
>>> @@ -940,9 +939,6 @@ int dpu_format_populate_layout(
>>> if (ret)
>>> return ret;
>>>
>>> - for (i = 0; i < DPU_MAX_PLANES; ++i)
>>> - plane_addr[i] = layout->plane_addr[i];
>>> -
>>> /* Populate the addresses given the fb */
>>> if (DPU_FORMAT_IS_UBWC(layout->format) ||
>>> DPU_FORMAT_IS_TILE(layout->format))
>>> @@ -950,10 +946,6 @@ int dpu_format_populate_layout(
>>> else
>>> ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
>>>
>>> - /* check if anything changed */
>>> - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
>>> - ret = -EAGAIN;
>>> -
>>> return ret;
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> index cdde7b9ec882..43fb8e00ada6 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> @@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
>>> int ret;
>>>
>>> ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
>>> - if (ret == -EAGAIN)
>>> - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
>>> - else if (ret)
>>> + if (ret)
>>> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
>>> else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
>>> trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
@ 2023-01-27 23:59 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-27 23:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 1/26/2023 10:05 PM, Dmitry Baryshkov wrote:
> On Fri, 27 Jan 2023 at 02:52, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> The pipe's layout is not cached, corresponding data structure is zeroed
>>> out each time in the dpu_plane_sspp_atomic_update(), right before the
>>> call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
>>>
>>> Drop plane_addr comparison against previous layout and corresponding
>>> EAGAIN handling.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>
>> The change itself LGTM, hence
>>
>> But, shouldnt we add this EAGAIN validation or in other words fix this
>> rather than drop this?
>
> What for? Does it really save us anything? What's the price of
> re-programming the SSPP_SRC0_ADDR registers?
>
There are 4 Src registers being programmed per sspp.
With number of layers going up this will be 4x.
So lets say there are 5 layers and only one of their address has
changed, we need to reprogram only 4 regs but now will reprogram 20.
Thats why i thought this is a good optimization.
But still, that is a separate change so I am fine if this goes in first
as its just removing dead code anyway.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>> Like I wrote in the review last time, this makes sure to fail the commit
>> if the same addr is being programmed.
>
> First, there is nothing wrong with committing the same source addr.
> For example setting the atomic property incurs an internal
> drm_atomic_commit() with no change to addresses at all.
> And then, this doesn't make atomic_commit fail. Instead it just
> shortcuts a call to SSPP->setup_sourceaddress.
>
Ack, yes it wont fail the commit but will skip programming the new address.
>>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +---------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +---
>>> 2 files changed, 2 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
>>> index d95540309d4d..ec1001e10f4f 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
>>> @@ -918,8 +918,7 @@ int dpu_format_populate_layout(
>>> struct drm_framebuffer *fb,
>>> struct dpu_hw_fmt_layout *layout)
>>> {
>>> - uint32_t plane_addr[DPU_MAX_PLANES];
>>> - int i, ret;
>>> + int ret;
>>>
>>> if (!fb || !layout) {
>>> DRM_ERROR("invalid arguments\n");
>>> @@ -940,9 +939,6 @@ int dpu_format_populate_layout(
>>> if (ret)
>>> return ret;
>>>
>>> - for (i = 0; i < DPU_MAX_PLANES; ++i)
>>> - plane_addr[i] = layout->plane_addr[i];
>>> -
>>> /* Populate the addresses given the fb */
>>> if (DPU_FORMAT_IS_UBWC(layout->format) ||
>>> DPU_FORMAT_IS_TILE(layout->format))
>>> @@ -950,10 +946,6 @@ int dpu_format_populate_layout(
>>> else
>>> ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
>>>
>>> - /* check if anything changed */
>>> - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr)))
>>> - ret = -EAGAIN;
>>> -
>>> return ret;
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> index cdde7b9ec882..43fb8e00ada6 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> @@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
>>> int ret;
>>>
>>> ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
>>> - if (ret == -EAGAIN)
>>> - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
>>> - else if (ret)
>>> + if (ret)
>>> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
>>> else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
>>> trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
2023-01-27 23:59 ` Abhinav Kumar
@ 2023-02-03 14:16 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-03 14:16 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 28/01/2023 01:59, Abhinav Kumar wrote:
>
>
> On 1/26/2023 10:05 PM, Dmitry Baryshkov wrote:
>> On Fri, 27 Jan 2023 at 02:52, Abhinav Kumar
>> <quic_abhinavk@quicinc.com> wrote:
>>>
>>>
>>>
>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>> The pipe's layout is not cached, corresponding data structure is zeroed
>>>> out each time in the dpu_plane_sspp_atomic_update(), right before the
>>>> call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
>>>>
>>>> Drop plane_addr comparison against previous layout and corresponding
>>>> EAGAIN handling.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>
>>> The change itself LGTM, hence
>>>
>>> But, shouldnt we add this EAGAIN validation or in other words fix this
>>> rather than drop this?
>>
>> What for? Does it really save us anything? What's the price of
>> re-programming the SSPP_SRC0_ADDR registers?
>>
> There are 4 Src registers being programmed per sspp.
>
> With number of layers going up this will be 4x.
>
> So lets say there are 5 layers and only one of their address has
> changed, we need to reprogram only 4 regs but now will reprogram 20.
I think this was the original intention for this change, however the
implementation ended up being written in a way when this condition
doesn't trigger at all.
>
> Thats why i thought this is a good optimization.
>
> But still, that is a separate change so I am fine if this goes in first
> as its just removing dead code anyway.
>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
@ 2023-02-03 14:16 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-03 14:16 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 28/01/2023 01:59, Abhinav Kumar wrote:
>
>
> On 1/26/2023 10:05 PM, Dmitry Baryshkov wrote:
>> On Fri, 27 Jan 2023 at 02:52, Abhinav Kumar
>> <quic_abhinavk@quicinc.com> wrote:
>>>
>>>
>>>
>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>> The pipe's layout is not cached, corresponding data structure is zeroed
>>>> out each time in the dpu_plane_sspp_atomic_update(), right before the
>>>> call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
>>>>
>>>> Drop plane_addr comparison against previous layout and corresponding
>>>> EAGAIN handling.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>
>>> The change itself LGTM, hence
>>>
>>> But, shouldnt we add this EAGAIN validation or in other words fix this
>>> rather than drop this?
>>
>> What for? Does it really save us anything? What's the price of
>> re-programming the SSPP_SRC0_ADDR registers?
>>
> There are 4 Src registers being programmed per sspp.
>
> With number of layers going up this will be 4x.
>
> So lets say there are 5 layers and only one of their address has
> changed, we need to reprogram only 4 regs but now will reprogram 20.
I think this was the original intention for this change, however the
implementation ended up being written in a way when this condition
doesn't trigger at all.
>
> Thats why i thought this is a good optimization.
>
> But still, that is a separate change so I am fine if this goes in first
> as its just removing dead code anyway.
>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
2023-02-03 14:16 ` Dmitry Baryshkov
@ 2023-02-03 17:32 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-03 17:32 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 2/3/2023 6:16 AM, Dmitry Baryshkov wrote:
> On 28/01/2023 01:59, Abhinav Kumar wrote:
>>
>>
>> On 1/26/2023 10:05 PM, Dmitry Baryshkov wrote:
>>> On Fri, 27 Jan 2023 at 02:52, Abhinav Kumar
>>> <quic_abhinavk@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>>> The pipe's layout is not cached, corresponding data structure is
>>>>> zeroed
>>>>> out each time in the dpu_plane_sspp_atomic_update(), right before the
>>>>> call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
>>>>>
>>>>> Drop plane_addr comparison against previous layout and corresponding
>>>>> EAGAIN handling.
>>>>>
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>
>>>> The change itself LGTM, hence
>>>>
>>>> But, shouldnt we add this EAGAIN validation or in other words fix this
>>>> rather than drop this?
>>>
>>> What for? Does it really save us anything? What's the price of
>>> re-programming the SSPP_SRC0_ADDR registers?
>>>
>> There are 4 Src registers being programmed per sspp.
>>
>> With number of layers going up this will be 4x.
>>
>> So lets say there are 5 layers and only one of their address has
>> changed, we need to reprogram only 4 regs but now will reprogram 20.
>
> I think this was the original intention for this change, however the
> implementation ended up being written in a way when this condition
> doesn't trigger at all.
>
Yes, and thats why I wrote that we should fix this rather than drop this.
>>
>> Thats why i thought this is a good optimization.
>>
>> But still, that is a separate change so I am fine if this goes in
>> first as its just removing dead code anyway.
>>
>> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 05/27] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout
@ 2023-02-03 17:32 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-03 17:32 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 2/3/2023 6:16 AM, Dmitry Baryshkov wrote:
> On 28/01/2023 01:59, Abhinav Kumar wrote:
>>
>>
>> On 1/26/2023 10:05 PM, Dmitry Baryshkov wrote:
>>> On Fri, 27 Jan 2023 at 02:52, Abhinav Kumar
>>> <quic_abhinavk@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>>> The pipe's layout is not cached, corresponding data structure is
>>>>> zeroed
>>>>> out each time in the dpu_plane_sspp_atomic_update(), right before the
>>>>> call to _dpu_plane_set_scanout() -> dpu_format_populate_layout().
>>>>>
>>>>> Drop plane_addr comparison against previous layout and corresponding
>>>>> EAGAIN handling.
>>>>>
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>
>>>> The change itself LGTM, hence
>>>>
>>>> But, shouldnt we add this EAGAIN validation or in other words fix this
>>>> rather than drop this?
>>>
>>> What for? Does it really save us anything? What's the price of
>>> re-programming the SSPP_SRC0_ADDR registers?
>>>
>> There are 4 Src registers being programmed per sspp.
>>
>> With number of layers going up this will be 4x.
>>
>> So lets say there are 5 layers and only one of their address has
>> changed, we need to reprogram only 4 regs but now will reprogram 20.
>
> I think this was the original intention for this change, however the
> implementation ended up being written in a way when this condition
> doesn't trigger at all.
>
Yes, and thats why I wrote that we should fix this rather than drop this.
>>
>> Thats why i thought this is a good optimization.
>>
>> But still, that is a separate change so I am fine if this goes in
>> first as its just removing dead code anyway.
>>
>> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 06/27] drm/msm/dpu: move pipe_hw to dpu_plane_state
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
In preparation to adding fully virtualized planes, move struct
dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as
it will become a part of state (allocated during atomic check) rather
than part of a plane (allocated during boot).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 102 ++++++++++++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
2 files changed, 57 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 43fb8e00ada6..7ba954c7b3e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -104,7 +104,6 @@ struct dpu_plane {
enum dpu_sspp pipe;
- struct dpu_hw_sspp *pipe_hw;
uint32_t color_fill;
bool is_error;
bool is_rt_pipe;
@@ -279,6 +278,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
const struct dpu_format *fmt = NULL;
u64 qos_lut;
u32 total_fl = 0, lut_usage;
@@ -310,7 +310,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
fmt ? (char *)&fmt->base.pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, qos_lut);
- pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
+ pstate->pipe_hw->ops.setup_creq_lut(pstate->pipe_hw, qos_lut);
}
/**
@@ -322,6 +322,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
struct drm_framebuffer *fb)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
const struct dpu_format *fmt = NULL;
u32 danger_lut, safe_lut;
@@ -361,7 +362,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
danger_lut,
safe_lut);
- pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
+ pstate->pipe_hw->ops.setup_danger_safe_lut(pstate->pipe_hw,
danger_lut, safe_lut);
}
@@ -375,14 +376,15 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
bool enable, u32 flags)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
- pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
+ pipe_qos_cfg.creq_vblank = pstate->pipe_hw->cap->sblk->creq_vblank;
pipe_qos_cfg.danger_vblank =
- pdpu->pipe_hw->cap->sblk->danger_vblank;
+ pstate->pipe_hw->cap->sblk->danger_vblank;
pipe_qos_cfg.vblank_en = enable;
}
@@ -408,7 +410,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
pipe_qos_cfg.danger_vblank,
pdpu->is_rt_pipe);
- pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
+ pstate->pipe_hw->ops.setup_qos_ctrl(pstate->pipe_hw,
&pipe_qos_cfg);
}
@@ -422,18 +424,19 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_vbif_set_ot_params ot_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&ot_params, 0, sizeof(ot_params));
- ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
- ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
+ ot_params.xin_id = pstate->pipe_hw->cap->xin_id;
+ ot_params.num = pstate->pipe_hw->idx - SSPP_NONE;
ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
ot_params.is_wfd = !pdpu->is_rt_pipe;
ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
ot_params.vbif_idx = VBIF_RT;
- ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
+ ot_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
ot_params.rd = true;
dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
@@ -446,14 +449,15 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_vbif_set_qos_params qos_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = VBIF_RT;
- qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
- qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
- qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
+ qos_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
+ qos_params.xin_id = pstate->pipe_hw->cap->xin_id;
+ qos_params.num = pstate->pipe_hw->idx - SSPP_VIG0;
qos_params.is_rt = pdpu->is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
@@ -478,11 +482,11 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
- else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
+ else if (pstate->pipe_hw->ops.setup_sourceaddress) {
+ trace_dpu_plane_set_scanout(pstate->pipe_hw->idx,
&pipe_cfg->layout,
pstate->multirect_index);
- pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
+ pstate->pipe_hw->ops.setup_sourceaddress(pstate->pipe_hw, pipe_cfg,
pstate->multirect_index);
}
}
@@ -534,7 +538,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->src_height[i] /= chroma_subsmpl_v;
}
- if (pdpu->pipe_hw->cap->features &
+ if (pstate->pipe_hw->cap->features &
BIT(DPU_SSPP_SCALER_QSEED4)) {
scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
@@ -607,6 +611,7 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
{
+ struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state);
const struct dpu_csc_cfg *csc_ptr;
if (!pdpu) {
@@ -617,7 +622,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
if (!DPU_FORMAT_IS_YUV(fmt))
return NULL;
- if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features)
+ if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe_hw->cap->features)
csc_ptr = &dpu_csc10_YUV2RGB_601L;
else
csc_ptr = &dpu_csc_YUV2RGB_601L;
@@ -660,8 +665,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
_dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
src_width, src_height, info->hsub, info->vsub);
- if (pdpu->pipe_hw->ops.setup_pe)
- pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_pe)
+ pstate->pipe_hw->ops.setup_pe(pstate->pipe_hw,
&pixel_ext);
/**
@@ -669,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
* bypassed. Still we need to update alpha and bitwidth
* ONLY for RECT0
*/
- if (pdpu->pipe_hw->ops.setup_scaler &&
+ if (pstate->pipe_hw->ops.setup_scaler &&
pstate->multirect_index != DPU_SSPP_RECT_1)
- pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
+ pstate->pipe_hw->ops.setup_scaler(pstate->pipe_hw,
pipe_cfg,
&scaler3_cfg);
}
@@ -700,8 +705,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
/* update sspp */
- if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
- pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
+ if (fmt && pstate->pipe_hw->ops.setup_solidfill) {
+ pstate->pipe_hw->ops.setup_solidfill(pstate->pipe_hw,
(color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
pstate->multirect_index);
@@ -715,13 +720,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
pipe_cfg.src_rect.y2 =
drm_rect_height(&pipe_cfg.dst_rect);
- if (pdpu->pipe_hw->ops.setup_format)
- pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_format)
+ pstate->pipe_hw->ops.setup_format(pstate->pipe_hw,
fmt, DPU_SSPP_SOLID_FILL,
pstate->multirect_index);
- if (pdpu->pipe_hw->ops.setup_rects)
- pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_rects)
+ pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
&pipe_cfg,
pstate->multirect_index);
@@ -973,8 +978,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
uint32_t min_src_size, max_linewidth;
unsigned int rotation;
uint32_t supported_rotations;
- const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap;
- const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk;
+ const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe_hw->cap;
+ const struct dpu_sspp_sub_blks *sblk = pstate->pipe_hw->cap->sblk;
if (new_plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
@@ -1087,12 +1092,12 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) {
+ else if (pstate->pipe_hw && pstate->pipe_hw->ops.setup_csc) {
const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
if (csc_ptr)
- pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr);
+ pstate->pipe_hw->ops.setup_csc(pstate->pipe_hw, csc_ptr);
}
/* flag h/w flush complete */
@@ -1162,21 +1167,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
return;
}
- if (pdpu->pipe_hw->ops.setup_rects) {
- pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_rects) {
+ pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
&pipe_cfg,
pstate->multirect_index);
}
_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
- if (pdpu->pipe_hw->ops.setup_multirect)
- pdpu->pipe_hw->ops.setup_multirect(
- pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_multirect)
+ pstate->pipe_hw->ops.setup_multirect(
+ pstate->pipe_hw,
pstate->multirect_index,
pstate->multirect_mode);
- if (pdpu->pipe_hw->ops.setup_format) {
+ if (pstate->pipe_hw->ops.setup_format) {
unsigned int rotation = pstate->rotation;
src_flags = 0x0;
@@ -1191,10 +1196,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
src_flags |= DPU_SSPP_ROT_90;
/* update format */
- pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
+ pstate->pipe_hw->ops.setup_format(pstate->pipe_hw, fmt, src_flags,
pstate->multirect_index);
- if (pdpu->pipe_hw->ops.setup_cdp) {
+ if (pstate->pipe_hw->ops.setup_cdp) {
struct dpu_hw_cdp_cfg cdp_cfg;
memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
@@ -1208,7 +1213,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_FORMAT_IS_TILE(fmt);
cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
- pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index);
+ pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, &cdp_cfg, pstate->multirect_index);
}
}
@@ -1348,10 +1353,9 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
const struct drm_plane_state *state)
{
const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
- const struct dpu_plane *pdpu = to_dpu_plane(state->plane);
drm_printf(p, "\tstage=%d\n", pstate->stage);
- drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name);
+ drm_printf(p, "\tsspp=%s\n", pstate->pipe_hw->cap->name);
drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode));
drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index));
}
@@ -1360,6 +1364,7 @@ static void dpu_plane_reset(struct drm_plane *plane)
{
struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
+ struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
if (!plane) {
DPU_ERROR("invalid plane\n");
@@ -1381,6 +1386,8 @@ static void dpu_plane_reset(struct drm_plane *plane)
return;
}
+ pstate->pipe_hw = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
+
__drm_atomic_helper_plane_reset(plane, &pstate->base);
}
@@ -1445,6 +1452,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
struct dpu_plane *pdpu;
struct msm_drm_private *priv = dev->dev_private;
struct dpu_kms *kms = to_dpu_kms(priv->kms);
+ struct dpu_hw_sspp *pipe_hw;
uint32_t num_formats;
uint32_t supported_rotations;
int ret = -EINVAL;
@@ -1462,14 +1470,14 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
pdpu->pipe = pipe;
/* initialize underlying h/w driver */
- pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
- if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
+ pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
+ if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) {
DPU_ERROR("[%u]SSPP is invalid\n", pipe);
goto clean_plane;
}
- format_list = pdpu->pipe_hw->cap->sblk->format_list;
- num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
+ format_list = pipe_hw->cap->sblk->format_list;
+ num_formats = pipe_hw->cap->sblk->num_formats;
ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
format_list, num_formats,
@@ -1491,7 +1499,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
- if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
+ if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
supported_rotations |= DRM_MODE_ROTATE_MASK;
drm_plane_create_rotation_property(plane,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index b7b1b05199c2..0d268729ce81 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -37,6 +37,8 @@ struct dpu_plane_state {
uint32_t multirect_mode;
bool pending;
+ struct dpu_hw_sspp *pipe_hw;
+
u64 plane_fetch_bw;
u64 plane_clk;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 06/27] drm/msm/dpu: move pipe_hw to dpu_plane_state
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
In preparation to adding fully virtualized planes, move struct
dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as
it will become a part of state (allocated during atomic check) rather
than part of a plane (allocated during boot).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 102 ++++++++++++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
2 files changed, 57 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 43fb8e00ada6..7ba954c7b3e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -104,7 +104,6 @@ struct dpu_plane {
enum dpu_sspp pipe;
- struct dpu_hw_sspp *pipe_hw;
uint32_t color_fill;
bool is_error;
bool is_rt_pipe;
@@ -279,6 +278,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
const struct dpu_format *fmt = NULL;
u64 qos_lut;
u32 total_fl = 0, lut_usage;
@@ -310,7 +310,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
fmt ? (char *)&fmt->base.pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, qos_lut);
- pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
+ pstate->pipe_hw->ops.setup_creq_lut(pstate->pipe_hw, qos_lut);
}
/**
@@ -322,6 +322,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
struct drm_framebuffer *fb)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
const struct dpu_format *fmt = NULL;
u32 danger_lut, safe_lut;
@@ -361,7 +362,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
danger_lut,
safe_lut);
- pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
+ pstate->pipe_hw->ops.setup_danger_safe_lut(pstate->pipe_hw,
danger_lut, safe_lut);
}
@@ -375,14 +376,15 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
bool enable, u32 flags)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
- pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
+ pipe_qos_cfg.creq_vblank = pstate->pipe_hw->cap->sblk->creq_vblank;
pipe_qos_cfg.danger_vblank =
- pdpu->pipe_hw->cap->sblk->danger_vblank;
+ pstate->pipe_hw->cap->sblk->danger_vblank;
pipe_qos_cfg.vblank_en = enable;
}
@@ -408,7 +410,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
pipe_qos_cfg.danger_vblank,
pdpu->is_rt_pipe);
- pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
+ pstate->pipe_hw->ops.setup_qos_ctrl(pstate->pipe_hw,
&pipe_qos_cfg);
}
@@ -422,18 +424,19 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_vbif_set_ot_params ot_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&ot_params, 0, sizeof(ot_params));
- ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
- ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
+ ot_params.xin_id = pstate->pipe_hw->cap->xin_id;
+ ot_params.num = pstate->pipe_hw->idx - SSPP_NONE;
ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
ot_params.is_wfd = !pdpu->is_rt_pipe;
ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
ot_params.vbif_idx = VBIF_RT;
- ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
+ ot_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
ot_params.rd = true;
dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
@@ -446,14 +449,15 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_vbif_set_qos_params qos_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = VBIF_RT;
- qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
- qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
- qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
+ qos_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
+ qos_params.xin_id = pstate->pipe_hw->cap->xin_id;
+ qos_params.num = pstate->pipe_hw->idx - SSPP_VIG0;
qos_params.is_rt = pdpu->is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
@@ -478,11 +482,11 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
- else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
+ else if (pstate->pipe_hw->ops.setup_sourceaddress) {
+ trace_dpu_plane_set_scanout(pstate->pipe_hw->idx,
&pipe_cfg->layout,
pstate->multirect_index);
- pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
+ pstate->pipe_hw->ops.setup_sourceaddress(pstate->pipe_hw, pipe_cfg,
pstate->multirect_index);
}
}
@@ -534,7 +538,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->src_height[i] /= chroma_subsmpl_v;
}
- if (pdpu->pipe_hw->cap->features &
+ if (pstate->pipe_hw->cap->features &
BIT(DPU_SSPP_SCALER_QSEED4)) {
scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
@@ -607,6 +611,7 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
{
+ struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state);
const struct dpu_csc_cfg *csc_ptr;
if (!pdpu) {
@@ -617,7 +622,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
if (!DPU_FORMAT_IS_YUV(fmt))
return NULL;
- if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features)
+ if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe_hw->cap->features)
csc_ptr = &dpu_csc10_YUV2RGB_601L;
else
csc_ptr = &dpu_csc_YUV2RGB_601L;
@@ -660,8 +665,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
_dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
src_width, src_height, info->hsub, info->vsub);
- if (pdpu->pipe_hw->ops.setup_pe)
- pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_pe)
+ pstate->pipe_hw->ops.setup_pe(pstate->pipe_hw,
&pixel_ext);
/**
@@ -669,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
* bypassed. Still we need to update alpha and bitwidth
* ONLY for RECT0
*/
- if (pdpu->pipe_hw->ops.setup_scaler &&
+ if (pstate->pipe_hw->ops.setup_scaler &&
pstate->multirect_index != DPU_SSPP_RECT_1)
- pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
+ pstate->pipe_hw->ops.setup_scaler(pstate->pipe_hw,
pipe_cfg,
&scaler3_cfg);
}
@@ -700,8 +705,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
/* update sspp */
- if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
- pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
+ if (fmt && pstate->pipe_hw->ops.setup_solidfill) {
+ pstate->pipe_hw->ops.setup_solidfill(pstate->pipe_hw,
(color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
pstate->multirect_index);
@@ -715,13 +720,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
pipe_cfg.src_rect.y2 =
drm_rect_height(&pipe_cfg.dst_rect);
- if (pdpu->pipe_hw->ops.setup_format)
- pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_format)
+ pstate->pipe_hw->ops.setup_format(pstate->pipe_hw,
fmt, DPU_SSPP_SOLID_FILL,
pstate->multirect_index);
- if (pdpu->pipe_hw->ops.setup_rects)
- pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_rects)
+ pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
&pipe_cfg,
pstate->multirect_index);
@@ -973,8 +978,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
uint32_t min_src_size, max_linewidth;
unsigned int rotation;
uint32_t supported_rotations;
- const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap;
- const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk;
+ const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe_hw->cap;
+ const struct dpu_sspp_sub_blks *sblk = pstate->pipe_hw->cap->sblk;
if (new_plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
@@ -1087,12 +1092,12 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) {
+ else if (pstate->pipe_hw && pstate->pipe_hw->ops.setup_csc) {
const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
if (csc_ptr)
- pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr);
+ pstate->pipe_hw->ops.setup_csc(pstate->pipe_hw, csc_ptr);
}
/* flag h/w flush complete */
@@ -1162,21 +1167,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
return;
}
- if (pdpu->pipe_hw->ops.setup_rects) {
- pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_rects) {
+ pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
&pipe_cfg,
pstate->multirect_index);
}
_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
- if (pdpu->pipe_hw->ops.setup_multirect)
- pdpu->pipe_hw->ops.setup_multirect(
- pdpu->pipe_hw,
+ if (pstate->pipe_hw->ops.setup_multirect)
+ pstate->pipe_hw->ops.setup_multirect(
+ pstate->pipe_hw,
pstate->multirect_index,
pstate->multirect_mode);
- if (pdpu->pipe_hw->ops.setup_format) {
+ if (pstate->pipe_hw->ops.setup_format) {
unsigned int rotation = pstate->rotation;
src_flags = 0x0;
@@ -1191,10 +1196,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
src_flags |= DPU_SSPP_ROT_90;
/* update format */
- pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
+ pstate->pipe_hw->ops.setup_format(pstate->pipe_hw, fmt, src_flags,
pstate->multirect_index);
- if (pdpu->pipe_hw->ops.setup_cdp) {
+ if (pstate->pipe_hw->ops.setup_cdp) {
struct dpu_hw_cdp_cfg cdp_cfg;
memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
@@ -1208,7 +1213,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_FORMAT_IS_TILE(fmt);
cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
- pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index);
+ pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, &cdp_cfg, pstate->multirect_index);
}
}
@@ -1348,10 +1353,9 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
const struct drm_plane_state *state)
{
const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
- const struct dpu_plane *pdpu = to_dpu_plane(state->plane);
drm_printf(p, "\tstage=%d\n", pstate->stage);
- drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name);
+ drm_printf(p, "\tsspp=%s\n", pstate->pipe_hw->cap->name);
drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode));
drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index));
}
@@ -1360,6 +1364,7 @@ static void dpu_plane_reset(struct drm_plane *plane)
{
struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
+ struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
if (!plane) {
DPU_ERROR("invalid plane\n");
@@ -1381,6 +1386,8 @@ static void dpu_plane_reset(struct drm_plane *plane)
return;
}
+ pstate->pipe_hw = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
+
__drm_atomic_helper_plane_reset(plane, &pstate->base);
}
@@ -1445,6 +1452,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
struct dpu_plane *pdpu;
struct msm_drm_private *priv = dev->dev_private;
struct dpu_kms *kms = to_dpu_kms(priv->kms);
+ struct dpu_hw_sspp *pipe_hw;
uint32_t num_formats;
uint32_t supported_rotations;
int ret = -EINVAL;
@@ -1462,14 +1470,14 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
pdpu->pipe = pipe;
/* initialize underlying h/w driver */
- pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
- if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
+ pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
+ if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) {
DPU_ERROR("[%u]SSPP is invalid\n", pipe);
goto clean_plane;
}
- format_list = pdpu->pipe_hw->cap->sblk->format_list;
- num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
+ format_list = pipe_hw->cap->sblk->format_list;
+ num_formats = pipe_hw->cap->sblk->num_formats;
ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
format_list, num_formats,
@@ -1491,7 +1499,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
- if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
+ if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
supported_rotations |= DRM_MODE_ROTATE_MASK;
drm_plane_create_rotation_property(plane,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index b7b1b05199c2..0d268729ce81 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -37,6 +37,8 @@ struct dpu_plane_state {
uint32_t multirect_mode;
bool pending;
+ struct dpu_hw_sspp *pipe_hw;
+
u64 plane_fetch_bw;
u64 plane_clk;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [PATCH v2 06/27] drm/msm/dpu: move pipe_hw to dpu_plane_state
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2023-01-30 21:51 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-30 21:51 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> In preparation to adding fully virtualized planes, move struct
> dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as
> it will become a part of state (allocated during atomic check) rather
> than part of a plane (allocated during boot).
>
I was thinking about a couple of things about this patch:
1) Since we are moving away from using "pipe" and using "sspp", perhaps
we can rename pipe_hw to hw_sspp in the below struct
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -35,6 +35,8 @@ struct dpu_plane_state {
uint32_t multirect_mode;
bool pending;
+ struct dpu_hw_pipe *hw_sspp;
+
u64 plane_fetch_bw;
u64 plane_clk;
};
2) I still dont see any comment as promised in v1 about why we are doing
this in dpu_plane_reset().
https://patchwork.freedesktop.org/patch/473155/?series=99909&rev=1#comment_875365
I think what we need to mention is that the dpu_plane_reset() is the one
which allocates the plane state today and hence pipe_hw can only be
assigned there.
Rest LGTM.
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 102 ++++++++++++----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
> 2 files changed, 57 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 43fb8e00ada6..7ba954c7b3e0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -104,7 +104,6 @@ struct dpu_plane {
>
> enum dpu_sspp pipe;
>
> - struct dpu_hw_sspp *pipe_hw;
> uint32_t color_fill;
> bool is_error;
> bool is_rt_pipe;
> @@ -279,6 +278,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
> struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> const struct dpu_format *fmt = NULL;
> u64 qos_lut;
> u32 total_fl = 0, lut_usage;
> @@ -310,7 +310,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
> fmt ? (char *)&fmt->base.pixel_format : NULL,
> pdpu->is_rt_pipe, total_fl, qos_lut);
>
> - pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
> + pstate->pipe_hw->ops.setup_creq_lut(pstate->pipe_hw, qos_lut);
> }
>
> /**
> @@ -322,6 +322,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
> struct drm_framebuffer *fb)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> const struct dpu_format *fmt = NULL;
> u32 danger_lut, safe_lut;
>
> @@ -361,7 +362,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
> danger_lut,
> safe_lut);
>
> - pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
> + pstate->pipe_hw->ops.setup_danger_safe_lut(pstate->pipe_hw,
> danger_lut, safe_lut);
> }
>
> @@ -375,14 +376,15 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
> bool enable, u32 flags)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
>
> memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
>
> if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
> - pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
> + pipe_qos_cfg.creq_vblank = pstate->pipe_hw->cap->sblk->creq_vblank;
> pipe_qos_cfg.danger_vblank =
> - pdpu->pipe_hw->cap->sblk->danger_vblank;
> + pstate->pipe_hw->cap->sblk->danger_vblank;
> pipe_qos_cfg.vblank_en = enable;
> }
>
> @@ -408,7 +410,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
> pipe_qos_cfg.danger_vblank,
> pdpu->is_rt_pipe);
>
> - pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
> + pstate->pipe_hw->ops.setup_qos_ctrl(pstate->pipe_hw,
> &pipe_qos_cfg);
> }
>
> @@ -422,18 +424,19 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
> struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> struct dpu_vbif_set_ot_params ot_params;
> struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
>
> memset(&ot_params, 0, sizeof(ot_params));
> - ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
> - ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
> + ot_params.xin_id = pstate->pipe_hw->cap->xin_id;
> + ot_params.num = pstate->pipe_hw->idx - SSPP_NONE;
> ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
> ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
> ot_params.is_wfd = !pdpu->is_rt_pipe;
> ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
> ot_params.vbif_idx = VBIF_RT;
> - ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
> + ot_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
> ot_params.rd = true;
>
> dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
> @@ -446,14 +449,15 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
> static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> struct dpu_vbif_set_qos_params qos_params;
> struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
>
> memset(&qos_params, 0, sizeof(qos_params));
> qos_params.vbif_idx = VBIF_RT;
> - qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
> - qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
> - qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
> + qos_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
> + qos_params.xin_id = pstate->pipe_hw->cap->xin_id;
> + qos_params.num = pstate->pipe_hw->idx - SSPP_VIG0;
> qos_params.is_rt = pdpu->is_rt_pipe;
>
> DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
> @@ -478,11 +482,11 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
> ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> if (ret)
> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> - else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
> - trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
> + else if (pstate->pipe_hw->ops.setup_sourceaddress) {
> + trace_dpu_plane_set_scanout(pstate->pipe_hw->idx,
> &pipe_cfg->layout,
> pstate->multirect_index);
> - pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
> + pstate->pipe_hw->ops.setup_sourceaddress(pstate->pipe_hw, pipe_cfg,
> pstate->multirect_index);
> }
> }
> @@ -534,7 +538,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
> scale_cfg->src_height[i] /= chroma_subsmpl_v;
> }
>
> - if (pdpu->pipe_hw->cap->features &
> + if (pstate->pipe_hw->cap->features &
> BIT(DPU_SSPP_SCALER_QSEED4)) {
> scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
> scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
> @@ -607,6 +611,7 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
>
> static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
> {
> + struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state);
> const struct dpu_csc_cfg *csc_ptr;
>
> if (!pdpu) {
> @@ -617,7 +622,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
> if (!DPU_FORMAT_IS_YUV(fmt))
> return NULL;
>
> - if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features)
> + if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe_hw->cap->features)
> csc_ptr = &dpu_csc10_YUV2RGB_601L;
> else
> csc_ptr = &dpu_csc_YUV2RGB_601L;
> @@ -660,8 +665,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
> _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
> src_width, src_height, info->hsub, info->vsub);
>
> - if (pdpu->pipe_hw->ops.setup_pe)
> - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_pe)
> + pstate->pipe_hw->ops.setup_pe(pstate->pipe_hw,
> &pixel_ext);
>
> /**
> @@ -669,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
> * bypassed. Still we need to update alpha and bitwidth
> * ONLY for RECT0
> */
> - if (pdpu->pipe_hw->ops.setup_scaler &&
> + if (pstate->pipe_hw->ops.setup_scaler &&
> pstate->multirect_index != DPU_SSPP_RECT_1)
> - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
> + pstate->pipe_hw->ops.setup_scaler(pstate->pipe_hw,
> pipe_cfg,
> &scaler3_cfg);
> }
> @@ -700,8 +705,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
> fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
>
> /* update sspp */
> - if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
> - pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
> + if (fmt && pstate->pipe_hw->ops.setup_solidfill) {
> + pstate->pipe_hw->ops.setup_solidfill(pstate->pipe_hw,
> (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
> pstate->multirect_index);
>
> @@ -715,13 +720,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
> pipe_cfg.src_rect.y2 =
> drm_rect_height(&pipe_cfg.dst_rect);
>
> - if (pdpu->pipe_hw->ops.setup_format)
> - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_format)
> + pstate->pipe_hw->ops.setup_format(pstate->pipe_hw,
> fmt, DPU_SSPP_SOLID_FILL,
> pstate->multirect_index);
>
> - if (pdpu->pipe_hw->ops.setup_rects)
> - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_rects)
> + pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
> &pipe_cfg,
> pstate->multirect_index);
>
> @@ -973,8 +978,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
> uint32_t min_src_size, max_linewidth;
> unsigned int rotation;
> uint32_t supported_rotations;
> - const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap;
> - const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk;
> + const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe_hw->cap;
> + const struct dpu_sspp_sub_blks *sblk = pstate->pipe_hw->cap->sblk;
>
> if (new_plane_state->crtc)
> crtc_state = drm_atomic_get_new_crtc_state(state,
> @@ -1087,12 +1092,12 @@ void dpu_plane_flush(struct drm_plane *plane)
> else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
> /* force 100% alpha */
> _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
> - else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) {
> + else if (pstate->pipe_hw && pstate->pipe_hw->ops.setup_csc) {
> const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
> const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
>
> if (csc_ptr)
> - pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr);
> + pstate->pipe_hw->ops.setup_csc(pstate->pipe_hw, csc_ptr);
> }
>
> /* flag h/w flush complete */
> @@ -1162,21 +1167,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> return;
> }
>
> - if (pdpu->pipe_hw->ops.setup_rects) {
> - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_rects) {
> + pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
> &pipe_cfg,
> pstate->multirect_index);
> }
>
> _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
>
> - if (pdpu->pipe_hw->ops.setup_multirect)
> - pdpu->pipe_hw->ops.setup_multirect(
> - pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_multirect)
> + pstate->pipe_hw->ops.setup_multirect(
> + pstate->pipe_hw,
> pstate->multirect_index,
> pstate->multirect_mode);
>
> - if (pdpu->pipe_hw->ops.setup_format) {
> + if (pstate->pipe_hw->ops.setup_format) {
> unsigned int rotation = pstate->rotation;
>
> src_flags = 0x0;
> @@ -1191,10 +1196,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> src_flags |= DPU_SSPP_ROT_90;
>
> /* update format */
> - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
> + pstate->pipe_hw->ops.setup_format(pstate->pipe_hw, fmt, src_flags,
> pstate->multirect_index);
>
> - if (pdpu->pipe_hw->ops.setup_cdp) {
> + if (pstate->pipe_hw->ops.setup_cdp) {
> struct dpu_hw_cdp_cfg cdp_cfg;
>
> memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
> @@ -1208,7 +1213,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> DPU_FORMAT_IS_TILE(fmt);
> cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
>
> - pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index);
> + pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, &cdp_cfg, pstate->multirect_index);
> }
> }
>
> @@ -1348,10 +1353,9 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
> const struct drm_plane_state *state)
> {
> const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> - const struct dpu_plane *pdpu = to_dpu_plane(state->plane);
>
> drm_printf(p, "\tstage=%d\n", pstate->stage);
> - drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name);
> + drm_printf(p, "\tsspp=%s\n", pstate->pipe_hw->cap->name);
> drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode));
> drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index));
> }
> @@ -1360,6 +1364,7 @@ static void dpu_plane_reset(struct drm_plane *plane)
> {
> struct dpu_plane *pdpu;
> struct dpu_plane_state *pstate;
> + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
>
> if (!plane) {
> DPU_ERROR("invalid plane\n");
> @@ -1381,6 +1386,8 @@ static void dpu_plane_reset(struct drm_plane *plane)
> return;
> }
>
> + pstate->pipe_hw = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
> +
> __drm_atomic_helper_plane_reset(plane, &pstate->base);
> }
>
> @@ -1445,6 +1452,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> struct dpu_plane *pdpu;
> struct msm_drm_private *priv = dev->dev_private;
> struct dpu_kms *kms = to_dpu_kms(priv->kms);
> + struct dpu_hw_sspp *pipe_hw;
> uint32_t num_formats;
> uint32_t supported_rotations;
> int ret = -EINVAL;
> @@ -1462,14 +1470,14 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> pdpu->pipe = pipe;
>
> /* initialize underlying h/w driver */
> - pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
> - if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> + pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
> + if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) {
> DPU_ERROR("[%u]SSPP is invalid\n", pipe);
> goto clean_plane;
> }
>
> - format_list = pdpu->pipe_hw->cap->sblk->format_list;
> - num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
> + format_list = pipe_hw->cap->sblk->format_list;
> + num_formats = pipe_hw->cap->sblk->num_formats;
>
> ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
> format_list, num_formats,
> @@ -1491,7 +1499,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>
> supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
>
> - if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
> + if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
> supported_rotations |= DRM_MODE_ROTATE_MASK;
>
> drm_plane_create_rotation_property(plane,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index b7b1b05199c2..0d268729ce81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -37,6 +37,8 @@ struct dpu_plane_state {
> uint32_t multirect_mode;
> bool pending;
>
> + struct dpu_hw_sspp *pipe_hw;
> +
> u64 plane_fetch_bw;
> u64 plane_clk;
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 06/27] drm/msm/dpu: move pipe_hw to dpu_plane_state
@ 2023-01-30 21:51 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-30 21:51 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> In preparation to adding fully virtualized planes, move struct
> dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as
> it will become a part of state (allocated during atomic check) rather
> than part of a plane (allocated during boot).
>
I was thinking about a couple of things about this patch:
1) Since we are moving away from using "pipe" and using "sspp", perhaps
we can rename pipe_hw to hw_sspp in the below struct
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -35,6 +35,8 @@ struct dpu_plane_state {
uint32_t multirect_mode;
bool pending;
+ struct dpu_hw_pipe *hw_sspp;
+
u64 plane_fetch_bw;
u64 plane_clk;
};
2) I still dont see any comment as promised in v1 about why we are doing
this in dpu_plane_reset().
https://patchwork.freedesktop.org/patch/473155/?series=99909&rev=1#comment_875365
I think what we need to mention is that the dpu_plane_reset() is the one
which allocates the plane state today and hence pipe_hw can only be
assigned there.
Rest LGTM.
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 102 ++++++++++++----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
> 2 files changed, 57 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 43fb8e00ada6..7ba954c7b3e0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -104,7 +104,6 @@ struct dpu_plane {
>
> enum dpu_sspp pipe;
>
> - struct dpu_hw_sspp *pipe_hw;
> uint32_t color_fill;
> bool is_error;
> bool is_rt_pipe;
> @@ -279,6 +278,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
> struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> const struct dpu_format *fmt = NULL;
> u64 qos_lut;
> u32 total_fl = 0, lut_usage;
> @@ -310,7 +310,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
> fmt ? (char *)&fmt->base.pixel_format : NULL,
> pdpu->is_rt_pipe, total_fl, qos_lut);
>
> - pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
> + pstate->pipe_hw->ops.setup_creq_lut(pstate->pipe_hw, qos_lut);
> }
>
> /**
> @@ -322,6 +322,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
> struct drm_framebuffer *fb)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> const struct dpu_format *fmt = NULL;
> u32 danger_lut, safe_lut;
>
> @@ -361,7 +362,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
> danger_lut,
> safe_lut);
>
> - pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
> + pstate->pipe_hw->ops.setup_danger_safe_lut(pstate->pipe_hw,
> danger_lut, safe_lut);
> }
>
> @@ -375,14 +376,15 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
> bool enable, u32 flags)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
>
> memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
>
> if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
> - pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
> + pipe_qos_cfg.creq_vblank = pstate->pipe_hw->cap->sblk->creq_vblank;
> pipe_qos_cfg.danger_vblank =
> - pdpu->pipe_hw->cap->sblk->danger_vblank;
> + pstate->pipe_hw->cap->sblk->danger_vblank;
> pipe_qos_cfg.vblank_en = enable;
> }
>
> @@ -408,7 +410,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
> pipe_qos_cfg.danger_vblank,
> pdpu->is_rt_pipe);
>
> - pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
> + pstate->pipe_hw->ops.setup_qos_ctrl(pstate->pipe_hw,
> &pipe_qos_cfg);
> }
>
> @@ -422,18 +424,19 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
> struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> struct dpu_vbif_set_ot_params ot_params;
> struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
>
> memset(&ot_params, 0, sizeof(ot_params));
> - ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
> - ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
> + ot_params.xin_id = pstate->pipe_hw->cap->xin_id;
> + ot_params.num = pstate->pipe_hw->idx - SSPP_NONE;
> ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
> ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
> ot_params.is_wfd = !pdpu->is_rt_pipe;
> ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
> ot_params.vbif_idx = VBIF_RT;
> - ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
> + ot_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
> ot_params.rd = true;
>
> dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
> @@ -446,14 +449,15 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
> static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> struct dpu_vbif_set_qos_params qos_params;
> struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
>
> memset(&qos_params, 0, sizeof(qos_params));
> qos_params.vbif_idx = VBIF_RT;
> - qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
> - qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
> - qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
> + qos_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
> + qos_params.xin_id = pstate->pipe_hw->cap->xin_id;
> + qos_params.num = pstate->pipe_hw->idx - SSPP_VIG0;
> qos_params.is_rt = pdpu->is_rt_pipe;
>
> DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
> @@ -478,11 +482,11 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
> ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> if (ret)
> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> - else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
> - trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
> + else if (pstate->pipe_hw->ops.setup_sourceaddress) {
> + trace_dpu_plane_set_scanout(pstate->pipe_hw->idx,
> &pipe_cfg->layout,
> pstate->multirect_index);
> - pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
> + pstate->pipe_hw->ops.setup_sourceaddress(pstate->pipe_hw, pipe_cfg,
> pstate->multirect_index);
> }
> }
> @@ -534,7 +538,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
> scale_cfg->src_height[i] /= chroma_subsmpl_v;
> }
>
> - if (pdpu->pipe_hw->cap->features &
> + if (pstate->pipe_hw->cap->features &
> BIT(DPU_SSPP_SCALER_QSEED4)) {
> scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
> scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
> @@ -607,6 +611,7 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
>
> static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
> {
> + struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state);
> const struct dpu_csc_cfg *csc_ptr;
>
> if (!pdpu) {
> @@ -617,7 +622,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
> if (!DPU_FORMAT_IS_YUV(fmt))
> return NULL;
>
> - if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features)
> + if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe_hw->cap->features)
> csc_ptr = &dpu_csc10_YUV2RGB_601L;
> else
> csc_ptr = &dpu_csc_YUV2RGB_601L;
> @@ -660,8 +665,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
> _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
> src_width, src_height, info->hsub, info->vsub);
>
> - if (pdpu->pipe_hw->ops.setup_pe)
> - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_pe)
> + pstate->pipe_hw->ops.setup_pe(pstate->pipe_hw,
> &pixel_ext);
>
> /**
> @@ -669,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
> * bypassed. Still we need to update alpha and bitwidth
> * ONLY for RECT0
> */
> - if (pdpu->pipe_hw->ops.setup_scaler &&
> + if (pstate->pipe_hw->ops.setup_scaler &&
> pstate->multirect_index != DPU_SSPP_RECT_1)
> - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
> + pstate->pipe_hw->ops.setup_scaler(pstate->pipe_hw,
> pipe_cfg,
> &scaler3_cfg);
> }
> @@ -700,8 +705,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
> fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
>
> /* update sspp */
> - if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
> - pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
> + if (fmt && pstate->pipe_hw->ops.setup_solidfill) {
> + pstate->pipe_hw->ops.setup_solidfill(pstate->pipe_hw,
> (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
> pstate->multirect_index);
>
> @@ -715,13 +720,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
> pipe_cfg.src_rect.y2 =
> drm_rect_height(&pipe_cfg.dst_rect);
>
> - if (pdpu->pipe_hw->ops.setup_format)
> - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_format)
> + pstate->pipe_hw->ops.setup_format(pstate->pipe_hw,
> fmt, DPU_SSPP_SOLID_FILL,
> pstate->multirect_index);
>
> - if (pdpu->pipe_hw->ops.setup_rects)
> - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_rects)
> + pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
> &pipe_cfg,
> pstate->multirect_index);
>
> @@ -973,8 +978,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
> uint32_t min_src_size, max_linewidth;
> unsigned int rotation;
> uint32_t supported_rotations;
> - const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap;
> - const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk;
> + const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe_hw->cap;
> + const struct dpu_sspp_sub_blks *sblk = pstate->pipe_hw->cap->sblk;
>
> if (new_plane_state->crtc)
> crtc_state = drm_atomic_get_new_crtc_state(state,
> @@ -1087,12 +1092,12 @@ void dpu_plane_flush(struct drm_plane *plane)
> else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
> /* force 100% alpha */
> _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
> - else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) {
> + else if (pstate->pipe_hw && pstate->pipe_hw->ops.setup_csc) {
> const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
> const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
>
> if (csc_ptr)
> - pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr);
> + pstate->pipe_hw->ops.setup_csc(pstate->pipe_hw, csc_ptr);
> }
>
> /* flag h/w flush complete */
> @@ -1162,21 +1167,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> return;
> }
>
> - if (pdpu->pipe_hw->ops.setup_rects) {
> - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_rects) {
> + pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
> &pipe_cfg,
> pstate->multirect_index);
> }
>
> _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
>
> - if (pdpu->pipe_hw->ops.setup_multirect)
> - pdpu->pipe_hw->ops.setup_multirect(
> - pdpu->pipe_hw,
> + if (pstate->pipe_hw->ops.setup_multirect)
> + pstate->pipe_hw->ops.setup_multirect(
> + pstate->pipe_hw,
> pstate->multirect_index,
> pstate->multirect_mode);
>
> - if (pdpu->pipe_hw->ops.setup_format) {
> + if (pstate->pipe_hw->ops.setup_format) {
> unsigned int rotation = pstate->rotation;
>
> src_flags = 0x0;
> @@ -1191,10 +1196,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> src_flags |= DPU_SSPP_ROT_90;
>
> /* update format */
> - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
> + pstate->pipe_hw->ops.setup_format(pstate->pipe_hw, fmt, src_flags,
> pstate->multirect_index);
>
> - if (pdpu->pipe_hw->ops.setup_cdp) {
> + if (pstate->pipe_hw->ops.setup_cdp) {
> struct dpu_hw_cdp_cfg cdp_cfg;
>
> memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
> @@ -1208,7 +1213,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> DPU_FORMAT_IS_TILE(fmt);
> cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
>
> - pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index);
> + pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, &cdp_cfg, pstate->multirect_index);
> }
> }
>
> @@ -1348,10 +1353,9 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
> const struct drm_plane_state *state)
> {
> const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> - const struct dpu_plane *pdpu = to_dpu_plane(state->plane);
>
> drm_printf(p, "\tstage=%d\n", pstate->stage);
> - drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name);
> + drm_printf(p, "\tsspp=%s\n", pstate->pipe_hw->cap->name);
> drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode));
> drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index));
> }
> @@ -1360,6 +1364,7 @@ static void dpu_plane_reset(struct drm_plane *plane)
> {
> struct dpu_plane *pdpu;
> struct dpu_plane_state *pstate;
> + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
>
> if (!plane) {
> DPU_ERROR("invalid plane\n");
> @@ -1381,6 +1386,8 @@ static void dpu_plane_reset(struct drm_plane *plane)
> return;
> }
>
> + pstate->pipe_hw = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
> +
> __drm_atomic_helper_plane_reset(plane, &pstate->base);
> }
>
> @@ -1445,6 +1452,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> struct dpu_plane *pdpu;
> struct msm_drm_private *priv = dev->dev_private;
> struct dpu_kms *kms = to_dpu_kms(priv->kms);
> + struct dpu_hw_sspp *pipe_hw;
> uint32_t num_formats;
> uint32_t supported_rotations;
> int ret = -EINVAL;
> @@ -1462,14 +1470,14 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> pdpu->pipe = pipe;
>
> /* initialize underlying h/w driver */
> - pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
> - if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
> + pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
> + if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) {
> DPU_ERROR("[%u]SSPP is invalid\n", pipe);
> goto clean_plane;
> }
>
> - format_list = pdpu->pipe_hw->cap->sblk->format_list;
> - num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
> + format_list = pipe_hw->cap->sblk->format_list;
> + num_formats = pipe_hw->cap->sblk->num_formats;
>
> ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
> format_list, num_formats,
> @@ -1491,7 +1499,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>
> supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
>
> - if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
> + if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
> supported_rotations |= DRM_MODE_ROTATE_MASK;
>
> drm_plane_create_rotation_property(plane,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index b7b1b05199c2..0d268729ce81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -37,6 +37,8 @@ struct dpu_plane_state {
> uint32_t multirect_mode;
> bool pending;
>
> + struct dpu_hw_sspp *pipe_hw;
> +
> u64 plane_fetch_bw;
> u64 plane_clk;
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 06/27] drm/msm/dpu: move pipe_hw to dpu_plane_state
2023-01-30 21:51 ` Abhinav Kumar
@ 2023-01-31 11:51 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-31 11:51 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 30/01/2023 23:51, Abhinav Kumar wrote:
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>> In preparation to adding fully virtualized planes, move struct
>> dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as
>> it will become a part of state (allocated during atomic check) rather
>> than part of a plane (allocated during boot).
>>
>
> I was thinking about a couple of things about this patch:
>
> 1) Since we are moving away from using "pipe" and using "sspp", perhaps
> we can rename pipe_hw to hw_sspp in the below struct
>
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -35,6 +35,8 @@ struct dpu_plane_state {
> uint32_t multirect_mode;
> bool pending;
>
> + struct dpu_hw_pipe *hw_sspp;
> +
Ack
> u64 plane_fetch_bw;
> u64 plane_clk;
> };
>
> 2) I still dont see any comment as promised in v1 about why we are doing
> this in dpu_plane_reset().
>
> https://patchwork.freedesktop.org/patch/473155/?series=99909&rev=1#comment_875365
>
> I think what we need to mention is that the dpu_plane_reset() is the one
> which allocates the plane state today and hence pipe_hw can only be
> assigned there.
Ack
>
> Rest LGTM.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 06/27] drm/msm/dpu: move pipe_hw to dpu_plane_state
@ 2023-01-31 11:51 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-31 11:51 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 30/01/2023 23:51, Abhinav Kumar wrote:
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>> In preparation to adding fully virtualized planes, move struct
>> dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as
>> it will become a part of state (allocated during atomic check) rather
>> than part of a plane (allocated during boot).
>>
>
> I was thinking about a couple of things about this patch:
>
> 1) Since we are moving away from using "pipe" and using "sspp", perhaps
> we can rename pipe_hw to hw_sspp in the below struct
>
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -35,6 +35,8 @@ struct dpu_plane_state {
> uint32_t multirect_mode;
> bool pending;
>
> + struct dpu_hw_pipe *hw_sspp;
> +
Ack
> u64 plane_fetch_bw;
> u64 plane_clk;
> };
>
> 2) I still dont see any comment as promised in v1 about why we are doing
> this in dpu_plane_reset().
>
> https://patchwork.freedesktop.org/patch/473155/?series=99909&rev=1#comment_875365
>
> I think what we need to mention is that the dpu_plane_reset() is the one
> which allocates the plane state today and hence pipe_hw can only be
> assigned there.
Ack
>
> Rest LGTM.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 07/27] drm/msm/dpu: drop dpu_plane_pipe function
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
There no more need for the dpu_plane_pipe() function, crtc code can
access pstate->pipe_hw.idx directly.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 5 -----
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 7 -------
3 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..78c21a976bad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -431,7 +431,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- sspp_idx = dpu_plane_pipe(plane);
+ sspp_idx = pstate->pipe_hw->idx;
set_bit(sspp_idx, fetch_active);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
@@ -1197,7 +1197,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
pstates[cnt].dpu_pstate = dpu_pstate;
pstates[cnt].drm_pstate = pstate;
pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = dpu_plane_pipe(plane);
+ pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe_hw->idx;
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 7ba954c7b3e0..493dcf04fa6d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1437,11 +1437,6 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
.atomic_update = dpu_plane_atomic_update,
};
-enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
-{
- return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
-}
-
/* initialize plane */
struct drm_plane *dpu_plane_init(struct drm_device *dev,
uint32_t pipe, enum drm_plane_type type,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 0d268729ce81..8786359a191c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -59,13 +59,6 @@ struct dpu_multirect_plane_states {
#define to_dpu_plane_state(x) \
container_of(x, struct dpu_plane_state, base)
-/**
- * dpu_plane_pipe - return sspp identifier for the given plane
- * @plane: Pointer to DRM plane object
- * Returns: sspp identifier of the given plane
- */
-enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane);
-
/**
* dpu_plane_flush - final plane operations before commit flush
* @plane: Pointer to drm plane structure
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 07/27] drm/msm/dpu: drop dpu_plane_pipe function
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
There no more need for the dpu_plane_pipe() function, crtc code can
access pstate->pipe_hw.idx directly.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 5 -----
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 7 -------
3 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..78c21a976bad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -431,7 +431,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- sspp_idx = dpu_plane_pipe(plane);
+ sspp_idx = pstate->pipe_hw->idx;
set_bit(sspp_idx, fetch_active);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
@@ -1197,7 +1197,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
pstates[cnt].dpu_pstate = dpu_pstate;
pstates[cnt].drm_pstate = pstate;
pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = dpu_plane_pipe(plane);
+ pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe_hw->idx;
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 7ba954c7b3e0..493dcf04fa6d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1437,11 +1437,6 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
.atomic_update = dpu_plane_atomic_update,
};
-enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
-{
- return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
-}
-
/* initialize plane */
struct drm_plane *dpu_plane_init(struct drm_device *dev,
uint32_t pipe, enum drm_plane_type type,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 0d268729ce81..8786359a191c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -59,13 +59,6 @@ struct dpu_multirect_plane_states {
#define to_dpu_plane_state(x) \
container_of(x, struct dpu_plane_state, base)
-/**
- * dpu_plane_pipe - return sspp identifier for the given plane
- * @plane: Pointer to DRM plane object
- * Returns: sspp identifier of the given plane
- */
-enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane);
-
/**
* dpu_plane_flush - final plane operations before commit flush
* @plane: Pointer to drm plane structure
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 08/27] drm/msm/dpu: introduce struct dpu_sw_pipe
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Wrap SSPP and multirect index/mode into a single structure that
represents software view on the pipe used.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 131 ++++++++++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +-
5 files changed, 88 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 78c21a976bad..04833d91caac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -431,7 +431,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- sspp_idx = pstate->pipe_hw->idx;
+ sspp_idx = pstate->pipe.sspp->idx;
set_bit(sspp_idx, fetch_active);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
@@ -450,11 +450,10 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
stage_cfg->stage[pstate->stage][stage_idx] =
sspp_idx;
stage_cfg->multirect_index[pstate->stage][stage_idx] =
- pstate->multirect_index;
+ pstate->pipe.multirect_index;
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
state, pstate, stage_idx,
- sspp_idx - SSPP_VIG0,
format->base.pixel_format,
fb ? fb->modifier : 0);
@@ -1197,7 +1196,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
pstates[cnt].dpu_pstate = dpu_pstate;
pstates[cnt].drm_pstate = pstate;
pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe_hw->idx;
+ pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe.sspp->idx;
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
@@ -1470,7 +1469,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
state->crtc_x, state->crtc_y, state->crtc_w,
state->crtc_h);
seq_printf(s, "\tmultirect: mode: %d index: %d\n",
- pstate->multirect_mode, pstate->multirect_index);
+ pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
seq_puts(s, "\n");
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 8c3e9090be4b..a96afc53e0f6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -158,15 +158,11 @@ struct dpu_hw_pixel_ext {
* @src_rect: src ROI, caller takes into account the different operations
* such as decimation, flip etc to program this field
* @dest_rect: destination ROI.
- * @index: index of the rectangle of SSPP
- * @mode: parallel or time multiplex multirect mode
*/
struct dpu_hw_pipe_cfg {
struct dpu_hw_fmt_layout layout;
struct drm_rect src_rect;
struct drm_rect dst_rect;
- enum dpu_sspp_multirect_index index;
- enum dpu_sspp_multirect_mode mode;
};
/**
@@ -201,6 +197,18 @@ struct dpu_hw_pipe_ts_cfg {
u64 time;
};
+/**
+ * struct dpu_sw_pipe - software pipe description
+ * @sspp: backing SSPP pipe
+ * @index: index of the rectangle of SSPP
+ * @mode: parallel or time multiplex multirect mode
+ */
+struct dpu_sw_pipe {
+ struct dpu_hw_sspp *sspp;
+ enum dpu_sspp_multirect_index multirect_index;
+ enum dpu_sspp_multirect_mode multirect_mode;
+};
+
/**
* struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
* Caller must call the init function to get the pipe context for each pipe
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 493dcf04fa6d..1b17213235dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -251,7 +251,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
((src_width + 32) * fmt->bpp);
}
} else {
- if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
+ if (pstate->pipe.multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
total_fl = (fixed_buff_size / 2) * 2 /
((src_width + 32) * fmt->bpp);
} else {
@@ -310,7 +310,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
fmt ? (char *)&fmt->base.pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, qos_lut);
- pstate->pipe_hw->ops.setup_creq_lut(pstate->pipe_hw, qos_lut);
+ pstate->pipe.sspp->ops.setup_creq_lut(pstate->pipe.sspp, qos_lut);
}
/**
@@ -362,7 +362,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
danger_lut,
safe_lut);
- pstate->pipe_hw->ops.setup_danger_safe_lut(pstate->pipe_hw,
+ pstate->pipe.sspp->ops.setup_danger_safe_lut(pstate->pipe.sspp,
danger_lut, safe_lut);
}
@@ -382,9 +382,9 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
- pipe_qos_cfg.creq_vblank = pstate->pipe_hw->cap->sblk->creq_vblank;
+ pipe_qos_cfg.creq_vblank = pstate->pipe.sspp->cap->sblk->creq_vblank;
pipe_qos_cfg.danger_vblank =
- pstate->pipe_hw->cap->sblk->danger_vblank;
+ pstate->pipe.sspp->cap->sblk->danger_vblank;
pipe_qos_cfg.vblank_en = enable;
}
@@ -410,7 +410,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
pipe_qos_cfg.danger_vblank,
pdpu->is_rt_pipe);
- pstate->pipe_hw->ops.setup_qos_ctrl(pstate->pipe_hw,
+ pstate->pipe.sspp->ops.setup_qos_ctrl(pstate->pipe.sspp,
&pipe_qos_cfg);
}
@@ -429,14 +429,14 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&ot_params, 0, sizeof(ot_params));
- ot_params.xin_id = pstate->pipe_hw->cap->xin_id;
- ot_params.num = pstate->pipe_hw->idx - SSPP_NONE;
+ ot_params.xin_id = pstate->pipe.sspp->cap->xin_id;
+ ot_params.num = pstate->pipe.sspp->idx - SSPP_NONE;
ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
ot_params.is_wfd = !pdpu->is_rt_pipe;
ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
ot_params.vbif_idx = VBIF_RT;
- ot_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
+ ot_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl;
ot_params.rd = true;
dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
@@ -455,9 +455,9 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = VBIF_RT;
- qos_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
- qos_params.xin_id = pstate->pipe_hw->cap->xin_id;
- qos_params.num = pstate->pipe_hw->idx - SSPP_VIG0;
+ qos_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl;
+ qos_params.xin_id = pstate->pipe.sspp->cap->xin_id;
+ qos_params.num = pstate->pipe.sspp->idx - SSPP_VIG0;
qos_params.is_rt = pdpu->is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
@@ -482,12 +482,12 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
- else if (pstate->pipe_hw->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(pstate->pipe_hw->idx,
+ else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
+ trace_dpu_plane_set_scanout(pstate->pipe.sspp->idx,
&pipe_cfg->layout,
- pstate->multirect_index);
- pstate->pipe_hw->ops.setup_sourceaddress(pstate->pipe_hw, pipe_cfg,
- pstate->multirect_index);
+ pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_sourceaddress(pstate->pipe.sspp, pipe_cfg,
+ pstate->pipe.multirect_index);
}
}
@@ -538,7 +538,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->src_height[i] /= chroma_subsmpl_v;
}
- if (pstate->pipe_hw->cap->features &
+ if (pstate->pipe.sspp->cap->features &
BIT(DPU_SSPP_SCALER_QSEED4)) {
scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
@@ -622,7 +622,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
if (!DPU_FORMAT_IS_YUV(fmt))
return NULL;
- if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe_hw->cap->features)
+ if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe.sspp->cap->features)
csc_ptr = &dpu_csc10_YUV2RGB_601L;
else
csc_ptr = &dpu_csc_YUV2RGB_601L;
@@ -665,8 +665,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
_dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
src_width, src_height, info->hsub, info->vsub);
- if (pstate->pipe_hw->ops.setup_pe)
- pstate->pipe_hw->ops.setup_pe(pstate->pipe_hw,
+ if (pstate->pipe.sspp->ops.setup_pe)
+ pstate->pipe.sspp->ops.setup_pe(pstate->pipe.sspp,
&pixel_ext);
/**
@@ -674,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
* bypassed. Still we need to update alpha and bitwidth
* ONLY for RECT0
*/
- if (pstate->pipe_hw->ops.setup_scaler &&
- pstate->multirect_index != DPU_SSPP_RECT_1)
- pstate->pipe_hw->ops.setup_scaler(pstate->pipe_hw,
+ if (pstate->pipe.sspp->ops.setup_scaler &&
+ pstate->pipe.multirect_index != DPU_SSPP_RECT_1)
+ pstate->pipe.sspp->ops.setup_scaler(pstate->pipe.sspp,
pipe_cfg,
&scaler3_cfg);
}
@@ -705,10 +705,10 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
/* update sspp */
- if (fmt && pstate->pipe_hw->ops.setup_solidfill) {
- pstate->pipe_hw->ops.setup_solidfill(pstate->pipe_hw,
+ if (fmt && pstate->pipe.sspp->ops.setup_solidfill) {
+ pstate->pipe.sspp->ops.setup_solidfill(pstate->pipe.sspp,
(color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
- pstate->multirect_index);
+ pstate->pipe.multirect_index);
/* override scaler/decimation if solid fill */
pipe_cfg.dst_rect = pstate->base.dst;
@@ -720,15 +720,15 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
pipe_cfg.src_rect.y2 =
drm_rect_height(&pipe_cfg.dst_rect);
- if (pstate->pipe_hw->ops.setup_format)
- pstate->pipe_hw->ops.setup_format(pstate->pipe_hw,
+ if (pstate->pipe.sspp->ops.setup_format)
+ pstate->pipe.sspp->ops.setup_format(pstate->pipe.sspp,
fmt, DPU_SSPP_SOLID_FILL,
- pstate->multirect_index);
+ pstate->pipe.multirect_index);
- if (pstate->pipe_hw->ops.setup_rects)
- pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
+ if (pstate->pipe.sspp->ops.setup_rects)
+ pstate->pipe.sspp->ops.setup_rects(pstate->pipe.sspp,
&pipe_cfg,
- pstate->multirect_index);
+ pstate->pipe.multirect_index);
_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
}
@@ -740,8 +740,8 @@ void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
{
struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
- pstate->multirect_index = DPU_SSPP_RECT_SOLO;
- pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
+ pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
}
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
@@ -823,8 +823,8 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
/* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
if (parallel_fetch_qualified) {
- pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
- pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+ pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+ pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
goto done;
}
@@ -834,8 +834,8 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
if (dst[R1].y1 >= dst[R0].y2 + buffer_lines ||
dst[R0].y1 >= dst[R1].y2 + buffer_lines) {
- pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
- pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
+ pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
+ pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
} else {
DPU_ERROR(
"No multirect mode possible for the planes (%d - %d)\n",
@@ -845,13 +845,13 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
}
done:
- pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
- pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
+ pstate[R0]->pipe.multirect_index = DPU_SSPP_RECT_0;
+ pstate[R1]->pipe.multirect_index = DPU_SSPP_RECT_1;
DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
- pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
+ pstate[R0]->pipe.multirect_mode, pstate[R0]->pipe.multirect_index);
DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
- pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
+ pstate[R1]->pipe.multirect_mode, pstate[R1]->pipe.multirect_index);
return 0;
}
@@ -978,8 +978,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
uint32_t min_src_size, max_linewidth;
unsigned int rotation;
uint32_t supported_rotations;
- const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe_hw->cap;
- const struct dpu_sspp_sub_blks *sblk = pstate->pipe_hw->cap->sblk;
+ const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap;
+ const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk;
if (new_plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
@@ -1092,12 +1092,12 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else if (pstate->pipe_hw && pstate->pipe_hw->ops.setup_csc) {
+ else if (pstate->pipe.sspp && pstate->pipe.sspp->ops.setup_csc) {
const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
if (csc_ptr)
- pstate->pipe_hw->ops.setup_csc(pstate->pipe_hw, csc_ptr);
+ pstate->pipe.sspp->ops.setup_csc(pstate->pipe.sspp, csc_ptr);
}
/* flag h/w flush complete */
@@ -1127,6 +1127,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct drm_plane_state *state = plane->state;
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ struct dpu_sw_pipe *pipe = &pstate->pipe;
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
bool is_rt_pipe;
@@ -1167,21 +1168,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
return;
}
- if (pstate->pipe_hw->ops.setup_rects) {
- pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
+ if (pipe->sspp->ops.setup_rects) {
+ pipe->sspp->ops.setup_rects(pipe->sspp,
&pipe_cfg,
- pstate->multirect_index);
+ pipe->multirect_index);
}
_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
- if (pstate->pipe_hw->ops.setup_multirect)
- pstate->pipe_hw->ops.setup_multirect(
- pstate->pipe_hw,
- pstate->multirect_index,
- pstate->multirect_mode);
+ if (pipe->sspp->ops.setup_multirect)
+ pipe->sspp->ops.setup_multirect(
+ pipe->sspp,
+ pipe->multirect_index,
+ pipe->multirect_mode);
- if (pstate->pipe_hw->ops.setup_format) {
+ if (pipe->sspp->ops.setup_format) {
unsigned int rotation = pstate->rotation;
src_flags = 0x0;
@@ -1196,10 +1197,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
src_flags |= DPU_SSPP_ROT_90;
/* update format */
- pstate->pipe_hw->ops.setup_format(pstate->pipe_hw, fmt, src_flags,
- pstate->multirect_index);
+ pipe->sspp->ops.setup_format(pipe->sspp, fmt, src_flags,
+ pipe->multirect_index);
- if (pstate->pipe_hw->ops.setup_cdp) {
+ if (pipe->sspp->ops.setup_cdp) {
struct dpu_hw_cdp_cfg cdp_cfg;
memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
@@ -1213,7 +1214,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_FORMAT_IS_TILE(fmt);
cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
- pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, &cdp_cfg, pstate->multirect_index);
+ pipe->sspp->ops.setup_cdp(pipe->sspp, &cdp_cfg, pipe->multirect_index);
}
}
@@ -1241,7 +1242,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane)
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
trace_dpu_plane_disable(DRMID(plane), false,
- pstate->multirect_mode);
+ pstate->pipe.multirect_mode);
pstate->pending = true;
}
@@ -1355,9 +1356,9 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
drm_printf(p, "\tstage=%d\n", pstate->stage);
- drm_printf(p, "\tsspp=%s\n", pstate->pipe_hw->cap->name);
- drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode));
- drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index));
+ drm_printf(p, "\tsspp=%s\n", pstate->pipe.sspp->cap->name);
+ drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->pipe.multirect_mode));
+ drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->pipe.multirect_index));
}
static void dpu_plane_reset(struct drm_plane *plane)
@@ -1386,7 +1387,7 @@ static void dpu_plane_reset(struct drm_plane *plane)
return;
}
- pstate->pipe_hw = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
+ pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
__drm_atomic_helper_plane_reset(plane, &pstate->base);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 8786359a191c..55ea221e8488 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -33,11 +33,9 @@ struct dpu_plane_state {
struct msm_gem_address_space *aspace;
enum dpu_stage stage;
bool needs_qos_remap;
- uint32_t multirect_index;
- uint32_t multirect_mode;
bool pending;
- struct dpu_hw_sspp *pipe_hw;
+ struct dpu_sw_pipe pipe;
u64 plane_fetch_bw;
u64 plane_clk;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 76169f406505..d7059972499f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -633,9 +633,9 @@ TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
TRACE_EVENT(dpu_crtc_setup_mixer,
TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
struct drm_plane_state *state, struct dpu_plane_state *pstate,
- uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format,
+ uint32_t stage_idx, uint32_t pixel_format,
uint64_t modifier),
- TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
+ TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
pixel_format, modifier),
TP_STRUCT__entry(
__field( uint32_t, crtc_id )
@@ -659,9 +659,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer,
__entry->dst_rect = drm_plane_state_dest(state);
__entry->stage_idx = stage_idx;
__entry->stage = pstate->stage;
- __entry->sspp = sspp;
- __entry->multirect_idx = pstate->multirect_index;
- __entry->multirect_mode = pstate->multirect_mode;
+ __entry->sspp = pstate->pipe.sspp->idx;
+ __entry->multirect_idx = pstate->pipe.multirect_index;
+ __entry->multirect_mode = pstate->pipe.multirect_mode;
__entry->pixel_format = pixel_format;
__entry->modifier = modifier;
),
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 08/27] drm/msm/dpu: introduce struct dpu_sw_pipe
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Wrap SSPP and multirect index/mode into a single structure that
represents software view on the pipe used.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 131 ++++++++++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +-
5 files changed, 88 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 78c21a976bad..04833d91caac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -431,7 +431,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- sspp_idx = pstate->pipe_hw->idx;
+ sspp_idx = pstate->pipe.sspp->idx;
set_bit(sspp_idx, fetch_active);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
@@ -450,11 +450,10 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
stage_cfg->stage[pstate->stage][stage_idx] =
sspp_idx;
stage_cfg->multirect_index[pstate->stage][stage_idx] =
- pstate->multirect_index;
+ pstate->pipe.multirect_index;
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
state, pstate, stage_idx,
- sspp_idx - SSPP_VIG0,
format->base.pixel_format,
fb ? fb->modifier : 0);
@@ -1197,7 +1196,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
pstates[cnt].dpu_pstate = dpu_pstate;
pstates[cnt].drm_pstate = pstate;
pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe_hw->idx;
+ pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe.sspp->idx;
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
@@ -1470,7 +1469,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
state->crtc_x, state->crtc_y, state->crtc_w,
state->crtc_h);
seq_printf(s, "\tmultirect: mode: %d index: %d\n",
- pstate->multirect_mode, pstate->multirect_index);
+ pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
seq_puts(s, "\n");
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 8c3e9090be4b..a96afc53e0f6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -158,15 +158,11 @@ struct dpu_hw_pixel_ext {
* @src_rect: src ROI, caller takes into account the different operations
* such as decimation, flip etc to program this field
* @dest_rect: destination ROI.
- * @index: index of the rectangle of SSPP
- * @mode: parallel or time multiplex multirect mode
*/
struct dpu_hw_pipe_cfg {
struct dpu_hw_fmt_layout layout;
struct drm_rect src_rect;
struct drm_rect dst_rect;
- enum dpu_sspp_multirect_index index;
- enum dpu_sspp_multirect_mode mode;
};
/**
@@ -201,6 +197,18 @@ struct dpu_hw_pipe_ts_cfg {
u64 time;
};
+/**
+ * struct dpu_sw_pipe - software pipe description
+ * @sspp: backing SSPP pipe
+ * @index: index of the rectangle of SSPP
+ * @mode: parallel or time multiplex multirect mode
+ */
+struct dpu_sw_pipe {
+ struct dpu_hw_sspp *sspp;
+ enum dpu_sspp_multirect_index multirect_index;
+ enum dpu_sspp_multirect_mode multirect_mode;
+};
+
/**
* struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
* Caller must call the init function to get the pipe context for each pipe
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 493dcf04fa6d..1b17213235dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -251,7 +251,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
((src_width + 32) * fmt->bpp);
}
} else {
- if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
+ if (pstate->pipe.multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
total_fl = (fixed_buff_size / 2) * 2 /
((src_width + 32) * fmt->bpp);
} else {
@@ -310,7 +310,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
fmt ? (char *)&fmt->base.pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, qos_lut);
- pstate->pipe_hw->ops.setup_creq_lut(pstate->pipe_hw, qos_lut);
+ pstate->pipe.sspp->ops.setup_creq_lut(pstate->pipe.sspp, qos_lut);
}
/**
@@ -362,7 +362,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
danger_lut,
safe_lut);
- pstate->pipe_hw->ops.setup_danger_safe_lut(pstate->pipe_hw,
+ pstate->pipe.sspp->ops.setup_danger_safe_lut(pstate->pipe.sspp,
danger_lut, safe_lut);
}
@@ -382,9 +382,9 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
- pipe_qos_cfg.creq_vblank = pstate->pipe_hw->cap->sblk->creq_vblank;
+ pipe_qos_cfg.creq_vblank = pstate->pipe.sspp->cap->sblk->creq_vblank;
pipe_qos_cfg.danger_vblank =
- pstate->pipe_hw->cap->sblk->danger_vblank;
+ pstate->pipe.sspp->cap->sblk->danger_vblank;
pipe_qos_cfg.vblank_en = enable;
}
@@ -410,7 +410,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
pipe_qos_cfg.danger_vblank,
pdpu->is_rt_pipe);
- pstate->pipe_hw->ops.setup_qos_ctrl(pstate->pipe_hw,
+ pstate->pipe.sspp->ops.setup_qos_ctrl(pstate->pipe.sspp,
&pipe_qos_cfg);
}
@@ -429,14 +429,14 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&ot_params, 0, sizeof(ot_params));
- ot_params.xin_id = pstate->pipe_hw->cap->xin_id;
- ot_params.num = pstate->pipe_hw->idx - SSPP_NONE;
+ ot_params.xin_id = pstate->pipe.sspp->cap->xin_id;
+ ot_params.num = pstate->pipe.sspp->idx - SSPP_NONE;
ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
ot_params.is_wfd = !pdpu->is_rt_pipe;
ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
ot_params.vbif_idx = VBIF_RT;
- ot_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
+ ot_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl;
ot_params.rd = true;
dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
@@ -455,9 +455,9 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = VBIF_RT;
- qos_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl;
- qos_params.xin_id = pstate->pipe_hw->cap->xin_id;
- qos_params.num = pstate->pipe_hw->idx - SSPP_VIG0;
+ qos_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl;
+ qos_params.xin_id = pstate->pipe.sspp->cap->xin_id;
+ qos_params.num = pstate->pipe.sspp->idx - SSPP_VIG0;
qos_params.is_rt = pdpu->is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
@@ -482,12 +482,12 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
- else if (pstate->pipe_hw->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(pstate->pipe_hw->idx,
+ else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
+ trace_dpu_plane_set_scanout(pstate->pipe.sspp->idx,
&pipe_cfg->layout,
- pstate->multirect_index);
- pstate->pipe_hw->ops.setup_sourceaddress(pstate->pipe_hw, pipe_cfg,
- pstate->multirect_index);
+ pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_sourceaddress(pstate->pipe.sspp, pipe_cfg,
+ pstate->pipe.multirect_index);
}
}
@@ -538,7 +538,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->src_height[i] /= chroma_subsmpl_v;
}
- if (pstate->pipe_hw->cap->features &
+ if (pstate->pipe.sspp->cap->features &
BIT(DPU_SSPP_SCALER_QSEED4)) {
scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
@@ -622,7 +622,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
if (!DPU_FORMAT_IS_YUV(fmt))
return NULL;
- if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe_hw->cap->features)
+ if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe.sspp->cap->features)
csc_ptr = &dpu_csc10_YUV2RGB_601L;
else
csc_ptr = &dpu_csc_YUV2RGB_601L;
@@ -665,8 +665,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
_dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
src_width, src_height, info->hsub, info->vsub);
- if (pstate->pipe_hw->ops.setup_pe)
- pstate->pipe_hw->ops.setup_pe(pstate->pipe_hw,
+ if (pstate->pipe.sspp->ops.setup_pe)
+ pstate->pipe.sspp->ops.setup_pe(pstate->pipe.sspp,
&pixel_ext);
/**
@@ -674,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
* bypassed. Still we need to update alpha and bitwidth
* ONLY for RECT0
*/
- if (pstate->pipe_hw->ops.setup_scaler &&
- pstate->multirect_index != DPU_SSPP_RECT_1)
- pstate->pipe_hw->ops.setup_scaler(pstate->pipe_hw,
+ if (pstate->pipe.sspp->ops.setup_scaler &&
+ pstate->pipe.multirect_index != DPU_SSPP_RECT_1)
+ pstate->pipe.sspp->ops.setup_scaler(pstate->pipe.sspp,
pipe_cfg,
&scaler3_cfg);
}
@@ -705,10 +705,10 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
/* update sspp */
- if (fmt && pstate->pipe_hw->ops.setup_solidfill) {
- pstate->pipe_hw->ops.setup_solidfill(pstate->pipe_hw,
+ if (fmt && pstate->pipe.sspp->ops.setup_solidfill) {
+ pstate->pipe.sspp->ops.setup_solidfill(pstate->pipe.sspp,
(color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
- pstate->multirect_index);
+ pstate->pipe.multirect_index);
/* override scaler/decimation if solid fill */
pipe_cfg.dst_rect = pstate->base.dst;
@@ -720,15 +720,15 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
pipe_cfg.src_rect.y2 =
drm_rect_height(&pipe_cfg.dst_rect);
- if (pstate->pipe_hw->ops.setup_format)
- pstate->pipe_hw->ops.setup_format(pstate->pipe_hw,
+ if (pstate->pipe.sspp->ops.setup_format)
+ pstate->pipe.sspp->ops.setup_format(pstate->pipe.sspp,
fmt, DPU_SSPP_SOLID_FILL,
- pstate->multirect_index);
+ pstate->pipe.multirect_index);
- if (pstate->pipe_hw->ops.setup_rects)
- pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
+ if (pstate->pipe.sspp->ops.setup_rects)
+ pstate->pipe.sspp->ops.setup_rects(pstate->pipe.sspp,
&pipe_cfg,
- pstate->multirect_index);
+ pstate->pipe.multirect_index);
_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
}
@@ -740,8 +740,8 @@ void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
{
struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
- pstate->multirect_index = DPU_SSPP_RECT_SOLO;
- pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
+ pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
}
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
@@ -823,8 +823,8 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
/* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
if (parallel_fetch_qualified) {
- pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
- pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+ pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+ pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
goto done;
}
@@ -834,8 +834,8 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
if (dst[R1].y1 >= dst[R0].y2 + buffer_lines ||
dst[R0].y1 >= dst[R1].y2 + buffer_lines) {
- pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
- pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
+ pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
+ pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
} else {
DPU_ERROR(
"No multirect mode possible for the planes (%d - %d)\n",
@@ -845,13 +845,13 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
}
done:
- pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
- pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
+ pstate[R0]->pipe.multirect_index = DPU_SSPP_RECT_0;
+ pstate[R1]->pipe.multirect_index = DPU_SSPP_RECT_1;
DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
- pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
+ pstate[R0]->pipe.multirect_mode, pstate[R0]->pipe.multirect_index);
DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
- pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
+ pstate[R1]->pipe.multirect_mode, pstate[R1]->pipe.multirect_index);
return 0;
}
@@ -978,8 +978,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
uint32_t min_src_size, max_linewidth;
unsigned int rotation;
uint32_t supported_rotations;
- const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe_hw->cap;
- const struct dpu_sspp_sub_blks *sblk = pstate->pipe_hw->cap->sblk;
+ const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap;
+ const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk;
if (new_plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
@@ -1092,12 +1092,12 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else if (pstate->pipe_hw && pstate->pipe_hw->ops.setup_csc) {
+ else if (pstate->pipe.sspp && pstate->pipe.sspp->ops.setup_csc) {
const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
if (csc_ptr)
- pstate->pipe_hw->ops.setup_csc(pstate->pipe_hw, csc_ptr);
+ pstate->pipe.sspp->ops.setup_csc(pstate->pipe.sspp, csc_ptr);
}
/* flag h/w flush complete */
@@ -1127,6 +1127,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct drm_plane_state *state = plane->state;
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ struct dpu_sw_pipe *pipe = &pstate->pipe;
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
bool is_rt_pipe;
@@ -1167,21 +1168,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
return;
}
- if (pstate->pipe_hw->ops.setup_rects) {
- pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw,
+ if (pipe->sspp->ops.setup_rects) {
+ pipe->sspp->ops.setup_rects(pipe->sspp,
&pipe_cfg,
- pstate->multirect_index);
+ pipe->multirect_index);
}
_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
- if (pstate->pipe_hw->ops.setup_multirect)
- pstate->pipe_hw->ops.setup_multirect(
- pstate->pipe_hw,
- pstate->multirect_index,
- pstate->multirect_mode);
+ if (pipe->sspp->ops.setup_multirect)
+ pipe->sspp->ops.setup_multirect(
+ pipe->sspp,
+ pipe->multirect_index,
+ pipe->multirect_mode);
- if (pstate->pipe_hw->ops.setup_format) {
+ if (pipe->sspp->ops.setup_format) {
unsigned int rotation = pstate->rotation;
src_flags = 0x0;
@@ -1196,10 +1197,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
src_flags |= DPU_SSPP_ROT_90;
/* update format */
- pstate->pipe_hw->ops.setup_format(pstate->pipe_hw, fmt, src_flags,
- pstate->multirect_index);
+ pipe->sspp->ops.setup_format(pipe->sspp, fmt, src_flags,
+ pipe->multirect_index);
- if (pstate->pipe_hw->ops.setup_cdp) {
+ if (pipe->sspp->ops.setup_cdp) {
struct dpu_hw_cdp_cfg cdp_cfg;
memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
@@ -1213,7 +1214,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_FORMAT_IS_TILE(fmt);
cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
- pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, &cdp_cfg, pstate->multirect_index);
+ pipe->sspp->ops.setup_cdp(pipe->sspp, &cdp_cfg, pipe->multirect_index);
}
}
@@ -1241,7 +1242,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane)
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
trace_dpu_plane_disable(DRMID(plane), false,
- pstate->multirect_mode);
+ pstate->pipe.multirect_mode);
pstate->pending = true;
}
@@ -1355,9 +1356,9 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
drm_printf(p, "\tstage=%d\n", pstate->stage);
- drm_printf(p, "\tsspp=%s\n", pstate->pipe_hw->cap->name);
- drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode));
- drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index));
+ drm_printf(p, "\tsspp=%s\n", pstate->pipe.sspp->cap->name);
+ drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->pipe.multirect_mode));
+ drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->pipe.multirect_index));
}
static void dpu_plane_reset(struct drm_plane *plane)
@@ -1386,7 +1387,7 @@ static void dpu_plane_reset(struct drm_plane *plane)
return;
}
- pstate->pipe_hw = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
+ pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
__drm_atomic_helper_plane_reset(plane, &pstate->base);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 8786359a191c..55ea221e8488 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -33,11 +33,9 @@ struct dpu_plane_state {
struct msm_gem_address_space *aspace;
enum dpu_stage stage;
bool needs_qos_remap;
- uint32_t multirect_index;
- uint32_t multirect_mode;
bool pending;
- struct dpu_hw_sspp *pipe_hw;
+ struct dpu_sw_pipe pipe;
u64 plane_fetch_bw;
u64 plane_clk;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 76169f406505..d7059972499f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -633,9 +633,9 @@ TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
TRACE_EVENT(dpu_crtc_setup_mixer,
TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
struct drm_plane_state *state, struct dpu_plane_state *pstate,
- uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format,
+ uint32_t stage_idx, uint32_t pixel_format,
uint64_t modifier),
- TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
+ TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
pixel_format, modifier),
TP_STRUCT__entry(
__field( uint32_t, crtc_id )
@@ -659,9 +659,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer,
__entry->dst_rect = drm_plane_state_dest(state);
__entry->stage_idx = stage_idx;
__entry->stage = pstate->stage;
- __entry->sspp = sspp;
- __entry->multirect_idx = pstate->multirect_index;
- __entry->multirect_mode = pstate->multirect_mode;
+ __entry->sspp = pstate->pipe.sspp->idx;
+ __entry->multirect_idx = pstate->pipe.multirect_index;
+ __entry->multirect_mode = pstate->pipe.multirect_mode;
__entry->pixel_format = pixel_format;
__entry->modifier = modifier;
),
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 09/27] drm/msm/dpu: use dpu_sw_pipe for dpu_hw_sspp callbacks
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Where feasible, use dpu_sw_pipe rather than a combo of dpu_hw_sspp and
multirect_index/_mode arguments.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 59 +++++++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 46 +++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 73 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 9 ++-
4 files changed, 84 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 93f01f767fd8..f7f81ab08fa2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -168,17 +168,16 @@ static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
return rc;
}
-static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
- enum dpu_sspp_multirect_index index,
- enum dpu_sspp_multirect_mode mode)
+static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
u32 mode_mask;
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (index == DPU_SSPP_RECT_SOLO) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
/**
* if rect index is RECT_SOLO, we cannot expect a
* virtual plane sharing the same SSPP id. So we go
@@ -187,8 +186,8 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
mode_mask = 0;
} else {
mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx);
- mode_mask |= index;
- if (mode == DPU_SSPP_MULTIRECT_TIME_MX)
+ mode_mask |= pipe->multirect_index;
+ if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
mode_mask |= BIT(2);
else
mode_mask &= ~BIT(2);
@@ -239,10 +238,10 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
/*
* Setup source pixel format, flip,
*/
-static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
- const struct dpu_format *fmt, u32 flags,
- enum dpu_sspp_multirect_index rect_mode)
+static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
+ const struct dpu_format *fmt, u32 flags)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
u32 chroma_samp, unpack, src_format;
u32 opmode = 0;
@@ -253,7 +252,8 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt)
return;
- if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0) {
op_mode_off = SSPP_SRC_OP_MODE;
unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
format_off = SSPP_SRC_FORMAT;
@@ -443,10 +443,10 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
/*
* dpu_hw_sspp_setup_rects()
*/
-static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index rect_index)
+static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *cfg)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
@@ -457,7 +457,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
c = &ctx->hw;
- if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0) {
src_size_off = SSPP_SRC_SIZE;
src_xy_off = SSPP_SRC_XY;
out_size_off = SSPP_OUT_SIZE;
@@ -478,7 +479,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
drm_rect_width(&cfg->dst_rect);
- if (rect_index == DPU_SSPP_RECT_SOLO) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
ystride0 = (cfg->layout.plane_pitch[0]) |
(cfg->layout.plane_pitch[1] << 16);
ystride1 = (cfg->layout.plane_pitch[2]) |
@@ -487,7 +488,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
- if (rect_index == DPU_SSPP_RECT_0) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_0) {
ystride0 = (ystride0 & 0xFFFF0000) |
(cfg->layout.plane_pitch[0] & 0x0000FFFF);
ystride1 = (ystride1 & 0xFFFF0000)|
@@ -512,21 +513,21 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
-static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index rect_mode)
+static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *cfg)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
int i;
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (rect_mode == DPU_SSPP_RECT_SOLO) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
cfg->layout.plane_addr[i]);
- } else if (rect_mode == DPU_SSPP_RECT_0) {
+ } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
cfg->layout.plane_addr[0]);
DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
@@ -556,15 +557,16 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
}
-static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32 color, enum
- dpu_sspp_multirect_index rect_index)
+static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0)
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0)
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);
else
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx,
@@ -626,10 +628,10 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
}
-static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
- struct dpu_hw_cdp_cfg *cfg,
- enum dpu_sspp_multirect_index index)
+static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_cdp_cfg *cfg)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
u32 idx;
u32 cdp_cntl = 0;
u32 cdp_cntl_offset = 0;
@@ -640,7 +642,8 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (index == DPU_SSPP_RECT_SOLO || index == DPU_SSPP_RECT_0)
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0)
cdp_cntl_offset = SSPP_CDP_CNTL;
else
cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index a96afc53e0f6..f5aae563741a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -217,24 +217,20 @@ struct dpu_sw_pipe {
struct dpu_hw_sspp_ops {
/**
* setup_format - setup pixel format cropping rectangle, flip
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @cfg: Pointer to pipe config structure
* @flags: Extra flags for format config
- * @index: rectangle index in multirect
*/
- void (*setup_format)(struct dpu_hw_sspp *ctx,
- const struct dpu_format *fmt, u32 flags,
- enum dpu_sspp_multirect_index index);
+ void (*setup_format)(struct dpu_sw_pipe *pipe,
+ const struct dpu_format *fmt, u32 flags);
/**
* setup_rects - setup pipe ROI rectangles
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @cfg: Pointer to pipe config structure
- * @index: rectangle index in multirect
*/
- void (*setup_rects)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index index);
+ void (*setup_rects)(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *cfg);
/**
* setup_pe - setup pipe pixel extension
@@ -246,13 +242,11 @@ struct dpu_hw_sspp_ops {
/**
* setup_sourceaddress - setup pipe source addresses
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @cfg: Pointer to pipe config structure
- * @index: rectangle index in multirect
*/
- void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index index);
+ void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
+ struct dpu_hw_pipe_cfg *cfg);
/**
* setup_csc - setup color space coversion
@@ -263,24 +257,18 @@ struct dpu_hw_sspp_ops {
/**
* setup_solidfill - enable/disable colorfill
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @const_color: Fill color value
* @flags: Pipe flags
- * @index: rectangle index in multirect
*/
- void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color,
- enum dpu_sspp_multirect_index index);
+ void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color);
/**
* setup_multirect - setup multirect configuration
- * @ctx: Pointer to pipe context
- * @index: rectangle index in multirect
- * @mode: parallel fetch / time multiplex multirect mode
+ * @pipe: Pointer to software pipe context
*/
- void (*setup_multirect)(struct dpu_hw_sspp *ctx,
- enum dpu_sspp_multirect_index index,
- enum dpu_sspp_multirect_mode mode);
+ void (*setup_multirect)(struct dpu_sw_pipe *pipe);
/**
* setup_sharpening - setup sharpening
@@ -345,13 +333,11 @@ struct dpu_hw_sspp_ops {
/**
* setup_cdp - setup client driven prefetch
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @cfg: Pointer to cdp configuration
- * @index: rectangle index in multirect
*/
- void (*setup_cdp)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_cdp_cfg *cfg,
- enum dpu_sspp_multirect_index index);
+ void (*setup_cdp)(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_cdp_cfg *cfg);
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 1b17213235dc..172a2c012917 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -483,23 +483,21 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(pstate->pipe.sspp->idx,
- &pipe_cfg->layout,
- pstate->pipe.multirect_index);
- pstate->pipe.sspp->ops.setup_sourceaddress(pstate->pipe.sspp, pipe_cfg,
- pstate->pipe.multirect_index);
+ trace_dpu_plane_set_scanout(&pstate->pipe,
+ &pipe_cfg->layout);
+ pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
}
}
-static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate,
+static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
const struct dpu_format *fmt,
- uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
+ uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
+ unsigned int rotation)
{
uint32_t i;
- bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90;
+ bool inline_rotation = rotation & DRM_MODE_ROTATE_90;
/*
* For inline rotation cases, scaler config is post-rotation,
@@ -538,7 +536,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->src_height[i] /= chroma_subsmpl_v;
}
- if (pstate->pipe.sspp->cap->features &
+ if (pipe_hw->cap->features &
BIT(DPU_SSPP_SCALER_QSEED4)) {
scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
@@ -635,11 +633,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
return csc_ptr;
}
-static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate,
+static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, bool color_fill,
- struct dpu_hw_pipe_cfg *pipe_cfg)
+ struct dpu_hw_pipe_cfg *pipe_cfg,
+ unsigned int rotation)
{
+ struct dpu_hw_sspp *pipe_hw = pipe->sspp;
const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
@@ -653,20 +652,21 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
/* don't chroma subsample if decimating */
/* update scaler. calculate default config for QSEED3 */
- _dpu_plane_setup_scaler3(pdpu, pstate,
+ _dpu_plane_setup_scaler3(pipe_hw,
src_width,
src_height,
dst_width,
dst_height,
&scaler3_cfg, fmt,
- info->hsub, info->vsub);
+ info->hsub, info->vsub,
+ rotation);
/* configure pixel extension based on scalar config */
_dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
src_width, src_height, info->hsub, info->vsub);
- if (pstate->pipe.sspp->ops.setup_pe)
- pstate->pipe.sspp->ops.setup_pe(pstate->pipe.sspp,
+ if (pipe_hw->ops.setup_pe)
+ pipe_hw->ops.setup_pe(pipe_hw,
&pixel_ext);
/**
@@ -674,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
* bypassed. Still we need to update alpha and bitwidth
* ONLY for RECT0
*/
- if (pstate->pipe.sspp->ops.setup_scaler &&
- pstate->pipe.multirect_index != DPU_SSPP_RECT_1)
- pstate->pipe.sspp->ops.setup_scaler(pstate->pipe.sspp,
+ if (pipe_hw->ops.setup_scaler &&
+ pipe->multirect_index != DPU_SSPP_RECT_1)
+ pipe_hw->ops.setup_scaler(pipe_hw,
pipe_cfg,
&scaler3_cfg);
}
@@ -706,9 +706,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
/* update sspp */
if (fmt && pstate->pipe.sspp->ops.setup_solidfill) {
- pstate->pipe.sspp->ops.setup_solidfill(pstate->pipe.sspp,
- (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_solidfill(&pstate->pipe,
+ (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
/* override scaler/decimation if solid fill */
pipe_cfg.dst_rect = pstate->base.dst;
@@ -721,16 +720,14 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
drm_rect_height(&pipe_cfg.dst_rect);
if (pstate->pipe.sspp->ops.setup_format)
- pstate->pipe.sspp->ops.setup_format(pstate->pipe.sspp,
- fmt, DPU_SSPP_SOLID_FILL,
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_format(&pstate->pipe,
+ fmt, DPU_SSPP_SOLID_FILL);
if (pstate->pipe.sspp->ops.setup_rects)
- pstate->pipe.sspp->ops.setup_rects(pstate->pipe.sspp,
- &pipe_cfg,
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_rects(&pstate->pipe,
+ &pipe_cfg);
- _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
+ _dpu_plane_setup_scaler(&pstate->pipe, fmt, true, &pipe_cfg, pstate->rotation);
}
return 0;
@@ -1169,18 +1166,15 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
if (pipe->sspp->ops.setup_rects) {
- pipe->sspp->ops.setup_rects(pipe->sspp,
- &pipe_cfg,
- pipe->multirect_index);
+ pipe->sspp->ops.setup_rects(pipe,
+ &pipe_cfg);
}
- _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
+ _dpu_plane_setup_scaler(pipe, fmt, false, &pipe_cfg, pstate->rotation);
if (pipe->sspp->ops.setup_multirect)
pipe->sspp->ops.setup_multirect(
- pipe->sspp,
- pipe->multirect_index,
- pipe->multirect_mode);
+ pipe);
if (pipe->sspp->ops.setup_format) {
unsigned int rotation = pstate->rotation;
@@ -1197,8 +1191,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
src_flags |= DPU_SSPP_ROT_90;
/* update format */
- pipe->sspp->ops.setup_format(pipe->sspp, fmt, src_flags,
- pipe->multirect_index);
+ pipe->sspp->ops.setup_format(pipe, fmt, src_flags);
if (pipe->sspp->ops.setup_cdp) {
struct dpu_hw_cdp_cfg cdp_cfg;
@@ -1214,7 +1207,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_FORMAT_IS_TILE(fmt);
cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
- pipe->sspp->ops.setup_cdp(pipe->sspp, &cdp_cfg, pipe->multirect_index);
+ pipe->sspp->ops.setup_cdp(pipe, &cdp_cfg);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index d7059972499f..0ad148cc2fb8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -762,18 +762,17 @@ TRACE_EVENT(dpu_crtc_disable_frame_pending,
);
TRACE_EVENT(dpu_plane_set_scanout,
- TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout,
- enum dpu_sspp_multirect_index multirect_index),
- TP_ARGS(index, layout, multirect_index),
+ TP_PROTO(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout),
+ TP_ARGS(pipe, layout),
TP_STRUCT__entry(
__field( enum dpu_sspp, index )
__field_struct( struct dpu_hw_fmt_layout, layout )
__field( enum dpu_sspp_multirect_index, multirect_index)
),
TP_fast_assign(
- __entry->index = index;
+ __entry->index = pipe->sspp->idx;
__entry->layout = *layout;
- __entry->multirect_index = multirect_index;
+ __entry->multirect_index = pipe->multirect_index;
),
TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
"multirect_index:%d", __entry->index, __entry->layout.width,
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 09/27] drm/msm/dpu: use dpu_sw_pipe for dpu_hw_sspp callbacks
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Where feasible, use dpu_sw_pipe rather than a combo of dpu_hw_sspp and
multirect_index/_mode arguments.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 59 +++++++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 46 +++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 73 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 9 ++-
4 files changed, 84 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 93f01f767fd8..f7f81ab08fa2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -168,17 +168,16 @@ static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx,
return rc;
}
-static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
- enum dpu_sspp_multirect_index index,
- enum dpu_sspp_multirect_mode mode)
+static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
u32 mode_mask;
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (index == DPU_SSPP_RECT_SOLO) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
/**
* if rect index is RECT_SOLO, we cannot expect a
* virtual plane sharing the same SSPP id. So we go
@@ -187,8 +186,8 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx,
mode_mask = 0;
} else {
mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx);
- mode_mask |= index;
- if (mode == DPU_SSPP_MULTIRECT_TIME_MX)
+ mode_mask |= pipe->multirect_index;
+ if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
mode_mask |= BIT(2);
else
mode_mask &= ~BIT(2);
@@ -239,10 +238,10 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
/*
* Setup source pixel format, flip,
*/
-static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
- const struct dpu_format *fmt, u32 flags,
- enum dpu_sspp_multirect_index rect_mode)
+static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
+ const struct dpu_format *fmt, u32 flags)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
u32 chroma_samp, unpack, src_format;
u32 opmode = 0;
@@ -253,7 +252,8 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx,
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt)
return;
- if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0) {
op_mode_off = SSPP_SRC_OP_MODE;
unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
format_off = SSPP_SRC_FORMAT;
@@ -443,10 +443,10 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
/*
* dpu_hw_sspp_setup_rects()
*/
-static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index rect_index)
+static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *cfg)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
@@ -457,7 +457,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
c = &ctx->hw;
- if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0) {
src_size_off = SSPP_SRC_SIZE;
src_xy_off = SSPP_SRC_XY;
out_size_off = SSPP_OUT_SIZE;
@@ -478,7 +479,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
drm_rect_width(&cfg->dst_rect);
- if (rect_index == DPU_SSPP_RECT_SOLO) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
ystride0 = (cfg->layout.plane_pitch[0]) |
(cfg->layout.plane_pitch[1] << 16);
ystride1 = (cfg->layout.plane_pitch[2]) |
@@ -487,7 +488,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
- if (rect_index == DPU_SSPP_RECT_0) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_0) {
ystride0 = (ystride0 & 0xFFFF0000) |
(cfg->layout.plane_pitch[0] & 0x0000FFFF);
ystride1 = (ystride1 & 0xFFFF0000)|
@@ -512,21 +513,21 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx,
DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
-static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index rect_mode)
+static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *cfg)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
int i;
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (rect_mode == DPU_SSPP_RECT_SOLO) {
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
cfg->layout.plane_addr[i]);
- } else if (rect_mode == DPU_SSPP_RECT_0) {
+ } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
cfg->layout.plane_addr[0]);
DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
@@ -556,15 +557,16 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
}
-static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32 color, enum
- dpu_sspp_multirect_index rect_index)
+static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
u32 idx;
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0)
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0)
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);
else
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx,
@@ -626,10 +628,10 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
}
-static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
- struct dpu_hw_cdp_cfg *cfg,
- enum dpu_sspp_multirect_index index)
+static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_cdp_cfg *cfg)
{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
u32 idx;
u32 cdp_cntl = 0;
u32 cdp_cntl_offset = 0;
@@ -640,7 +642,8 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx,
if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
return;
- if (index == DPU_SSPP_RECT_SOLO || index == DPU_SSPP_RECT_0)
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0)
cdp_cntl_offset = SSPP_CDP_CNTL;
else
cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index a96afc53e0f6..f5aae563741a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -217,24 +217,20 @@ struct dpu_sw_pipe {
struct dpu_hw_sspp_ops {
/**
* setup_format - setup pixel format cropping rectangle, flip
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @cfg: Pointer to pipe config structure
* @flags: Extra flags for format config
- * @index: rectangle index in multirect
*/
- void (*setup_format)(struct dpu_hw_sspp *ctx,
- const struct dpu_format *fmt, u32 flags,
- enum dpu_sspp_multirect_index index);
+ void (*setup_format)(struct dpu_sw_pipe *pipe,
+ const struct dpu_format *fmt, u32 flags);
/**
* setup_rects - setup pipe ROI rectangles
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @cfg: Pointer to pipe config structure
- * @index: rectangle index in multirect
*/
- void (*setup_rects)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index index);
+ void (*setup_rects)(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *cfg);
/**
* setup_pe - setup pipe pixel extension
@@ -246,13 +242,11 @@ struct dpu_hw_sspp_ops {
/**
* setup_sourceaddress - setup pipe source addresses
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @cfg: Pointer to pipe config structure
- * @index: rectangle index in multirect
*/
- void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *cfg,
- enum dpu_sspp_multirect_index index);
+ void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
+ struct dpu_hw_pipe_cfg *cfg);
/**
* setup_csc - setup color space coversion
@@ -263,24 +257,18 @@ struct dpu_hw_sspp_ops {
/**
* setup_solidfill - enable/disable colorfill
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @const_color: Fill color value
* @flags: Pipe flags
- * @index: rectangle index in multirect
*/
- void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color,
- enum dpu_sspp_multirect_index index);
+ void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color);
/**
* setup_multirect - setup multirect configuration
- * @ctx: Pointer to pipe context
- * @index: rectangle index in multirect
- * @mode: parallel fetch / time multiplex multirect mode
+ * @pipe: Pointer to software pipe context
*/
- void (*setup_multirect)(struct dpu_hw_sspp *ctx,
- enum dpu_sspp_multirect_index index,
- enum dpu_sspp_multirect_mode mode);
+ void (*setup_multirect)(struct dpu_sw_pipe *pipe);
/**
* setup_sharpening - setup sharpening
@@ -345,13 +333,11 @@ struct dpu_hw_sspp_ops {
/**
* setup_cdp - setup client driven prefetch
- * @ctx: Pointer to pipe context
+ * @pipe: Pointer to software pipe context
* @cfg: Pointer to cdp configuration
- * @index: rectangle index in multirect
*/
- void (*setup_cdp)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_cdp_cfg *cfg,
- enum dpu_sspp_multirect_index index);
+ void (*setup_cdp)(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_cdp_cfg *cfg);
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 1b17213235dc..172a2c012917 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -483,23 +483,21 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(pstate->pipe.sspp->idx,
- &pipe_cfg->layout,
- pstate->pipe.multirect_index);
- pstate->pipe.sspp->ops.setup_sourceaddress(pstate->pipe.sspp, pipe_cfg,
- pstate->pipe.multirect_index);
+ trace_dpu_plane_set_scanout(&pstate->pipe,
+ &pipe_cfg->layout);
+ pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
}
}
-static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate,
+static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
const struct dpu_format *fmt,
- uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
+ uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
+ unsigned int rotation)
{
uint32_t i;
- bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90;
+ bool inline_rotation = rotation & DRM_MODE_ROTATE_90;
/*
* For inline rotation cases, scaler config is post-rotation,
@@ -538,7 +536,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->src_height[i] /= chroma_subsmpl_v;
}
- if (pstate->pipe.sspp->cap->features &
+ if (pipe_hw->cap->features &
BIT(DPU_SSPP_SCALER_QSEED4)) {
scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
@@ -635,11 +633,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
return csc_ptr;
}
-static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate,
+static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, bool color_fill,
- struct dpu_hw_pipe_cfg *pipe_cfg)
+ struct dpu_hw_pipe_cfg *pipe_cfg,
+ unsigned int rotation)
{
+ struct dpu_hw_sspp *pipe_hw = pipe->sspp;
const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
@@ -653,20 +652,21 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
/* don't chroma subsample if decimating */
/* update scaler. calculate default config for QSEED3 */
- _dpu_plane_setup_scaler3(pdpu, pstate,
+ _dpu_plane_setup_scaler3(pipe_hw,
src_width,
src_height,
dst_width,
dst_height,
&scaler3_cfg, fmt,
- info->hsub, info->vsub);
+ info->hsub, info->vsub,
+ rotation);
/* configure pixel extension based on scalar config */
_dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
src_width, src_height, info->hsub, info->vsub);
- if (pstate->pipe.sspp->ops.setup_pe)
- pstate->pipe.sspp->ops.setup_pe(pstate->pipe.sspp,
+ if (pipe_hw->ops.setup_pe)
+ pipe_hw->ops.setup_pe(pipe_hw,
&pixel_ext);
/**
@@ -674,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
* bypassed. Still we need to update alpha and bitwidth
* ONLY for RECT0
*/
- if (pstate->pipe.sspp->ops.setup_scaler &&
- pstate->pipe.multirect_index != DPU_SSPP_RECT_1)
- pstate->pipe.sspp->ops.setup_scaler(pstate->pipe.sspp,
+ if (pipe_hw->ops.setup_scaler &&
+ pipe->multirect_index != DPU_SSPP_RECT_1)
+ pipe_hw->ops.setup_scaler(pipe_hw,
pipe_cfg,
&scaler3_cfg);
}
@@ -706,9 +706,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
/* update sspp */
if (fmt && pstate->pipe.sspp->ops.setup_solidfill) {
- pstate->pipe.sspp->ops.setup_solidfill(pstate->pipe.sspp,
- (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_solidfill(&pstate->pipe,
+ (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
/* override scaler/decimation if solid fill */
pipe_cfg.dst_rect = pstate->base.dst;
@@ -721,16 +720,14 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
drm_rect_height(&pipe_cfg.dst_rect);
if (pstate->pipe.sspp->ops.setup_format)
- pstate->pipe.sspp->ops.setup_format(pstate->pipe.sspp,
- fmt, DPU_SSPP_SOLID_FILL,
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_format(&pstate->pipe,
+ fmt, DPU_SSPP_SOLID_FILL);
if (pstate->pipe.sspp->ops.setup_rects)
- pstate->pipe.sspp->ops.setup_rects(pstate->pipe.sspp,
- &pipe_cfg,
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_rects(&pstate->pipe,
+ &pipe_cfg);
- _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
+ _dpu_plane_setup_scaler(&pstate->pipe, fmt, true, &pipe_cfg, pstate->rotation);
}
return 0;
@@ -1169,18 +1166,15 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
if (pipe->sspp->ops.setup_rects) {
- pipe->sspp->ops.setup_rects(pipe->sspp,
- &pipe_cfg,
- pipe->multirect_index);
+ pipe->sspp->ops.setup_rects(pipe,
+ &pipe_cfg);
}
- _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
+ _dpu_plane_setup_scaler(pipe, fmt, false, &pipe_cfg, pstate->rotation);
if (pipe->sspp->ops.setup_multirect)
pipe->sspp->ops.setup_multirect(
- pipe->sspp,
- pipe->multirect_index,
- pipe->multirect_mode);
+ pipe);
if (pipe->sspp->ops.setup_format) {
unsigned int rotation = pstate->rotation;
@@ -1197,8 +1191,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
src_flags |= DPU_SSPP_ROT_90;
/* update format */
- pipe->sspp->ops.setup_format(pipe->sspp, fmt, src_flags,
- pipe->multirect_index);
+ pipe->sspp->ops.setup_format(pipe, fmt, src_flags);
if (pipe->sspp->ops.setup_cdp) {
struct dpu_hw_cdp_cfg cdp_cfg;
@@ -1214,7 +1207,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_FORMAT_IS_TILE(fmt);
cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
- pipe->sspp->ops.setup_cdp(pipe->sspp, &cdp_cfg, pipe->multirect_index);
+ pipe->sspp->ops.setup_cdp(pipe, &cdp_cfg);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index d7059972499f..0ad148cc2fb8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -762,18 +762,17 @@ TRACE_EVENT(dpu_crtc_disable_frame_pending,
);
TRACE_EVENT(dpu_plane_set_scanout,
- TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout,
- enum dpu_sspp_multirect_index multirect_index),
- TP_ARGS(index, layout, multirect_index),
+ TP_PROTO(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout),
+ TP_ARGS(pipe, layout),
TP_STRUCT__entry(
__field( enum dpu_sspp, index )
__field_struct( struct dpu_hw_fmt_layout, layout )
__field( enum dpu_sspp_multirect_index, multirect_index)
),
TP_fast_assign(
- __entry->index = index;
+ __entry->index = pipe->sspp->idx;
__entry->layout = *layout;
- __entry->multirect_index = multirect_index;
+ __entry->multirect_index = pipe->multirect_index;
),
TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
"multirect_index:%d", __entry->index, __entry->layout.width,
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 10/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
There is no need to pass full dpu_hw_pipe_cfg instance to
_dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7 +++----
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
3 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index f7f81ab08fa2..176cd6dc9a69 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -415,19 +415,18 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
}
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *sspp,
- void *scaler_cfg)
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct dpu_format *format)
{
u32 idx;
- struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
- if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
+ if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
|| !scaler3_cfg)
return;
dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
ctx->cap->sblk->scaler_blk.version,
- sspp->layout.format);
+ format);
}
static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index f5aae563741a..c713343378aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops {
/**
* setup_scaler - setup scaler
- * @ctx: Pointer to pipe context
- * @pipe_cfg: Pointer to pipe configuration
* @scaler_cfg: Pointer to scaler configuration
+ * @format: pixel format parameters
*/
void (*setup_scaler)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *pipe_cfg,
- void *scaler_cfg);
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct dpu_format *format);
/**
* get_scaler_ver - get scaler h/w version
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 172a2c012917..cbff4dea8662 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
if (pipe_hw->ops.setup_scaler &&
pipe->multirect_index != DPU_SSPP_RECT_1)
pipe_hw->ops.setup_scaler(pipe_hw,
- pipe_cfg,
- &scaler3_cfg);
+ &scaler3_cfg,
+ fmt);
}
/**
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 10/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
There is no need to pass full dpu_hw_pipe_cfg instance to
_dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7 +++----
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
3 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index f7f81ab08fa2..176cd6dc9a69 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -415,19 +415,18 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
}
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *sspp,
- void *scaler_cfg)
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct dpu_format *format)
{
u32 idx;
- struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
- if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
+ if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
|| !scaler3_cfg)
return;
dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
ctx->cap->sblk->scaler_blk.version,
- sspp->layout.format);
+ format);
}
static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index f5aae563741a..c713343378aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops {
/**
* setup_scaler - setup scaler
- * @ctx: Pointer to pipe context
- * @pipe_cfg: Pointer to pipe configuration
* @scaler_cfg: Pointer to scaler configuration
+ * @format: pixel format parameters
*/
void (*setup_scaler)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_pipe_cfg *pipe_cfg,
- void *scaler_cfg);
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct dpu_format *format);
/**
* get_scaler_ver - get scaler h/w version
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 172a2c012917..cbff4dea8662 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
if (pipe_hw->ops.setup_scaler &&
pipe->multirect_index != DPU_SSPP_RECT_1)
pipe_hw->ops.setup_scaler(pipe_hw,
- pipe_cfg,
- &scaler3_cfg);
+ &scaler3_cfg,
+ fmt);
}
/**
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [PATCH v2 10/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2023-01-31 5:13 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-31 5:13 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> There is no need to pass full dpu_hw_pipe_cfg instance to
> _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++-----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7 +++----
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
> 3 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index f7f81ab08fa2..176cd6dc9a69 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -415,19 +415,18 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> }
>
> static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> - struct dpu_hw_pipe_cfg *sspp,
> - void *scaler_cfg)
> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> + const struct dpu_format *format)
> {
> u32 idx;
> - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
>
> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
> + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
> || !scaler3_cfg)
Do we need to check for !format ?
> return;
>
> dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
> ctx->cap->sblk->scaler_blk.version,
> - sspp->layout.format);
> + format);
> }
>
> static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index f5aae563741a..c713343378aa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops {
>
> /**
> * setup_scaler - setup scaler
> - * @ctx: Pointer to pipe context
> - * @pipe_cfg: Pointer to pipe configuration
> * @scaler_cfg: Pointer to scaler configuration
This doc needs to be fixed from scaler_cfg to scaler3_cfg
> + * @format: pixel format parameters
> */
> void (*setup_scaler)(struct dpu_hw_sspp *ctx,
> - struct dpu_hw_pipe_cfg *pipe_cfg,
> - void *scaler_cfg);
> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> + const struct dpu_format *format);
>
> /**
> * get_scaler_ver - get scaler h/w version
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 172a2c012917..cbff4dea8662 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
> if (pipe_hw->ops.setup_scaler &&
> pipe->multirect_index != DPU_SSPP_RECT_1)
> pipe_hw->ops.setup_scaler(pipe_hw,
> - pipe_cfg,
> - &scaler3_cfg);
> + &scaler3_cfg,
> + fmt);
> }
>
> /**
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 10/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
@ 2023-01-31 5:13 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-01-31 5:13 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> There is no need to pass full dpu_hw_pipe_cfg instance to
> _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++-----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7 +++----
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
> 3 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index f7f81ab08fa2..176cd6dc9a69 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -415,19 +415,18 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> }
>
> static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> - struct dpu_hw_pipe_cfg *sspp,
> - void *scaler_cfg)
> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> + const struct dpu_format *format)
> {
> u32 idx;
> - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
>
> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
> + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
> || !scaler3_cfg)
Do we need to check for !format ?
> return;
>
> dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
> ctx->cap->sblk->scaler_blk.version,
> - sspp->layout.format);
> + format);
> }
>
> static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index f5aae563741a..c713343378aa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops {
>
> /**
> * setup_scaler - setup scaler
> - * @ctx: Pointer to pipe context
> - * @pipe_cfg: Pointer to pipe configuration
> * @scaler_cfg: Pointer to scaler configuration
This doc needs to be fixed from scaler_cfg to scaler3_cfg
> + * @format: pixel format parameters
> */
> void (*setup_scaler)(struct dpu_hw_sspp *ctx,
> - struct dpu_hw_pipe_cfg *pipe_cfg,
> - void *scaler_cfg);
> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> + const struct dpu_format *format);
>
> /**
> * get_scaler_ver - get scaler h/w version
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 172a2c012917..cbff4dea8662 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
> if (pipe_hw->ops.setup_scaler &&
> pipe->multirect_index != DPU_SSPP_RECT_1)
> pipe_hw->ops.setup_scaler(pipe_hw,
> - pipe_cfg,
> - &scaler3_cfg);
> + &scaler3_cfg,
> + fmt);
> }
>
> /**
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 10/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
2023-01-31 5:13 ` Abhinav Kumar
@ 2023-01-31 12:10 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-31 12:10 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 31/01/2023 07:13, Abhinav Kumar wrote:
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>> There is no need to pass full dpu_hw_pipe_cfg instance to
>> _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++-----
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7 +++----
>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
>> 3 files changed, 9 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> index f7f81ab08fa2..176cd6dc9a69 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> @@ -415,19 +415,18 @@ static void dpu_hw_sspp_setup_pe_config(struct
>> dpu_hw_sspp *ctx,
>> }
>> static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
>> - struct dpu_hw_pipe_cfg *sspp,
>> - void *scaler_cfg)
>> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
>> + const struct dpu_format *format)
>> {
>> u32 idx;
>> - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
>> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
>> + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
>> || !scaler3_cfg)
>
> Do we need to check for !format ?
We don't have since the calling sequence ensures that it is not NULL,
but let's check for it since it's a different module.
>
>> return;
>> dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
>> ctx->cap->sblk->scaler_blk.version,
>> - sspp->layout.format);
>> + format);
>> }
>> static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> index f5aae563741a..c713343378aa 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops {
>> /**
>> * setup_scaler - setup scaler
>> - * @ctx: Pointer to pipe context
>> - * @pipe_cfg: Pointer to pipe configuration
>> * @scaler_cfg: Pointer to scaler configuration
>
> This doc needs to be fixed from scaler_cfg to scaler3_cfg
>
>> + * @format: pixel format parameters
>> */
>> void (*setup_scaler)(struct dpu_hw_sspp *ctx,
>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>> - void *scaler_cfg);
>> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
>> + const struct dpu_format *format);
>> /**
>> * get_scaler_ver - get scaler h/w version
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> index 172a2c012917..cbff4dea8662 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> @@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct
>> dpu_sw_pipe *pipe,
>> if (pipe_hw->ops.setup_scaler &&
>> pipe->multirect_index != DPU_SSPP_RECT_1)
>> pipe_hw->ops.setup_scaler(pipe_hw,
>> - pipe_cfg,
>> - &scaler3_cfg);
>> + &scaler3_cfg,
>> + fmt);
>> }
>> /**
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 10/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
@ 2023-01-31 12:10 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-31 12:10 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 31/01/2023 07:13, Abhinav Kumar wrote:
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>> There is no need to pass full dpu_hw_pipe_cfg instance to
>> _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++-----
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7 +++----
>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
>> 3 files changed, 9 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> index f7f81ab08fa2..176cd6dc9a69 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>> @@ -415,19 +415,18 @@ static void dpu_hw_sspp_setup_pe_config(struct
>> dpu_hw_sspp *ctx,
>> }
>> static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
>> - struct dpu_hw_pipe_cfg *sspp,
>> - void *scaler_cfg)
>> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
>> + const struct dpu_format *format)
>> {
>> u32 idx;
>> - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
>> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
>> + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
>> || !scaler3_cfg)
>
> Do we need to check for !format ?
We don't have since the calling sequence ensures that it is not NULL,
but let's check for it since it's a different module.
>
>> return;
>> dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
>> ctx->cap->sblk->scaler_blk.version,
>> - sspp->layout.format);
>> + format);
>> }
>> static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> index f5aae563741a..c713343378aa 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>> @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops {
>> /**
>> * setup_scaler - setup scaler
>> - * @ctx: Pointer to pipe context
>> - * @pipe_cfg: Pointer to pipe configuration
>> * @scaler_cfg: Pointer to scaler configuration
>
> This doc needs to be fixed from scaler_cfg to scaler3_cfg
>
>> + * @format: pixel format parameters
>> */
>> void (*setup_scaler)(struct dpu_hw_sspp *ctx,
>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>> - void *scaler_cfg);
>> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
>> + const struct dpu_format *format);
>> /**
>> * get_scaler_ver - get scaler h/w version
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> index 172a2c012917..cbff4dea8662 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> @@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct
>> dpu_sw_pipe *pipe,
>> if (pipe_hw->ops.setup_scaler &&
>> pipe->multirect_index != DPU_SSPP_RECT_1)
>> pipe_hw->ops.setup_scaler(pipe_hw,
>> - pipe_cfg,
>> - &scaler3_cfg);
>> + &scaler3_cfg,
>> + fmt);
>> }
>> /**
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 10/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
2023-01-31 12:10 ` Dmitry Baryshkov
@ 2023-01-31 12:15 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-31 12:15 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 31/01/2023 14:10, Dmitry Baryshkov wrote:
> On 31/01/2023 07:13, Abhinav Kumar wrote:
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> There is no need to pass full dpu_hw_pipe_cfg instance to
>>> _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++-----
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7 +++----
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
>>> 3 files changed, 9 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> index f7f81ab08fa2..176cd6dc9a69 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> @@ -415,19 +415,18 @@ static void dpu_hw_sspp_setup_pe_config(struct
>>> dpu_hw_sspp *ctx,
>>> }
>>> static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
>>> - struct dpu_hw_pipe_cfg *sspp,
>>> - void *scaler_cfg)
>>> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
>>> + const struct dpu_format *format)
>>> {
>>> u32 idx;
>>> - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
>>> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
>>> + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
>>> || !scaler3_cfg)
>>
>> Do we need to check for !format ?
>
> We don't have since the calling sequence ensures that it is not NULL,
> but let's check for it since it's a different module.
On the other hand, dpu_hw_setup_scaler3() properly handles the !format
case and programs the rest of the scaler setup. So in the end I'll skip
this check.
>
>>
>>> return;
>>> dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
>>> ctx->cap->sblk->scaler_blk.version,
>>> - sspp->layout.format);
>>> + format);
>>> }
>>> static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> index f5aae563741a..c713343378aa 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops {
>>> /**
>>> * setup_scaler - setup scaler
>>> - * @ctx: Pointer to pipe context
>>> - * @pipe_cfg: Pointer to pipe configuration
>>> * @scaler_cfg: Pointer to scaler configuration
>>
>> This doc needs to be fixed from scaler_cfg to scaler3_cfg
>>
>>> + * @format: pixel format parameters
>>> */
>>> void (*setup_scaler)(struct dpu_hw_sspp *ctx,
>>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>>> - void *scaler_cfg);
>>> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
>>> + const struct dpu_format *format);
>>> /**
>>> * get_scaler_ver - get scaler h/w version
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> index 172a2c012917..cbff4dea8662 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> @@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct
>>> dpu_sw_pipe *pipe,
>>> if (pipe_hw->ops.setup_scaler &&
>>> pipe->multirect_index != DPU_SSPP_RECT_1)
>>> pipe_hw->ops.setup_scaler(pipe_hw,
>>> - pipe_cfg,
>>> - &scaler3_cfg);
>>> + &scaler3_cfg,
>>> + fmt);
>>> }
>>> /**
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 10/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3()
@ 2023-01-31 12:15 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-01-31 12:15 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 31/01/2023 14:10, Dmitry Baryshkov wrote:
> On 31/01/2023 07:13, Abhinav Kumar wrote:
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> There is no need to pass full dpu_hw_pipe_cfg instance to
>>> _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++-----
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7 +++----
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
>>> 3 files changed, 9 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> index f7f81ab08fa2..176cd6dc9a69 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> @@ -415,19 +415,18 @@ static void dpu_hw_sspp_setup_pe_config(struct
>>> dpu_hw_sspp *ctx,
>>> }
>>> static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
>>> - struct dpu_hw_pipe_cfg *sspp,
>>> - void *scaler_cfg)
>>> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
>>> + const struct dpu_format *format)
>>> {
>>> u32 idx;
>>> - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
>>> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
>>> + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
>>> || !scaler3_cfg)
>>
>> Do we need to check for !format ?
>
> We don't have since the calling sequence ensures that it is not NULL,
> but let's check for it since it's a different module.
On the other hand, dpu_hw_setup_scaler3() properly handles the !format
case and programs the rest of the scaler setup. So in the end I'll skip
this check.
>
>>
>>> return;
>>> dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
>>> ctx->cap->sblk->scaler_blk.version,
>>> - sspp->layout.format);
>>> + format);
>>> }
>>> static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> index f5aae563741a..c713343378aa 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops {
>>> /**
>>> * setup_scaler - setup scaler
>>> - * @ctx: Pointer to pipe context
>>> - * @pipe_cfg: Pointer to pipe configuration
>>> * @scaler_cfg: Pointer to scaler configuration
>>
>> This doc needs to be fixed from scaler_cfg to scaler3_cfg
>>
>>> + * @format: pixel format parameters
>>> */
>>> void (*setup_scaler)(struct dpu_hw_sspp *ctx,
>>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>>> - void *scaler_cfg);
>>> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
>>> + const struct dpu_format *format);
>>> /**
>>> * get_scaler_ver - get scaler h/w version
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> index 172a2c012917..cbff4dea8662 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> @@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct
>>> dpu_sw_pipe *pipe,
>>> if (pipe_hw->ops.setup_scaler &&
>>> pipe->multirect_index != DPU_SSPP_RECT_1)
>>> pipe_hw->ops.setup_scaler(pipe_hw,
>>> - pipe_cfg,
>>> - &scaler3_cfg);
>>> + &scaler3_cfg,
>>> + fmt);
>>> }
>>> /**
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
dpu_hw_sspp_setup_rects() programs only source and destination
rectangles.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 176cd6dc9a69..2bd39c13d54d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
- u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
+ u32 src_size, src_xy, dst_size, dst_xy;
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
u32 idx;
@@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
drm_rect_width(&cfg->dst_rect);
- if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
- ystride0 = (cfg->layout.plane_pitch[0]) |
- (cfg->layout.plane_pitch[1] << 16);
- ystride1 = (cfg->layout.plane_pitch[2]) |
- (cfg->layout.plane_pitch[3] << 16);
- } else {
- ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
- ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
-
- if (pipe->multirect_index == DPU_SSPP_RECT_0) {
- ystride0 = (ystride0 & 0xFFFF0000) |
- (cfg->layout.plane_pitch[0] & 0x0000FFFF);
- ystride1 = (ystride1 & 0xFFFF0000)|
- (cfg->layout.plane_pitch[2] & 0x0000FFFF);
- } else {
- ystride0 = (ystride0 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[0] << 16) &
- 0xFFFF0000);
- ystride1 = (ystride1 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[2] << 16) &
- 0xFFFF0000);
- }
- }
-
/* rectangle register programming */
DPU_REG_WRITE(c, src_size_off + idx, src_size);
DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
DPU_REG_WRITE(c, out_size_off + idx, dst_size);
DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
-
- DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
- DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
struct dpu_hw_pipe_cfg *cfg)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 ystride0, ystride1;
int i;
u32 idx;
@@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
cfg->layout.plane_addr[2]);
}
+
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
+ ystride0 = (cfg->layout.plane_pitch[0]) |
+ (cfg->layout.plane_pitch[1] << 16);
+ ystride1 = (cfg->layout.plane_pitch[2]) |
+ (cfg->layout.plane_pitch[3] << 16);
+ } else {
+ ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
+ ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
+
+ if (pipe->multirect_index == DPU_SSPP_RECT_0) {
+ ystride0 = (ystride0 & 0xFFFF0000) |
+ (cfg->layout.plane_pitch[0] & 0x0000FFFF);
+ ystride1 = (ystride1 & 0xFFFF0000)|
+ (cfg->layout.plane_pitch[2] & 0x0000FFFF);
+ } else {
+ ystride0 = (ystride0 & 0x0000FFFF) |
+ ((cfg->layout.plane_pitch[0] << 16) &
+ 0xFFFF0000);
+ ystride1 = (ystride1 & 0x0000FFFF) |
+ ((cfg->layout.plane_pitch[2] << 16) &
+ 0xFFFF0000);
+ }
+ }
+
+ DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
+ DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
dpu_hw_sspp_setup_rects() programs only source and destination
rectangles.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 176cd6dc9a69..2bd39c13d54d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
- u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
+ u32 src_size, src_xy, dst_size, dst_xy;
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
u32 idx;
@@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
drm_rect_width(&cfg->dst_rect);
- if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
- ystride0 = (cfg->layout.plane_pitch[0]) |
- (cfg->layout.plane_pitch[1] << 16);
- ystride1 = (cfg->layout.plane_pitch[2]) |
- (cfg->layout.plane_pitch[3] << 16);
- } else {
- ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
- ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
-
- if (pipe->multirect_index == DPU_SSPP_RECT_0) {
- ystride0 = (ystride0 & 0xFFFF0000) |
- (cfg->layout.plane_pitch[0] & 0x0000FFFF);
- ystride1 = (ystride1 & 0xFFFF0000)|
- (cfg->layout.plane_pitch[2] & 0x0000FFFF);
- } else {
- ystride0 = (ystride0 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[0] << 16) &
- 0xFFFF0000);
- ystride1 = (ystride1 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[2] << 16) &
- 0xFFFF0000);
- }
- }
-
/* rectangle register programming */
DPU_REG_WRITE(c, src_size_off + idx, src_size);
DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
DPU_REG_WRITE(c, out_size_off + idx, dst_size);
DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
-
- DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
- DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
struct dpu_hw_pipe_cfg *cfg)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 ystride0, ystride1;
int i;
u32 idx;
@@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
cfg->layout.plane_addr[2]);
}
+
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
+ ystride0 = (cfg->layout.plane_pitch[0]) |
+ (cfg->layout.plane_pitch[1] << 16);
+ ystride1 = (cfg->layout.plane_pitch[2]) |
+ (cfg->layout.plane_pitch[3] << 16);
+ } else {
+ ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
+ ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
+
+ if (pipe->multirect_index == DPU_SSPP_RECT_0) {
+ ystride0 = (ystride0 & 0xFFFF0000) |
+ (cfg->layout.plane_pitch[0] & 0x0000FFFF);
+ ystride1 = (ystride1 & 0xFFFF0000)|
+ (cfg->layout.plane_pitch[2] & 0x0000FFFF);
+ } else {
+ ystride0 = (ystride0 & 0x0000FFFF) |
+ ((cfg->layout.plane_pitch[0] << 16) &
+ 0xFFFF0000);
+ ystride1 = (ystride1 & 0x0000FFFF) |
+ ((cfg->layout.plane_pitch[2] << 16) &
+ 0xFFFF0000);
+ }
+ }
+
+ DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
+ DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
}
static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2023-02-02 18:41 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 18:41 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
> dpu_hw_sspp_setup_rects() programs only source and destination
> rectangles.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sorry but once again, I dont see a response to my comment
https://patchwork.freedesktop.org/patch/473166/?series=99909&rev=1#comment_875313
So let me repeat that here:
"This separation is logically correct, but there is another codepath
using this.
_dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
So for solid fill, I presume that stride getting programmed is 0 as
there is no buffer to fetch from.
But with this separation, we will miss re-programming stride and it will
remain at the old value even for solid fil cases?
You might want to add setup_sourceaddress call there? But that wont make
sense either because for solid fill there is nothing to fetch from.
Perhaps, another op for stride programming then?
"
Also, this is the second patch in the series where the previous comments
were not resolved/responded to.
Hope that this was not just another rebase without looking at the prior
comments.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
> 1 file changed, 29 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 176cd6dc9a69..2bd39c13d54d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> struct dpu_hw_blk_reg_map *c;
> - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
> + u32 src_size, src_xy, dst_size, dst_xy;
> u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
> u32 idx;
>
> @@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
> drm_rect_width(&cfg->dst_rect);
>
> - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> - ystride0 = (cfg->layout.plane_pitch[0]) |
> - (cfg->layout.plane_pitch[1] << 16);
> - ystride1 = (cfg->layout.plane_pitch[2]) |
> - (cfg->layout.plane_pitch[3] << 16);
> - } else {
> - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
> - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
> -
> - if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> - ystride0 = (ystride0 & 0xFFFF0000) |
> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> - ystride1 = (ystride1 & 0xFFFF0000)|
> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> - } else {
> - ystride0 = (ystride0 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[0] << 16) &
> - 0xFFFF0000);
> - ystride1 = (ystride1 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[2] << 16) &
> - 0xFFFF0000);
> - }
> - }
> -
> /* rectangle register programming */
> DPU_REG_WRITE(c, src_size_off + idx, src_size);
> DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
> DPU_REG_WRITE(c, out_size_off + idx, dst_size);
> DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
> -
> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> }
>
> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> struct dpu_hw_pipe_cfg *cfg)
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> + u32 ystride0, ystride1;
> int i;
> u32 idx;
>
> @@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> cfg->layout.plane_addr[2]);
> }
> +
> + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> + ystride0 = (cfg->layout.plane_pitch[0]) |
> + (cfg->layout.plane_pitch[1] << 16);
> + ystride1 = (cfg->layout.plane_pitch[2]) |
> + (cfg->layout.plane_pitch[3] << 16);
> + } else {
> + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
> +
> + if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> + ystride0 = (ystride0 & 0xFFFF0000) |
> + (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> + ystride1 = (ystride1 & 0xFFFF0000)|
> + (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> + } else {
> + ystride0 = (ystride0 & 0x0000FFFF) |
> + ((cfg->layout.plane_pitch[0] << 16) &
> + 0xFFFF0000);
> + ystride1 = (ystride1 & 0x0000FFFF) |
> + ((cfg->layout.plane_pitch[2] << 16) &
> + 0xFFFF0000);
> + }
> + }
> +
> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> }
>
> static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
@ 2023-02-02 18:41 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 18:41 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
> dpu_hw_sspp_setup_rects() programs only source and destination
> rectangles.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sorry but once again, I dont see a response to my comment
https://patchwork.freedesktop.org/patch/473166/?series=99909&rev=1#comment_875313
So let me repeat that here:
"This separation is logically correct, but there is another codepath
using this.
_dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
So for solid fill, I presume that stride getting programmed is 0 as
there is no buffer to fetch from.
But with this separation, we will miss re-programming stride and it will
remain at the old value even for solid fil cases?
You might want to add setup_sourceaddress call there? But that wont make
sense either because for solid fill there is nothing to fetch from.
Perhaps, another op for stride programming then?
"
Also, this is the second patch in the series where the previous comments
were not resolved/responded to.
Hope that this was not just another rebase without looking at the prior
comments.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
> 1 file changed, 29 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 176cd6dc9a69..2bd39c13d54d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> struct dpu_hw_blk_reg_map *c;
> - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
> + u32 src_size, src_xy, dst_size, dst_xy;
> u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
> u32 idx;
>
> @@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
> drm_rect_width(&cfg->dst_rect);
>
> - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> - ystride0 = (cfg->layout.plane_pitch[0]) |
> - (cfg->layout.plane_pitch[1] << 16);
> - ystride1 = (cfg->layout.plane_pitch[2]) |
> - (cfg->layout.plane_pitch[3] << 16);
> - } else {
> - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
> - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
> -
> - if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> - ystride0 = (ystride0 & 0xFFFF0000) |
> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> - ystride1 = (ystride1 & 0xFFFF0000)|
> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> - } else {
> - ystride0 = (ystride0 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[0] << 16) &
> - 0xFFFF0000);
> - ystride1 = (ystride1 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[2] << 16) &
> - 0xFFFF0000);
> - }
> - }
> -
> /* rectangle register programming */
> DPU_REG_WRITE(c, src_size_off + idx, src_size);
> DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
> DPU_REG_WRITE(c, out_size_off + idx, dst_size);
> DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
> -
> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> }
>
> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> struct dpu_hw_pipe_cfg *cfg)
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> + u32 ystride0, ystride1;
> int i;
> u32 idx;
>
> @@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> cfg->layout.plane_addr[2]);
> }
> +
> + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> + ystride0 = (cfg->layout.plane_pitch[0]) |
> + (cfg->layout.plane_pitch[1] << 16);
> + ystride1 = (cfg->layout.plane_pitch[2]) |
> + (cfg->layout.plane_pitch[3] << 16);
> + } else {
> + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
> +
> + if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> + ystride0 = (ystride0 & 0xFFFF0000) |
> + (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> + ystride1 = (ystride1 & 0xFFFF0000)|
> + (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> + } else {
> + ystride0 = (ystride0 & 0x0000FFFF) |
> + ((cfg->layout.plane_pitch[0] << 16) &
> + 0xFFFF0000);
> + ystride1 = (ystride1 & 0x0000FFFF) |
> + ((cfg->layout.plane_pitch[2] << 16) &
> + 0xFFFF0000);
> + }
> + }
> +
> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> }
>
> static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
2023-02-02 18:41 ` Abhinav Kumar
@ 2023-02-02 18:55 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-02 18:55 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
Hi Abhinav,
On Thu, 2 Feb 2023 at 20:41, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> > Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
> > dpu_hw_sspp_setup_rects() programs only source and destination
> > rectangles.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Sorry but once again, I dont see a response to my comment
>
> https://patchwork.freedesktop.org/patch/473166/?series=99909&rev=1#comment_875313
>
> So let me repeat that here:
>
> "This separation is logically correct, but there is another codepath
> using this.
>
> _dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
>
> So for solid fill, I presume that stride getting programmed is 0 as
> there is no buffer to fetch from.
Could you please verify with the HW team what should be the correct
stride programming for the solid fill? I'll have to check what is
being programmed ATM.
>
> But with this separation, we will miss re-programming stride and it will
> remain at the old value even for solid fil cases?
>
> You might want to add setup_sourceaddress call there? But that wont make
> sense either because for solid fill there is nothing to fetch from.
>
> Perhaps, another op for stride programming then?
> "
>
> Also, this is the second patch in the series where the previous comments
> were not resolved/responded to.
>
> Hope that this was not just another rebase without looking at the prior
> comments.
I might have missed some of the comments during the rebase, please
excuse me. There was no intent to ignore them.
>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
> > 1 file changed, 29 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > index 176cd6dc9a69..2bd39c13d54d 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > @@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> > {
> > struct dpu_hw_sspp *ctx = pipe->sspp;
> > struct dpu_hw_blk_reg_map *c;
> > - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
> > + u32 src_size, src_xy, dst_size, dst_xy;
> > u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
> > u32 idx;
> >
> > @@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> > dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
> > drm_rect_width(&cfg->dst_rect);
> >
> > - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> > - ystride0 = (cfg->layout.plane_pitch[0]) |
> > - (cfg->layout.plane_pitch[1] << 16);
> > - ystride1 = (cfg->layout.plane_pitch[2]) |
> > - (cfg->layout.plane_pitch[3] << 16);
> > - } else {
> > - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
> > - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
> > -
> > - if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> > - ystride0 = (ystride0 & 0xFFFF0000) |
> > - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> > - ystride1 = (ystride1 & 0xFFFF0000)|
> > - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> > - } else {
> > - ystride0 = (ystride0 & 0x0000FFFF) |
> > - ((cfg->layout.plane_pitch[0] << 16) &
> > - 0xFFFF0000);
> > - ystride1 = (ystride1 & 0x0000FFFF) |
> > - ((cfg->layout.plane_pitch[2] << 16) &
> > - 0xFFFF0000);
> > - }
> > - }
> > -
> > /* rectangle register programming */
> > DPU_REG_WRITE(c, src_size_off + idx, src_size);
> > DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
> > DPU_REG_WRITE(c, out_size_off + idx, dst_size);
> > DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
> > -
> > - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> > - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> > }
> >
> > static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> > struct dpu_hw_pipe_cfg *cfg)
> > {
> > struct dpu_hw_sspp *ctx = pipe->sspp;
> > + u32 ystride0, ystride1;
> > int i;
> > u32 idx;
> >
> > @@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> > cfg->layout.plane_addr[2]);
> > }
> > +
> > + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> > + ystride0 = (cfg->layout.plane_pitch[0]) |
> > + (cfg->layout.plane_pitch[1] << 16);
> > + ystride1 = (cfg->layout.plane_pitch[2]) |
> > + (cfg->layout.plane_pitch[3] << 16);
> > + } else {
> > + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> > + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
> > +
> > + if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> > + ystride0 = (ystride0 & 0xFFFF0000) |
> > + (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> > + ystride1 = (ystride1 & 0xFFFF0000)|
> > + (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> > + } else {
> > + ystride0 = (ystride0 & 0x0000FFFF) |
> > + ((cfg->layout.plane_pitch[0] << 16) &
> > + 0xFFFF0000);
> > + ystride1 = (ystride1 & 0x0000FFFF) |
> > + ((cfg->layout.plane_pitch[2] << 16) &
> > + 0xFFFF0000);
> > + }
> > + }
> > +
> > + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> > + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> > }
> >
> > static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
@ 2023-02-02 18:55 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-02 18:55 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
Hi Abhinav,
On Thu, 2 Feb 2023 at 20:41, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> > Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
> > dpu_hw_sspp_setup_rects() programs only source and destination
> > rectangles.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Sorry but once again, I dont see a response to my comment
>
> https://patchwork.freedesktop.org/patch/473166/?series=99909&rev=1#comment_875313
>
> So let me repeat that here:
>
> "This separation is logically correct, but there is another codepath
> using this.
>
> _dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
>
> So for solid fill, I presume that stride getting programmed is 0 as
> there is no buffer to fetch from.
Could you please verify with the HW team what should be the correct
stride programming for the solid fill? I'll have to check what is
being programmed ATM.
>
> But with this separation, we will miss re-programming stride and it will
> remain at the old value even for solid fil cases?
>
> You might want to add setup_sourceaddress call there? But that wont make
> sense either because for solid fill there is nothing to fetch from.
>
> Perhaps, another op for stride programming then?
> "
>
> Also, this is the second patch in the series where the previous comments
> were not resolved/responded to.
>
> Hope that this was not just another rebase without looking at the prior
> comments.
I might have missed some of the comments during the rebase, please
excuse me. There was no intent to ignore them.
>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
> > 1 file changed, 29 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > index 176cd6dc9a69..2bd39c13d54d 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > @@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> > {
> > struct dpu_hw_sspp *ctx = pipe->sspp;
> > struct dpu_hw_blk_reg_map *c;
> > - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
> > + u32 src_size, src_xy, dst_size, dst_xy;
> > u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
> > u32 idx;
> >
> > @@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> > dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
> > drm_rect_width(&cfg->dst_rect);
> >
> > - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> > - ystride0 = (cfg->layout.plane_pitch[0]) |
> > - (cfg->layout.plane_pitch[1] << 16);
> > - ystride1 = (cfg->layout.plane_pitch[2]) |
> > - (cfg->layout.plane_pitch[3] << 16);
> > - } else {
> > - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
> > - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
> > -
> > - if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> > - ystride0 = (ystride0 & 0xFFFF0000) |
> > - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> > - ystride1 = (ystride1 & 0xFFFF0000)|
> > - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> > - } else {
> > - ystride0 = (ystride0 & 0x0000FFFF) |
> > - ((cfg->layout.plane_pitch[0] << 16) &
> > - 0xFFFF0000);
> > - ystride1 = (ystride1 & 0x0000FFFF) |
> > - ((cfg->layout.plane_pitch[2] << 16) &
> > - 0xFFFF0000);
> > - }
> > - }
> > -
> > /* rectangle register programming */
> > DPU_REG_WRITE(c, src_size_off + idx, src_size);
> > DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
> > DPU_REG_WRITE(c, out_size_off + idx, dst_size);
> > DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
> > -
> > - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> > - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> > }
> >
> > static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> > struct dpu_hw_pipe_cfg *cfg)
> > {
> > struct dpu_hw_sspp *ctx = pipe->sspp;
> > + u32 ystride0, ystride1;
> > int i;
> > u32 idx;
> >
> > @@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> > cfg->layout.plane_addr[2]);
> > }
> > +
> > + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> > + ystride0 = (cfg->layout.plane_pitch[0]) |
> > + (cfg->layout.plane_pitch[1] << 16);
> > + ystride1 = (cfg->layout.plane_pitch[2]) |
> > + (cfg->layout.plane_pitch[3] << 16);
> > + } else {
> > + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> > + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
> > +
> > + if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> > + ystride0 = (ystride0 & 0xFFFF0000) |
> > + (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> > + ystride1 = (ystride1 & 0xFFFF0000)|
> > + (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> > + } else {
> > + ystride0 = (ystride0 & 0x0000FFFF) |
> > + ((cfg->layout.plane_pitch[0] << 16) &
> > + 0xFFFF0000);
> > + ystride1 = (ystride1 & 0x0000FFFF) |
> > + ((cfg->layout.plane_pitch[2] << 16) &
> > + 0xFFFF0000);
> > + }
> > + }
> > +
> > + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
> > + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
> > }
> >
> > static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
2023-02-02 18:55 ` Dmitry Baryshkov
@ 2023-02-02 19:15 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 19:15 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 2/2/2023 10:55 AM, Dmitry Baryshkov wrote:
> Hi Abhinav,
>
> On Thu, 2 Feb 2023 at 20:41, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
>>> dpu_hw_sspp_setup_rects() programs only source and destination
>>> rectangles.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>
>> Sorry but once again, I dont see a response to my comment
>>
>> https://patchwork.freedesktop.org/patch/473166/?series=99909&rev=1#comment_875313
>>
>> So let me repeat that here:
>>
>> "This separation is logically correct, but there is another codepath
>> using this.
>>
>> _dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
>>
>> So for solid fill, I presume that stride getting programmed is 0 as
>> there is no buffer to fetch from.
>
> Could you please verify with the HW team what should be the correct
> stride programming for the solid fill? I'll have to check what is
> being programmed ATM.
>
Sure, I can check but in the _dpu_plane_color_fill() method the
pipe_cfg->layout is not filled up so it should be a 0 stride.
>>
>> But with this separation, we will miss re-programming stride and it will
>> remain at the old value even for solid fil cases?
>>
>> You might want to add setup_sourceaddress call there? But that wont make
>> sense either because for solid fill there is nothing to fetch from.
>>
>> Perhaps, another op for stride programming then?
>> "
>>
>> Also, this is the second patch in the series where the previous comments
>> were not resolved/responded to.
>>
>> Hope that this was not just another rebase without looking at the prior
>> comments.
>
> I might have missed some of the comments during the rebase, please
> excuse me. There was no intent to ignore them.
>
Ack.
>
>>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
>>> 1 file changed, 29 insertions(+), 28 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> index 176cd6dc9a69..2bd39c13d54d 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> @@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
>>> {
>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>> struct dpu_hw_blk_reg_map *c;
>>> - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
>>> + u32 src_size, src_xy, dst_size, dst_xy;
>>> u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
>>> u32 idx;
>>>
>>> @@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
>>> dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
>>> drm_rect_width(&cfg->dst_rect);
>>>
>>> - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>> - ystride0 = (cfg->layout.plane_pitch[0]) |
>>> - (cfg->layout.plane_pitch[1] << 16);
>>> - ystride1 = (cfg->layout.plane_pitch[2]) |
>>> - (cfg->layout.plane_pitch[3] << 16);
>>> - } else {
>>> - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
>>> - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
>>> -
>>> - if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>> - ystride0 = (ystride0 & 0xFFFF0000) |
>>> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
>>> - ystride1 = (ystride1 & 0xFFFF0000)|
>>> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
>>> - } else {
>>> - ystride0 = (ystride0 & 0x0000FFFF) |
>>> - ((cfg->layout.plane_pitch[0] << 16) &
>>> - 0xFFFF0000);
>>> - ystride1 = (ystride1 & 0x0000FFFF) |
>>> - ((cfg->layout.plane_pitch[2] << 16) &
>>> - 0xFFFF0000);
>>> - }
>>> - }
>>> -
>>> /* rectangle register programming */
>>> DPU_REG_WRITE(c, src_size_off + idx, src_size);
>>> DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
>>> DPU_REG_WRITE(c, out_size_off + idx, dst_size);
>>> DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
>>> -
>>> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
>>> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
>>> }
>>>
>>> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>> struct dpu_hw_pipe_cfg *cfg)
>>> {
>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>> + u32 ystride0, ystride1;
>>> int i;
>>> u32 idx;
>>>
>>> @@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
>>> cfg->layout.plane_addr[2]);
>>> }
>>> +
>>> + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>> + ystride0 = (cfg->layout.plane_pitch[0]) |
>>> + (cfg->layout.plane_pitch[1] << 16);
>>> + ystride1 = (cfg->layout.plane_pitch[2]) |
>>> + (cfg->layout.plane_pitch[3] << 16);
>>> + } else {
>>> + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
>>> + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
>>> +
>>> + if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>> + ystride0 = (ystride0 & 0xFFFF0000) |
>>> + (cfg->layout.plane_pitch[0] & 0x0000FFFF);
>>> + ystride1 = (ystride1 & 0xFFFF0000)|
>>> + (cfg->layout.plane_pitch[2] & 0x0000FFFF);
>>> + } else {
>>> + ystride0 = (ystride0 & 0x0000FFFF) |
>>> + ((cfg->layout.plane_pitch[0] << 16) &
>>> + 0xFFFF0000);
>>> + ystride1 = (ystride1 & 0x0000FFFF) |
>>> + ((cfg->layout.plane_pitch[2] << 16) &
>>> + 0xFFFF0000);
>>> + }
>>> + }
>>> +
>>> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
>>> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
>>> }
>>>
>>> static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
@ 2023-02-02 19:15 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 19:15 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 2/2/2023 10:55 AM, Dmitry Baryshkov wrote:
> Hi Abhinav,
>
> On Thu, 2 Feb 2023 at 20:41, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
>>> dpu_hw_sspp_setup_rects() programs only source and destination
>>> rectangles.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>
>> Sorry but once again, I dont see a response to my comment
>>
>> https://patchwork.freedesktop.org/patch/473166/?series=99909&rev=1#comment_875313
>>
>> So let me repeat that here:
>>
>> "This separation is logically correct, but there is another codepath
>> using this.
>>
>> _dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
>>
>> So for solid fill, I presume that stride getting programmed is 0 as
>> there is no buffer to fetch from.
>
> Could you please verify with the HW team what should be the correct
> stride programming for the solid fill? I'll have to check what is
> being programmed ATM.
>
Sure, I can check but in the _dpu_plane_color_fill() method the
pipe_cfg->layout is not filled up so it should be a 0 stride.
>>
>> But with this separation, we will miss re-programming stride and it will
>> remain at the old value even for solid fil cases?
>>
>> You might want to add setup_sourceaddress call there? But that wont make
>> sense either because for solid fill there is nothing to fetch from.
>>
>> Perhaps, another op for stride programming then?
>> "
>>
>> Also, this is the second patch in the series where the previous comments
>> were not resolved/responded to.
>>
>> Hope that this was not just another rebase without looking at the prior
>> comments.
>
> I might have missed some of the comments during the rebase, please
> excuse me. There was no intent to ignore them.
>
Ack.
>
>>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++----------
>>> 1 file changed, 29 insertions(+), 28 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> index 176cd6dc9a69..2bd39c13d54d 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> @@ -447,7 +447,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
>>> {
>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>> struct dpu_hw_blk_reg_map *c;
>>> - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
>>> + u32 src_size, src_xy, dst_size, dst_xy;
>>> u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
>>> u32 idx;
>>>
>>> @@ -478,44 +478,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
>>> dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
>>> drm_rect_width(&cfg->dst_rect);
>>>
>>> - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>> - ystride0 = (cfg->layout.plane_pitch[0]) |
>>> - (cfg->layout.plane_pitch[1] << 16);
>>> - ystride1 = (cfg->layout.plane_pitch[2]) |
>>> - (cfg->layout.plane_pitch[3] << 16);
>>> - } else {
>>> - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
>>> - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
>>> -
>>> - if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>> - ystride0 = (ystride0 & 0xFFFF0000) |
>>> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
>>> - ystride1 = (ystride1 & 0xFFFF0000)|
>>> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
>>> - } else {
>>> - ystride0 = (ystride0 & 0x0000FFFF) |
>>> - ((cfg->layout.plane_pitch[0] << 16) &
>>> - 0xFFFF0000);
>>> - ystride1 = (ystride1 & 0x0000FFFF) |
>>> - ((cfg->layout.plane_pitch[2] << 16) &
>>> - 0xFFFF0000);
>>> - }
>>> - }
>>> -
>>> /* rectangle register programming */
>>> DPU_REG_WRITE(c, src_size_off + idx, src_size);
>>> DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
>>> DPU_REG_WRITE(c, out_size_off + idx, dst_size);
>>> DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
>>> -
>>> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
>>> - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
>>> }
>>>
>>> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>> struct dpu_hw_pipe_cfg *cfg)
>>> {
>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>> + u32 ystride0, ystride1;
>>> int i;
>>> u32 idx;
>>>
>>> @@ -537,6 +511,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
>>> cfg->layout.plane_addr[2]);
>>> }
>>> +
>>> + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>> + ystride0 = (cfg->layout.plane_pitch[0]) |
>>> + (cfg->layout.plane_pitch[1] << 16);
>>> + ystride1 = (cfg->layout.plane_pitch[2]) |
>>> + (cfg->layout.plane_pitch[3] << 16);
>>> + } else {
>>> + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
>>> + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
>>> +
>>> + if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>> + ystride0 = (ystride0 & 0xFFFF0000) |
>>> + (cfg->layout.plane_pitch[0] & 0x0000FFFF);
>>> + ystride1 = (ystride1 & 0xFFFF0000)|
>>> + (cfg->layout.plane_pitch[2] & 0x0000FFFF);
>>> + } else {
>>> + ystride0 = (ystride0 & 0x0000FFFF) |
>>> + ((cfg->layout.plane_pitch[0] << 16) &
>>> + 0xFFFF0000);
>>> + ystride1 = (ystride1 & 0x0000FFFF) |
>>> + ((cfg->layout.plane_pitch[2] << 16) &
>>> + 0xFFFF0000);
>>> + }
>>> + }
>>> +
>>> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0);
>>> + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1);
>>> }
>>>
>>> static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
2023-02-02 19:15 ` Abhinav Kumar
@ 2023-02-03 14:12 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-03 14:12 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 02/02/2023 21:15, Abhinav Kumar wrote:
>
>
> On 2/2/2023 10:55 AM, Dmitry Baryshkov wrote:
>> Hi Abhinav,
>>
>> On Thu, 2 Feb 2023 at 20:41, Abhinav Kumar <quic_abhinavk@quicinc.com>
>> wrote:
>>>
>>>
>>>
>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>> Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
>>>> dpu_hw_sspp_setup_rects() programs only source and destination
>>>> rectangles.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>
>>> Sorry but once again, I dont see a response to my comment
>>>
>>> https://patchwork.freedesktop.org/patch/473166/?series=99909&rev=1#comment_875313
>>>
>>> So let me repeat that here:
>>>
>>> "This separation is logically correct, but there is another codepath
>>> using this.
>>>
>>> _dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
>>>
>>> So for solid fill, I presume that stride getting programmed is 0 as
>>> there is no buffer to fetch from.
>>
>> Could you please verify with the HW team what should be the correct
>> stride programming for the solid fill? I'll have to check what is
>> being programmed ATM.
>>
>
> Sure, I can check but in the _dpu_plane_color_fill() method the
> pipe_cfg->layout is not filled up so it should be a 0 stride.
Actually I think we should call setup_sourceaddress for the color-filled
planes too. Otherwise the SSPP's adddress registers can point to the
memory regions which are no longer mapped/available.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 11/27] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress
@ 2023-02-03 14:12 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-03 14:12 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 02/02/2023 21:15, Abhinav Kumar wrote:
>
>
> On 2/2/2023 10:55 AM, Dmitry Baryshkov wrote:
>> Hi Abhinav,
>>
>> On Thu, 2 Feb 2023 at 20:41, Abhinav Kumar <quic_abhinavk@quicinc.com>
>> wrote:
>>>
>>>
>>>
>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>> Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that
>>>> dpu_hw_sspp_setup_rects() programs only source and destination
>>>> rectangles.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>
>>> Sorry but once again, I dont see a response to my comment
>>>
>>> https://patchwork.freedesktop.org/patch/473166/?series=99909&rev=1#comment_875313
>>>
>>> So let me repeat that here:
>>>
>>> "This separation is logically correct, but there is another codepath
>>> using this.
>>>
>>> _dpu_plane_color_fill() calls pdpu->pipe_hw->ops.setup_rects.
>>>
>>> So for solid fill, I presume that stride getting programmed is 0 as
>>> there is no buffer to fetch from.
>>
>> Could you please verify with the HW team what should be the correct
>> stride programming for the solid fill? I'll have to check what is
>> being programmed ATM.
>>
>
> Sure, I can check but in the _dpu_plane_color_fill() method the
> pipe_cfg->layout is not filled up so it should be a 0 stride.
Actually I think we should call setup_sourceaddress for the color-filled
planes too. Otherwise the SSPP's adddress registers can point to the
memory regions which are no longer mapped/available.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
only src_rect and dst_rect. This way right and left pipes will have
separate dpu_hw_pipe_cfg isntances, while the layout is common to both
of them.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
3 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 2bd39c13d54d..400d043f37fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
}
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
- struct dpu_hw_pipe_cfg *cfg)
+ struct dpu_hw_fmt_layout *layout)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
u32 ystride0, ystride1;
@@ -497,41 +497,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
return;
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
- for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
+ for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
- cfg->layout.plane_addr[i]);
+ layout->plane_addr[i]);
} else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
- cfg->layout.plane_addr[0]);
+ layout->plane_addr[0]);
DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
- cfg->layout.plane_addr[2]);
+ layout->plane_addr[2]);
} else {
DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
- cfg->layout.plane_addr[0]);
+ layout->plane_addr[0]);
DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
- cfg->layout.plane_addr[2]);
+ layout->plane_addr[2]);
}
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
- ystride0 = (cfg->layout.plane_pitch[0]) |
- (cfg->layout.plane_pitch[1] << 16);
- ystride1 = (cfg->layout.plane_pitch[2]) |
- (cfg->layout.plane_pitch[3] << 16);
+ ystride0 = (layout->plane_pitch[0]) |
+ (layout->plane_pitch[1] << 16);
+ ystride1 = (layout->plane_pitch[2]) |
+ (layout->plane_pitch[3] << 16);
} else {
ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
if (pipe->multirect_index == DPU_SSPP_RECT_0) {
ystride0 = (ystride0 & 0xFFFF0000) |
- (cfg->layout.plane_pitch[0] & 0x0000FFFF);
+ (layout->plane_pitch[0] & 0x0000FFFF);
ystride1 = (ystride1 & 0xFFFF0000)|
- (cfg->layout.plane_pitch[2] & 0x0000FFFF);
+ (layout->plane_pitch[2] & 0x0000FFFF);
} else {
ystride0 = (ystride0 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[0] << 16) &
+ ((layout->plane_pitch[0] << 16) &
0xFFFF0000);
ystride1 = (ystride1 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[2] << 16) &
+ ((layout->plane_pitch[2] << 16) &
0xFFFF0000);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index c713343378aa..8dad52eb2a90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
/**
* struct dpu_hw_pipe_cfg : Pipe description
- * @layout: format layout information for programming buffer to hardware
* @src_rect: src ROI, caller takes into account the different operations
* such as decimation, flip etc to program this field
* @dest_rect: destination ROI.
*/
struct dpu_hw_pipe_cfg {
- struct dpu_hw_fmt_layout layout;
struct drm_rect src_rect;
struct drm_rect dst_rect;
};
@@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
/**
* setup_sourceaddress - setup pipe source addresses
* @pipe: Pointer to software pipe context
- * @cfg: Pointer to pipe config structure
+ * @layout: format layout information for programming buffer to hardware
*/
void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
- struct dpu_hw_pipe_cfg *cfg);
+ struct dpu_hw_fmt_layout *layout);
/**
* setup_csc - setup color space coversion
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index cbff4dea8662..0d2a7170e0ab 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
static void _dpu_plane_set_scanout(struct drm_plane *plane,
struct dpu_plane_state *pstate,
- struct dpu_hw_pipe_cfg *pipe_cfg,
struct drm_framebuffer *fb)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
struct msm_gem_address_space *aspace = kms->base.aspace;
+ struct dpu_hw_fmt_layout layout;
int ret;
- ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
+ ret = dpu_format_populate_layout(aspace, fb, &layout);
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
trace_dpu_plane_set_scanout(&pstate->pipe,
- &pipe_cfg->layout);
- pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
+ &layout);
+ pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
}
}
@@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
- _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
+ _dpu_plane_set_scanout(plane, pstate, fb);
pstate->pending = true;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
only src_rect and dst_rect. This way right and left pipes will have
separate dpu_hw_pipe_cfg isntances, while the layout is common to both
of them.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
3 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 2bd39c13d54d..400d043f37fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
}
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
- struct dpu_hw_pipe_cfg *cfg)
+ struct dpu_hw_fmt_layout *layout)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
u32 ystride0, ystride1;
@@ -497,41 +497,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
return;
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
- for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
+ for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
- cfg->layout.plane_addr[i]);
+ layout->plane_addr[i]);
} else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
- cfg->layout.plane_addr[0]);
+ layout->plane_addr[0]);
DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
- cfg->layout.plane_addr[2]);
+ layout->plane_addr[2]);
} else {
DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
- cfg->layout.plane_addr[0]);
+ layout->plane_addr[0]);
DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
- cfg->layout.plane_addr[2]);
+ layout->plane_addr[2]);
}
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
- ystride0 = (cfg->layout.plane_pitch[0]) |
- (cfg->layout.plane_pitch[1] << 16);
- ystride1 = (cfg->layout.plane_pitch[2]) |
- (cfg->layout.plane_pitch[3] << 16);
+ ystride0 = (layout->plane_pitch[0]) |
+ (layout->plane_pitch[1] << 16);
+ ystride1 = (layout->plane_pitch[2]) |
+ (layout->plane_pitch[3] << 16);
} else {
ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
if (pipe->multirect_index == DPU_SSPP_RECT_0) {
ystride0 = (ystride0 & 0xFFFF0000) |
- (cfg->layout.plane_pitch[0] & 0x0000FFFF);
+ (layout->plane_pitch[0] & 0x0000FFFF);
ystride1 = (ystride1 & 0xFFFF0000)|
- (cfg->layout.plane_pitch[2] & 0x0000FFFF);
+ (layout->plane_pitch[2] & 0x0000FFFF);
} else {
ystride0 = (ystride0 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[0] << 16) &
+ ((layout->plane_pitch[0] << 16) &
0xFFFF0000);
ystride1 = (ystride1 & 0x0000FFFF) |
- ((cfg->layout.plane_pitch[2] << 16) &
+ ((layout->plane_pitch[2] << 16) &
0xFFFF0000);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index c713343378aa..8dad52eb2a90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
/**
* struct dpu_hw_pipe_cfg : Pipe description
- * @layout: format layout information for programming buffer to hardware
* @src_rect: src ROI, caller takes into account the different operations
* such as decimation, flip etc to program this field
* @dest_rect: destination ROI.
*/
struct dpu_hw_pipe_cfg {
- struct dpu_hw_fmt_layout layout;
struct drm_rect src_rect;
struct drm_rect dst_rect;
};
@@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
/**
* setup_sourceaddress - setup pipe source addresses
* @pipe: Pointer to software pipe context
- * @cfg: Pointer to pipe config structure
+ * @layout: format layout information for programming buffer to hardware
*/
void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
- struct dpu_hw_pipe_cfg *cfg);
+ struct dpu_hw_fmt_layout *layout);
/**
* setup_csc - setup color space coversion
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index cbff4dea8662..0d2a7170e0ab 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
static void _dpu_plane_set_scanout(struct drm_plane *plane,
struct dpu_plane_state *pstate,
- struct dpu_hw_pipe_cfg *pipe_cfg,
struct drm_framebuffer *fb)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
struct msm_gem_address_space *aspace = kms->base.aspace;
+ struct dpu_hw_fmt_layout layout;
int ret;
- ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
+ ret = dpu_format_populate_layout(aspace, fb, &layout);
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
trace_dpu_plane_set_scanout(&pstate->pipe,
- &pipe_cfg->layout);
- pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
+ &layout);
+ pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
}
}
@@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
- _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
+ _dpu_plane_set_scanout(plane, pstate, fb);
pstate->pending = true;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2023-02-02 19:38 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 19:38 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
> only src_rect and dst_rect. This way right and left pipes will have
> separate dpu_hw_pipe_cfg isntances, while the layout is common to both
> of them.
>
Sorry for not responding to this comment earlier.
https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
From the perspective of wide planes you are right that the layout is
common but not true from smart DMA point of view.
For wide planes, yes, its usually the same buffer with just the src_x
being different but conceptually and even HW wise each rectangle of the
smart DMA is capable of fetching from a different buffer.
From the pov, this decision of not having the dpu_hw_fmt_layout as part
of dpu_hw_pipe_cfg seems incorrect to me.
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
> 3 files changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 2bd39c13d54d..400d043f37fa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> }
>
> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> - struct dpu_hw_pipe_cfg *cfg)
> + struct dpu_hw_fmt_layout *layout)
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> u32 ystride0, ystride1;
> @@ -497,41 +497,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> return;
>
> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
> + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
> - cfg->layout.plane_addr[i]);
> + layout->plane_addr[i]);
> } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
> - cfg->layout.plane_addr[0]);
> + layout->plane_addr[0]);
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
> - cfg->layout.plane_addr[2]);
> + layout->plane_addr[2]);
> } else {
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
> - cfg->layout.plane_addr[0]);
> + layout->plane_addr[0]);
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> - cfg->layout.plane_addr[2]);
> + layout->plane_addr[2]);
> }
>
> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> - ystride0 = (cfg->layout.plane_pitch[0]) |
> - (cfg->layout.plane_pitch[1] << 16);
> - ystride1 = (cfg->layout.plane_pitch[2]) |
> - (cfg->layout.plane_pitch[3] << 16);
> + ystride0 = (layout->plane_pitch[0]) |
> + (layout->plane_pitch[1] << 16);
> + ystride1 = (layout->plane_pitch[2]) |
> + (layout->plane_pitch[3] << 16);
> } else {
> ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
>
> if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> ystride0 = (ystride0 & 0xFFFF0000) |
> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> + (layout->plane_pitch[0] & 0x0000FFFF);
> ystride1 = (ystride1 & 0xFFFF0000)|
> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> + (layout->plane_pitch[2] & 0x0000FFFF);
> } else {
> ystride0 = (ystride0 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[0] << 16) &
> + ((layout->plane_pitch[0] << 16) &
> 0xFFFF0000);
> ystride1 = (ystride1 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[2] << 16) &
> + ((layout->plane_pitch[2] << 16) &
> 0xFFFF0000);
> }
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index c713343378aa..8dad52eb2a90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
>
> /**
> * struct dpu_hw_pipe_cfg : Pipe description
> - * @layout: format layout information for programming buffer to hardware
> * @src_rect: src ROI, caller takes into account the different operations
> * such as decimation, flip etc to program this field
> * @dest_rect: destination ROI.
> */
> struct dpu_hw_pipe_cfg {
> - struct dpu_hw_fmt_layout layout;
> struct drm_rect src_rect;
> struct drm_rect dst_rect;
> };
> @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
> /**
> * setup_sourceaddress - setup pipe source addresses
> * @pipe: Pointer to software pipe context
> - * @cfg: Pointer to pipe config structure
> + * @layout: format layout information for programming buffer to hardware
> */
> void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
> - struct dpu_hw_pipe_cfg *cfg);
> + struct dpu_hw_fmt_layout *layout);
>
> /**
> * setup_csc - setup color space coversion
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index cbff4dea8662..0d2a7170e0ab 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
>
> static void _dpu_plane_set_scanout(struct drm_plane *plane,
> struct dpu_plane_state *pstate,
> - struct dpu_hw_pipe_cfg *pipe_cfg,
> struct drm_framebuffer *fb)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
> struct msm_gem_address_space *aspace = kms->base.aspace;
> + struct dpu_hw_fmt_layout layout;
> int ret;
>
> - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> + ret = dpu_format_populate_layout(aspace, fb, &layout);
> if (ret)
> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
> trace_dpu_plane_set_scanout(&pstate->pipe,
> - &pipe_cfg->layout);
> - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
> + &layout);
> + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
> }
> }
>
> @@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>
> memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
>
> - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
> + _dpu_plane_set_scanout(plane, pstate, fb);
>
> pstate->pending = true;
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
@ 2023-02-02 19:38 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 19:38 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
> only src_rect and dst_rect. This way right and left pipes will have
> separate dpu_hw_pipe_cfg isntances, while the layout is common to both
> of them.
>
Sorry for not responding to this comment earlier.
https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
From the perspective of wide planes you are right that the layout is
common but not true from smart DMA point of view.
For wide planes, yes, its usually the same buffer with just the src_x
being different but conceptually and even HW wise each rectangle of the
smart DMA is capable of fetching from a different buffer.
From the pov, this decision of not having the dpu_hw_fmt_layout as part
of dpu_hw_pipe_cfg seems incorrect to me.
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
> 3 files changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 2bd39c13d54d..400d043f37fa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> }
>
> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> - struct dpu_hw_pipe_cfg *cfg)
> + struct dpu_hw_fmt_layout *layout)
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> u32 ystride0, ystride1;
> @@ -497,41 +497,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> return;
>
> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
> + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
> - cfg->layout.plane_addr[i]);
> + layout->plane_addr[i]);
> } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
> - cfg->layout.plane_addr[0]);
> + layout->plane_addr[0]);
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
> - cfg->layout.plane_addr[2]);
> + layout->plane_addr[2]);
> } else {
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
> - cfg->layout.plane_addr[0]);
> + layout->plane_addr[0]);
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> - cfg->layout.plane_addr[2]);
> + layout->plane_addr[2]);
> }
>
> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> - ystride0 = (cfg->layout.plane_pitch[0]) |
> - (cfg->layout.plane_pitch[1] << 16);
> - ystride1 = (cfg->layout.plane_pitch[2]) |
> - (cfg->layout.plane_pitch[3] << 16);
> + ystride0 = (layout->plane_pitch[0]) |
> + (layout->plane_pitch[1] << 16);
> + ystride1 = (layout->plane_pitch[2]) |
> + (layout->plane_pitch[3] << 16);
> } else {
> ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
>
> if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> ystride0 = (ystride0 & 0xFFFF0000) |
> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> + (layout->plane_pitch[0] & 0x0000FFFF);
> ystride1 = (ystride1 & 0xFFFF0000)|
> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> + (layout->plane_pitch[2] & 0x0000FFFF);
> } else {
> ystride0 = (ystride0 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[0] << 16) &
> + ((layout->plane_pitch[0] << 16) &
> 0xFFFF0000);
> ystride1 = (ystride1 & 0x0000FFFF) |
> - ((cfg->layout.plane_pitch[2] << 16) &
> + ((layout->plane_pitch[2] << 16) &
> 0xFFFF0000);
> }
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index c713343378aa..8dad52eb2a90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
>
> /**
> * struct dpu_hw_pipe_cfg : Pipe description
> - * @layout: format layout information for programming buffer to hardware
> * @src_rect: src ROI, caller takes into account the different operations
> * such as decimation, flip etc to program this field
> * @dest_rect: destination ROI.
> */
> struct dpu_hw_pipe_cfg {
> - struct dpu_hw_fmt_layout layout;
> struct drm_rect src_rect;
> struct drm_rect dst_rect;
> };
> @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
> /**
> * setup_sourceaddress - setup pipe source addresses
> * @pipe: Pointer to software pipe context
> - * @cfg: Pointer to pipe config structure
> + * @layout: format layout information for programming buffer to hardware
> */
> void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
> - struct dpu_hw_pipe_cfg *cfg);
> + struct dpu_hw_fmt_layout *layout);
>
> /**
> * setup_csc - setup color space coversion
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index cbff4dea8662..0d2a7170e0ab 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
>
> static void _dpu_plane_set_scanout(struct drm_plane *plane,
> struct dpu_plane_state *pstate,
> - struct dpu_hw_pipe_cfg *pipe_cfg,
> struct drm_framebuffer *fb)
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
> struct msm_gem_address_space *aspace = kms->base.aspace;
> + struct dpu_hw_fmt_layout layout;
> int ret;
>
> - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> + ret = dpu_format_populate_layout(aspace, fb, &layout);
> if (ret)
> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
> trace_dpu_plane_set_scanout(&pstate->pipe,
> - &pipe_cfg->layout);
> - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
> + &layout);
> + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
> }
> }
>
> @@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>
> memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
>
> - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
> + _dpu_plane_set_scanout(plane, pstate, fb);
>
> pstate->pending = true;
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
2023-02-02 19:38 ` Abhinav Kumar
@ 2023-02-02 19:45 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-02 19:45 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> > Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
> > only src_rect and dst_rect. This way right and left pipes will have
> > separate dpu_hw_pipe_cfg isntances, while the layout is common to both
> > of them.
> >
>
> Sorry for not responding to this comment earlier.
>
> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>
> From the perspective of wide planes you are right that the layout is
> common but not true from smart DMA point of view.
>
> For wide planes, yes, its usually the same buffer with just the src_x
> being different but conceptually and even HW wise each rectangle of the
> smart DMA is capable of fetching from a different buffer.
>
> From the pov, this decision of not having the dpu_hw_fmt_layout as part
> of dpu_hw_pipe_cfg seems incorrect to me.
Yes, each rectangle/pipe can fetch from a different buffer. However in
our use case the layout is not defined for each pipe. It is defined
for a plane, no matter how many pipes are used for the plane, since
the buffer is also defined per plane.
>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++++++++++-----------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
> > 3 files changed, 22 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > index 2bd39c13d54d..400d043f37fa 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> > }
> >
> > static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> > - struct dpu_hw_pipe_cfg *cfg)
> > + struct dpu_hw_fmt_layout *layout)
> > {
> > struct dpu_hw_sspp *ctx = pipe->sspp;
> > u32 ystride0, ystride1;
> > @@ -497,41 +497,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> > return;
> >
> > if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> > - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
> > + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
> > - cfg->layout.plane_addr[i]);
> > + layout->plane_addr[i]);
> > } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
> > - cfg->layout.plane_addr[0]);
> > + layout->plane_addr[0]);
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
> > - cfg->layout.plane_addr[2]);
> > + layout->plane_addr[2]);
> > } else {
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
> > - cfg->layout.plane_addr[0]);
> > + layout->plane_addr[0]);
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> > - cfg->layout.plane_addr[2]);
> > + layout->plane_addr[2]);
> > }
> >
> > if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> > - ystride0 = (cfg->layout.plane_pitch[0]) |
> > - (cfg->layout.plane_pitch[1] << 16);
> > - ystride1 = (cfg->layout.plane_pitch[2]) |
> > - (cfg->layout.plane_pitch[3] << 16);
> > + ystride0 = (layout->plane_pitch[0]) |
> > + (layout->plane_pitch[1] << 16);
> > + ystride1 = (layout->plane_pitch[2]) |
> > + (layout->plane_pitch[3] << 16);
> > } else {
> > ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> > ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
> >
> > if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> > ystride0 = (ystride0 & 0xFFFF0000) |
> > - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> > + (layout->plane_pitch[0] & 0x0000FFFF);
> > ystride1 = (ystride1 & 0xFFFF0000)|
> > - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> > + (layout->plane_pitch[2] & 0x0000FFFF);
> > } else {
> > ystride0 = (ystride0 & 0x0000FFFF) |
> > - ((cfg->layout.plane_pitch[0] << 16) &
> > + ((layout->plane_pitch[0] << 16) &
> > 0xFFFF0000);
> > ystride1 = (ystride1 & 0x0000FFFF) |
> > - ((cfg->layout.plane_pitch[2] << 16) &
> > + ((layout->plane_pitch[2] << 16) &
> > 0xFFFF0000);
> > }
> > }
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> > index c713343378aa..8dad52eb2a90 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> > @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
> >
> > /**
> > * struct dpu_hw_pipe_cfg : Pipe description
> > - * @layout: format layout information for programming buffer to hardware
> > * @src_rect: src ROI, caller takes into account the different operations
> > * such as decimation, flip etc to program this field
> > * @dest_rect: destination ROI.
> > */
> > struct dpu_hw_pipe_cfg {
> > - struct dpu_hw_fmt_layout layout;
> > struct drm_rect src_rect;
> > struct drm_rect dst_rect;
> > };
> > @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
> > /**
> > * setup_sourceaddress - setup pipe source addresses
> > * @pipe: Pointer to software pipe context
> > - * @cfg: Pointer to pipe config structure
> > + * @layout: format layout information for programming buffer to hardware
> > */
> > void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
> > - struct dpu_hw_pipe_cfg *cfg);
> > + struct dpu_hw_fmt_layout *layout);
> >
> > /**
> > * setup_csc - setup color space coversion
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index cbff4dea8662..0d2a7170e0ab 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
> >
> > static void _dpu_plane_set_scanout(struct drm_plane *plane,
> > struct dpu_plane_state *pstate,
> > - struct dpu_hw_pipe_cfg *pipe_cfg,
> > struct drm_framebuffer *fb)
> > {
> > struct dpu_plane *pdpu = to_dpu_plane(plane);
> > struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
> > struct msm_gem_address_space *aspace = kms->base.aspace;
> > + struct dpu_hw_fmt_layout layout;
> > int ret;
> >
> > - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> > + ret = dpu_format_populate_layout(aspace, fb, &layout);
> > if (ret)
> > DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> > else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
> > trace_dpu_plane_set_scanout(&pstate->pipe,
> > - &pipe_cfg->layout);
> > - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
> > + &layout);
> > + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
> > }
> > }
> >
> > @@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> >
> > memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
> >
> > - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
> > + _dpu_plane_set_scanout(plane, pstate, fb);
> >
> > pstate->pending = true;
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
@ 2023-02-02 19:45 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-02 19:45 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
> > Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
> > only src_rect and dst_rect. This way right and left pipes will have
> > separate dpu_hw_pipe_cfg isntances, while the layout is common to both
> > of them.
> >
>
> Sorry for not responding to this comment earlier.
>
> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>
> From the perspective of wide planes you are right that the layout is
> common but not true from smart DMA point of view.
>
> For wide planes, yes, its usually the same buffer with just the src_x
> being different but conceptually and even HW wise each rectangle of the
> smart DMA is capable of fetching from a different buffer.
>
> From the pov, this decision of not having the dpu_hw_fmt_layout as part
> of dpu_hw_pipe_cfg seems incorrect to me.
Yes, each rectangle/pipe can fetch from a different buffer. However in
our use case the layout is not defined for each pipe. It is defined
for a plane, no matter how many pipes are used for the plane, since
the buffer is also defined per plane.
>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++++++++++-----------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
> > 3 files changed, 22 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > index 2bd39c13d54d..400d043f37fa 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> > }
> >
> > static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> > - struct dpu_hw_pipe_cfg *cfg)
> > + struct dpu_hw_fmt_layout *layout)
> > {
> > struct dpu_hw_sspp *ctx = pipe->sspp;
> > u32 ystride0, ystride1;
> > @@ -497,41 +497,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> > return;
> >
> > if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> > - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
> > + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
> > - cfg->layout.plane_addr[i]);
> > + layout->plane_addr[i]);
> > } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
> > - cfg->layout.plane_addr[0]);
> > + layout->plane_addr[0]);
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
> > - cfg->layout.plane_addr[2]);
> > + layout->plane_addr[2]);
> > } else {
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
> > - cfg->layout.plane_addr[0]);
> > + layout->plane_addr[0]);
> > DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
> > - cfg->layout.plane_addr[2]);
> > + layout->plane_addr[2]);
> > }
> >
> > if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> > - ystride0 = (cfg->layout.plane_pitch[0]) |
> > - (cfg->layout.plane_pitch[1] << 16);
> > - ystride1 = (cfg->layout.plane_pitch[2]) |
> > - (cfg->layout.plane_pitch[3] << 16);
> > + ystride0 = (layout->plane_pitch[0]) |
> > + (layout->plane_pitch[1] << 16);
> > + ystride1 = (layout->plane_pitch[2]) |
> > + (layout->plane_pitch[3] << 16);
> > } else {
> > ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
> > ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
> >
> > if (pipe->multirect_index == DPU_SSPP_RECT_0) {
> > ystride0 = (ystride0 & 0xFFFF0000) |
> > - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
> > + (layout->plane_pitch[0] & 0x0000FFFF);
> > ystride1 = (ystride1 & 0xFFFF0000)|
> > - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
> > + (layout->plane_pitch[2] & 0x0000FFFF);
> > } else {
> > ystride0 = (ystride0 & 0x0000FFFF) |
> > - ((cfg->layout.plane_pitch[0] << 16) &
> > + ((layout->plane_pitch[0] << 16) &
> > 0xFFFF0000);
> > ystride1 = (ystride1 & 0x0000FFFF) |
> > - ((cfg->layout.plane_pitch[2] << 16) &
> > + ((layout->plane_pitch[2] << 16) &
> > 0xFFFF0000);
> > }
> > }
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> > index c713343378aa..8dad52eb2a90 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> > @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
> >
> > /**
> > * struct dpu_hw_pipe_cfg : Pipe description
> > - * @layout: format layout information for programming buffer to hardware
> > * @src_rect: src ROI, caller takes into account the different operations
> > * such as decimation, flip etc to program this field
> > * @dest_rect: destination ROI.
> > */
> > struct dpu_hw_pipe_cfg {
> > - struct dpu_hw_fmt_layout layout;
> > struct drm_rect src_rect;
> > struct drm_rect dst_rect;
> > };
> > @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
> > /**
> > * setup_sourceaddress - setup pipe source addresses
> > * @pipe: Pointer to software pipe context
> > - * @cfg: Pointer to pipe config structure
> > + * @layout: format layout information for programming buffer to hardware
> > */
> > void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
> > - struct dpu_hw_pipe_cfg *cfg);
> > + struct dpu_hw_fmt_layout *layout);
> >
> > /**
> > * setup_csc - setup color space coversion
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index cbff4dea8662..0d2a7170e0ab 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
> >
> > static void _dpu_plane_set_scanout(struct drm_plane *plane,
> > struct dpu_plane_state *pstate,
> > - struct dpu_hw_pipe_cfg *pipe_cfg,
> > struct drm_framebuffer *fb)
> > {
> > struct dpu_plane *pdpu = to_dpu_plane(plane);
> > struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
> > struct msm_gem_address_space *aspace = kms->base.aspace;
> > + struct dpu_hw_fmt_layout layout;
> > int ret;
> >
> > - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
> > + ret = dpu_format_populate_layout(aspace, fb, &layout);
> > if (ret)
> > DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> > else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
> > trace_dpu_plane_set_scanout(&pstate->pipe,
> > - &pipe_cfg->layout);
> > - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
> > + &layout);
> > + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
> > }
> > }
> >
> > @@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
> >
> > memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
> >
> > - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
> > + _dpu_plane_set_scanout(plane, pstate, fb);
> >
> > pstate->pending = true;
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
2023-02-02 19:45 ` Dmitry Baryshkov
@ 2023-02-02 19:54 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 19:54 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
>>> only src_rect and dst_rect. This way right and left pipes will have
>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to both
>>> of them.
>>>
>>
>> Sorry for not responding to this comment earlier.
>>
>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>
>> From the perspective of wide planes you are right that the layout is
>> common but not true from smart DMA point of view.
>>
>> For wide planes, yes, its usually the same buffer with just the src_x
>> being different but conceptually and even HW wise each rectangle of the
>> smart DMA is capable of fetching from a different buffer.
>>
>> From the pov, this decision of not having the dpu_hw_fmt_layout as part
>> of dpu_hw_pipe_cfg seems incorrect to me.
>
> Yes, each rectangle/pipe can fetch from a different buffer. However in
> our use case the layout is not defined for each pipe. It is defined
> for a plane, no matter how many pipes are used for the plane, since
> the buffer is also defined per plane.
>
Even if the layout is defined per plane.
So lets say
plane A with layout A maps to rect 1 of DMA0
plane B with layout B maps to rect 2 of DMA0
How can layout be assumed to be duplicated in this case?
This is not a wide plane use-case but just smartDMA case of two
different layers.
Maybe I am missing something but this is the example i am interested about.
>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++++++++++-----------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
>>> 3 files changed, 22 insertions(+), 24 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> index 2bd39c13d54d..400d043f37fa 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
>>> }
>>>
>>> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>> - struct dpu_hw_pipe_cfg *cfg)
>>> + struct dpu_hw_fmt_layout *layout)
>>> {
>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>> u32 ystride0, ystride1;
>>> @@ -497,41 +497,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>> return;
>>>
>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>> - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
>>> + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
>>> - cfg->layout.plane_addr[i]);
>>> + layout->plane_addr[i]);
>>> } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
>>> - cfg->layout.plane_addr[0]);
>>> + layout->plane_addr[0]);
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
>>> - cfg->layout.plane_addr[2]);
>>> + layout->plane_addr[2]);
>>> } else {
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
>>> - cfg->layout.plane_addr[0]);
>>> + layout->plane_addr[0]);
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
>>> - cfg->layout.plane_addr[2]);
>>> + layout->plane_addr[2]);
>>> }
>>>
>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>> - ystride0 = (cfg->layout.plane_pitch[0]) |
>>> - (cfg->layout.plane_pitch[1] << 16);
>>> - ystride1 = (cfg->layout.plane_pitch[2]) |
>>> - (cfg->layout.plane_pitch[3] << 16);
>>> + ystride0 = (layout->plane_pitch[0]) |
>>> + (layout->plane_pitch[1] << 16);
>>> + ystride1 = (layout->plane_pitch[2]) |
>>> + (layout->plane_pitch[3] << 16);
>>> } else {
>>> ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
>>> ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
>>>
>>> if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>> ystride0 = (ystride0 & 0xFFFF0000) |
>>> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
>>> + (layout->plane_pitch[0] & 0x0000FFFF);
>>> ystride1 = (ystride1 & 0xFFFF0000)|
>>> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
>>> + (layout->plane_pitch[2] & 0x0000FFFF);
>>> } else {
>>> ystride0 = (ystride0 & 0x0000FFFF) |
>>> - ((cfg->layout.plane_pitch[0] << 16) &
>>> + ((layout->plane_pitch[0] << 16) &
>>> 0xFFFF0000);
>>> ystride1 = (ystride1 & 0x0000FFFF) |
>>> - ((cfg->layout.plane_pitch[2] << 16) &
>>> + ((layout->plane_pitch[2] << 16) &
>>> 0xFFFF0000);
>>> }
>>> }
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> index c713343378aa..8dad52eb2a90 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
>>>
>>> /**
>>> * struct dpu_hw_pipe_cfg : Pipe description
>>> - * @layout: format layout information for programming buffer to hardware
>>> * @src_rect: src ROI, caller takes into account the different operations
>>> * such as decimation, flip etc to program this field
>>> * @dest_rect: destination ROI.
>>> */
>>> struct dpu_hw_pipe_cfg {
>>> - struct dpu_hw_fmt_layout layout;
>>> struct drm_rect src_rect;
>>> struct drm_rect dst_rect;
>>> };
>>> @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
>>> /**
>>> * setup_sourceaddress - setup pipe source addresses
>>> * @pipe: Pointer to software pipe context
>>> - * @cfg: Pointer to pipe config structure
>>> + * @layout: format layout information for programming buffer to hardware
>>> */
>>> void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
>>> - struct dpu_hw_pipe_cfg *cfg);
>>> + struct dpu_hw_fmt_layout *layout);
>>>
>>> /**
>>> * setup_csc - setup color space coversion
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> index cbff4dea8662..0d2a7170e0ab 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
>>>
>>> static void _dpu_plane_set_scanout(struct drm_plane *plane,
>>> struct dpu_plane_state *pstate,
>>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>>> struct drm_framebuffer *fb)
>>> {
>>> struct dpu_plane *pdpu = to_dpu_plane(plane);
>>> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
>>> struct msm_gem_address_space *aspace = kms->base.aspace;
>>> + struct dpu_hw_fmt_layout layout;
>>> int ret;
>>>
>>> - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
>>> + ret = dpu_format_populate_layout(aspace, fb, &layout);
>>> if (ret)
>>> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
>>> else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
>>> trace_dpu_plane_set_scanout(&pstate->pipe,
>>> - &pipe_cfg->layout);
>>> - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
>>> + &layout);
>>> + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
>>> }
>>> }
>>>
>>> @@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>>>
>>> memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
>>>
>>> - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
>>> + _dpu_plane_set_scanout(plane, pstate, fb);
>>>
>>> pstate->pending = true;
>>>
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
@ 2023-02-02 19:54 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 19:54 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
>>> only src_rect and dst_rect. This way right and left pipes will have
>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to both
>>> of them.
>>>
>>
>> Sorry for not responding to this comment earlier.
>>
>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>
>> From the perspective of wide planes you are right that the layout is
>> common but not true from smart DMA point of view.
>>
>> For wide planes, yes, its usually the same buffer with just the src_x
>> being different but conceptually and even HW wise each rectangle of the
>> smart DMA is capable of fetching from a different buffer.
>>
>> From the pov, this decision of not having the dpu_hw_fmt_layout as part
>> of dpu_hw_pipe_cfg seems incorrect to me.
>
> Yes, each rectangle/pipe can fetch from a different buffer. However in
> our use case the layout is not defined for each pipe. It is defined
> for a plane, no matter how many pipes are used for the plane, since
> the buffer is also defined per plane.
>
Even if the layout is defined per plane.
So lets say
plane A with layout A maps to rect 1 of DMA0
plane B with layout B maps to rect 2 of DMA0
How can layout be assumed to be duplicated in this case?
This is not a wide plane use-case but just smartDMA case of two
different layers.
Maybe I am missing something but this is the example i am interested about.
>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++++++++++-----------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
>>> 3 files changed, 22 insertions(+), 24 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> index 2bd39c13d54d..400d043f37fa 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>> @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
>>> }
>>>
>>> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>> - struct dpu_hw_pipe_cfg *cfg)
>>> + struct dpu_hw_fmt_layout *layout)
>>> {
>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>> u32 ystride0, ystride1;
>>> @@ -497,41 +497,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>> return;
>>>
>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>> - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
>>> + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
>>> - cfg->layout.plane_addr[i]);
>>> + layout->plane_addr[i]);
>>> } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
>>> - cfg->layout.plane_addr[0]);
>>> + layout->plane_addr[0]);
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
>>> - cfg->layout.plane_addr[2]);
>>> + layout->plane_addr[2]);
>>> } else {
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
>>> - cfg->layout.plane_addr[0]);
>>> + layout->plane_addr[0]);
>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
>>> - cfg->layout.plane_addr[2]);
>>> + layout->plane_addr[2]);
>>> }
>>>
>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>> - ystride0 = (cfg->layout.plane_pitch[0]) |
>>> - (cfg->layout.plane_pitch[1] << 16);
>>> - ystride1 = (cfg->layout.plane_pitch[2]) |
>>> - (cfg->layout.plane_pitch[3] << 16);
>>> + ystride0 = (layout->plane_pitch[0]) |
>>> + (layout->plane_pitch[1] << 16);
>>> + ystride1 = (layout->plane_pitch[2]) |
>>> + (layout->plane_pitch[3] << 16);
>>> } else {
>>> ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
>>> ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
>>>
>>> if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>> ystride0 = (ystride0 & 0xFFFF0000) |
>>> - (cfg->layout.plane_pitch[0] & 0x0000FFFF);
>>> + (layout->plane_pitch[0] & 0x0000FFFF);
>>> ystride1 = (ystride1 & 0xFFFF0000)|
>>> - (cfg->layout.plane_pitch[2] & 0x0000FFFF);
>>> + (layout->plane_pitch[2] & 0x0000FFFF);
>>> } else {
>>> ystride0 = (ystride0 & 0x0000FFFF) |
>>> - ((cfg->layout.plane_pitch[0] << 16) &
>>> + ((layout->plane_pitch[0] << 16) &
>>> 0xFFFF0000);
>>> ystride1 = (ystride1 & 0x0000FFFF) |
>>> - ((cfg->layout.plane_pitch[2] << 16) &
>>> + ((layout->plane_pitch[2] << 16) &
>>> 0xFFFF0000);
>>> }
>>> }
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> index c713343378aa..8dad52eb2a90 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>> @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
>>>
>>> /**
>>> * struct dpu_hw_pipe_cfg : Pipe description
>>> - * @layout: format layout information for programming buffer to hardware
>>> * @src_rect: src ROI, caller takes into account the different operations
>>> * such as decimation, flip etc to program this field
>>> * @dest_rect: destination ROI.
>>> */
>>> struct dpu_hw_pipe_cfg {
>>> - struct dpu_hw_fmt_layout layout;
>>> struct drm_rect src_rect;
>>> struct drm_rect dst_rect;
>>> };
>>> @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
>>> /**
>>> * setup_sourceaddress - setup pipe source addresses
>>> * @pipe: Pointer to software pipe context
>>> - * @cfg: Pointer to pipe config structure
>>> + * @layout: format layout information for programming buffer to hardware
>>> */
>>> void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
>>> - struct dpu_hw_pipe_cfg *cfg);
>>> + struct dpu_hw_fmt_layout *layout);
>>>
>>> /**
>>> * setup_csc - setup color space coversion
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> index cbff4dea8662..0d2a7170e0ab 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>> @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
>>>
>>> static void _dpu_plane_set_scanout(struct drm_plane *plane,
>>> struct dpu_plane_state *pstate,
>>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>>> struct drm_framebuffer *fb)
>>> {
>>> struct dpu_plane *pdpu = to_dpu_plane(plane);
>>> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
>>> struct msm_gem_address_space *aspace = kms->base.aspace;
>>> + struct dpu_hw_fmt_layout layout;
>>> int ret;
>>>
>>> - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
>>> + ret = dpu_format_populate_layout(aspace, fb, &layout);
>>> if (ret)
>>> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
>>> else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
>>> trace_dpu_plane_set_scanout(&pstate->pipe,
>>> - &pipe_cfg->layout);
>>> - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
>>> + &layout);
>>> + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
>>> }
>>> }
>>>
>>> @@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>>>
>>> memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
>>>
>>> - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
>>> + _dpu_plane_set_scanout(plane, pstate, fb);
>>>
>>> pstate->pending = true;
>>>
>
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
2023-02-02 19:54 ` Abhinav Kumar
@ 2023-02-02 20:10 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-02 20:10 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 02/02/2023 21:54, Abhinav Kumar wrote:
>
>
> On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
>> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar <quic_abhinavk@quicinc.com>
>> wrote:
>>>
>>>
>>>
>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
>>>> only src_rect and dst_rect. This way right and left pipes will have
>>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to both
>>>> of them.
>>>>
>>>
>>> Sorry for not responding to this comment earlier.
>>>
>>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>>
>>> From the perspective of wide planes you are right that the layout is
>>> common but not true from smart DMA point of view.
>>>
>>> For wide planes, yes, its usually the same buffer with just the src_x
>>> being different but conceptually and even HW wise each rectangle of the
>>> smart DMA is capable of fetching from a different buffer.
>>>
>>> From the pov, this decision of not having the dpu_hw_fmt_layout as
>>> part
>>> of dpu_hw_pipe_cfg seems incorrect to me.
>>
>> Yes, each rectangle/pipe can fetch from a different buffer. However in
>> our use case the layout is not defined for each pipe. It is defined
>> for a plane, no matter how many pipes are used for the plane, since
>> the buffer is also defined per plane.
>>
> Even if the layout is defined per plane.
>
> So lets say
>
> plane A with layout A maps to rect 1 of DMA0
> plane B with layout B maps to rect 2 of DMA0
>
> How can layout be assumed to be duplicated in this case?
>
> This is not a wide plane use-case but just smartDMA case of two
> different layers.
>
> Maybe I am missing something but this is the example i am interested about.
PlaneA has layoutA. So dpu_plane_sspp_update_pipe() will program layoutA
using (DMA0, rect1)->setup_sourceaddress(layoutA).
PlaneB has layoutB, so (DMA0, rect2)->setup_sourceaddress(layoutB).
Maybe the commit message is misleading. The layout is not common to
rect1 and rect2. It is common to all pipes/rectangles driving a single
plane.
>
>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30
>>>> ++++++++++-----------
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
>>>> 3 files changed, 22 insertions(+), 24 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>> index 2bd39c13d54d..400d043f37fa 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>> @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct
>>>> dpu_sw_pipe *pipe,
>>>> }
>>>>
>>>> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe
>>>> *pipe,
>>>> - struct dpu_hw_pipe_cfg *cfg)
>>>> + struct dpu_hw_fmt_layout *layout)
>>>> {
>>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>>> u32 ystride0, ystride1;
>>>> @@ -497,41 +497,41 @@ static void
>>>> dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>>> return;
>>>>
>>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>>> - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
>>>> + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx
>>>> + i * 0x4,
>>>> - cfg->layout.plane_addr[i]);
>>>> + layout->plane_addr[i]);
>>>> } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
>>>> - cfg->layout.plane_addr[0]);
>>>> + layout->plane_addr[0]);
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
>>>> - cfg->layout.plane_addr[2]);
>>>> + layout->plane_addr[2]);
>>>> } else {
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
>>>> - cfg->layout.plane_addr[0]);
>>>> + layout->plane_addr[0]);
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
>>>> - cfg->layout.plane_addr[2]);
>>>> + layout->plane_addr[2]);
>>>> }
>>>>
>>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>>> - ystride0 = (cfg->layout.plane_pitch[0]) |
>>>> - (cfg->layout.plane_pitch[1] << 16);
>>>> - ystride1 = (cfg->layout.plane_pitch[2]) |
>>>> - (cfg->layout.plane_pitch[3] << 16);
>>>> + ystride0 = (layout->plane_pitch[0]) |
>>>> + (layout->plane_pitch[1] << 16);
>>>> + ystride1 = (layout->plane_pitch[2]) |
>>>> + (layout->plane_pitch[3] << 16);
>>>> } else {
>>>> ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 +
>>>> idx);
>>>> ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 +
>>>> idx);
>>>>
>>>> if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>>> ystride0 = (ystride0 & 0xFFFF0000) |
>>>> - (cfg->layout.plane_pitch[0] &
>>>> 0x0000FFFF);
>>>> + (layout->plane_pitch[0] & 0x0000FFFF);
>>>> ystride1 = (ystride1 & 0xFFFF0000)|
>>>> - (cfg->layout.plane_pitch[2] &
>>>> 0x0000FFFF);
>>>> + (layout->plane_pitch[2] & 0x0000FFFF);
>>>> } else {
>>>> ystride0 = (ystride0 & 0x0000FFFF) |
>>>> - ((cfg->layout.plane_pitch[0] << 16) &
>>>> + ((layout->plane_pitch[0] << 16) &
>>>> 0xFFFF0000);
>>>> ystride1 = (ystride1 & 0x0000FFFF) |
>>>> - ((cfg->layout.plane_pitch[2] << 16) &
>>>> + ((layout->plane_pitch[2] << 16) &
>>>> 0xFFFF0000);
>>>> }
>>>> }
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>> index c713343378aa..8dad52eb2a90 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>> @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
>>>>
>>>> /**
>>>> * struct dpu_hw_pipe_cfg : Pipe description
>>>> - * @layout: format layout information for programming buffer to
>>>> hardware
>>>> * @src_rect: src ROI, caller takes into account the different
>>>> operations
>>>> * such as decimation, flip etc to program this field
>>>> * @dest_rect: destination ROI.
>>>> */
>>>> struct dpu_hw_pipe_cfg {
>>>> - struct dpu_hw_fmt_layout layout;
>>>> struct drm_rect src_rect;
>>>> struct drm_rect dst_rect;
>>>> };
>>>> @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
>>>> /**
>>>> * setup_sourceaddress - setup pipe source addresses
>>>> * @pipe: Pointer to software pipe context
>>>> - * @cfg: Pointer to pipe config structure
>>>> + * @layout: format layout information for programming buffer
>>>> to hardware
>>>> */
>>>> void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
>>>> - struct dpu_hw_pipe_cfg *cfg);
>>>> + struct dpu_hw_fmt_layout *layout);
>>>>
>>>> /**
>>>> * setup_csc - setup color space coversion
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>> index cbff4dea8662..0d2a7170e0ab 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>> @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct
>>>> drm_plane *plane)
>>>>
>>>> static void _dpu_plane_set_scanout(struct drm_plane *plane,
>>>> struct dpu_plane_state *pstate,
>>>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>>>> struct drm_framebuffer *fb)
>>>> {
>>>> struct dpu_plane *pdpu = to_dpu_plane(plane);
>>>> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
>>>> struct msm_gem_address_space *aspace = kms->base.aspace;
>>>> + struct dpu_hw_fmt_layout layout;
>>>> int ret;
>>>>
>>>> - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
>>>> + ret = dpu_format_populate_layout(aspace, fb, &layout);
>>>> if (ret)
>>>> DPU_ERROR_PLANE(pdpu, "failed to get format layout,
>>>> %d\n", ret);
>>>> else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
>>>> trace_dpu_plane_set_scanout(&pstate->pipe,
>>>> - &pipe_cfg->layout);
>>>> -
>>>> pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
>>>> + &layout);
>>>> +
>>>> pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
>>>> }
>>>> }
>>>>
>>>> @@ -1134,7 +1134,7 @@ static void
>>>> dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>>>>
>>>> memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
>>>>
>>>> - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
>>>> + _dpu_plane_set_scanout(plane, pstate, fb);
>>>>
>>>> pstate->pending = true;
>>>>
>>
>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
@ 2023-02-02 20:10 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-02 20:10 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 02/02/2023 21:54, Abhinav Kumar wrote:
>
>
> On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
>> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar <quic_abhinavk@quicinc.com>
>> wrote:
>>>
>>>
>>>
>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
>>>> only src_rect and dst_rect. This way right and left pipes will have
>>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to both
>>>> of them.
>>>>
>>>
>>> Sorry for not responding to this comment earlier.
>>>
>>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>>
>>> From the perspective of wide planes you are right that the layout is
>>> common but not true from smart DMA point of view.
>>>
>>> For wide planes, yes, its usually the same buffer with just the src_x
>>> being different but conceptually and even HW wise each rectangle of the
>>> smart DMA is capable of fetching from a different buffer.
>>>
>>> From the pov, this decision of not having the dpu_hw_fmt_layout as
>>> part
>>> of dpu_hw_pipe_cfg seems incorrect to me.
>>
>> Yes, each rectangle/pipe can fetch from a different buffer. However in
>> our use case the layout is not defined for each pipe. It is defined
>> for a plane, no matter how many pipes are used for the plane, since
>> the buffer is also defined per plane.
>>
> Even if the layout is defined per plane.
>
> So lets say
>
> plane A with layout A maps to rect 1 of DMA0
> plane B with layout B maps to rect 2 of DMA0
>
> How can layout be assumed to be duplicated in this case?
>
> This is not a wide plane use-case but just smartDMA case of two
> different layers.
>
> Maybe I am missing something but this is the example i am interested about.
PlaneA has layoutA. So dpu_plane_sspp_update_pipe() will program layoutA
using (DMA0, rect1)->setup_sourceaddress(layoutA).
PlaneB has layoutB, so (DMA0, rect2)->setup_sourceaddress(layoutB).
Maybe the commit message is misleading. The layout is not common to
rect1 and rect2. It is common to all pipes/rectangles driving a single
plane.
>
>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30
>>>> ++++++++++-----------
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
>>>> 3 files changed, 22 insertions(+), 24 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>> index 2bd39c13d54d..400d043f37fa 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>> @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct
>>>> dpu_sw_pipe *pipe,
>>>> }
>>>>
>>>> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe
>>>> *pipe,
>>>> - struct dpu_hw_pipe_cfg *cfg)
>>>> + struct dpu_hw_fmt_layout *layout)
>>>> {
>>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>>> u32 ystride0, ystride1;
>>>> @@ -497,41 +497,41 @@ static void
>>>> dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>>> return;
>>>>
>>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>>> - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
>>>> + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx
>>>> + i * 0x4,
>>>> - cfg->layout.plane_addr[i]);
>>>> + layout->plane_addr[i]);
>>>> } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
>>>> - cfg->layout.plane_addr[0]);
>>>> + layout->plane_addr[0]);
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
>>>> - cfg->layout.plane_addr[2]);
>>>> + layout->plane_addr[2]);
>>>> } else {
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
>>>> - cfg->layout.plane_addr[0]);
>>>> + layout->plane_addr[0]);
>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
>>>> - cfg->layout.plane_addr[2]);
>>>> + layout->plane_addr[2]);
>>>> }
>>>>
>>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>>> - ystride0 = (cfg->layout.plane_pitch[0]) |
>>>> - (cfg->layout.plane_pitch[1] << 16);
>>>> - ystride1 = (cfg->layout.plane_pitch[2]) |
>>>> - (cfg->layout.plane_pitch[3] << 16);
>>>> + ystride0 = (layout->plane_pitch[0]) |
>>>> + (layout->plane_pitch[1] << 16);
>>>> + ystride1 = (layout->plane_pitch[2]) |
>>>> + (layout->plane_pitch[3] << 16);
>>>> } else {
>>>> ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 +
>>>> idx);
>>>> ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 +
>>>> idx);
>>>>
>>>> if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>>> ystride0 = (ystride0 & 0xFFFF0000) |
>>>> - (cfg->layout.plane_pitch[0] &
>>>> 0x0000FFFF);
>>>> + (layout->plane_pitch[0] & 0x0000FFFF);
>>>> ystride1 = (ystride1 & 0xFFFF0000)|
>>>> - (cfg->layout.plane_pitch[2] &
>>>> 0x0000FFFF);
>>>> + (layout->plane_pitch[2] & 0x0000FFFF);
>>>> } else {
>>>> ystride0 = (ystride0 & 0x0000FFFF) |
>>>> - ((cfg->layout.plane_pitch[0] << 16) &
>>>> + ((layout->plane_pitch[0] << 16) &
>>>> 0xFFFF0000);
>>>> ystride1 = (ystride1 & 0x0000FFFF) |
>>>> - ((cfg->layout.plane_pitch[2] << 16) &
>>>> + ((layout->plane_pitch[2] << 16) &
>>>> 0xFFFF0000);
>>>> }
>>>> }
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>> index c713343378aa..8dad52eb2a90 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>> @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
>>>>
>>>> /**
>>>> * struct dpu_hw_pipe_cfg : Pipe description
>>>> - * @layout: format layout information for programming buffer to
>>>> hardware
>>>> * @src_rect: src ROI, caller takes into account the different
>>>> operations
>>>> * such as decimation, flip etc to program this field
>>>> * @dest_rect: destination ROI.
>>>> */
>>>> struct dpu_hw_pipe_cfg {
>>>> - struct dpu_hw_fmt_layout layout;
>>>> struct drm_rect src_rect;
>>>> struct drm_rect dst_rect;
>>>> };
>>>> @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
>>>> /**
>>>> * setup_sourceaddress - setup pipe source addresses
>>>> * @pipe: Pointer to software pipe context
>>>> - * @cfg: Pointer to pipe config structure
>>>> + * @layout: format layout information for programming buffer
>>>> to hardware
>>>> */
>>>> void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
>>>> - struct dpu_hw_pipe_cfg *cfg);
>>>> + struct dpu_hw_fmt_layout *layout);
>>>>
>>>> /**
>>>> * setup_csc - setup color space coversion
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>> index cbff4dea8662..0d2a7170e0ab 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>> @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct
>>>> drm_plane *plane)
>>>>
>>>> static void _dpu_plane_set_scanout(struct drm_plane *plane,
>>>> struct dpu_plane_state *pstate,
>>>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>>>> struct drm_framebuffer *fb)
>>>> {
>>>> struct dpu_plane *pdpu = to_dpu_plane(plane);
>>>> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
>>>> struct msm_gem_address_space *aspace = kms->base.aspace;
>>>> + struct dpu_hw_fmt_layout layout;
>>>> int ret;
>>>>
>>>> - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
>>>> + ret = dpu_format_populate_layout(aspace, fb, &layout);
>>>> if (ret)
>>>> DPU_ERROR_PLANE(pdpu, "failed to get format layout,
>>>> %d\n", ret);
>>>> else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
>>>> trace_dpu_plane_set_scanout(&pstate->pipe,
>>>> - &pipe_cfg->layout);
>>>> -
>>>> pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
>>>> + &layout);
>>>> +
>>>> pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
>>>> }
>>>> }
>>>>
>>>> @@ -1134,7 +1134,7 @@ static void
>>>> dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>>>>
>>>> memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
>>>>
>>>> - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
>>>> + _dpu_plane_set_scanout(plane, pstate, fb);
>>>>
>>>> pstate->pending = true;
>>>>
>>
>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
2023-02-02 20:10 ` Dmitry Baryshkov
@ 2023-02-02 20:14 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 20:14 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 2/2/2023 12:10 PM, Dmitry Baryshkov wrote:
> On 02/02/2023 21:54, Abhinav Kumar wrote:
>>
>>
>> On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
>>> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar
>>> <quic_abhinavk@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
>>>>> only src_rect and dst_rect. This way right and left pipes will have
>>>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to both
>>>>> of them.
>>>>>
>>>>
>>>> Sorry for not responding to this comment earlier.
>>>>
>>>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>>>
>>>>
>>>> From the perspective of wide planes you are right that the layout is
>>>> common but not true from smart DMA point of view.
>>>>
>>>> For wide planes, yes, its usually the same buffer with just the src_x
>>>> being different but conceptually and even HW wise each rectangle of the
>>>> smart DMA is capable of fetching from a different buffer.
>>>>
>>>> From the pov, this decision of not having the dpu_hw_fmt_layout as
>>>> part
>>>> of dpu_hw_pipe_cfg seems incorrect to me.
>>>
>>> Yes, each rectangle/pipe can fetch from a different buffer. However in
>>> our use case the layout is not defined for each pipe. It is defined
>>> for a plane, no matter how many pipes are used for the plane, since
>>> the buffer is also defined per plane.
>>>
>> Even if the layout is defined per plane.
>>
>> So lets say
>>
>> plane A with layout A maps to rect 1 of DMA0
>> plane B with layout B maps to rect 2 of DMA0
>>
>> How can layout be assumed to be duplicated in this case?
>>
>> This is not a wide plane use-case but just smartDMA case of two
>> different layers.
>>
>> Maybe I am missing something but this is the example i am interested
>> about.
>
> PlaneA has layoutA. So dpu_plane_sspp_update_pipe() will program layoutA
> using (DMA0, rect1)->setup_sourceaddress(layoutA).
>
> PlaneB has layoutB, so (DMA0, rect2)->setup_sourceaddress(layoutB).
>
> Maybe the commit message is misleading. The layout is not common to
> rect1 and rect2. It is common to all pipes/rectangles driving a single
> plane.
>
Ack, Its clear now.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>>>>
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>> ---
>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30
>>>>> ++++++++++-----------
>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
>>>>> 3 files changed, 22 insertions(+), 24 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>>> index 2bd39c13d54d..400d043f37fa 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>>> @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct
>>>>> dpu_sw_pipe *pipe,
>>>>> }
>>>>>
>>>>> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe
>>>>> *pipe,
>>>>> - struct dpu_hw_pipe_cfg *cfg)
>>>>> + struct dpu_hw_fmt_layout *layout)
>>>>> {
>>>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>>>> u32 ystride0, ystride1;
>>>>> @@ -497,41 +497,41 @@ static void
>>>>> dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>>>> return;
>>>>>
>>>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>>>> - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
>>>>> + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx
>>>>> + i * 0x4,
>>>>> - cfg->layout.plane_addr[i]);
>>>>> + layout->plane_addr[i]);
>>>>> } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
>>>>> - cfg->layout.plane_addr[0]);
>>>>> + layout->plane_addr[0]);
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
>>>>> - cfg->layout.plane_addr[2]);
>>>>> + layout->plane_addr[2]);
>>>>> } else {
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
>>>>> - cfg->layout.plane_addr[0]);
>>>>> + layout->plane_addr[0]);
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
>>>>> - cfg->layout.plane_addr[2]);
>>>>> + layout->plane_addr[2]);
>>>>> }
>>>>>
>>>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>>>> - ystride0 = (cfg->layout.plane_pitch[0]) |
>>>>> - (cfg->layout.plane_pitch[1] << 16);
>>>>> - ystride1 = (cfg->layout.plane_pitch[2]) |
>>>>> - (cfg->layout.plane_pitch[3] << 16);
>>>>> + ystride0 = (layout->plane_pitch[0]) |
>>>>> + (layout->plane_pitch[1] << 16);
>>>>> + ystride1 = (layout->plane_pitch[2]) |
>>>>> + (layout->plane_pitch[3] << 16);
>>>>> } else {
>>>>> ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0
>>>>> + idx);
>>>>> ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1
>>>>> + idx);
>>>>>
>>>>> if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>>>> ystride0 = (ystride0 & 0xFFFF0000) |
>>>>> - (cfg->layout.plane_pitch[0] &
>>>>> 0x0000FFFF);
>>>>> + (layout->plane_pitch[0] & 0x0000FFFF);
>>>>> ystride1 = (ystride1 & 0xFFFF0000)|
>>>>> - (cfg->layout.plane_pitch[2] &
>>>>> 0x0000FFFF);
>>>>> + (layout->plane_pitch[2] & 0x0000FFFF);
>>>>> } else {
>>>>> ystride0 = (ystride0 & 0x0000FFFF) |
>>>>> - ((cfg->layout.plane_pitch[0] << 16) &
>>>>> + ((layout->plane_pitch[0] << 16) &
>>>>> 0xFFFF0000);
>>>>> ystride1 = (ystride1 & 0x0000FFFF) |
>>>>> - ((cfg->layout.plane_pitch[2] << 16) &
>>>>> + ((layout->plane_pitch[2] << 16) &
>>>>> 0xFFFF0000);
>>>>> }
>>>>> }
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>>> index c713343378aa..8dad52eb2a90 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>>> @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
>>>>>
>>>>> /**
>>>>> * struct dpu_hw_pipe_cfg : Pipe description
>>>>> - * @layout: format layout information for programming buffer to
>>>>> hardware
>>>>> * @src_rect: src ROI, caller takes into account the different
>>>>> operations
>>>>> * such as decimation, flip etc to program this field
>>>>> * @dest_rect: destination ROI.
>>>>> */
>>>>> struct dpu_hw_pipe_cfg {
>>>>> - struct dpu_hw_fmt_layout layout;
>>>>> struct drm_rect src_rect;
>>>>> struct drm_rect dst_rect;
>>>>> };
>>>>> @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
>>>>> /**
>>>>> * setup_sourceaddress - setup pipe source addresses
>>>>> * @pipe: Pointer to software pipe context
>>>>> - * @cfg: Pointer to pipe config structure
>>>>> + * @layout: format layout information for programming buffer
>>>>> to hardware
>>>>> */
>>>>> void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
>>>>> - struct dpu_hw_pipe_cfg *cfg);
>>>>> + struct dpu_hw_fmt_layout *layout);
>>>>>
>>>>> /**
>>>>> * setup_csc - setup color space coversion
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>>> index cbff4dea8662..0d2a7170e0ab 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>>> @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct
>>>>> drm_plane *plane)
>>>>>
>>>>> static void _dpu_plane_set_scanout(struct drm_plane *plane,
>>>>> struct dpu_plane_state *pstate,
>>>>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>>>>> struct drm_framebuffer *fb)
>>>>> {
>>>>> struct dpu_plane *pdpu = to_dpu_plane(plane);
>>>>> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
>>>>> struct msm_gem_address_space *aspace = kms->base.aspace;
>>>>> + struct dpu_hw_fmt_layout layout;
>>>>> int ret;
>>>>>
>>>>> - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
>>>>> + ret = dpu_format_populate_layout(aspace, fb, &layout);
>>>>> if (ret)
>>>>> DPU_ERROR_PLANE(pdpu, "failed to get format layout,
>>>>> %d\n", ret);
>>>>> else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
>>>>> trace_dpu_plane_set_scanout(&pstate->pipe,
>>>>> - &pipe_cfg->layout);
>>>>> - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
>>>>> + &layout);
>>>>> + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
>>>>> }
>>>>> }
>>>>>
>>>>> @@ -1134,7 +1134,7 @@ static void
>>>>> dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>>>>>
>>>>> memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
>>>>>
>>>>> - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
>>>>> + _dpu_plane_set_scanout(plane, pstate, fb);
>>>>>
>>>>> pstate->pending = true;
>>>>>
>>>
>>>
>>>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
@ 2023-02-02 20:14 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-02 20:14 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 2/2/2023 12:10 PM, Dmitry Baryshkov wrote:
> On 02/02/2023 21:54, Abhinav Kumar wrote:
>>
>>
>> On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
>>> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar
>>> <quic_abhinavk@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg, leaving
>>>>> only src_rect and dst_rect. This way right and left pipes will have
>>>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to both
>>>>> of them.
>>>>>
>>>>
>>>> Sorry for not responding to this comment earlier.
>>>>
>>>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>>>
>>>>
>>>> From the perspective of wide planes you are right that the layout is
>>>> common but not true from smart DMA point of view.
>>>>
>>>> For wide planes, yes, its usually the same buffer with just the src_x
>>>> being different but conceptually and even HW wise each rectangle of the
>>>> smart DMA is capable of fetching from a different buffer.
>>>>
>>>> From the pov, this decision of not having the dpu_hw_fmt_layout as
>>>> part
>>>> of dpu_hw_pipe_cfg seems incorrect to me.
>>>
>>> Yes, each rectangle/pipe can fetch from a different buffer. However in
>>> our use case the layout is not defined for each pipe. It is defined
>>> for a plane, no matter how many pipes are used for the plane, since
>>> the buffer is also defined per plane.
>>>
>> Even if the layout is defined per plane.
>>
>> So lets say
>>
>> plane A with layout A maps to rect 1 of DMA0
>> plane B with layout B maps to rect 2 of DMA0
>>
>> How can layout be assumed to be duplicated in this case?
>>
>> This is not a wide plane use-case but just smartDMA case of two
>> different layers.
>>
>> Maybe I am missing something but this is the example i am interested
>> about.
>
> PlaneA has layoutA. So dpu_plane_sspp_update_pipe() will program layoutA
> using (DMA0, rect1)->setup_sourceaddress(layoutA).
>
> PlaneB has layoutB, so (DMA0, rect2)->setup_sourceaddress(layoutB).
>
> Maybe the commit message is misleading. The layout is not common to
> rect1 and rect2. It is common to all pipes/rectangles driving a single
> plane.
>
Ack, Its clear now.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>>>>
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>> ---
>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30
>>>>> ++++++++++-----------
>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++---
>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++----
>>>>> 3 files changed, 22 insertions(+), 24 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>>> index 2bd39c13d54d..400d043f37fa 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
>>>>> @@ -486,7 +486,7 @@ static void dpu_hw_sspp_setup_rects(struct
>>>>> dpu_sw_pipe *pipe,
>>>>> }
>>>>>
>>>>> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe
>>>>> *pipe,
>>>>> - struct dpu_hw_pipe_cfg *cfg)
>>>>> + struct dpu_hw_fmt_layout *layout)
>>>>> {
>>>>> struct dpu_hw_sspp *ctx = pipe->sspp;
>>>>> u32 ystride0, ystride1;
>>>>> @@ -497,41 +497,41 @@ static void
>>>>> dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
>>>>> return;
>>>>>
>>>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>>>> - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
>>>>> + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx
>>>>> + i * 0x4,
>>>>> - cfg->layout.plane_addr[i]);
>>>>> + layout->plane_addr[i]);
>>>>> } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
>>>>> - cfg->layout.plane_addr[0]);
>>>>> + layout->plane_addr[0]);
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
>>>>> - cfg->layout.plane_addr[2]);
>>>>> + layout->plane_addr[2]);
>>>>> } else {
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
>>>>> - cfg->layout.plane_addr[0]);
>>>>> + layout->plane_addr[0]);
>>>>> DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
>>>>> - cfg->layout.plane_addr[2]);
>>>>> + layout->plane_addr[2]);
>>>>> }
>>>>>
>>>>> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
>>>>> - ystride0 = (cfg->layout.plane_pitch[0]) |
>>>>> - (cfg->layout.plane_pitch[1] << 16);
>>>>> - ystride1 = (cfg->layout.plane_pitch[2]) |
>>>>> - (cfg->layout.plane_pitch[3] << 16);
>>>>> + ystride0 = (layout->plane_pitch[0]) |
>>>>> + (layout->plane_pitch[1] << 16);
>>>>> + ystride1 = (layout->plane_pitch[2]) |
>>>>> + (layout->plane_pitch[3] << 16);
>>>>> } else {
>>>>> ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0
>>>>> + idx);
>>>>> ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1
>>>>> + idx);
>>>>>
>>>>> if (pipe->multirect_index == DPU_SSPP_RECT_0) {
>>>>> ystride0 = (ystride0 & 0xFFFF0000) |
>>>>> - (cfg->layout.plane_pitch[0] &
>>>>> 0x0000FFFF);
>>>>> + (layout->plane_pitch[0] & 0x0000FFFF);
>>>>> ystride1 = (ystride1 & 0xFFFF0000)|
>>>>> - (cfg->layout.plane_pitch[2] &
>>>>> 0x0000FFFF);
>>>>> + (layout->plane_pitch[2] & 0x0000FFFF);
>>>>> } else {
>>>>> ystride0 = (ystride0 & 0x0000FFFF) |
>>>>> - ((cfg->layout.plane_pitch[0] << 16) &
>>>>> + ((layout->plane_pitch[0] << 16) &
>>>>> 0xFFFF0000);
>>>>> ystride1 = (ystride1 & 0x0000FFFF) |
>>>>> - ((cfg->layout.plane_pitch[2] << 16) &
>>>>> + ((layout->plane_pitch[2] << 16) &
>>>>> 0xFFFF0000);
>>>>> }
>>>>> }
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>>> index c713343378aa..8dad52eb2a90 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
>>>>> @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
>>>>>
>>>>> /**
>>>>> * struct dpu_hw_pipe_cfg : Pipe description
>>>>> - * @layout: format layout information for programming buffer to
>>>>> hardware
>>>>> * @src_rect: src ROI, caller takes into account the different
>>>>> operations
>>>>> * such as decimation, flip etc to program this field
>>>>> * @dest_rect: destination ROI.
>>>>> */
>>>>> struct dpu_hw_pipe_cfg {
>>>>> - struct dpu_hw_fmt_layout layout;
>>>>> struct drm_rect src_rect;
>>>>> struct drm_rect dst_rect;
>>>>> };
>>>>> @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
>>>>> /**
>>>>> * setup_sourceaddress - setup pipe source addresses
>>>>> * @pipe: Pointer to software pipe context
>>>>> - * @cfg: Pointer to pipe config structure
>>>>> + * @layout: format layout information for programming buffer
>>>>> to hardware
>>>>> */
>>>>> void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
>>>>> - struct dpu_hw_pipe_cfg *cfg);
>>>>> + struct dpu_hw_fmt_layout *layout);
>>>>>
>>>>> /**
>>>>> * setup_csc - setup color space coversion
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>>> index cbff4dea8662..0d2a7170e0ab 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>>>>> @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct
>>>>> drm_plane *plane)
>>>>>
>>>>> static void _dpu_plane_set_scanout(struct drm_plane *plane,
>>>>> struct dpu_plane_state *pstate,
>>>>> - struct dpu_hw_pipe_cfg *pipe_cfg,
>>>>> struct drm_framebuffer *fb)
>>>>> {
>>>>> struct dpu_plane *pdpu = to_dpu_plane(plane);
>>>>> struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
>>>>> struct msm_gem_address_space *aspace = kms->base.aspace;
>>>>> + struct dpu_hw_fmt_layout layout;
>>>>> int ret;
>>>>>
>>>>> - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
>>>>> + ret = dpu_format_populate_layout(aspace, fb, &layout);
>>>>> if (ret)
>>>>> DPU_ERROR_PLANE(pdpu, "failed to get format layout,
>>>>> %d\n", ret);
>>>>> else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
>>>>> trace_dpu_plane_set_scanout(&pstate->pipe,
>>>>> - &pipe_cfg->layout);
>>>>> - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
>>>>> + &layout);
>>>>> + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
>>>>> }
>>>>> }
>>>>>
>>>>> @@ -1134,7 +1134,7 @@ static void
>>>>> dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>>>>>
>>>>> memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
>>>>>
>>>>> - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
>>>>> + _dpu_plane_set_scanout(plane, pstate, fb);
>>>>>
>>>>> pstate->pending = true;
>>>>>
>>>
>>>
>>>
>
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
2023-02-02 20:14 ` Abhinav Kumar
@ 2023-02-03 14:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-03 14:09 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 02/02/2023 22:14, Abhinav Kumar wrote:
>
>
> On 2/2/2023 12:10 PM, Dmitry Baryshkov wrote:
>> On 02/02/2023 21:54, Abhinav Kumar wrote:
>>>
>>>
>>> On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
>>>> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar
>>>> <quic_abhinavk@quicinc.com> wrote:
>>>>>
>>>>>
>>>>>
>>>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg,
>>>>>> leaving
>>>>>> only src_rect and dst_rect. This way right and left pipes will have
>>>>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to
>>>>>> both
>>>>>> of them.
>>>>>>
>>>>>
>>>>> Sorry for not responding to this comment earlier.
>>>>>
>>>>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>>>>
>>>>> From the perspective of wide planes you are right that the layout is
>>>>> common but not true from smart DMA point of view.
>>>>>
>>>>> For wide planes, yes, its usually the same buffer with just the src_x
>>>>> being different but conceptually and even HW wise each rectangle of
>>>>> the
>>>>> smart DMA is capable of fetching from a different buffer.
>>>>>
>>>>> From the pov, this decision of not having the dpu_hw_fmt_layout
>>>>> as part
>>>>> of dpu_hw_pipe_cfg seems incorrect to me.
>>>>
>>>> Yes, each rectangle/pipe can fetch from a different buffer. However in
>>>> our use case the layout is not defined for each pipe. It is defined
>>>> for a plane, no matter how many pipes are used for the plane, since
>>>> the buffer is also defined per plane.
>>>>
>>> Even if the layout is defined per plane.
>>>
>>> So lets say
>>>
>>> plane A with layout A maps to rect 1 of DMA0
>>> plane B with layout B maps to rect 2 of DMA0
>>>
>>> How can layout be assumed to be duplicated in this case?
>>>
>>> This is not a wide plane use-case but just smartDMA case of two
>>> different layers.
>>>
>>> Maybe I am missing something but this is the example i am interested
>>> about.
>>
>> PlaneA has layoutA. So dpu_plane_sspp_update_pipe() will program
>> layoutA using (DMA0, rect1)->setup_sourceaddress(layoutA).
>>
>> PlaneB has layoutB, so (DMA0, rect2)->setup_sourceaddress(layoutB).
>>
>> Maybe the commit message is misleading. The layout is not common to
>> rect1 and rect2. It is common to all pipes/rectangles driving a single
>> plane.
>>
>
> Ack, Its clear now.
>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
I have rephrased the last sentence of the commit message in the
following way. Hopefully it will be cleaner now:
This way all the pipes used by the plane
will have a common layout instance (as the framebuffer is shared between
them), while still keeping a separate src/dst rectangle configuration
for each pipe.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
@ 2023-02-03 14:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2023-02-03 14:09 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 02/02/2023 22:14, Abhinav Kumar wrote:
>
>
> On 2/2/2023 12:10 PM, Dmitry Baryshkov wrote:
>> On 02/02/2023 21:54, Abhinav Kumar wrote:
>>>
>>>
>>> On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
>>>> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar
>>>> <quic_abhinavk@quicinc.com> wrote:
>>>>>
>>>>>
>>>>>
>>>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg,
>>>>>> leaving
>>>>>> only src_rect and dst_rect. This way right and left pipes will have
>>>>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to
>>>>>> both
>>>>>> of them.
>>>>>>
>>>>>
>>>>> Sorry for not responding to this comment earlier.
>>>>>
>>>>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>>>>
>>>>> From the perspective of wide planes you are right that the layout is
>>>>> common but not true from smart DMA point of view.
>>>>>
>>>>> For wide planes, yes, its usually the same buffer with just the src_x
>>>>> being different but conceptually and even HW wise each rectangle of
>>>>> the
>>>>> smart DMA is capable of fetching from a different buffer.
>>>>>
>>>>> From the pov, this decision of not having the dpu_hw_fmt_layout
>>>>> as part
>>>>> of dpu_hw_pipe_cfg seems incorrect to me.
>>>>
>>>> Yes, each rectangle/pipe can fetch from a different buffer. However in
>>>> our use case the layout is not defined for each pipe. It is defined
>>>> for a plane, no matter how many pipes are used for the plane, since
>>>> the buffer is also defined per plane.
>>>>
>>> Even if the layout is defined per plane.
>>>
>>> So lets say
>>>
>>> plane A with layout A maps to rect 1 of DMA0
>>> plane B with layout B maps to rect 2 of DMA0
>>>
>>> How can layout be assumed to be duplicated in this case?
>>>
>>> This is not a wide plane use-case but just smartDMA case of two
>>> different layers.
>>>
>>> Maybe I am missing something but this is the example i am interested
>>> about.
>>
>> PlaneA has layoutA. So dpu_plane_sspp_update_pipe() will program
>> layoutA using (DMA0, rect1)->setup_sourceaddress(layoutA).
>>
>> PlaneB has layoutB, so (DMA0, rect2)->setup_sourceaddress(layoutB).
>>
>> Maybe the commit message is misleading. The layout is not common to
>> rect1 and rect2. It is common to all pipes/rectangles driving a single
>> plane.
>>
>
> Ack, Its clear now.
>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
I have rephrased the last sentence of the commit message in the
following way. Hopefully it will be cleaner now:
This way all the pipes used by the plane
will have a common layout instance (as the framebuffer is shared between
them), while still keeping a separate src/dst rectangle configuration
for each pipe.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
2023-02-03 14:09 ` Dmitry Baryshkov
@ 2023-02-03 17:47 ` Abhinav Kumar
-1 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-03 17:47 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 2/3/2023 6:09 AM, Dmitry Baryshkov wrote:
> On 02/02/2023 22:14, Abhinav Kumar wrote:
>>
>>
>> On 2/2/2023 12:10 PM, Dmitry Baryshkov wrote:
>>> On 02/02/2023 21:54, Abhinav Kumar wrote:
>>>>
>>>>
>>>> On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
>>>>> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar
>>>>> <quic_abhinavk@quicinc.com> wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>>>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg,
>>>>>>> leaving
>>>>>>> only src_rect and dst_rect. This way right and left pipes will have
>>>>>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to
>>>>>>> both
>>>>>>> of them.
>>>>>>>
>>>>>>
>>>>>> Sorry for not responding to this comment earlier.
>>>>>>
>>>>>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>>>>>
>>>>>>
>>>>>> From the perspective of wide planes you are right that the
>>>>>> layout is
>>>>>> common but not true from smart DMA point of view.
>>>>>>
>>>>>> For wide planes, yes, its usually the same buffer with just the src_x
>>>>>> being different but conceptually and even HW wise each rectangle
>>>>>> of the
>>>>>> smart DMA is capable of fetching from a different buffer.
>>>>>>
>>>>>> From the pov, this decision of not having the dpu_hw_fmt_layout
>>>>>> as part
>>>>>> of dpu_hw_pipe_cfg seems incorrect to me.
>>>>>
>>>>> Yes, each rectangle/pipe can fetch from a different buffer. However in
>>>>> our use case the layout is not defined for each pipe. It is defined
>>>>> for a plane, no matter how many pipes are used for the plane, since
>>>>> the buffer is also defined per plane.
>>>>>
>>>> Even if the layout is defined per plane.
>>>>
>>>> So lets say
>>>>
>>>> plane A with layout A maps to rect 1 of DMA0
>>>> plane B with layout B maps to rect 2 of DMA0
>>>>
>>>> How can layout be assumed to be duplicated in this case?
>>>>
>>>> This is not a wide plane use-case but just smartDMA case of two
>>>> different layers.
>>>>
>>>> Maybe I am missing something but this is the example i am interested
>>>> about.
>>>
>>> PlaneA has layoutA. So dpu_plane_sspp_update_pipe() will program
>>> layoutA using (DMA0, rect1)->setup_sourceaddress(layoutA).
>>>
>>> PlaneB has layoutB, so (DMA0, rect2)->setup_sourceaddress(layoutB).
>>>
>>> Maybe the commit message is misleading. The layout is not common to
>>> rect1 and rect2. It is common to all pipes/rectangles driving a
>>> single plane.
>>>
>>
>> Ack, Its clear now.
>>
>> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> I have rephrased the last sentence of the commit message in the
> following way. Hopefully it will be cleaner now:
>
> This way all the pipes used by the plane
> will have a common layout instance (as the framebuffer is shared between
> them), while still keeping a separate src/dst rectangle configuration
> for each pipe.
>
Ack, thanks.
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v2 12/27] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_pipe_cfg
@ 2023-02-03 17:47 ` Abhinav Kumar
0 siblings, 0 replies; 110+ messages in thread
From: Abhinav Kumar @ 2023-02-03 17:47 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 2/3/2023 6:09 AM, Dmitry Baryshkov wrote:
> On 02/02/2023 22:14, Abhinav Kumar wrote:
>>
>>
>> On 2/2/2023 12:10 PM, Dmitry Baryshkov wrote:
>>> On 02/02/2023 21:54, Abhinav Kumar wrote:
>>>>
>>>>
>>>> On 2/2/2023 11:45 AM, Dmitry Baryshkov wrote:
>>>>> On Thu, 2 Feb 2023 at 21:38, Abhinav Kumar
>>>>> <quic_abhinavk@quicinc.com> wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
>>>>>>> Remove dpu_hw_fmt_layout instance from struct dpu_hw_pipe_cfg,
>>>>>>> leaving
>>>>>>> only src_rect and dst_rect. This way right and left pipes will have
>>>>>>> separate dpu_hw_pipe_cfg isntances, while the layout is common to
>>>>>>> both
>>>>>>> of them.
>>>>>>>
>>>>>>
>>>>>> Sorry for not responding to this comment earlier.
>>>>>>
>>>>>> https://patchwork.freedesktop.org/patch/473168/?series=99909&rev=1#comment_875370
>>>>>>
>>>>>>
>>>>>> From the perspective of wide planes you are right that the
>>>>>> layout is
>>>>>> common but not true from smart DMA point of view.
>>>>>>
>>>>>> For wide planes, yes, its usually the same buffer with just the src_x
>>>>>> being different but conceptually and even HW wise each rectangle
>>>>>> of the
>>>>>> smart DMA is capable of fetching from a different buffer.
>>>>>>
>>>>>> From the pov, this decision of not having the dpu_hw_fmt_layout
>>>>>> as part
>>>>>> of dpu_hw_pipe_cfg seems incorrect to me.
>>>>>
>>>>> Yes, each rectangle/pipe can fetch from a different buffer. However in
>>>>> our use case the layout is not defined for each pipe. It is defined
>>>>> for a plane, no matter how many pipes are used for the plane, since
>>>>> the buffer is also defined per plane.
>>>>>
>>>> Even if the layout is defined per plane.
>>>>
>>>> So lets say
>>>>
>>>> plane A with layout A maps to rect 1 of DMA0
>>>> plane B with layout B maps to rect 2 of DMA0
>>>>
>>>> How can layout be assumed to be duplicated in this case?
>>>>
>>>> This is not a wide plane use-case but just smartDMA case of two
>>>> different layers.
>>>>
>>>> Maybe I am missing something but this is the example i am interested
>>>> about.
>>>
>>> PlaneA has layoutA. So dpu_plane_sspp_update_pipe() will program
>>> layoutA using (DMA0, rect1)->setup_sourceaddress(layoutA).
>>>
>>> PlaneB has layoutB, so (DMA0, rect2)->setup_sourceaddress(layoutB).
>>>
>>> Maybe the commit message is misleading. The layout is not common to
>>> rect1 and rect2. It is common to all pipes/rectangles driving a
>>> single plane.
>>>
>>
>> Ack, Its clear now.
>>
>> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> I have rephrased the last sentence of the commit message in the
> following way. Hopefully it will be cleaner now:
>
> This way all the pipes used by the plane
> will have a common layout instance (as the framebuffer is shared between
> them), while still keeping a separate src/dst rectangle configuration
> for each pipe.
>
Ack, thanks.
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v2 13/27] drm/msm/dpu: drop src_split and multirect check from dpu_crtc_atomic_check
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Neither source split nor multirect are properly supported at this
moment. Both of these checks depend on normalized_zpos being equal for
several planes (which is never the case for normalized zpos).
Drop these checks to simplify dpu_crtc_atomic_check(). The actual
support for either of these features is not removed from the backend
code (sspp, ctl, etc).
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 166 ++---------------------
1 file changed, 12 insertions(+), 154 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 04833d91caac..cdaf48a849bc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1105,13 +1105,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
drm_crtc_vblank_on(crtc);
}
-struct plane_state {
- struct dpu_plane_state *dpu_pstate;
- const struct drm_plane_state *drm_pstate;
- int stage;
- u32 pipe_id;
-};
-
static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
{
struct drm_crtc *crtc = cstate->crtc;
@@ -1133,29 +1126,22 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
crtc);
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
- struct plane_state *pstates;
const struct drm_plane_state *pstate;
struct drm_plane *plane;
struct drm_display_mode *mode;
- int cnt = 0, rc = 0, mixer_width = 0, i, z_pos;
+ int rc = 0;
- struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2];
- int multirect_count = 0;
- const struct drm_plane_state *pipe_staged[SSPP_MAX];
- int left_zpos_cnt = 0, right_zpos_cnt = 0;
struct drm_rect crtc_rect = { 0 };
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
- pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
-
if (!crtc_state->enable || !crtc_state->active) {
DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
crtc->base.id, crtc_state->enable,
crtc_state->active);
memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
- goto end;
+ return 0;
}
mode = &crtc_state->adjusted_mode;
@@ -1165,13 +1151,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (crtc_state->active_changed)
crtc_state->mode_changed = true;
- memset(pipe_staged, 0, sizeof(pipe_staged));
-
- if (cstate->num_mixers) {
- mixer_width = mode->hdisplay / cstate->num_mixers;
-
+ if (cstate->num_mixers)
_dpu_crtc_setup_lm_bounds(crtc, crtc_state);
- }
crtc_rect.x2 = mode->hdisplay;
crtc_rect.y2 = mode->vdisplay;
@@ -1180,38 +1161,21 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
struct drm_rect dst, clip = crtc_rect;
+ int z_pos;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
DPU_ERROR("%s: failed to get plane%d state, %d\n",
dpu_crtc->name, plane->base.id, rc);
- goto end;
+ return rc;
}
- if (cnt >= DPU_STAGE_MAX * 4)
- continue;
if (!pstate->visible)
continue;
- pstates[cnt].dpu_pstate = dpu_pstate;
- pstates[cnt].drm_pstate = pstate;
- pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe.sspp->idx;
-
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
- if (pipe_staged[pstates[cnt].pipe_id]) {
- multirect_plane[multirect_count].r0 =
- pipe_staged[pstates[cnt].pipe_id];
- multirect_plane[multirect_count].r1 = pstate;
- multirect_count++;
-
- pipe_staged[pstates[cnt].pipe_id] = NULL;
- } else {
- pipe_staged[pstates[cnt].pipe_id] = pstate;
- }
-
- cnt++;
+ dpu_plane_clear_multirect(pstate);
dst = drm_plane_state_dest(pstate);
if (!drm_rect_intersect(&clip, &dst)) {
@@ -1219,63 +1183,21 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
DPU_ERROR("display: " DRM_RECT_FMT " plane: "
DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect),
DRM_RECT_ARG(&dst));
- rc = -E2BIG;
- goto end;
+ return -E2BIG;
}
- }
- for (i = 1; i < SSPP_MAX; i++) {
- if (pipe_staged[i])
- dpu_plane_clear_multirect(pipe_staged[i]);
- }
-
- z_pos = -1;
- for (i = 0; i < cnt; i++) {
- /* reset counts at every new blend stage */
- if (pstates[i].stage != z_pos) {
- left_zpos_cnt = 0;
- right_zpos_cnt = 0;
- z_pos = pstates[i].stage;
- }
+ z_pos = pstate->normalized_zpos;
/* verify z_pos setting before using it */
if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) {
DPU_ERROR("> %d plane stages assigned\n",
DPU_STAGE_MAX - DPU_STAGE_0);
- rc = -EINVAL;
- goto end;
- } else if (pstates[i].drm_pstate->crtc_x < mixer_width) {
- if (left_zpos_cnt == 2) {
- DPU_ERROR("> 2 planes @ stage %d on left\n",
- z_pos);
- rc = -EINVAL;
- goto end;
- }
- left_zpos_cnt++;
-
- } else {
- if (right_zpos_cnt == 2) {
- DPU_ERROR("> 2 planes @ stage %d on right\n",
- z_pos);
- rc = -EINVAL;
- goto end;
- }
- right_zpos_cnt++;
+ return -EINVAL;
}
- pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
+ to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0;
DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
- }
- for (i = 0; i < multirect_count; i++) {
- if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) {
- DPU_ERROR(
- "multirect validation failed for planes (%d - %d)\n",
- multirect_plane[i].r0->plane->base.id,
- multirect_plane[i].r1->plane->base.id);
- rc = -EINVAL;
- goto end;
- }
}
atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
@@ -1284,74 +1206,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (rc) {
DPU_ERROR("crtc%d failed performance check %d\n",
crtc->base.id, rc);
- goto end;
- }
-
- /* validate source split:
- * use pstates sorted by stage to check planes on same stage
- * we assume that all pipes are in source split so its valid to compare
- * without taking into account left/right mixer placement
- */
- for (i = 1; i < cnt; i++) {
- struct plane_state *prv_pstate, *cur_pstate;
- struct drm_rect left_rect, right_rect;
- int32_t left_pid, right_pid;
- int32_t stage;
-
- prv_pstate = &pstates[i - 1];
- cur_pstate = &pstates[i];
- if (prv_pstate->stage != cur_pstate->stage)
- continue;
-
- stage = cur_pstate->stage;
-
- left_pid = prv_pstate->dpu_pstate->base.plane->base.id;
- left_rect = drm_plane_state_dest(prv_pstate->drm_pstate);
-
- right_pid = cur_pstate->dpu_pstate->base.plane->base.id;
- right_rect = drm_plane_state_dest(cur_pstate->drm_pstate);
-
- if (right_rect.x1 < left_rect.x1) {
- swap(left_pid, right_pid);
- swap(left_rect, right_rect);
- }
-
- /**
- * - planes are enumerated in pipe-priority order such that
- * planes with lower drm_id must be left-most in a shared
- * blend-stage when using source split.
- * - planes in source split must be contiguous in width
- * - planes in source split must have same dest yoff and height
- */
- if (right_pid < left_pid) {
- DPU_ERROR(
- "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n",
- stage, left_pid, right_pid);
- rc = -EINVAL;
- goto end;
- } else if (right_rect.x1 != drm_rect_width(&left_rect)) {
- DPU_ERROR("non-contiguous coordinates for src split. "
- "stage: %d left: " DRM_RECT_FMT " right: "
- DRM_RECT_FMT "\n", stage,
- DRM_RECT_ARG(&left_rect),
- DRM_RECT_ARG(&right_rect));
- rc = -EINVAL;
- goto end;
- } else if (left_rect.y1 != right_rect.y1 ||
- drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) {
- DPU_ERROR("source split at stage: %d. invalid "
- "yoff/height: left: " DRM_RECT_FMT " right: "
- DRM_RECT_FMT "\n", stage,
- DRM_RECT_ARG(&left_rect),
- DRM_RECT_ARG(&right_rect));
- rc = -EINVAL;
- goto end;
- }
+ return rc;
}
-end:
- kfree(pstates);
- return rc;
+ return 0;
}
int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 13/27] drm/msm/dpu: drop src_split and multirect check from dpu_crtc_atomic_check
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Neither source split nor multirect are properly supported at this
moment. Both of these checks depend on normalized_zpos being equal for
several planes (which is never the case for normalized zpos).
Drop these checks to simplify dpu_crtc_atomic_check(). The actual
support for either of these features is not removed from the backend
code (sspp, ctl, etc).
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 166 ++---------------------
1 file changed, 12 insertions(+), 154 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 04833d91caac..cdaf48a849bc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1105,13 +1105,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
drm_crtc_vblank_on(crtc);
}
-struct plane_state {
- struct dpu_plane_state *dpu_pstate;
- const struct drm_plane_state *drm_pstate;
- int stage;
- u32 pipe_id;
-};
-
static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
{
struct drm_crtc *crtc = cstate->crtc;
@@ -1133,29 +1126,22 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
crtc);
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
- struct plane_state *pstates;
const struct drm_plane_state *pstate;
struct drm_plane *plane;
struct drm_display_mode *mode;
- int cnt = 0, rc = 0, mixer_width = 0, i, z_pos;
+ int rc = 0;
- struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2];
- int multirect_count = 0;
- const struct drm_plane_state *pipe_staged[SSPP_MAX];
- int left_zpos_cnt = 0, right_zpos_cnt = 0;
struct drm_rect crtc_rect = { 0 };
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
- pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
-
if (!crtc_state->enable || !crtc_state->active) {
DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
crtc->base.id, crtc_state->enable,
crtc_state->active);
memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
- goto end;
+ return 0;
}
mode = &crtc_state->adjusted_mode;
@@ -1165,13 +1151,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (crtc_state->active_changed)
crtc_state->mode_changed = true;
- memset(pipe_staged, 0, sizeof(pipe_staged));
-
- if (cstate->num_mixers) {
- mixer_width = mode->hdisplay / cstate->num_mixers;
-
+ if (cstate->num_mixers)
_dpu_crtc_setup_lm_bounds(crtc, crtc_state);
- }
crtc_rect.x2 = mode->hdisplay;
crtc_rect.y2 = mode->vdisplay;
@@ -1180,38 +1161,21 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
struct drm_rect dst, clip = crtc_rect;
+ int z_pos;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
DPU_ERROR("%s: failed to get plane%d state, %d\n",
dpu_crtc->name, plane->base.id, rc);
- goto end;
+ return rc;
}
- if (cnt >= DPU_STAGE_MAX * 4)
- continue;
if (!pstate->visible)
continue;
- pstates[cnt].dpu_pstate = dpu_pstate;
- pstates[cnt].drm_pstate = pstate;
- pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe.sspp->idx;
-
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
- if (pipe_staged[pstates[cnt].pipe_id]) {
- multirect_plane[multirect_count].r0 =
- pipe_staged[pstates[cnt].pipe_id];
- multirect_plane[multirect_count].r1 = pstate;
- multirect_count++;
-
- pipe_staged[pstates[cnt].pipe_id] = NULL;
- } else {
- pipe_staged[pstates[cnt].pipe_id] = pstate;
- }
-
- cnt++;
+ dpu_plane_clear_multirect(pstate);
dst = drm_plane_state_dest(pstate);
if (!drm_rect_intersect(&clip, &dst)) {
@@ -1219,63 +1183,21 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
DPU_ERROR("display: " DRM_RECT_FMT " plane: "
DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect),
DRM_RECT_ARG(&dst));
- rc = -E2BIG;
- goto end;
+ return -E2BIG;
}
- }
- for (i = 1; i < SSPP_MAX; i++) {
- if (pipe_staged[i])
- dpu_plane_clear_multirect(pipe_staged[i]);
- }
-
- z_pos = -1;
- for (i = 0; i < cnt; i++) {
- /* reset counts at every new blend stage */
- if (pstates[i].stage != z_pos) {
- left_zpos_cnt = 0;
- right_zpos_cnt = 0;
- z_pos = pstates[i].stage;
- }
+ z_pos = pstate->normalized_zpos;
/* verify z_pos setting before using it */
if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) {
DPU_ERROR("> %d plane stages assigned\n",
DPU_STAGE_MAX - DPU_STAGE_0);
- rc = -EINVAL;
- goto end;
- } else if (pstates[i].drm_pstate->crtc_x < mixer_width) {
- if (left_zpos_cnt == 2) {
- DPU_ERROR("> 2 planes @ stage %d on left\n",
- z_pos);
- rc = -EINVAL;
- goto end;
- }
- left_zpos_cnt++;
-
- } else {
- if (right_zpos_cnt == 2) {
- DPU_ERROR("> 2 planes @ stage %d on right\n",
- z_pos);
- rc = -EINVAL;
- goto end;
- }
- right_zpos_cnt++;
+ return -EINVAL;
}
- pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
+ to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0;
DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
- }
- for (i = 0; i < multirect_count; i++) {
- if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) {
- DPU_ERROR(
- "multirect validation failed for planes (%d - %d)\n",
- multirect_plane[i].r0->plane->base.id,
- multirect_plane[i].r1->plane->base.id);
- rc = -EINVAL;
- goto end;
- }
}
atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
@@ -1284,74 +1206,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (rc) {
DPU_ERROR("crtc%d failed performance check %d\n",
crtc->base.id, rc);
- goto end;
- }
-
- /* validate source split:
- * use pstates sorted by stage to check planes on same stage
- * we assume that all pipes are in source split so its valid to compare
- * without taking into account left/right mixer placement
- */
- for (i = 1; i < cnt; i++) {
- struct plane_state *prv_pstate, *cur_pstate;
- struct drm_rect left_rect, right_rect;
- int32_t left_pid, right_pid;
- int32_t stage;
-
- prv_pstate = &pstates[i - 1];
- cur_pstate = &pstates[i];
- if (prv_pstate->stage != cur_pstate->stage)
- continue;
-
- stage = cur_pstate->stage;
-
- left_pid = prv_pstate->dpu_pstate->base.plane->base.id;
- left_rect = drm_plane_state_dest(prv_pstate->drm_pstate);
-
- right_pid = cur_pstate->dpu_pstate->base.plane->base.id;
- right_rect = drm_plane_state_dest(cur_pstate->drm_pstate);
-
- if (right_rect.x1 < left_rect.x1) {
- swap(left_pid, right_pid);
- swap(left_rect, right_rect);
- }
-
- /**
- * - planes are enumerated in pipe-priority order such that
- * planes with lower drm_id must be left-most in a shared
- * blend-stage when using source split.
- * - planes in source split must be contiguous in width
- * - planes in source split must have same dest yoff and height
- */
- if (right_pid < left_pid) {
- DPU_ERROR(
- "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n",
- stage, left_pid, right_pid);
- rc = -EINVAL;
- goto end;
- } else if (right_rect.x1 != drm_rect_width(&left_rect)) {
- DPU_ERROR("non-contiguous coordinates for src split. "
- "stage: %d left: " DRM_RECT_FMT " right: "
- DRM_RECT_FMT "\n", stage,
- DRM_RECT_ARG(&left_rect),
- DRM_RECT_ARG(&right_rect));
- rc = -EINVAL;
- goto end;
- } else if (left_rect.y1 != right_rect.y1 ||
- drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) {
- DPU_ERROR("source split at stage: %d. invalid "
- "yoff/height: left: " DRM_RECT_FMT " right: "
- DRM_RECT_FMT "\n", stage,
- DRM_RECT_ARG(&left_rect),
- DRM_RECT_ARG(&right_rect));
- rc = -EINVAL;
- goto end;
- }
+ return rc;
}
-end:
- kfree(pstates);
- return rc;
+ return 0;
}
int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 14/27] drm/msm/dpu: don't use unsupported blend stages
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
The dpu_crtc_atomic_check() compares blending stage with DPU_STAGE_MAX
(maximum amount of blending stages supported by the driver), however we
should compare it against .max_mixer_blendstages, the maximum blend
stage supported by the mixer.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index cdaf48a849bc..cf7be1427298 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1126,6 +1126,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
crtc);
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
+ struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
const struct drm_plane_state *pstate;
struct drm_plane *plane;
@@ -1161,7 +1162,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
struct drm_rect dst, clip = crtc_rect;
- int z_pos;
+ int stage;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
@@ -1186,17 +1187,16 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
return -E2BIG;
}
- z_pos = pstate->normalized_zpos;
-
- /* verify z_pos setting before using it */
- if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) {
+ /* verify stage setting before using it */
+ stage = DPU_STAGE_0 + pstate->normalized_zpos;
+ if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) {
DPU_ERROR("> %d plane stages assigned\n",
- DPU_STAGE_MAX - DPU_STAGE_0);
+ dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
return -EINVAL;
}
- to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0;
- DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
+ to_dpu_plane_state(pstate)->stage = stage;
+ DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage);
}
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 14/27] drm/msm/dpu: don't use unsupported blend stages
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
The dpu_crtc_atomic_check() compares blending stage with DPU_STAGE_MAX
(maximum amount of blending stages supported by the driver), however we
should compare it against .max_mixer_blendstages, the maximum blend
stage supported by the mixer.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index cdaf48a849bc..cf7be1427298 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1126,6 +1126,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
crtc);
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
+ struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
const struct drm_plane_state *pstate;
struct drm_plane *plane;
@@ -1161,7 +1162,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
struct drm_rect dst, clip = crtc_rect;
- int z_pos;
+ int stage;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
@@ -1186,17 +1187,16 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
return -E2BIG;
}
- z_pos = pstate->normalized_zpos;
-
- /* verify z_pos setting before using it */
- if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) {
+ /* verify stage setting before using it */
+ stage = DPU_STAGE_0 + pstate->normalized_zpos;
+ if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) {
DPU_ERROR("> %d plane stages assigned\n",
- DPU_STAGE_MAX - DPU_STAGE_0);
+ dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
return -EINVAL;
}
- to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0;
- DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
+ to_dpu_plane_state(pstate)->stage = stage;
+ DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage);
}
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 15/27] drm/msm/dpu: move the rest of plane checks to dpu_plane_atomic_check()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Move plane state updates from dpu_crtc_atomic_check() to the function
where they belong: to dpu_plane_atomic_check().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 18 +-----------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 ++++++++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 ------
3 files changed, 11 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index cf7be1427298..3c33bb4dfaf9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1126,7 +1126,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
crtc);
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
- struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
const struct drm_plane_state *pstate;
struct drm_plane *plane;
@@ -1158,11 +1157,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
crtc_rect.x2 = mode->hdisplay;
crtc_rect.y2 = mode->vdisplay;
- /* get plane state for all drm planes associated with crtc state */
+ /* FIXME: move this to dpu_plane_atomic_check? */
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
struct drm_rect dst, clip = crtc_rect;
- int stage;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
@@ -1176,8 +1174,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
- dpu_plane_clear_multirect(pstate);
-
dst = drm_plane_state_dest(pstate);
if (!drm_rect_intersect(&clip, &dst)) {
DPU_ERROR("invalid vertical/horizontal destination\n");
@@ -1186,18 +1182,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
DRM_RECT_ARG(&dst));
return -E2BIG;
}
-
- /* verify stage setting before using it */
- stage = DPU_STAGE_0 + pstate->normalized_zpos;
- if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) {
- DPU_ERROR("> %d plane stages assigned\n",
- dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
- return -EINVAL;
- }
-
- to_dpu_plane_state(pstate)->stage = stage;
- DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage);
-
}
atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 0d2a7170e0ab..50ce4653bbba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -733,14 +733,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
return 0;
}
-void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
-{
- struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
-
- pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
- pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
-}
-
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
{
struct dpu_plane_state *pstate[R_MAX];
@@ -994,6 +986,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
if (!new_plane_state->visible)
return 0;
+ pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
+ pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+
+ pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
+ if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
+ DPU_ERROR("> %d plane stages assigned\n",
+ pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
+ return -EINVAL;
+ }
+
src.x1 = new_plane_state->src_x >> 16;
src.y1 = new_plane_state->src_y >> 16;
src.x2 = src.x1 + (new_plane_state->src_w >> 16);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 55ea221e8488..36a82c06ab7a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -88,12 +88,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
*/
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane);
-/**
- * dpu_plane_clear_multirect - clear multirect bits for the given pipe
- * @drm_state: Pointer to DRM plane state
- */
-void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state);
-
/**
* dpu_plane_color_fill - enables color fill on plane
* @plane: Pointer to DRM plane object
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 15/27] drm/msm/dpu: move the rest of plane checks to dpu_plane_atomic_check()
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Move plane state updates from dpu_crtc_atomic_check() to the function
where they belong: to dpu_plane_atomic_check().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 18 +-----------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 ++++++++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 ------
3 files changed, 11 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index cf7be1427298..3c33bb4dfaf9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1126,7 +1126,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
crtc);
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
- struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
const struct drm_plane_state *pstate;
struct drm_plane *plane;
@@ -1158,11 +1157,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
crtc_rect.x2 = mode->hdisplay;
crtc_rect.y2 = mode->vdisplay;
- /* get plane state for all drm planes associated with crtc state */
+ /* FIXME: move this to dpu_plane_atomic_check? */
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
struct drm_rect dst, clip = crtc_rect;
- int stage;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
@@ -1176,8 +1174,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
- dpu_plane_clear_multirect(pstate);
-
dst = drm_plane_state_dest(pstate);
if (!drm_rect_intersect(&clip, &dst)) {
DPU_ERROR("invalid vertical/horizontal destination\n");
@@ -1186,18 +1182,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
DRM_RECT_ARG(&dst));
return -E2BIG;
}
-
- /* verify stage setting before using it */
- stage = DPU_STAGE_0 + pstate->normalized_zpos;
- if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) {
- DPU_ERROR("> %d plane stages assigned\n",
- dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
- return -EINVAL;
- }
-
- to_dpu_plane_state(pstate)->stage = stage;
- DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage);
-
}
atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 0d2a7170e0ab..50ce4653bbba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -733,14 +733,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
return 0;
}
-void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
-{
- struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
-
- pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
- pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
-}
-
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
{
struct dpu_plane_state *pstate[R_MAX];
@@ -994,6 +986,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
if (!new_plane_state->visible)
return 0;
+ pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
+ pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+
+ pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
+ if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
+ DPU_ERROR("> %d plane stages assigned\n",
+ pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
+ return -EINVAL;
+ }
+
src.x1 = new_plane_state->src_x >> 16;
src.y1 = new_plane_state->src_y >> 16;
src.x2 = src.x1 + (new_plane_state->src_w >> 16);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 55ea221e8488..36a82c06ab7a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -88,12 +88,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
*/
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane);
-/**
- * dpu_plane_clear_multirect - clear multirect bits for the given pipe
- * @drm_state: Pointer to DRM plane state
- */
-void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state);
-
/**
* dpu_plane_color_fill - enables color fill on plane
* @plane: Pointer to DRM plane object
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 16/27] drm/msm/dpu: drop redundant plane dst check from dpu_crtc_atomic_check()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
The helper drm_atomic_helper_check_plane_state() already checks whether
the scaled and clipped plane falls into the CRTC visible region (and
clears plane_state->visible if it doesn't). Drop the redundant check
from dpu_crtc_atomic_check().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 3c33bb4dfaf9..78981271b28a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1129,11 +1129,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
const struct drm_plane_state *pstate;
struct drm_plane *plane;
- struct drm_display_mode *mode;
int rc = 0;
- struct drm_rect crtc_rect = { 0 };
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
if (!crtc_state->enable || !crtc_state->active) {
@@ -1144,7 +1142,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
return 0;
}
- mode = &crtc_state->adjusted_mode;
DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
/* force a full mode set if active state changed */
@@ -1154,13 +1151,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (cstate->num_mixers)
_dpu_crtc_setup_lm_bounds(crtc, crtc_state);
- crtc_rect.x2 = mode->hdisplay;
- crtc_rect.y2 = mode->vdisplay;
-
/* FIXME: move this to dpu_plane_atomic_check? */
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
- struct drm_rect dst, clip = crtc_rect;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
@@ -1173,15 +1166,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
continue;
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
-
- dst = drm_plane_state_dest(pstate);
- if (!drm_rect_intersect(&clip, &dst)) {
- DPU_ERROR("invalid vertical/horizontal destination\n");
- DPU_ERROR("display: " DRM_RECT_FMT " plane: "
- DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect),
- DRM_RECT_ARG(&dst));
- return -E2BIG;
- }
}
atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 16/27] drm/msm/dpu: drop redundant plane dst check from dpu_crtc_atomic_check()
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
The helper drm_atomic_helper_check_plane_state() already checks whether
the scaled and clipped plane falls into the CRTC visible region (and
clears plane_state->visible if it doesn't). Drop the redundant check
from dpu_crtc_atomic_check().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 3c33bb4dfaf9..78981271b28a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1129,11 +1129,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
const struct drm_plane_state *pstate;
struct drm_plane *plane;
- struct drm_display_mode *mode;
int rc = 0;
- struct drm_rect crtc_rect = { 0 };
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
if (!crtc_state->enable || !crtc_state->active) {
@@ -1144,7 +1142,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
return 0;
}
- mode = &crtc_state->adjusted_mode;
DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
/* force a full mode set if active state changed */
@@ -1154,13 +1151,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (cstate->num_mixers)
_dpu_crtc_setup_lm_bounds(crtc, crtc_state);
- crtc_rect.x2 = mode->hdisplay;
- crtc_rect.y2 = mode->vdisplay;
-
/* FIXME: move this to dpu_plane_atomic_check? */
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
- struct drm_rect dst, clip = crtc_rect;
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
@@ -1173,15 +1166,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
continue;
dpu_pstate->needs_dirtyfb = needs_dirtyfb;
-
- dst = drm_plane_state_dest(pstate);
- if (!drm_rect_intersect(&clip, &dst)) {
- DPU_ERROR("invalid vertical/horizontal destination\n");
- DPU_ERROR("display: " DRM_RECT_FMT " plane: "
- DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect),
- DRM_RECT_ARG(&dst));
- return -E2BIG;
- }
}
atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 17/27] drm/msm/dpu: add dpu_hw_pipe_cfg to dpu_plane_state
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Now as all accesses to pipe_cfg and pstate have been cleaned, re-add
struct dpu_hw_pipe_cfg back to dpu_plane_state, so that
dpu_plane_atomic_check() and dpu_plane_atomic_update() do not have a
chance to disagree about src/dst rectangles (currently
dpu_plane_atomic_check() uses unclipped rectangles, while
dpu_plane_atomic_update() uses clipped rectangles calculated by
drm_atomic_helper_check_plane_state()).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 64 ++++++++++-------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 1 +
2 files changed, 29 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 50ce4653bbba..ff32c28ee16a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -963,7 +963,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
const struct drm_crtc_state *crtc_state = NULL;
const struct dpu_format *fmt;
- struct drm_rect src, dst, fb_rect = { 0 };
+ struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+ struct drm_rect fb_rect = { 0 };
uint32_t min_src_size, max_linewidth;
unsigned int rotation;
uint32_t supported_rotations;
@@ -996,12 +997,15 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
}
- src.x1 = new_plane_state->src_x >> 16;
- src.y1 = new_plane_state->src_y >> 16;
- src.x2 = src.x1 + (new_plane_state->src_w >> 16);
- src.y2 = src.y1 + (new_plane_state->src_h >> 16);
+ pipe_cfg->src_rect = new_plane_state->src;
- dst = drm_plane_state_dest(new_plane_state);
+ /* state->src is 16.16, src_rect is not */
+ pipe_cfg->src_rect.x1 >>= 16;
+ pipe_cfg->src_rect.x2 >>= 16;
+ pipe_cfg->src_rect.y1 >>= 16;
+ pipe_cfg->src_rect.y2 >>= 16;
+
+ pipe_cfg->dst_rect = new_plane_state->dst;
fb_rect.x2 = new_plane_state->fb->width;
fb_rect.y2 = new_plane_state->fb->height;
@@ -1020,30 +1024,30 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
/* check src bounds */
- } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
+ } else if (!dpu_plane_validate_src(&pipe_cfg->src_rect, &fb_rect, min_src_size)) {
DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&src));
+ DRM_RECT_ARG(&pipe_cfg->src_rect));
return -E2BIG;
/* valid yuv image */
} else if (DPU_FORMAT_IS_YUV(fmt) &&
- (src.x1 & 0x1 || src.y1 & 0x1 ||
- drm_rect_width(&src) & 0x1 ||
- drm_rect_height(&src) & 0x1)) {
+ (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 ||
+ drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
+ drm_rect_height(&pipe_cfg->src_rect) & 0x1)) {
DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&src));
+ DRM_RECT_ARG(&pipe_cfg->src_rect));
return -EINVAL;
/* min dst support */
- } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
+ } else if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || drm_rect_height(&pipe_cfg->dst_rect) < 0x1) {
DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&dst));
+ DRM_RECT_ARG(&pipe_cfg->dst_rect));
return -EINVAL;
/* check decimated source width */
- } else if (drm_rect_width(&src) > max_linewidth) {
+ } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
- DRM_RECT_ARG(&src), max_linewidth);
+ DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
return -E2BIG;
}
@@ -1057,7 +1061,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) &&
(rotation & DRM_MODE_ROTATE_90)) {
- ret = dpu_plane_check_inline_rotation(pdpu, sblk, src, fmt);
+ ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt);
if (ret)
return ret;
}
@@ -1132,9 +1136,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
bool is_rt_pipe;
const struct dpu_format *fmt =
to_dpu_format(msm_framebuffer_format(fb));
- struct dpu_hw_pipe_cfg pipe_cfg;
-
- memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
+ struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
_dpu_plane_set_scanout(plane, pstate, fb);
@@ -1151,16 +1153,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
crtc->base.id, DRM_RECT_ARG(&state->dst),
(char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
- pipe_cfg.src_rect = state->src;
-
- /* state->src is 16.16, src_rect is not */
- pipe_cfg.src_rect.x1 >>= 16;
- pipe_cfg.src_rect.x2 >>= 16;
- pipe_cfg.src_rect.y1 >>= 16;
- pipe_cfg.src_rect.y2 >>= 16;
-
- pipe_cfg.dst_rect = state->dst;
-
/* override for color fill */
if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
/* skip remaining processing on color fill */
@@ -1169,10 +1161,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
if (pipe->sspp->ops.setup_rects) {
pipe->sspp->ops.setup_rects(pipe,
- &pipe_cfg);
+ pipe_cfg);
}
- _dpu_plane_setup_scaler(pipe, fmt, false, &pipe_cfg, pstate->rotation);
+ _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation);
if (pipe->sspp->ops.setup_multirect)
pipe->sspp->ops.setup_multirect(
@@ -1213,12 +1205,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
}
- _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg);
+ _dpu_plane_set_qos_lut(plane, fb, &pstate->pipe_cfg);
_dpu_plane_set_danger_lut(plane, fb);
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
_dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
- _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
+ _dpu_plane_set_ot_limit(plane, crtc, &pstate->pipe_cfg);
}
if (pstate->needs_qos_remap) {
@@ -1226,9 +1218,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
_dpu_plane_set_qos_remap(plane);
}
- _dpu_plane_calc_bw(plane, fb, &pipe_cfg);
+ _dpu_plane_calc_bw(plane, fb, &pstate->pipe_cfg);
- _dpu_plane_calc_clk(plane, &pipe_cfg);
+ _dpu_plane_calc_clk(plane, &pstate->pipe_cfg);
}
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 36a82c06ab7a..95031e8b00f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -36,6 +36,7 @@ struct dpu_plane_state {
bool pending;
struct dpu_sw_pipe pipe;
+ struct dpu_hw_pipe_cfg pipe_cfg;
u64 plane_fetch_bw;
u64 plane_clk;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 17/27] drm/msm/dpu: add dpu_hw_pipe_cfg to dpu_plane_state
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Now as all accesses to pipe_cfg and pstate have been cleaned, re-add
struct dpu_hw_pipe_cfg back to dpu_plane_state, so that
dpu_plane_atomic_check() and dpu_plane_atomic_update() do not have a
chance to disagree about src/dst rectangles (currently
dpu_plane_atomic_check() uses unclipped rectangles, while
dpu_plane_atomic_update() uses clipped rectangles calculated by
drm_atomic_helper_check_plane_state()).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 64 ++++++++++-------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 1 +
2 files changed, 29 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 50ce4653bbba..ff32c28ee16a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -963,7 +963,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
const struct drm_crtc_state *crtc_state = NULL;
const struct dpu_format *fmt;
- struct drm_rect src, dst, fb_rect = { 0 };
+ struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+ struct drm_rect fb_rect = { 0 };
uint32_t min_src_size, max_linewidth;
unsigned int rotation;
uint32_t supported_rotations;
@@ -996,12 +997,15 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
}
- src.x1 = new_plane_state->src_x >> 16;
- src.y1 = new_plane_state->src_y >> 16;
- src.x2 = src.x1 + (new_plane_state->src_w >> 16);
- src.y2 = src.y1 + (new_plane_state->src_h >> 16);
+ pipe_cfg->src_rect = new_plane_state->src;
- dst = drm_plane_state_dest(new_plane_state);
+ /* state->src is 16.16, src_rect is not */
+ pipe_cfg->src_rect.x1 >>= 16;
+ pipe_cfg->src_rect.x2 >>= 16;
+ pipe_cfg->src_rect.y1 >>= 16;
+ pipe_cfg->src_rect.y2 >>= 16;
+
+ pipe_cfg->dst_rect = new_plane_state->dst;
fb_rect.x2 = new_plane_state->fb->width;
fb_rect.y2 = new_plane_state->fb->height;
@@ -1020,30 +1024,30 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
/* check src bounds */
- } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
+ } else if (!dpu_plane_validate_src(&pipe_cfg->src_rect, &fb_rect, min_src_size)) {
DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&src));
+ DRM_RECT_ARG(&pipe_cfg->src_rect));
return -E2BIG;
/* valid yuv image */
} else if (DPU_FORMAT_IS_YUV(fmt) &&
- (src.x1 & 0x1 || src.y1 & 0x1 ||
- drm_rect_width(&src) & 0x1 ||
- drm_rect_height(&src) & 0x1)) {
+ (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 ||
+ drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
+ drm_rect_height(&pipe_cfg->src_rect) & 0x1)) {
DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&src));
+ DRM_RECT_ARG(&pipe_cfg->src_rect));
return -EINVAL;
/* min dst support */
- } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
+ } else if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || drm_rect_height(&pipe_cfg->dst_rect) < 0x1) {
DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&dst));
+ DRM_RECT_ARG(&pipe_cfg->dst_rect));
return -EINVAL;
/* check decimated source width */
- } else if (drm_rect_width(&src) > max_linewidth) {
+ } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
- DRM_RECT_ARG(&src), max_linewidth);
+ DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
return -E2BIG;
}
@@ -1057,7 +1061,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) &&
(rotation & DRM_MODE_ROTATE_90)) {
- ret = dpu_plane_check_inline_rotation(pdpu, sblk, src, fmt);
+ ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt);
if (ret)
return ret;
}
@@ -1132,9 +1136,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
bool is_rt_pipe;
const struct dpu_format *fmt =
to_dpu_format(msm_framebuffer_format(fb));
- struct dpu_hw_pipe_cfg pipe_cfg;
-
- memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
+ struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
_dpu_plane_set_scanout(plane, pstate, fb);
@@ -1151,16 +1153,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
crtc->base.id, DRM_RECT_ARG(&state->dst),
(char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
- pipe_cfg.src_rect = state->src;
-
- /* state->src is 16.16, src_rect is not */
- pipe_cfg.src_rect.x1 >>= 16;
- pipe_cfg.src_rect.x2 >>= 16;
- pipe_cfg.src_rect.y1 >>= 16;
- pipe_cfg.src_rect.y2 >>= 16;
-
- pipe_cfg.dst_rect = state->dst;
-
/* override for color fill */
if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
/* skip remaining processing on color fill */
@@ -1169,10 +1161,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
if (pipe->sspp->ops.setup_rects) {
pipe->sspp->ops.setup_rects(pipe,
- &pipe_cfg);
+ pipe_cfg);
}
- _dpu_plane_setup_scaler(pipe, fmt, false, &pipe_cfg, pstate->rotation);
+ _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation);
if (pipe->sspp->ops.setup_multirect)
pipe->sspp->ops.setup_multirect(
@@ -1213,12 +1205,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
}
- _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg);
+ _dpu_plane_set_qos_lut(plane, fb, &pstate->pipe_cfg);
_dpu_plane_set_danger_lut(plane, fb);
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
_dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
- _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
+ _dpu_plane_set_ot_limit(plane, crtc, &pstate->pipe_cfg);
}
if (pstate->needs_qos_remap) {
@@ -1226,9 +1218,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
_dpu_plane_set_qos_remap(plane);
}
- _dpu_plane_calc_bw(plane, fb, &pipe_cfg);
+ _dpu_plane_calc_bw(plane, fb, &pstate->pipe_cfg);
- _dpu_plane_calc_clk(plane, &pipe_cfg);
+ _dpu_plane_calc_clk(plane, &pstate->pipe_cfg);
}
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 36a82c06ab7a..95031e8b00f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -36,6 +36,7 @@ struct dpu_plane_state {
bool pending;
struct dpu_sw_pipe pipe;
+ struct dpu_hw_pipe_cfg pipe_cfg;
u64 plane_fetch_bw;
u64 plane_clk;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 18/27] drm/msm/dpu: simplify dpu_plane_validate_src()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Since the driver uses clipped src coordinates, there is no need to check
against the fb coordinates. Remove corresponding checks and inline
dpu_plane_validate_src().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ++++++++---------------
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index ff32c28ee16a..a2c891034512 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -906,25 +906,6 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
old_pstate->needs_dirtyfb);
}
-static bool dpu_plane_validate_src(struct drm_rect *src,
- struct drm_rect *fb_rect,
- uint32_t min_src_size)
-{
- /* Ensure fb size is supported */
- if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH ||
- drm_rect_height(fb_rect) > MAX_IMG_HEIGHT)
- return false;
-
- /* Ensure src rect is above the minimum size */
- if (drm_rect_width(src) < min_src_size ||
- drm_rect_height(src) < min_src_size)
- return false;
-
- /* Ensure src is fully encapsulated in fb */
- return drm_rect_intersect(fb_rect, src) &&
- drm_rect_equals(fb_rect, src);
-}
-
static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
const struct dpu_sspp_sub_blks *sblk,
struct drm_rect src, const struct dpu_format *fmt)
@@ -1010,6 +991,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fb_rect.x2 = new_plane_state->fb->width;
fb_rect.y2 = new_plane_state->fb->height;
+ /* Ensure fb size is supported */
+ if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH ||
+ drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) {
+ DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n",
+ DRM_RECT_ARG(&fb_rect));
+ return -E2BIG;
+ }
+
max_linewidth = pdpu->catalog->caps->max_linewidth;
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
@@ -1024,7 +1013,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
/* check src bounds */
- } else if (!dpu_plane_validate_src(&pipe_cfg->src_rect, &fb_rect, min_src_size)) {
+ } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size ||
+ drm_rect_height(&pipe_cfg->src_rect) < min_src_size) {
DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
DRM_RECT_ARG(&pipe_cfg->src_rect));
return -E2BIG;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 18/27] drm/msm/dpu: simplify dpu_plane_validate_src()
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Since the driver uses clipped src coordinates, there is no need to check
against the fb coordinates. Remove corresponding checks and inline
dpu_plane_validate_src().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ++++++++---------------
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index ff32c28ee16a..a2c891034512 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -906,25 +906,6 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
old_pstate->needs_dirtyfb);
}
-static bool dpu_plane_validate_src(struct drm_rect *src,
- struct drm_rect *fb_rect,
- uint32_t min_src_size)
-{
- /* Ensure fb size is supported */
- if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH ||
- drm_rect_height(fb_rect) > MAX_IMG_HEIGHT)
- return false;
-
- /* Ensure src rect is above the minimum size */
- if (drm_rect_width(src) < min_src_size ||
- drm_rect_height(src) < min_src_size)
- return false;
-
- /* Ensure src is fully encapsulated in fb */
- return drm_rect_intersect(fb_rect, src) &&
- drm_rect_equals(fb_rect, src);
-}
-
static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
const struct dpu_sspp_sub_blks *sblk,
struct drm_rect src, const struct dpu_format *fmt)
@@ -1010,6 +991,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fb_rect.x2 = new_plane_state->fb->width;
fb_rect.y2 = new_plane_state->fb->height;
+ /* Ensure fb size is supported */
+ if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH ||
+ drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) {
+ DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n",
+ DRM_RECT_ARG(&fb_rect));
+ return -E2BIG;
+ }
+
max_linewidth = pdpu->catalog->caps->max_linewidth;
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
@@ -1024,7 +1013,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
/* check src bounds */
- } else if (!dpu_plane_validate_src(&pipe_cfg->src_rect, &fb_rect, min_src_size)) {
+ } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size ||
+ drm_rect_height(&pipe_cfg->src_rect) < min_src_size) {
DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
DRM_RECT_ARG(&pipe_cfg->src_rect));
return -E2BIG;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 19/27] drm/msm/dpu: rewrite plane's QoS-related functions to take dpu_sw_pipe and dpu_format
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Rewrite dpu_plane's QoS related functions to take struct dpu_sw_pipe and
struct dpu_format as arguments rather than fetching them from the
pstate or drm_framebuffer.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 98 +++++++++++------------
1 file changed, 47 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index a2c891034512..7fc2c767c6d1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -128,19 +128,18 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
/**
* _dpu_plane_calc_bw - calculate bandwidth required for a plane
* @plane: Pointer to drm plane.
- * @fb: Pointer to framebuffer associated with the given plane
+ * @fmt: Pointer to source buffer format
* @pipe_cfg: Pointer to pipe configuration
* Result: Updates calculated bandwidth in the plane state.
* BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
* Prefill BW Equation: line src bytes * line_time
*/
static void _dpu_plane_calc_bw(struct drm_plane *plane,
- struct drm_framebuffer *fb,
+ const struct dpu_format *fmt,
struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane_state *pstate;
struct drm_display_mode *mode;
- const struct dpu_format *fmt = NULL;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
int src_width, src_height, dst_height, fps;
u64 plane_prefill_bw;
@@ -152,8 +151,6 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
pstate = to_dpu_plane_state(plane->state);
mode = &plane->state->crtc->mode;
- fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
-
src_width = drm_rect_width(&pipe_cfg->src_rect);
src_height = drm_rect_height(&pipe_cfg->src_rect);
dst_height = drm_rect_height(&pipe_cfg->dst_rect);
@@ -217,25 +214,25 @@ static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg
/**
* _dpu_plane_calc_fill_level - calculate fill level of the given source format
* @plane: Pointer to drm plane
+ * @pipe: Pointer to software pipe
* @fmt: Pointer to source buffer format
* @src_width: width of source buffer
* Return: fill level corresponding to the source buffer/format or 0 if error
*/
static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, u32 src_width)
{
struct dpu_plane *pdpu;
- struct dpu_plane_state *pstate;
u32 fixed_buff_size;
u32 total_fl;
- if (!fmt || !plane->state || !src_width || !fmt->bpp) {
+ if (!fmt || !pipe || !src_width || !fmt->bpp) {
DPU_ERROR("invalid arguments\n");
return 0;
}
pdpu = to_dpu_plane(plane);
- pstate = to_dpu_plane_state(plane->state);
fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
/* FIXME: in multirect case account for the src_width of all the planes */
@@ -251,7 +248,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
((src_width + 32) * fmt->bpp);
}
} else {
- if (pstate->pipe.multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
+ if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
total_fl = (fixed_buff_size / 2) * 2 /
((src_width + 32) * fmt->bpp);
} else {
@@ -261,7 +258,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
}
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
- pdpu->pipe - SSPP_VIG0,
+ pipe->sspp->idx - SSPP_VIG0,
(char *)&fmt->base.pixel_format,
src_width, total_fl);
@@ -271,25 +268,22 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
/**
* _dpu_plane_set_qos_lut - set QoS LUT of the given plane
* @plane: Pointer to drm plane
- * @fb: Pointer to framebuffer associated with the given plane
+ * @pipe: Pointer to software pipe
+ * @fmt: Pointer to source buffer format
* @pipe_cfg: Pointer to pipe configuration
*/
static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
- struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
+ struct dpu_sw_pipe *pipe,
+ const struct dpu_format *fmt, struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
- const struct dpu_format *fmt = NULL;
u64 qos_lut;
u32 total_fl = 0, lut_usage;
if (!pdpu->is_rt_pipe) {
lut_usage = DPU_QOS_LUT_USAGE_NRT;
} else {
- fmt = dpu_get_dpu_format_ext(
- fb->format->format,
- fb->modifier);
- total_fl = _dpu_plane_calc_fill_level(plane, fmt,
+ total_fl = _dpu_plane_calc_fill_level(plane, pipe, fmt,
drm_rect_width(&pipe_cfg->src_rect));
if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
@@ -301,7 +295,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
qos_lut = _dpu_hw_get_qos_lut(
&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
- trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
+ trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
(fmt) ? fmt->base.pixel_format : 0,
pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
@@ -310,20 +304,20 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
fmt ? (char *)&fmt->base.pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, qos_lut);
- pstate->pipe.sspp->ops.setup_creq_lut(pstate->pipe.sspp, qos_lut);
+ pipe->sspp->ops.setup_creq_lut(pipe->sspp, qos_lut);
}
/**
* _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane
* @plane: Pointer to drm plane
- * @fb: Pointer to framebuffer associated with the given plane
+ * @pipe: Pointer to software pipe
+ * @fmt: Pointer to source buffer format
*/
static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
- struct drm_framebuffer *fb)
+ struct dpu_sw_pipe *pipe,
+ const struct dpu_format *fmt)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
- const struct dpu_format *fmt = NULL;
u32 danger_lut, safe_lut;
if (!pdpu->is_rt_pipe) {
@@ -332,10 +326,6 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
safe_lut = pdpu->catalog->perf->safe_lut_tbl
[DPU_QOS_LUT_USAGE_NRT];
} else {
- fmt = dpu_get_dpu_format_ext(
- fb->format->format,
- fb->modifier);
-
if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
danger_lut = pdpu->catalog->perf->danger_lut_tbl
[DPU_QOS_LUT_USAGE_LINEAR];
@@ -362,29 +352,30 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
danger_lut,
safe_lut);
- pstate->pipe.sspp->ops.setup_danger_safe_lut(pstate->pipe.sspp,
+ pipe->sspp->ops.setup_danger_safe_lut(pipe->sspp,
danger_lut, safe_lut);
}
/**
* _dpu_plane_set_qos_ctrl - set QoS control of the given plane
* @plane: Pointer to drm plane
+ * @pipe: Pointer to software pipe
* @enable: true to enable QoS control
* @flags: QoS control mode (enum dpu_plane_qos)
*/
static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe,
bool enable, u32 flags)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
- pipe_qos_cfg.creq_vblank = pstate->pipe.sspp->cap->sblk->creq_vblank;
+ pipe_qos_cfg.creq_vblank = pipe->sspp->cap->sblk->creq_vblank;
pipe_qos_cfg.danger_vblank =
- pstate->pipe.sspp->cap->sblk->danger_vblank;
+ pipe->sspp->cap->sblk->danger_vblank;
pipe_qos_cfg.vblank_en = enable;
}
@@ -410,33 +401,34 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
pipe_qos_cfg.danger_vblank,
pdpu->is_rt_pipe);
- pstate->pipe.sspp->ops.setup_qos_ctrl(pstate->pipe.sspp,
+ pipe->sspp->ops.setup_qos_ctrl(pipe->sspp,
&pipe_qos_cfg);
}
/**
* _dpu_plane_set_ot_limit - set OT limit for the given plane
* @plane: Pointer to drm plane
+ * @pipe: Pointer to software pipe
* @crtc: Pointer to drm crtc
* @pipe_cfg: Pointer to pipe configuration
*/
static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe,
struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_vbif_set_ot_params ot_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&ot_params, 0, sizeof(ot_params));
- ot_params.xin_id = pstate->pipe.sspp->cap->xin_id;
- ot_params.num = pstate->pipe.sspp->idx - SSPP_NONE;
+ ot_params.xin_id = pipe->sspp->cap->xin_id;
+ ot_params.num = pipe->sspp->idx - SSPP_NONE;
ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
ot_params.is_wfd = !pdpu->is_rt_pipe;
ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
ot_params.vbif_idx = VBIF_RT;
- ot_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl;
+ ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl;
ot_params.rd = true;
dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
@@ -445,19 +437,20 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
/**
* _dpu_plane_set_qos_remap - set vbif QoS for the given plane
* @plane: Pointer to drm plane
+ * @pipe: Pointer to software pipe
*/
-static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
+static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_vbif_set_qos_params qos_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = VBIF_RT;
- qos_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl;
- qos_params.xin_id = pstate->pipe.sspp->cap->xin_id;
- qos_params.num = pstate->pipe.sspp->idx - SSPP_VIG0;
+ qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl;
+ qos_params.xin_id = pipe->sspp->cap->xin_id;
+ qos_params.num = pipe->sspp->idx - SSPP_VIG0;
qos_params.is_rt = pdpu->is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
@@ -1136,7 +1129,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
pdpu->is_rt_pipe = is_rt_pipe;
- _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
@@ -1195,20 +1188,20 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
}
- _dpu_plane_set_qos_lut(plane, fb, &pstate->pipe_cfg);
- _dpu_plane_set_danger_lut(plane, fb);
+ _dpu_plane_set_qos_lut(plane, pipe, fmt, &pstate->pipe_cfg);
+ _dpu_plane_set_danger_lut(plane, pipe, fmt);
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
- _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
- _dpu_plane_set_ot_limit(plane, crtc, &pstate->pipe_cfg);
+ _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_ot_limit(plane, pipe, crtc, &pstate->pipe_cfg);
}
if (pstate->needs_qos_remap) {
pstate->needs_qos_remap = false;
- _dpu_plane_set_qos_remap(plane);
+ _dpu_plane_set_qos_remap(plane, pipe);
}
- _dpu_plane_calc_bw(plane, fb, &pstate->pipe_cfg);
+ _dpu_plane_calc_bw(plane, fmt, &pstate->pipe_cfg);
_dpu_plane_calc_clk(plane, &pstate->pipe_cfg);
}
@@ -1245,11 +1238,13 @@ static void dpu_plane_atomic_update(struct drm_plane *plane,
static void dpu_plane_destroy(struct drm_plane *plane)
{
struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
+ struct dpu_plane_state *pstate;
DPU_DEBUG_PLANE(pdpu, "\n");
if (pdpu) {
- _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
+ pstate = to_dpu_plane_state(plane->state);
+ _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
mutex_destroy(&pdpu->lock);
@@ -1373,13 +1368,14 @@ static void dpu_plane_reset(struct drm_plane *plane)
void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
if (!pdpu->is_rt_pipe)
return;
pm_runtime_get_sync(&dpu_kms->pdev->dev);
- _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
}
#endif
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 19/27] drm/msm/dpu: rewrite plane's QoS-related functions to take dpu_sw_pipe and dpu_format
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Rewrite dpu_plane's QoS related functions to take struct dpu_sw_pipe and
struct dpu_format as arguments rather than fetching them from the
pstate or drm_framebuffer.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 98 +++++++++++------------
1 file changed, 47 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index a2c891034512..7fc2c767c6d1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -128,19 +128,18 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
/**
* _dpu_plane_calc_bw - calculate bandwidth required for a plane
* @plane: Pointer to drm plane.
- * @fb: Pointer to framebuffer associated with the given plane
+ * @fmt: Pointer to source buffer format
* @pipe_cfg: Pointer to pipe configuration
* Result: Updates calculated bandwidth in the plane state.
* BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
* Prefill BW Equation: line src bytes * line_time
*/
static void _dpu_plane_calc_bw(struct drm_plane *plane,
- struct drm_framebuffer *fb,
+ const struct dpu_format *fmt,
struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane_state *pstate;
struct drm_display_mode *mode;
- const struct dpu_format *fmt = NULL;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
int src_width, src_height, dst_height, fps;
u64 plane_prefill_bw;
@@ -152,8 +151,6 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
pstate = to_dpu_plane_state(plane->state);
mode = &plane->state->crtc->mode;
- fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
-
src_width = drm_rect_width(&pipe_cfg->src_rect);
src_height = drm_rect_height(&pipe_cfg->src_rect);
dst_height = drm_rect_height(&pipe_cfg->dst_rect);
@@ -217,25 +214,25 @@ static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg
/**
* _dpu_plane_calc_fill_level - calculate fill level of the given source format
* @plane: Pointer to drm plane
+ * @pipe: Pointer to software pipe
* @fmt: Pointer to source buffer format
* @src_width: width of source buffer
* Return: fill level corresponding to the source buffer/format or 0 if error
*/
static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, u32 src_width)
{
struct dpu_plane *pdpu;
- struct dpu_plane_state *pstate;
u32 fixed_buff_size;
u32 total_fl;
- if (!fmt || !plane->state || !src_width || !fmt->bpp) {
+ if (!fmt || !pipe || !src_width || !fmt->bpp) {
DPU_ERROR("invalid arguments\n");
return 0;
}
pdpu = to_dpu_plane(plane);
- pstate = to_dpu_plane_state(plane->state);
fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
/* FIXME: in multirect case account for the src_width of all the planes */
@@ -251,7 +248,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
((src_width + 32) * fmt->bpp);
}
} else {
- if (pstate->pipe.multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
+ if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
total_fl = (fixed_buff_size / 2) * 2 /
((src_width + 32) * fmt->bpp);
} else {
@@ -261,7 +258,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
}
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
- pdpu->pipe - SSPP_VIG0,
+ pipe->sspp->idx - SSPP_VIG0,
(char *)&fmt->base.pixel_format,
src_width, total_fl);
@@ -271,25 +268,22 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
/**
* _dpu_plane_set_qos_lut - set QoS LUT of the given plane
* @plane: Pointer to drm plane
- * @fb: Pointer to framebuffer associated with the given plane
+ * @pipe: Pointer to software pipe
+ * @fmt: Pointer to source buffer format
* @pipe_cfg: Pointer to pipe configuration
*/
static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
- struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
+ struct dpu_sw_pipe *pipe,
+ const struct dpu_format *fmt, struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
- const struct dpu_format *fmt = NULL;
u64 qos_lut;
u32 total_fl = 0, lut_usage;
if (!pdpu->is_rt_pipe) {
lut_usage = DPU_QOS_LUT_USAGE_NRT;
} else {
- fmt = dpu_get_dpu_format_ext(
- fb->format->format,
- fb->modifier);
- total_fl = _dpu_plane_calc_fill_level(plane, fmt,
+ total_fl = _dpu_plane_calc_fill_level(plane, pipe, fmt,
drm_rect_width(&pipe_cfg->src_rect));
if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
@@ -301,7 +295,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
qos_lut = _dpu_hw_get_qos_lut(
&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
- trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
+ trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
(fmt) ? fmt->base.pixel_format : 0,
pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
@@ -310,20 +304,20 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
fmt ? (char *)&fmt->base.pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, qos_lut);
- pstate->pipe.sspp->ops.setup_creq_lut(pstate->pipe.sspp, qos_lut);
+ pipe->sspp->ops.setup_creq_lut(pipe->sspp, qos_lut);
}
/**
* _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane
* @plane: Pointer to drm plane
- * @fb: Pointer to framebuffer associated with the given plane
+ * @pipe: Pointer to software pipe
+ * @fmt: Pointer to source buffer format
*/
static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
- struct drm_framebuffer *fb)
+ struct dpu_sw_pipe *pipe,
+ const struct dpu_format *fmt)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
- const struct dpu_format *fmt = NULL;
u32 danger_lut, safe_lut;
if (!pdpu->is_rt_pipe) {
@@ -332,10 +326,6 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
safe_lut = pdpu->catalog->perf->safe_lut_tbl
[DPU_QOS_LUT_USAGE_NRT];
} else {
- fmt = dpu_get_dpu_format_ext(
- fb->format->format,
- fb->modifier);
-
if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
danger_lut = pdpu->catalog->perf->danger_lut_tbl
[DPU_QOS_LUT_USAGE_LINEAR];
@@ -362,29 +352,30 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
danger_lut,
safe_lut);
- pstate->pipe.sspp->ops.setup_danger_safe_lut(pstate->pipe.sspp,
+ pipe->sspp->ops.setup_danger_safe_lut(pipe->sspp,
danger_lut, safe_lut);
}
/**
* _dpu_plane_set_qos_ctrl - set QoS control of the given plane
* @plane: Pointer to drm plane
+ * @pipe: Pointer to software pipe
* @enable: true to enable QoS control
* @flags: QoS control mode (enum dpu_plane_qos)
*/
static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe,
bool enable, u32 flags)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
- pipe_qos_cfg.creq_vblank = pstate->pipe.sspp->cap->sblk->creq_vblank;
+ pipe_qos_cfg.creq_vblank = pipe->sspp->cap->sblk->creq_vblank;
pipe_qos_cfg.danger_vblank =
- pstate->pipe.sspp->cap->sblk->danger_vblank;
+ pipe->sspp->cap->sblk->danger_vblank;
pipe_qos_cfg.vblank_en = enable;
}
@@ -410,33 +401,34 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
pipe_qos_cfg.danger_vblank,
pdpu->is_rt_pipe);
- pstate->pipe.sspp->ops.setup_qos_ctrl(pstate->pipe.sspp,
+ pipe->sspp->ops.setup_qos_ctrl(pipe->sspp,
&pipe_qos_cfg);
}
/**
* _dpu_plane_set_ot_limit - set OT limit for the given plane
* @plane: Pointer to drm plane
+ * @pipe: Pointer to software pipe
* @crtc: Pointer to drm crtc
* @pipe_cfg: Pointer to pipe configuration
*/
static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe,
struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_vbif_set_ot_params ot_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&ot_params, 0, sizeof(ot_params));
- ot_params.xin_id = pstate->pipe.sspp->cap->xin_id;
- ot_params.num = pstate->pipe.sspp->idx - SSPP_NONE;
+ ot_params.xin_id = pipe->sspp->cap->xin_id;
+ ot_params.num = pipe->sspp->idx - SSPP_NONE;
ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
ot_params.is_wfd = !pdpu->is_rt_pipe;
ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
ot_params.vbif_idx = VBIF_RT;
- ot_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl;
+ ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl;
ot_params.rd = true;
dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
@@ -445,19 +437,20 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
/**
* _dpu_plane_set_qos_remap - set vbif QoS for the given plane
* @plane: Pointer to drm plane
+ * @pipe: Pointer to software pipe
*/
-static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
+static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_vbif_set_qos_params qos_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = VBIF_RT;
- qos_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl;
- qos_params.xin_id = pstate->pipe.sspp->cap->xin_id;
- qos_params.num = pstate->pipe.sspp->idx - SSPP_VIG0;
+ qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl;
+ qos_params.xin_id = pipe->sspp->cap->xin_id;
+ qos_params.num = pipe->sspp->idx - SSPP_VIG0;
qos_params.is_rt = pdpu->is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
@@ -1136,7 +1129,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
pdpu->is_rt_pipe = is_rt_pipe;
- _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
@@ -1195,20 +1188,20 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
}
- _dpu_plane_set_qos_lut(plane, fb, &pstate->pipe_cfg);
- _dpu_plane_set_danger_lut(plane, fb);
+ _dpu_plane_set_qos_lut(plane, pipe, fmt, &pstate->pipe_cfg);
+ _dpu_plane_set_danger_lut(plane, pipe, fmt);
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
- _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
- _dpu_plane_set_ot_limit(plane, crtc, &pstate->pipe_cfg);
+ _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_ot_limit(plane, pipe, crtc, &pstate->pipe_cfg);
}
if (pstate->needs_qos_remap) {
pstate->needs_qos_remap = false;
- _dpu_plane_set_qos_remap(plane);
+ _dpu_plane_set_qos_remap(plane, pipe);
}
- _dpu_plane_calc_bw(plane, fb, &pstate->pipe_cfg);
+ _dpu_plane_calc_bw(plane, fmt, &pstate->pipe_cfg);
_dpu_plane_calc_clk(plane, &pstate->pipe_cfg);
}
@@ -1245,11 +1238,13 @@ static void dpu_plane_atomic_update(struct drm_plane *plane,
static void dpu_plane_destroy(struct drm_plane *plane)
{
struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
+ struct dpu_plane_state *pstate;
DPU_DEBUG_PLANE(pdpu, "\n");
if (pdpu) {
- _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
+ pstate = to_dpu_plane_state(plane->state);
+ _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
mutex_destroy(&pdpu->lock);
@@ -1373,13 +1368,14 @@ static void dpu_plane_reset(struct drm_plane *plane)
void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
if (!pdpu->is_rt_pipe)
return;
pm_runtime_get_sync(&dpu_kms->pdev->dev);
- _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
}
#endif
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 20/27] drm/msm/dpu: populate SmartDMA features in hw catalog
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Downstream driver uses dpu->caps->smart_dma_rev to update
sspp->cap->features with the bit corresponding to the supported SmartDMA
version. Upstream driver does not do this, resulting in SSPP subdriver
not enbaling setup_multirect callback. Add corresponding SmartDMA SSPP
feature bits to dpu hw catalog.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2196e205efa5..61e95fb21403 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -21,13 +21,16 @@
(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
#define VIG_SDM845_MASK \
- (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3) |\
+ BIT(DPU_SSPP_SMART_DMA_V2))
#define VIG_SC7180_MASK \
- (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4) |\
+ BIT(DPU_SSPP_SMART_DMA_V2))
#define VIG_SM8250_MASK \
- (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE) |\
+ BIT(DPU_SSPP_SMART_DMA_V2))
#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
@@ -42,6 +45,7 @@
#define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
+ BIT(DPU_SSPP_SMART_DMA_V2) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
#define DMA_CURSOR_SDM845_MASK \
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 20/27] drm/msm/dpu: populate SmartDMA features in hw catalog
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Downstream driver uses dpu->caps->smart_dma_rev to update
sspp->cap->features with the bit corresponding to the supported SmartDMA
version. Upstream driver does not do this, resulting in SSPP subdriver
not enbaling setup_multirect callback. Add corresponding SmartDMA SSPP
feature bits to dpu hw catalog.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2196e205efa5..61e95fb21403 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -21,13 +21,16 @@
(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
#define VIG_SDM845_MASK \
- (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3) |\
+ BIT(DPU_SSPP_SMART_DMA_V2))
#define VIG_SC7180_MASK \
- (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4) |\
+ BIT(DPU_SSPP_SMART_DMA_V2))
#define VIG_SM8250_MASK \
- (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE) |\
+ BIT(DPU_SSPP_SMART_DMA_V2))
#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
@@ -42,6 +45,7 @@
#define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
+ BIT(DPU_SSPP_SMART_DMA_V2) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
#define DMA_CURSOR_SDM845_MASK \
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 21/27] drm/msm/dpu: make _dpu_plane_calc_clk accept mode directly
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Rework bandwidth/clock calculation functions to use mode directly rather
than fetching it through the plane data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 39 ++++++++++-------------
1 file changed, 17 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 7fc2c767c6d1..3d0c5a36a7dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -127,20 +127,19 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
/**
* _dpu_plane_calc_bw - calculate bandwidth required for a plane
- * @plane: Pointer to drm plane.
+ * @catalog: Points to dpu catalog structure
* @fmt: Pointer to source buffer format
+ * @mode: Pointer to drm display mode
* @pipe_cfg: Pointer to pipe configuration
* Result: Updates calculated bandwidth in the plane state.
* BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
* Prefill BW Equation: line src bytes * line_time
*/
-static void _dpu_plane_calc_bw(struct drm_plane *plane,
+static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
const struct dpu_format *fmt,
+ const struct drm_display_mode *mode,
struct dpu_hw_pipe_cfg *pipe_cfg)
{
- struct dpu_plane_state *pstate;
- struct drm_display_mode *mode;
- struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
int src_width, src_height, dst_height, fps;
u64 plane_prefill_bw;
u64 plane_bw;
@@ -148,9 +147,6 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
u64 scale_factor;
int vbp, vpw, vfp;
- pstate = to_dpu_plane_state(plane->state);
- mode = &plane->state->crtc->mode;
-
src_width = drm_rect_width(&pipe_cfg->src_rect);
src_height = drm_rect_height(&pipe_cfg->src_rect);
dst_height = drm_rect_height(&pipe_cfg->dst_rect);
@@ -158,7 +154,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
vbp = mode->vtotal - mode->vsync_end;
vpw = mode->vsync_end - mode->vsync_start;
vfp = mode->vsync_start - mode->vdisplay;
- hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines;
+ hw_latency_lines = catalog->perf->min_prefill_lines;
scale_factor = src_height > dst_height ?
mult_frac(src_height, 1, dst_height) : 1;
@@ -178,37 +174,36 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
do_div(plane_prefill_bw, hw_latency_lines);
- pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
+ return max(plane_bw, plane_prefill_bw);
}
/**
* _dpu_plane_calc_clk - calculate clock required for a plane
- * @plane: Pointer to drm plane.
+ * @mode: Pointer to drm display mode
* @pipe_cfg: Pointer to pipe configuration
* Result: Updates calculated clock in the plane state.
* Clock equation: dst_w * v_total * fps * (src_h / dst_h)
*/
-static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg)
+static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode,
+ struct dpu_hw_pipe_cfg *pipe_cfg)
{
- struct dpu_plane_state *pstate;
- struct drm_display_mode *mode;
int dst_width, src_height, dst_height, fps;
-
- pstate = to_dpu_plane_state(plane->state);
- mode = &plane->state->crtc->mode;
+ u64 plane_clk;
src_height = drm_rect_height(&pipe_cfg->src_rect);
dst_width = drm_rect_width(&pipe_cfg->dst_rect);
dst_height = drm_rect_height(&pipe_cfg->dst_rect);
fps = drm_mode_vrefresh(mode);
- pstate->plane_clk =
+ plane_clk =
dst_width * mode->vtotal * fps;
if (src_height > dst_height) {
- pstate->plane_clk *= src_height;
- do_div(pstate->plane_clk, dst_height);
+ plane_clk *= src_height;
+ do_div(plane_clk, dst_height);
}
+
+ return plane_clk;
}
/**
@@ -1201,9 +1196,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
_dpu_plane_set_qos_remap(plane, pipe);
}
- _dpu_plane_calc_bw(plane, fmt, &pstate->pipe_cfg);
+ pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, &pstate->pipe_cfg);
- _dpu_plane_calc_clk(plane, &pstate->pipe_cfg);
+ pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pstate->pipe_cfg);
}
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 21/27] drm/msm/dpu: make _dpu_plane_calc_clk accept mode directly
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Rework bandwidth/clock calculation functions to use mode directly rather
than fetching it through the plane data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 39 ++++++++++-------------
1 file changed, 17 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 7fc2c767c6d1..3d0c5a36a7dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -127,20 +127,19 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
/**
* _dpu_plane_calc_bw - calculate bandwidth required for a plane
- * @plane: Pointer to drm plane.
+ * @catalog: Points to dpu catalog structure
* @fmt: Pointer to source buffer format
+ * @mode: Pointer to drm display mode
* @pipe_cfg: Pointer to pipe configuration
* Result: Updates calculated bandwidth in the plane state.
* BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
* Prefill BW Equation: line src bytes * line_time
*/
-static void _dpu_plane_calc_bw(struct drm_plane *plane,
+static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
const struct dpu_format *fmt,
+ const struct drm_display_mode *mode,
struct dpu_hw_pipe_cfg *pipe_cfg)
{
- struct dpu_plane_state *pstate;
- struct drm_display_mode *mode;
- struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
int src_width, src_height, dst_height, fps;
u64 plane_prefill_bw;
u64 plane_bw;
@@ -148,9 +147,6 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
u64 scale_factor;
int vbp, vpw, vfp;
- pstate = to_dpu_plane_state(plane->state);
- mode = &plane->state->crtc->mode;
-
src_width = drm_rect_width(&pipe_cfg->src_rect);
src_height = drm_rect_height(&pipe_cfg->src_rect);
dst_height = drm_rect_height(&pipe_cfg->dst_rect);
@@ -158,7 +154,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
vbp = mode->vtotal - mode->vsync_end;
vpw = mode->vsync_end - mode->vsync_start;
vfp = mode->vsync_start - mode->vdisplay;
- hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines;
+ hw_latency_lines = catalog->perf->min_prefill_lines;
scale_factor = src_height > dst_height ?
mult_frac(src_height, 1, dst_height) : 1;
@@ -178,37 +174,36 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
do_div(plane_prefill_bw, hw_latency_lines);
- pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
+ return max(plane_bw, plane_prefill_bw);
}
/**
* _dpu_plane_calc_clk - calculate clock required for a plane
- * @plane: Pointer to drm plane.
+ * @mode: Pointer to drm display mode
* @pipe_cfg: Pointer to pipe configuration
* Result: Updates calculated clock in the plane state.
* Clock equation: dst_w * v_total * fps * (src_h / dst_h)
*/
-static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg)
+static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode,
+ struct dpu_hw_pipe_cfg *pipe_cfg)
{
- struct dpu_plane_state *pstate;
- struct drm_display_mode *mode;
int dst_width, src_height, dst_height, fps;
-
- pstate = to_dpu_plane_state(plane->state);
- mode = &plane->state->crtc->mode;
+ u64 plane_clk;
src_height = drm_rect_height(&pipe_cfg->src_rect);
dst_width = drm_rect_width(&pipe_cfg->dst_rect);
dst_height = drm_rect_height(&pipe_cfg->dst_rect);
fps = drm_mode_vrefresh(mode);
- pstate->plane_clk =
+ plane_clk =
dst_width * mode->vtotal * fps;
if (src_height > dst_height) {
- pstate->plane_clk *= src_height;
- do_div(pstate->plane_clk, dst_height);
+ plane_clk *= src_height;
+ do_div(plane_clk, dst_height);
}
+
+ return plane_clk;
}
/**
@@ -1201,9 +1196,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
_dpu_plane_set_qos_remap(plane, pipe);
}
- _dpu_plane_calc_bw(plane, fmt, &pstate->pipe_cfg);
+ pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, &pstate->pipe_cfg);
- _dpu_plane_calc_clk(plane, &pstate->pipe_cfg);
+ pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pstate->pipe_cfg);
}
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 22/27] drm/msm/dpu: rework dpu_plane_sspp_atomic_update()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Split pipe-dependent code from dpu_plane_sspp_atomic_update() into the
separate function dpu_plane_sspp_update_pipe(). This is one of
preparational steps to add r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 113 ++++++++++++----------
1 file changed, 63 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 3d0c5a36a7dc..b80c5adf91d2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -404,12 +404,13 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
* _dpu_plane_set_ot_limit - set OT limit for the given plane
* @plane: Pointer to drm plane
* @pipe: Pointer to software pipe
- * @crtc: Pointer to drm crtc
* @pipe_cfg: Pointer to pipe configuration
+ * @frame_rate: CRTC's frame rate
*/
static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
- struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
+ struct dpu_hw_pipe_cfg *pipe_cfg,
+ int frame_rate)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_vbif_set_ot_params ot_params;
@@ -421,7 +422,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
ot_params.is_wfd = !pdpu->is_rt_pipe;
- ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
+ ot_params.frame_rate = frame_rate;
ot_params.vbif_idx = VBIF_RT;
ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl;
ot_params.rd = true;
@@ -457,26 +458,6 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
}
-static void _dpu_plane_set_scanout(struct drm_plane *plane,
- struct dpu_plane_state *pstate,
- struct drm_framebuffer *fb)
-{
- struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
- struct msm_gem_address_space *aspace = kms->base.aspace;
- struct dpu_hw_fmt_layout layout;
- int ret;
-
- ret = dpu_format_populate_layout(aspace, fb, &layout);
- if (ret)
- DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
- else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(&pstate->pipe,
- &layout);
- pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
- }
-}
-
static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
@@ -1102,35 +1083,25 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error)
pdpu->is_error = error;
}
-static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
+static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *pipe_cfg,
+ const struct dpu_format *fmt,
+ int frame_rate,
+ struct dpu_hw_fmt_layout *layout)
{
uint32_t src_flags;
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct drm_plane_state *state = plane->state;
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
- struct dpu_sw_pipe *pipe = &pstate->pipe;
- struct drm_crtc *crtc = state->crtc;
- struct drm_framebuffer *fb = state->fb;
- bool is_rt_pipe;
- const struct dpu_format *fmt =
- to_dpu_format(msm_framebuffer_format(fb));
- struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
- _dpu_plane_set_scanout(plane, pstate, fb);
-
- pstate->pending = true;
-
- is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
- pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
- pdpu->is_rt_pipe = is_rt_pipe;
+ if (layout && pipe->sspp->ops.setup_sourceaddress) {
+ trace_dpu_plane_set_scanout(pipe, layout);
+ pipe->sspp->ops.setup_sourceaddress(pipe, layout);
+ }
_dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
- DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
- ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
- crtc->base.id, DRM_RECT_ARG(&state->dst),
- (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
-
/* override for color fill */
if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
/* skip remaining processing on color fill */
@@ -1183,22 +1154,64 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
}
- _dpu_plane_set_qos_lut(plane, pipe, fmt, &pstate->pipe_cfg);
+ _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg);
_dpu_plane_set_danger_lut(plane, pipe, fmt);
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
_dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL);
- _dpu_plane_set_ot_limit(plane, pipe, crtc, &pstate->pipe_cfg);
+ _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate);
}
- if (pstate->needs_qos_remap) {
- pstate->needs_qos_remap = false;
+ if (pstate->needs_qos_remap)
_dpu_plane_set_qos_remap(plane, pipe);
- }
+}
+
+static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
+{
+ struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct drm_plane_state *state = plane->state;
+ struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ struct dpu_sw_pipe *pipe = &pstate->pipe;
+ struct drm_crtc *crtc = state->crtc;
+ struct drm_framebuffer *fb = state->fb;
+ bool is_rt_pipe;
+ const struct dpu_format *fmt =
+ to_dpu_format(msm_framebuffer_format(fb));
+ struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+
+ struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
+ struct msm_gem_address_space *aspace = kms->base.aspace;
+ struct dpu_hw_fmt_layout layout;
+ bool layout_valid = false;
+ int ret;
+
+ ret = dpu_format_populate_layout(aspace, fb, &layout);
+ if (ret)
+ DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
+ else
+ layout_valid = true;
+
+ pstate->pending = true;
+
+ is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
+ pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
+ pdpu->is_rt_pipe = is_rt_pipe;
+
+ DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
+ ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
+ crtc->base.id, DRM_RECT_ARG(&state->dst),
+ (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
+
+ dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
+ drm_mode_vrefresh(&crtc->mode),
+ layout_valid ? &layout: NULL);
+
+ if (pstate->needs_qos_remap)
+ pstate->needs_qos_remap = false;
- pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, &pstate->pipe_cfg);
+ pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, pipe_cfg);
- pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pstate->pipe_cfg);
+ pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
}
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 22/27] drm/msm/dpu: rework dpu_plane_sspp_atomic_update()
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Split pipe-dependent code from dpu_plane_sspp_atomic_update() into the
separate function dpu_plane_sspp_update_pipe(). This is one of
preparational steps to add r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 113 ++++++++++++----------
1 file changed, 63 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 3d0c5a36a7dc..b80c5adf91d2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -404,12 +404,13 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
* _dpu_plane_set_ot_limit - set OT limit for the given plane
* @plane: Pointer to drm plane
* @pipe: Pointer to software pipe
- * @crtc: Pointer to drm crtc
* @pipe_cfg: Pointer to pipe configuration
+ * @frame_rate: CRTC's frame rate
*/
static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
- struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
+ struct dpu_hw_pipe_cfg *pipe_cfg,
+ int frame_rate)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_vbif_set_ot_params ot_params;
@@ -421,7 +422,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
ot_params.is_wfd = !pdpu->is_rt_pipe;
- ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
+ ot_params.frame_rate = frame_rate;
ot_params.vbif_idx = VBIF_RT;
ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl;
ot_params.rd = true;
@@ -457,26 +458,6 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
}
-static void _dpu_plane_set_scanout(struct drm_plane *plane,
- struct dpu_plane_state *pstate,
- struct drm_framebuffer *fb)
-{
- struct dpu_plane *pdpu = to_dpu_plane(plane);
- struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
- struct msm_gem_address_space *aspace = kms->base.aspace;
- struct dpu_hw_fmt_layout layout;
- int ret;
-
- ret = dpu_format_populate_layout(aspace, fb, &layout);
- if (ret)
- DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
- else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(&pstate->pipe,
- &layout);
- pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout);
- }
-}
-
static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
@@ -1102,35 +1083,25 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error)
pdpu->is_error = error;
}
-static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
+static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
+ struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *pipe_cfg,
+ const struct dpu_format *fmt,
+ int frame_rate,
+ struct dpu_hw_fmt_layout *layout)
{
uint32_t src_flags;
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct drm_plane_state *state = plane->state;
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
- struct dpu_sw_pipe *pipe = &pstate->pipe;
- struct drm_crtc *crtc = state->crtc;
- struct drm_framebuffer *fb = state->fb;
- bool is_rt_pipe;
- const struct dpu_format *fmt =
- to_dpu_format(msm_framebuffer_format(fb));
- struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
- _dpu_plane_set_scanout(plane, pstate, fb);
-
- pstate->pending = true;
-
- is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
- pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
- pdpu->is_rt_pipe = is_rt_pipe;
+ if (layout && pipe->sspp->ops.setup_sourceaddress) {
+ trace_dpu_plane_set_scanout(pipe, layout);
+ pipe->sspp->ops.setup_sourceaddress(pipe, layout);
+ }
_dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
- DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
- ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
- crtc->base.id, DRM_RECT_ARG(&state->dst),
- (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
-
/* override for color fill */
if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
/* skip remaining processing on color fill */
@@ -1183,22 +1154,64 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
}
- _dpu_plane_set_qos_lut(plane, pipe, fmt, &pstate->pipe_cfg);
+ _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg);
_dpu_plane_set_danger_lut(plane, pipe, fmt);
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
_dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL);
- _dpu_plane_set_ot_limit(plane, pipe, crtc, &pstate->pipe_cfg);
+ _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate);
}
- if (pstate->needs_qos_remap) {
- pstate->needs_qos_remap = false;
+ if (pstate->needs_qos_remap)
_dpu_plane_set_qos_remap(plane, pipe);
- }
+}
+
+static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
+{
+ struct dpu_plane *pdpu = to_dpu_plane(plane);
+ struct drm_plane_state *state = plane->state;
+ struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ struct dpu_sw_pipe *pipe = &pstate->pipe;
+ struct drm_crtc *crtc = state->crtc;
+ struct drm_framebuffer *fb = state->fb;
+ bool is_rt_pipe;
+ const struct dpu_format *fmt =
+ to_dpu_format(msm_framebuffer_format(fb));
+ struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+
+ struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
+ struct msm_gem_address_space *aspace = kms->base.aspace;
+ struct dpu_hw_fmt_layout layout;
+ bool layout_valid = false;
+ int ret;
+
+ ret = dpu_format_populate_layout(aspace, fb, &layout);
+ if (ret)
+ DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
+ else
+ layout_valid = true;
+
+ pstate->pending = true;
+
+ is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
+ pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
+ pdpu->is_rt_pipe = is_rt_pipe;
+
+ DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
+ ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
+ crtc->base.id, DRM_RECT_ARG(&state->dst),
+ (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
+
+ dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
+ drm_mode_vrefresh(&crtc->mode),
+ layout_valid ? &layout: NULL);
+
+ if (pstate->needs_qos_remap)
+ pstate->needs_qos_remap = false;
- pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, &pstate->pipe_cfg);
+ pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, pipe_cfg);
- pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pstate->pipe_cfg);
+ pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
}
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 23/27] drm/msm/dpu: rework dpu_plane_atomic_check()
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Split pipe-dependent code from dpu_plane_atomic_check() into the
separate function dpu_plane_atomic_check_pipe(). This is one of
preparational steps to add r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 91 +++++++++++++----------
1 file changed, 53 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index b80c5adf91d2..c20e0d9fe0ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -903,6 +903,55 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
return 0;
}
+static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
+ struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *pipe_cfg,
+ uint32_t max_linewidth,
+ const struct dpu_format *fmt)
+{
+ uint32_t min_src_size;
+
+ min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
+
+ if (DPU_FORMAT_IS_YUV(fmt) &&
+ (!(pipe->sspp->cap->features & DPU_SSPP_SCALER) ||
+ !(pipe->sspp->cap->features & DPU_SSPP_CSC_ANY))) {
+ DPU_DEBUG_PLANE(pdpu,
+ "plane doesn't have scaler/csc for yuv\n");
+ return -EINVAL;
+
+ /* check src bounds */
+ } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size ||
+ drm_rect_height(&pipe_cfg->src_rect) < min_src_size) {
+ DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect));
+ return -E2BIG;
+
+ /* valid yuv image */
+ } else if (DPU_FORMAT_IS_YUV(fmt) &&
+ (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 ||
+ drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
+ drm_rect_height(&pipe_cfg->src_rect) & 0x1)) {
+ DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect));
+ return -EINVAL;
+
+ /* min dst support */
+ } else if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || drm_rect_height(&pipe_cfg->dst_rect) < 0x1) {
+ DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
+ DRM_RECT_ARG(&pipe_cfg->dst_rect));
+ return -EINVAL;
+
+ /* check decimated source width */
+ } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
+ DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
+ return -E2BIG;
+ }
+
+ return 0;
+}
+
static int dpu_plane_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
@@ -915,7 +964,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
const struct dpu_format *fmt;
struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct drm_rect fb_rect = { 0 };
- uint32_t min_src_size, max_linewidth;
+ uint32_t max_linewidth;
unsigned int rotation;
uint32_t supported_rotations;
const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap;
@@ -972,43 +1021,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
- min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
-
- if (DPU_FORMAT_IS_YUV(fmt) &&
- (!(pipe_hw_caps->features & DPU_SSPP_SCALER) ||
- !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) {
- DPU_DEBUG_PLANE(pdpu,
- "plane doesn't have scaler/csc for yuv\n");
- return -EINVAL;
-
- /* check src bounds */
- } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size ||
- drm_rect_height(&pipe_cfg->src_rect) < min_src_size) {
- DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect));
- return -E2BIG;
-
- /* valid yuv image */
- } else if (DPU_FORMAT_IS_YUV(fmt) &&
- (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 ||
- drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
- drm_rect_height(&pipe_cfg->src_rect) & 0x1)) {
- DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect));
- return -EINVAL;
-
- /* min dst support */
- } else if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || drm_rect_height(&pipe_cfg->dst_rect) < 0x1) {
- DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&pipe_cfg->dst_rect));
- return -EINVAL;
-
- /* check decimated source width */
- } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
- DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
- return -E2BIG;
- }
+ ret = dpu_plane_atomic_check_pipe(pdpu, &pstate->pipe, pipe_cfg, max_linewidth, fmt);
+ if (ret)
+ return ret;
supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 23/27] drm/msm/dpu: rework dpu_plane_atomic_check()
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Split pipe-dependent code from dpu_plane_atomic_check() into the
separate function dpu_plane_atomic_check_pipe(). This is one of
preparational steps to add r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 91 +++++++++++++----------
1 file changed, 53 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index b80c5adf91d2..c20e0d9fe0ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -903,6 +903,55 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
return 0;
}
+static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
+ struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *pipe_cfg,
+ uint32_t max_linewidth,
+ const struct dpu_format *fmt)
+{
+ uint32_t min_src_size;
+
+ min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
+
+ if (DPU_FORMAT_IS_YUV(fmt) &&
+ (!(pipe->sspp->cap->features & DPU_SSPP_SCALER) ||
+ !(pipe->sspp->cap->features & DPU_SSPP_CSC_ANY))) {
+ DPU_DEBUG_PLANE(pdpu,
+ "plane doesn't have scaler/csc for yuv\n");
+ return -EINVAL;
+
+ /* check src bounds */
+ } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size ||
+ drm_rect_height(&pipe_cfg->src_rect) < min_src_size) {
+ DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect));
+ return -E2BIG;
+
+ /* valid yuv image */
+ } else if (DPU_FORMAT_IS_YUV(fmt) &&
+ (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 ||
+ drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
+ drm_rect_height(&pipe_cfg->src_rect) & 0x1)) {
+ DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect));
+ return -EINVAL;
+
+ /* min dst support */
+ } else if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || drm_rect_height(&pipe_cfg->dst_rect) < 0x1) {
+ DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
+ DRM_RECT_ARG(&pipe_cfg->dst_rect));
+ return -EINVAL;
+
+ /* check decimated source width */
+ } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
+ DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
+ return -E2BIG;
+ }
+
+ return 0;
+}
+
static int dpu_plane_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
@@ -915,7 +964,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
const struct dpu_format *fmt;
struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct drm_rect fb_rect = { 0 };
- uint32_t min_src_size, max_linewidth;
+ uint32_t max_linewidth;
unsigned int rotation;
uint32_t supported_rotations;
const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap;
@@ -972,43 +1021,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
- min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
-
- if (DPU_FORMAT_IS_YUV(fmt) &&
- (!(pipe_hw_caps->features & DPU_SSPP_SCALER) ||
- !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) {
- DPU_DEBUG_PLANE(pdpu,
- "plane doesn't have scaler/csc for yuv\n");
- return -EINVAL;
-
- /* check src bounds */
- } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size ||
- drm_rect_height(&pipe_cfg->src_rect) < min_src_size) {
- DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect));
- return -E2BIG;
-
- /* valid yuv image */
- } else if (DPU_FORMAT_IS_YUV(fmt) &&
- (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 ||
- drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
- drm_rect_height(&pipe_cfg->src_rect) & 0x1)) {
- DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect));
- return -EINVAL;
-
- /* min dst support */
- } else if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || drm_rect_height(&pipe_cfg->dst_rect) < 0x1) {
- DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
- DRM_RECT_ARG(&pipe_cfg->dst_rect));
- return -EINVAL;
-
- /* check decimated source width */
- } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
- DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
- return -E2BIG;
- }
+ ret = dpu_plane_atomic_check_pipe(pdpu, &pstate->pipe, pipe_cfg, max_linewidth, fmt);
+ if (ret)
+ return ret;
supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 24/27] drm/msm/dpu: rework plane CSC setting
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Rework the code flushing CSC settings for the plane. Separate out the
pipe and pipe_cfg as a preparation for r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 45 +++++++++++++----------
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index c20e0d9fe0ca..fa59ae007de1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -576,29 +576,18 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
};
-static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
+static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, const struct dpu_format *fmt)
{
- struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state);
const struct dpu_csc_cfg *csc_ptr;
- if (!pdpu) {
- DPU_ERROR("invalid plane\n");
- return NULL;
- }
-
if (!DPU_FORMAT_IS_YUV(fmt))
return NULL;
- if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe.sspp->cap->features)
+ if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
csc_ptr = &dpu_csc10_YUV2RGB_601L;
else
csc_ptr = &dpu_csc_YUV2RGB_601L;
- DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
- csc_ptr->csc_mv[0],
- csc_ptr->csc_mv[1],
- csc_ptr->csc_mv[2]);
-
return csc_ptr;
}
@@ -1046,6 +1035,27 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return 0;
}
+static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
+{
+ const struct dpu_format *format = to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb));
+ const struct dpu_csc_cfg *csc_ptr;
+
+ if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
+ return;
+
+ csc_ptr = _dpu_plane_get_csc(pipe, format);
+ if (!csc_ptr)
+ return;
+
+ DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
+ csc_ptr->csc_mv[0],
+ csc_ptr->csc_mv[1],
+ csc_ptr->csc_mv[2]);
+
+ pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr);
+
+}
+
void dpu_plane_flush(struct drm_plane *plane)
{
struct dpu_plane *pdpu;
@@ -1069,13 +1079,8 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else if (pstate->pipe.sspp && pstate->pipe.sspp->ops.setup_csc) {
- const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
- const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
-
- if (csc_ptr)
- pstate->pipe.sspp->ops.setup_csc(pstate->pipe.sspp, csc_ptr);
- }
+ else
+ dpu_plane_flush_csc(pdpu, &pstate->pipe);
/* flag h/w flush complete */
if (plane->state)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 24/27] drm/msm/dpu: rework plane CSC setting
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Rework the code flushing CSC settings for the plane. Separate out the
pipe and pipe_cfg as a preparation for r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 45 +++++++++++++----------
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index c20e0d9fe0ca..fa59ae007de1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -576,29 +576,18 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
};
-static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
+static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, const struct dpu_format *fmt)
{
- struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state);
const struct dpu_csc_cfg *csc_ptr;
- if (!pdpu) {
- DPU_ERROR("invalid plane\n");
- return NULL;
- }
-
if (!DPU_FORMAT_IS_YUV(fmt))
return NULL;
- if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe.sspp->cap->features)
+ if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
csc_ptr = &dpu_csc10_YUV2RGB_601L;
else
csc_ptr = &dpu_csc_YUV2RGB_601L;
- DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
- csc_ptr->csc_mv[0],
- csc_ptr->csc_mv[1],
- csc_ptr->csc_mv[2]);
-
return csc_ptr;
}
@@ -1046,6 +1035,27 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return 0;
}
+static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
+{
+ const struct dpu_format *format = to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb));
+ const struct dpu_csc_cfg *csc_ptr;
+
+ if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
+ return;
+
+ csc_ptr = _dpu_plane_get_csc(pipe, format);
+ if (!csc_ptr)
+ return;
+
+ DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
+ csc_ptr->csc_mv[0],
+ csc_ptr->csc_mv[1],
+ csc_ptr->csc_mv[2]);
+
+ pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr);
+
+}
+
void dpu_plane_flush(struct drm_plane *plane)
{
struct dpu_plane *pdpu;
@@ -1069,13 +1079,8 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else if (pstate->pipe.sspp && pstate->pipe.sspp->ops.setup_csc) {
- const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
- const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
-
- if (csc_ptr)
- pstate->pipe.sspp->ops.setup_csc(pstate->pipe.sspp, csc_ptr);
- }
+ else
+ dpu_plane_flush_csc(pdpu, &pstate->pipe);
/* flag h/w flush complete */
if (plane->state)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 25/27] drm/msm/dpu: rework static color fill code
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Rework static color fill code to separate the pipe / pipe_cfg handling.
This is a preparation for the r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 70 +++++++++++++----------
1 file changed, 41 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index fa59ae007de1..2851f40cb915 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -639,20 +639,54 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
fmt);
}
+static int _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
+ struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *old_pipe_cfg,
+ u32 fill_color,
+ const struct dpu_format *fmt)
+{
+ struct dpu_hw_pipe_cfg pipe_cfg;
+
+ /* update sspp */
+ if (!pipe->sspp->ops.setup_solidfill)
+ return 0;
+
+ pipe->sspp->ops.setup_solidfill(pipe, fill_color);
+
+ /* override scaler/decimation if solid fill */
+ pipe_cfg.dst_rect = old_pipe_cfg->dst_rect;
+
+ pipe_cfg.src_rect.x1 = 0;
+ pipe_cfg.src_rect.y1 = 0;
+ pipe_cfg.src_rect.x2 =
+ drm_rect_width(&pipe_cfg.dst_rect);
+ pipe_cfg.src_rect.y2 =
+ drm_rect_height(&pipe_cfg.dst_rect);
+
+ if (pipe->sspp->ops.setup_format)
+ pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL);
+
+ if (pipe->sspp->ops.setup_rects)
+ pipe->sspp->ops.setup_rects(pipe, &pipe_cfg);
+
+ _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation);
+
+ return 0;
+}
+
/**
* _dpu_plane_color_fill - enables color fill on plane
* @pdpu: Pointer to DPU plane object
* @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
* @alpha: 8-bit fill alpha value, 255 selects 100% alpha
- * Returns: 0 on success
*/
-static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
+static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
uint32_t color, uint32_t alpha)
{
const struct dpu_format *fmt;
const struct drm_plane *plane = &pdpu->base;
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
- struct dpu_hw_pipe_cfg pipe_cfg;
+ u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
DPU_DEBUG_PLANE(pdpu, "\n");
@@ -661,34 +695,12 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
* h/w only supports RGB variants
*/
fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
+ /* should not happen ever */
+ if (!fmt)
+ return;
/* update sspp */
- if (fmt && pstate->pipe.sspp->ops.setup_solidfill) {
- pstate->pipe.sspp->ops.setup_solidfill(&pstate->pipe,
- (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
-
- /* override scaler/decimation if solid fill */
- pipe_cfg.dst_rect = pstate->base.dst;
-
- pipe_cfg.src_rect.x1 = 0;
- pipe_cfg.src_rect.y1 = 0;
- pipe_cfg.src_rect.x2 =
- drm_rect_width(&pipe_cfg.dst_rect);
- pipe_cfg.src_rect.y2 =
- drm_rect_height(&pipe_cfg.dst_rect);
-
- if (pstate->pipe.sspp->ops.setup_format)
- pstate->pipe.sspp->ops.setup_format(&pstate->pipe,
- fmt, DPU_SSPP_SOLID_FILL);
-
- if (pstate->pipe.sspp->ops.setup_rects)
- pstate->pipe.sspp->ops.setup_rects(&pstate->pipe,
- &pipe_cfg);
-
- _dpu_plane_setup_scaler(&pstate->pipe, fmt, true, &pipe_cfg, pstate->rotation);
- }
-
- return 0;
+ _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg, fill_color, fmt);
}
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 25/27] drm/msm/dpu: rework static color fill code
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Rework static color fill code to separate the pipe / pipe_cfg handling.
This is a preparation for the r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 70 +++++++++++++----------
1 file changed, 41 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index fa59ae007de1..2851f40cb915 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -639,20 +639,54 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
fmt);
}
+static int _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
+ struct dpu_sw_pipe *pipe,
+ struct dpu_hw_pipe_cfg *old_pipe_cfg,
+ u32 fill_color,
+ const struct dpu_format *fmt)
+{
+ struct dpu_hw_pipe_cfg pipe_cfg;
+
+ /* update sspp */
+ if (!pipe->sspp->ops.setup_solidfill)
+ return 0;
+
+ pipe->sspp->ops.setup_solidfill(pipe, fill_color);
+
+ /* override scaler/decimation if solid fill */
+ pipe_cfg.dst_rect = old_pipe_cfg->dst_rect;
+
+ pipe_cfg.src_rect.x1 = 0;
+ pipe_cfg.src_rect.y1 = 0;
+ pipe_cfg.src_rect.x2 =
+ drm_rect_width(&pipe_cfg.dst_rect);
+ pipe_cfg.src_rect.y2 =
+ drm_rect_height(&pipe_cfg.dst_rect);
+
+ if (pipe->sspp->ops.setup_format)
+ pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL);
+
+ if (pipe->sspp->ops.setup_rects)
+ pipe->sspp->ops.setup_rects(pipe, &pipe_cfg);
+
+ _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation);
+
+ return 0;
+}
+
/**
* _dpu_plane_color_fill - enables color fill on plane
* @pdpu: Pointer to DPU plane object
* @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
* @alpha: 8-bit fill alpha value, 255 selects 100% alpha
- * Returns: 0 on success
*/
-static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
+static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
uint32_t color, uint32_t alpha)
{
const struct dpu_format *fmt;
const struct drm_plane *plane = &pdpu->base;
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
- struct dpu_hw_pipe_cfg pipe_cfg;
+ u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
DPU_DEBUG_PLANE(pdpu, "\n");
@@ -661,34 +695,12 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
* h/w only supports RGB variants
*/
fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
+ /* should not happen ever */
+ if (!fmt)
+ return;
/* update sspp */
- if (fmt && pstate->pipe.sspp->ops.setup_solidfill) {
- pstate->pipe.sspp->ops.setup_solidfill(&pstate->pipe,
- (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
-
- /* override scaler/decimation if solid fill */
- pipe_cfg.dst_rect = pstate->base.dst;
-
- pipe_cfg.src_rect.x1 = 0;
- pipe_cfg.src_rect.y1 = 0;
- pipe_cfg.src_rect.x2 =
- drm_rect_width(&pipe_cfg.dst_rect);
- pipe_cfg.src_rect.y2 =
- drm_rect_height(&pipe_cfg.dst_rect);
-
- if (pstate->pipe.sspp->ops.setup_format)
- pstate->pipe.sspp->ops.setup_format(&pstate->pipe,
- fmt, DPU_SSPP_SOLID_FILL);
-
- if (pstate->pipe.sspp->ops.setup_rects)
- pstate->pipe.sspp->ops.setup_rects(&pstate->pipe,
- &pipe_cfg);
-
- _dpu_plane_setup_scaler(&pstate->pipe, fmt, true, &pipe_cfg, pstate->rotation);
- }
-
- return 0;
+ _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg, fill_color, fmt);
}
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 26/27] drm/msm/dpu: split pipe handling from _dpu_crtc_blend_setup_mixer
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Rework _dpu_crtc_blend_setup_mixer() to split away pipe handling to a
separate functon. This is a preparation for the r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 86 ++++++++++++++++-------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 ++-
2 files changed, 63 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 78981271b28a..d0d1cb355062 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -400,6 +400,47 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
}
}
+static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
+ struct drm_plane *plane,
+ struct dpu_crtc_mixer *mixer,
+ u32 num_mixers,
+ struct dpu_hw_stage_cfg *stage_cfg,
+ enum dpu_stage stage,
+ unsigned int stage_idx,
+ unsigned long *fetch_active,
+ struct dpu_sw_pipe *pipe
+ )
+{
+ uint32_t lm_idx;
+ enum dpu_sspp sspp_idx;
+ struct drm_plane_state *state;
+
+ if (pipe->sspp)
+ return;
+
+ sspp_idx = pipe->sspp->idx;
+
+ state = plane->state;
+
+ DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
+ crtc->base.id,
+ stage,
+ plane->base.id,
+ sspp_idx - SSPP_NONE,
+ state->fb ? state->fb->base.id : -1);
+
+ set_bit(sspp_idx, fetch_active);
+
+ stage_cfg->stage[stage][stage_idx] = sspp_idx;
+ stage_cfg->multirect_index[stage][stage_idx] =
+ pipe->multirect_index;
+
+ /* blend config update */
+ for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
+ mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl,
+ sspp_idx);
+}
+
static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
struct dpu_hw_stage_cfg *stage_cfg)
@@ -412,15 +453,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct dpu_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
- uint32_t stage_idx, lm_idx;
- int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
+ uint32_t lm_idx;
bool bg_alpha_enable = false;
DECLARE_BITMAP(fetch_active, SSPP_MAX);
memset(fetch_active, 0, sizeof(fetch_active));
drm_atomic_crtc_for_each_plane(plane, crtc) {
- enum dpu_sspp sspp_idx;
-
state = plane->state;
if (!state)
continue;
@@ -431,39 +469,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- sspp_idx = pstate->pipe.sspp->idx;
- set_bit(sspp_idx, fetch_active);
-
- DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
- crtc->base.id,
- pstate->stage,
- plane->base.id,
- sspp_idx - SSPP_VIG0,
- state->fb ? state->fb->base.id : -1);
-
format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
- stage_idx = zpos_cnt[pstate->stage]++;
- stage_cfg->stage[pstate->stage][stage_idx] =
- sspp_idx;
- stage_cfg->multirect_index[pstate->stage][stage_idx] =
- pstate->pipe.multirect_index;
-
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
- state, pstate, stage_idx,
+ state, pstate,
format->base.pixel_format,
fb ? fb->modifier : 0);
+ _dpu_crtc_blend_setup_pipe(crtc, plane,
+ mixer, cstate->num_mixers,
+ stage_cfg, pstate->stage, 0,
+ fetch_active,
+ &pstate->pipe);
+
/* blend config update */
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
- _dpu_crtc_setup_blend_cfg(mixer + lm_idx,
- pstate, format);
-
- mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl,
- sspp_idx);
+ _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
if (bg_alpha_enable && !format->alpha_enable)
mixer[lm_idx].mixer_op_mode = 0;
@@ -1294,8 +1318,16 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
state->crtc_x, state->crtc_y, state->crtc_w,
state->crtc_h);
- seq_printf(s, "\tmultirect: mode: %d index: %d\n",
+ seq_printf(s, "\tsspp[0]:%d\n",
+ pstate->pipe.sspp->idx - SSPP_NONE);
+ seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
+ if (pstate->r_pipe.sspp) {
+ seq_printf(s, "\tsspp[1]:%d\n",
+ pstate->r_pipe.sspp->idx - SSPP_NONE);
+ seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
+ pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
+ }
seq_puts(s, "\n");
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 0ad148cc2fb8..5ec4f89e8814 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -633,9 +633,9 @@ TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
TRACE_EVENT(dpu_crtc_setup_mixer,
TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
struct drm_plane_state *state, struct dpu_plane_state *pstate,
- uint32_t stage_idx, uint32_t pixel_format,
+ uint32_t pixel_format,
uint64_t modifier),
- TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
+ TP_ARGS(crtc_id, plane_id, state, pstate,
pixel_format, modifier),
TP_STRUCT__entry(
__field( uint32_t, crtc_id )
@@ -643,7 +643,6 @@ TRACE_EVENT(dpu_crtc_setup_mixer,
__field( uint32_t, fb_id )
__field_struct( struct drm_rect, src_rect )
__field_struct( struct drm_rect, dst_rect )
- __field( uint32_t, stage_idx )
__field( enum dpu_stage, stage )
__field( enum dpu_sspp, sspp )
__field( uint32_t, multirect_idx )
@@ -657,7 +656,6 @@ TRACE_EVENT(dpu_crtc_setup_mixer,
__entry->fb_id = state ? state->fb->base.id : 0;
__entry->src_rect = drm_plane_state_src(state);
__entry->dst_rect = drm_plane_state_dest(state);
- __entry->stage_idx = stage_idx;
__entry->stage = pstate->stage;
__entry->sspp = pstate->pipe.sspp->idx;
__entry->multirect_idx = pstate->pipe.multirect_index;
@@ -666,13 +664,13 @@ TRACE_EVENT(dpu_crtc_setup_mixer,
__entry->modifier = modifier;
),
TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT
- " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d "
+ " dst:" DRM_RECT_FMT " stage:%d, sspp:%d "
"multirect_index:%d multirect_mode:%u pix_format:%u "
"modifier:%llu",
__entry->crtc_id, __entry->plane_id, __entry->fb_id,
DRM_RECT_FP_ARG(&__entry->src_rect),
DRM_RECT_ARG(&__entry->dst_rect),
- __entry->stage_idx, __entry->stage, __entry->sspp,
+ __entry->stage, __entry->sspp,
__entry->multirect_idx, __entry->multirect_mode,
__entry->pixel_format, __entry->modifier)
);
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 26/27] drm/msm/dpu: split pipe handling from _dpu_crtc_blend_setup_mixer
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Rework _dpu_crtc_blend_setup_mixer() to split away pipe handling to a
separate functon. This is a preparation for the r_pipe support.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 86 ++++++++++++++++-------
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 ++-
2 files changed, 63 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 78981271b28a..d0d1cb355062 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -400,6 +400,47 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
}
}
+static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
+ struct drm_plane *plane,
+ struct dpu_crtc_mixer *mixer,
+ u32 num_mixers,
+ struct dpu_hw_stage_cfg *stage_cfg,
+ enum dpu_stage stage,
+ unsigned int stage_idx,
+ unsigned long *fetch_active,
+ struct dpu_sw_pipe *pipe
+ )
+{
+ uint32_t lm_idx;
+ enum dpu_sspp sspp_idx;
+ struct drm_plane_state *state;
+
+ if (pipe->sspp)
+ return;
+
+ sspp_idx = pipe->sspp->idx;
+
+ state = plane->state;
+
+ DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
+ crtc->base.id,
+ stage,
+ plane->base.id,
+ sspp_idx - SSPP_NONE,
+ state->fb ? state->fb->base.id : -1);
+
+ set_bit(sspp_idx, fetch_active);
+
+ stage_cfg->stage[stage][stage_idx] = sspp_idx;
+ stage_cfg->multirect_index[stage][stage_idx] =
+ pipe->multirect_index;
+
+ /* blend config update */
+ for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
+ mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl,
+ sspp_idx);
+}
+
static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
struct dpu_hw_stage_cfg *stage_cfg)
@@ -412,15 +453,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct dpu_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
- uint32_t stage_idx, lm_idx;
- int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
+ uint32_t lm_idx;
bool bg_alpha_enable = false;
DECLARE_BITMAP(fetch_active, SSPP_MAX);
memset(fetch_active, 0, sizeof(fetch_active));
drm_atomic_crtc_for_each_plane(plane, crtc) {
- enum dpu_sspp sspp_idx;
-
state = plane->state;
if (!state)
continue;
@@ -431,39 +469,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- sspp_idx = pstate->pipe.sspp->idx;
- set_bit(sspp_idx, fetch_active);
-
- DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
- crtc->base.id,
- pstate->stage,
- plane->base.id,
- sspp_idx - SSPP_VIG0,
- state->fb ? state->fb->base.id : -1);
-
format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
- stage_idx = zpos_cnt[pstate->stage]++;
- stage_cfg->stage[pstate->stage][stage_idx] =
- sspp_idx;
- stage_cfg->multirect_index[pstate->stage][stage_idx] =
- pstate->pipe.multirect_index;
-
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
- state, pstate, stage_idx,
+ state, pstate,
format->base.pixel_format,
fb ? fb->modifier : 0);
+ _dpu_crtc_blend_setup_pipe(crtc, plane,
+ mixer, cstate->num_mixers,
+ stage_cfg, pstate->stage, 0,
+ fetch_active,
+ &pstate->pipe);
+
/* blend config update */
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
- _dpu_crtc_setup_blend_cfg(mixer + lm_idx,
- pstate, format);
-
- mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl,
- sspp_idx);
+ _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
if (bg_alpha_enable && !format->alpha_enable)
mixer[lm_idx].mixer_op_mode = 0;
@@ -1294,8 +1318,16 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
state->crtc_x, state->crtc_y, state->crtc_w,
state->crtc_h);
- seq_printf(s, "\tmultirect: mode: %d index: %d\n",
+ seq_printf(s, "\tsspp[0]:%d\n",
+ pstate->pipe.sspp->idx - SSPP_NONE);
+ seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
+ if (pstate->r_pipe.sspp) {
+ seq_printf(s, "\tsspp[1]:%d\n",
+ pstate->r_pipe.sspp->idx - SSPP_NONE);
+ seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
+ pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
+ }
seq_puts(s, "\n");
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 0ad148cc2fb8..5ec4f89e8814 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -633,9 +633,9 @@ TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
TRACE_EVENT(dpu_crtc_setup_mixer,
TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
struct drm_plane_state *state, struct dpu_plane_state *pstate,
- uint32_t stage_idx, uint32_t pixel_format,
+ uint32_t pixel_format,
uint64_t modifier),
- TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
+ TP_ARGS(crtc_id, plane_id, state, pstate,
pixel_format, modifier),
TP_STRUCT__entry(
__field( uint32_t, crtc_id )
@@ -643,7 +643,6 @@ TRACE_EVENT(dpu_crtc_setup_mixer,
__field( uint32_t, fb_id )
__field_struct( struct drm_rect, src_rect )
__field_struct( struct drm_rect, dst_rect )
- __field( uint32_t, stage_idx )
__field( enum dpu_stage, stage )
__field( enum dpu_sspp, sspp )
__field( uint32_t, multirect_idx )
@@ -657,7 +656,6 @@ TRACE_EVENT(dpu_crtc_setup_mixer,
__entry->fb_id = state ? state->fb->base.id : 0;
__entry->src_rect = drm_plane_state_src(state);
__entry->dst_rect = drm_plane_state_dest(state);
- __entry->stage_idx = stage_idx;
__entry->stage = pstate->stage;
__entry->sspp = pstate->pipe.sspp->idx;
__entry->multirect_idx = pstate->pipe.multirect_index;
@@ -666,13 +664,13 @@ TRACE_EVENT(dpu_crtc_setup_mixer,
__entry->modifier = modifier;
),
TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT
- " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d "
+ " dst:" DRM_RECT_FMT " stage:%d, sspp:%d "
"multirect_index:%d multirect_mode:%u pix_format:%u "
"modifier:%llu",
__entry->crtc_id, __entry->plane_id, __entry->fb_id,
DRM_RECT_FP_ARG(&__entry->src_rect),
DRM_RECT_ARG(&__entry->dst_rect),
- __entry->stage_idx, __entry->stage, __entry->sspp,
+ __entry->stage, __entry->sspp,
__entry->multirect_idx, __entry->multirect_mode,
__entry->pixel_format, __entry->modifier)
);
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v2 27/27] drm/msm/dpu: add support for wide planes
2022-12-29 19:18 ` Dmitry Baryshkov
@ 2022-12-29 19:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Typically SSPP can support rectangle with width up to 2560. However it's
possible to use multirect feature and split source to use the SSPP to
output two consecutive rectangles. This commit brings in this capability
to support wider screen resolutions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 120 +++++++++++++++++++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
3 files changed, 114 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d0d1cb355062..7f0f467dbabd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -415,7 +415,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
enum dpu_sspp sspp_idx;
struct drm_plane_state *state;
- if (pipe->sspp)
+ if (!pipe->sspp)
return;
sspp_idx = pipe->sspp->idx;
@@ -485,6 +485,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
fetch_active,
&pstate->pipe);
+ _dpu_crtc_blend_setup_pipe(crtc, plane,
+ mixer, cstate->num_mixers,
+ stage_cfg, pstate->stage, 1,
+ fetch_active,
+ &pstate->r_pipe);
+
/* blend config update */
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 2851f40cb915..786b656cc45d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -365,6 +365,9 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
+ if (!pipe->sspp)
+ return;
+
memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
@@ -647,6 +650,9 @@ static int _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
{
struct dpu_hw_pipe_cfg pipe_cfg;
+ if (!pipe->sspp)
+ return 0;
+
/* update sspp */
if (!pipe->sspp->ops.setup_solidfill)
return 0;
@@ -701,6 +707,8 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
/* update sspp */
_dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg, fill_color, fmt);
+
+ _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg, fill_color, fmt);
}
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
@@ -907,11 +915,13 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
struct dpu_sw_pipe *pipe,
struct dpu_hw_pipe_cfg *pipe_cfg,
- uint32_t max_linewidth,
const struct dpu_format *fmt)
{
uint32_t min_src_size;
+ if (!pipe->sspp)
+ return 0;
+
min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
if (DPU_FORMAT_IS_YUV(fmt) &&
@@ -942,12 +952,6 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
DRM_RECT_ARG(&pipe_cfg->dst_rect));
return -EINVAL;
-
- /* check decimated source width */
- } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
- DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
- return -E2BIG;
}
return 0;
@@ -961,9 +965,12 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
int ret = 0, min_scale;
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
+ struct dpu_sw_pipe *pipe = &pstate->pipe;
+ struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
const struct drm_crtc_state *crtc_state = NULL;
const struct dpu_format *fmt;
struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+ struct dpu_hw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct drm_rect fb_rect = { 0 };
uint32_t max_linewidth;
unsigned int rotation;
@@ -987,8 +994,11 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
if (!new_plane_state->visible)
return 0;
- pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
- pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ r_pipe->sspp = NULL;
pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
@@ -1022,7 +1032,49 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
- ret = dpu_plane_atomic_check_pipe(pdpu, &pstate->pipe, pipe_cfg, max_linewidth, fmt);
+ if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
+ /* struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); */
+
+ if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
+ DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
+ return -E2BIG;
+ /*
+ * FIXME: it's not possible to check if sourcesplit is supported,
+ * LMs is not assigned yet. It happens in dpu_encoder_virt_mode_set
+ */
+ } else if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) ||
+ drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
+ (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
+ !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
+ /* cstate->num_mixers < 2 ||
+ !test_bit(DPU_MIXER_SOURCESPLIT, &cstate->mixers[0].hw_lm->cap->features) || */
+ DPU_FORMAT_IS_YUV(fmt)) {
+ DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
+ return -E2BIG;
+ }
+
+ /* Use multirect for wide plane. We do not support dynamic assignment of SSPPs, so we know the configuration. */
+ pipe->multirect_index = DPU_SSPP_RECT_0;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+
+ r_pipe->sspp = pipe->sspp;
+ r_pipe->multirect_index = DPU_SSPP_RECT_1;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+
+ *r_pipe_cfg = *pipe_cfg;
+ pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
+ pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
+ r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
+ r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
+ }
+
+ ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt);
+ if (ret)
+ return ret;
+
+ ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt);
if (ret)
return ret;
@@ -1091,8 +1143,10 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else
+ else {
dpu_plane_flush_csc(pdpu, &pstate->pipe);
+ dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
+ }
/* flag h/w flush complete */
if (plane->state)
@@ -1127,6 +1181,9 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
struct drm_plane_state *state = plane->state;
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ if (!pipe->sspp)
+ return;
+
if (layout && pipe->sspp->ops.setup_sourceaddress) {
trace_dpu_plane_set_scanout(pipe, layout);
pipe->sspp->ops.setup_sourceaddress(pipe, layout);
@@ -1204,13 +1261,14 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct drm_plane_state *state = plane->state;
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
struct dpu_sw_pipe *pipe = &pstate->pipe;
+ struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
bool is_rt_pipe;
const struct dpu_format *fmt =
to_dpu_format(msm_framebuffer_format(fb));
struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
-
+ struct dpu_hw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
struct msm_gem_address_space *aspace = kms->base.aspace;
struct dpu_hw_fmt_layout layout;
@@ -1238,12 +1296,22 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
drm_mode_vrefresh(&crtc->mode),
layout_valid ? &layout: NULL);
+ dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt,
+ drm_mode_vrefresh(&crtc->mode),
+ layout_valid ? &layout: NULL);
+
if (pstate->needs_qos_remap)
pstate->needs_qos_remap = false;
pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, pipe_cfg);
pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
+
+ if (r_pipe->sspp) {
+ pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
+
+ pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg));
+ }
}
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
@@ -1286,6 +1354,8 @@ static void dpu_plane_destroy(struct drm_plane *plane)
pstate = to_dpu_plane_state(plane->state);
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
+
mutex_destroy(&pdpu->lock);
/* this will destroy the states as well */
@@ -1366,11 +1436,26 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
const struct drm_plane_state *state)
{
const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ const struct dpu_sw_pipe *pipe = &pstate->pipe;
+ const struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+ const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
+ const struct dpu_hw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
drm_printf(p, "\tstage=%d\n", pstate->stage);
- drm_printf(p, "\tsspp=%s\n", pstate->pipe.sspp->cap->name);
- drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->pipe.multirect_mode));
- drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->pipe.multirect_index));
+
+ drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name);
+ drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode));
+ drm_printf(p, "\tmultirect_index[0]=%s\n", dpu_get_multirect_index(pipe->multirect_index));
+ drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect));
+ drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect));
+
+ if (r_pipe->sspp) {
+ drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name);
+ drm_printf(p, "\tmultirect_mode[1]=%s\n", dpu_get_multirect_mode(r_pipe->multirect_mode));
+ drm_printf(p, "\tmultirect_index[1]=%s\n", dpu_get_multirect_index(r_pipe->multirect_index));
+ drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect));
+ drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect));
+ }
}
static void dpu_plane_reset(struct drm_plane *plane)
@@ -1400,6 +1485,10 @@ static void dpu_plane_reset(struct drm_plane *plane)
}
pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
+ pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
+ pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+
+ pstate->r_pipe.sspp = NULL;
__drm_atomic_helper_plane_reset(plane, &pstate->base);
}
@@ -1416,6 +1505,7 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
pm_runtime_get_sync(&dpu_kms->pdev->dev);
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable, DPU_PLANE_QOS_PANIC_CTRL);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
}
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 95031e8b00f8..a0b98f29a3bb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -36,7 +36,9 @@ struct dpu_plane_state {
bool pending;
struct dpu_sw_pipe pipe;
+ struct dpu_sw_pipe r_pipe;
struct dpu_hw_pipe_cfg pipe_cfg;
+ struct dpu_hw_pipe_cfg r_pipe_cfg;
u64 plane_fetch_bw;
u64 plane_clk;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread* [PATCH v2 27/27] drm/msm/dpu: add support for wide planes
@ 2022-12-29 19:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 110+ messages in thread
From: Dmitry Baryshkov @ 2022-12-29 19:18 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Typically SSPP can support rectangle with width up to 2560. However it's
possible to use multirect feature and split source to use the SSPP to
output two consecutive rectangles. This commit brings in this capability
to support wider screen resolutions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 120 +++++++++++++++++++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
3 files changed, 114 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d0d1cb355062..7f0f467dbabd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -415,7 +415,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
enum dpu_sspp sspp_idx;
struct drm_plane_state *state;
- if (pipe->sspp)
+ if (!pipe->sspp)
return;
sspp_idx = pipe->sspp->idx;
@@ -485,6 +485,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
fetch_active,
&pstate->pipe);
+ _dpu_crtc_blend_setup_pipe(crtc, plane,
+ mixer, cstate->num_mixers,
+ stage_cfg, pstate->stage, 1,
+ fetch_active,
+ &pstate->r_pipe);
+
/* blend config update */
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 2851f40cb915..786b656cc45d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -365,6 +365,9 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
+ if (!pipe->sspp)
+ return;
+
memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
@@ -647,6 +650,9 @@ static int _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
{
struct dpu_hw_pipe_cfg pipe_cfg;
+ if (!pipe->sspp)
+ return 0;
+
/* update sspp */
if (!pipe->sspp->ops.setup_solidfill)
return 0;
@@ -701,6 +707,8 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
/* update sspp */
_dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg, fill_color, fmt);
+
+ _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg, fill_color, fmt);
}
int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
@@ -907,11 +915,13 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
struct dpu_sw_pipe *pipe,
struct dpu_hw_pipe_cfg *pipe_cfg,
- uint32_t max_linewidth,
const struct dpu_format *fmt)
{
uint32_t min_src_size;
+ if (!pipe->sspp)
+ return 0;
+
min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
if (DPU_FORMAT_IS_YUV(fmt) &&
@@ -942,12 +952,6 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
DRM_RECT_ARG(&pipe_cfg->dst_rect));
return -EINVAL;
-
- /* check decimated source width */
- } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
- DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
- return -E2BIG;
}
return 0;
@@ -961,9 +965,12 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
int ret = 0, min_scale;
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
+ struct dpu_sw_pipe *pipe = &pstate->pipe;
+ struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
const struct drm_crtc_state *crtc_state = NULL;
const struct dpu_format *fmt;
struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+ struct dpu_hw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct drm_rect fb_rect = { 0 };
uint32_t max_linewidth;
unsigned int rotation;
@@ -987,8 +994,11 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
if (!new_plane_state->visible)
return 0;
- pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
- pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ r_pipe->sspp = NULL;
pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
@@ -1022,7 +1032,49 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
- ret = dpu_plane_atomic_check_pipe(pdpu, &pstate->pipe, pipe_cfg, max_linewidth, fmt);
+ if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
+ /* struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); */
+
+ if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
+ DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
+ return -E2BIG;
+ /*
+ * FIXME: it's not possible to check if sourcesplit is supported,
+ * LMs is not assigned yet. It happens in dpu_encoder_virt_mode_set
+ */
+ } else if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) ||
+ drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
+ (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
+ !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
+ /* cstate->num_mixers < 2 ||
+ !test_bit(DPU_MIXER_SOURCESPLIT, &cstate->mixers[0].hw_lm->cap->features) || */
+ DPU_FORMAT_IS_YUV(fmt)) {
+ DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
+ return -E2BIG;
+ }
+
+ /* Use multirect for wide plane. We do not support dynamic assignment of SSPPs, so we know the configuration. */
+ pipe->multirect_index = DPU_SSPP_RECT_0;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+
+ r_pipe->sspp = pipe->sspp;
+ r_pipe->multirect_index = DPU_SSPP_RECT_1;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+
+ *r_pipe_cfg = *pipe_cfg;
+ pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
+ pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
+ r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
+ r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
+ }
+
+ ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt);
+ if (ret)
+ return ret;
+
+ ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt);
if (ret)
return ret;
@@ -1091,8 +1143,10 @@ void dpu_plane_flush(struct drm_plane *plane)
else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
- else
+ else {
dpu_plane_flush_csc(pdpu, &pstate->pipe);
+ dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
+ }
/* flag h/w flush complete */
if (plane->state)
@@ -1127,6 +1181,9 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
struct drm_plane_state *state = plane->state;
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ if (!pipe->sspp)
+ return;
+
if (layout && pipe->sspp->ops.setup_sourceaddress) {
trace_dpu_plane_set_scanout(pipe, layout);
pipe->sspp->ops.setup_sourceaddress(pipe, layout);
@@ -1204,13 +1261,14 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct drm_plane_state *state = plane->state;
struct dpu_plane_state *pstate = to_dpu_plane_state(state);
struct dpu_sw_pipe *pipe = &pstate->pipe;
+ struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
bool is_rt_pipe;
const struct dpu_format *fmt =
to_dpu_format(msm_framebuffer_format(fb));
struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
-
+ struct dpu_hw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
struct msm_gem_address_space *aspace = kms->base.aspace;
struct dpu_hw_fmt_layout layout;
@@ -1238,12 +1296,22 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
drm_mode_vrefresh(&crtc->mode),
layout_valid ? &layout: NULL);
+ dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt,
+ drm_mode_vrefresh(&crtc->mode),
+ layout_valid ? &layout: NULL);
+
if (pstate->needs_qos_remap)
pstate->needs_qos_remap = false;
pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, pipe_cfg);
pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
+
+ if (r_pipe->sspp) {
+ pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
+
+ pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg));
+ }
}
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
@@ -1286,6 +1354,8 @@ static void dpu_plane_destroy(struct drm_plane *plane)
pstate = to_dpu_plane_state(plane->state);
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false, DPU_PLANE_QOS_PANIC_CTRL);
+
mutex_destroy(&pdpu->lock);
/* this will destroy the states as well */
@@ -1366,11 +1436,26 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
const struct drm_plane_state *state)
{
const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
+ const struct dpu_sw_pipe *pipe = &pstate->pipe;
+ const struct dpu_hw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+ const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
+ const struct dpu_hw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
drm_printf(p, "\tstage=%d\n", pstate->stage);
- drm_printf(p, "\tsspp=%s\n", pstate->pipe.sspp->cap->name);
- drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->pipe.multirect_mode));
- drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->pipe.multirect_index));
+
+ drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name);
+ drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode));
+ drm_printf(p, "\tmultirect_index[0]=%s\n", dpu_get_multirect_index(pipe->multirect_index));
+ drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect));
+ drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect));
+
+ if (r_pipe->sspp) {
+ drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name);
+ drm_printf(p, "\tmultirect_mode[1]=%s\n", dpu_get_multirect_mode(r_pipe->multirect_mode));
+ drm_printf(p, "\tmultirect_index[1]=%s\n", dpu_get_multirect_index(r_pipe->multirect_index));
+ drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect));
+ drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect));
+ }
}
static void dpu_plane_reset(struct drm_plane *plane)
@@ -1400,6 +1485,10 @@ static void dpu_plane_reset(struct drm_plane *plane)
}
pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
+ pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
+ pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+
+ pstate->r_pipe.sspp = NULL;
__drm_atomic_helper_plane_reset(plane, &pstate->base);
}
@@ -1416,6 +1505,7 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
pm_runtime_get_sync(&dpu_kms->pdev->dev);
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL);
+ _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable, DPU_PLANE_QOS_PANIC_CTRL);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
}
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 95031e8b00f8..a0b98f29a3bb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -36,7 +36,9 @@ struct dpu_plane_state {
bool pending;
struct dpu_sw_pipe pipe;
+ struct dpu_sw_pipe r_pipe;
struct dpu_hw_pipe_cfg pipe_cfg;
+ struct dpu_hw_pipe_cfg r_pipe_cfg;
u64 plane_fetch_bw;
u64 plane_clk;
--
2.39.0
^ permalink raw reply related [flat|nested] 110+ messages in thread