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From: Chanwoo Choi <cw00.choi@samsung.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Kukjin Kim <kgene@kernel.org>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH 3/4] clk: samsung: exynos5410: Add gate clock for ADC
Date: Wed, 13 Feb 2019 16:11:38 +0900	[thread overview]
Message-ID: <c75f4582-18e4-f123-382d-e50626b650c8@samsung.com> (raw)
In-Reply-To: <20190212175052.6310-4-krzk@kernel.org>

Hi,

On 19. 2. 13. 오전 2:50, Krzysztof Kozlowski wrote:
> Add the gate clock for ADC block on Exynos5410.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  drivers/clk/samsung/clk-exynos5410.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
> index 0a0b09591e6f..b2da2c8fa0c7 100644
> --- a/drivers/clk/samsung/clk-exynos5410.c
> +++ b/drivers/clk/samsung/clk-exynos5410.c
> @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
>  	GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
>  	GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
>  	GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
> +	GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
>  	GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
>  
>  	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> 

I checked it on Exynos5410 TRM. Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

WARNING: multiple messages have this Message-ID (diff)
From: Chanwoo Choi <cw00.choi@samsung.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Kukjin Kim <kgene@kernel.org>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH 3/4] clk: samsung: exynos5410: Add gate clock for ADC
Date: Wed, 13 Feb 2019 16:11:38 +0900	[thread overview]
Message-ID: <c75f4582-18e4-f123-382d-e50626b650c8@samsung.com> (raw)
In-Reply-To: <20190212175052.6310-4-krzk@kernel.org>

Hi,

On 19. 2. 13. 오전 2:50, Krzysztof Kozlowski wrote:
> Add the gate clock for ADC block on Exynos5410.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  drivers/clk/samsung/clk-exynos5410.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
> index 0a0b09591e6f..b2da2c8fa0c7 100644
> --- a/drivers/clk/samsung/clk-exynos5410.c
> +++ b/drivers/clk/samsung/clk-exynos5410.c
> @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
>  	GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
>  	GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
>  	GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
> +	GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
>  	GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
>  
>  	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> 

I checked it on Exynos5410 TRM. Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2019-02-13  7:11 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20190212175145epcas4p1760db3c6a3e2497528925d081c12cecc@epcas4p1.samsung.com>
2019-02-12 17:50 ` [PATCH 0/4] clk/ARM: exynos: Add ADC to Exynos5410 (Odroid XU) Krzysztof Kozlowski
2019-02-12 17:50   ` Krzysztof Kozlowski
2019-02-12 17:50   ` [PATCH 1/4] dt-bindings: clock: exynos: Put CLK_UART3 in order Krzysztof Kozlowski
2019-02-12 17:50     ` Krzysztof Kozlowski
2019-02-13  7:04     ` Chanwoo Choi
2019-02-13  7:04       ` Chanwoo Choi
2019-02-28 18:22     ` Rob Herring
2019-02-28 18:22       ` Rob Herring
2019-02-12 17:50   ` [PATCH 2/4] dt-bindings: clock: exynos: Add ADC clock ID to Exynos5410 Krzysztof Kozlowski
2019-02-12 17:50     ` Krzysztof Kozlowski
2019-02-13  7:07     ` Chanwoo Choi
2019-02-13  7:07       ` Chanwoo Choi
2019-02-28 18:23     ` Rob Herring
2019-02-28 18:23       ` Rob Herring
2019-02-12 17:50   ` [PATCH 3/4] clk: samsung: exynos5410: Add gate clock for ADC Krzysztof Kozlowski
2019-02-12 17:50     ` Krzysztof Kozlowski
2019-02-13  7:11     ` Chanwoo Choi [this message]
2019-02-13  7:11       ` Chanwoo Choi
2019-02-12 17:50   ` [PATCH 4/4] ARM: dts: exynos: Add ADC node to Exynos5410 and Odroid XU Krzysztof Kozlowski
2019-02-12 17:50     ` Krzysztof Kozlowski
2019-03-26 14:56   ` [PATCH 0/4] clk/ARM: exynos: Add ADC to Exynos5410 (Odroid XU) Sylwester Nawrocki
2019-03-26 14:56     ` Sylwester Nawrocki

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