[PATCH 00/19] shadow page table support V2

[PATCH 00/19] shadow page table support V2

[Chunming Zhou]

Since we cannot make sure VRAM is safe after gpu reset, page table backup
is neccessary, shadow page table is sense way to recovery page talbe when
gpu reset happens.
We need to allocate GTT bo as the shadow of VRAM bo when creating page table,
and make them same. After gpu reset, we will need to use SDMA to copy GTT bo
content to VRAM bo, then page table will be recoveried. 

V2:
Shadow bo uses a shadow entity running on normal run queue, after gpu reset,
we need to wait for all shadow jobs finished first, then recovery page table from shadow.

Chunming Zhou (19):
  drm/amdgpu: add shadow bo support
  drm/amdgpu: validate shadow as well when validating bo
  drm/amdgpu: allocate shadow for pd/pt bo
  drm/amdgpu: add shadow flag
  drm/amdgpu: sync bo and shadow
  drm/amdgpu: implement vm recovery function from shadow
  drm/amdgpu: fix vm init error path
  drm/amdgpu: add shadow_entity for shadow page table updates
  drm/amdgpu: update pd shadow bo
  drm/amdgpu: update pt shadow
  drm/amd: add last fence in sched entity
  drm/amdgpu: link all vm clients
  drm/amdgpu: add vm_list_lock
  drm/amd: add block entity function
  drm/amdgpu: add shadow fence owner
  drm/amd: block entity
  drm/amdgpu: recover page tables after gpu reset
  drm/amdgpu: add need backup function
  drm/amdgpu: add backup condition for vm

 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  25 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  82 +++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  88 ++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c    | 104 +++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h    |   5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c      |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c        | 270 +++++++++++++++++++-------
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  38 +++-
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |   5 +
 include/uapi/drm/amdgpu_drm.h                 |   2 +
 10 files changed, 519 insertions(+), 103 deletions(-)

-- 
1.9.1

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[PATCH 01/19] drm/amdgpu: add shadow bo support

[Chunming Zhou]

shadow bo is the shadow of a bo, which is always in GTT,
which can be used to backup the original bo.

Change-Id: Ia27d4225c47ff41d3053eb691276e29fb2d64026
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 52 +++++++++++++++++++++++++++---
 include/uapi/drm/amdgpu_drm.h              |  2 ++
 3 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8e2ca06..8c2ac1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -506,6 +506,7 @@ struct amdgpu_bo {
 	struct amdgpu_device		*adev;
 	struct drm_gem_object		gem_base;
 	struct amdgpu_bo		*parent;
+	struct amdgpu_bo		*shadow;
 
 	struct ttm_bo_kmap_obj		dma_buf_vmap;
 	struct amdgpu_mn		*mn;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index d8e69a7..d6ca3dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -380,6 +380,32 @@ fail_free:
 	return r;
 }
 
+static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
+				   unsigned long size, int byte_align,
+				   struct amdgpu_bo *bo)
+{
+	struct ttm_placement placement = {0};
+	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
+
+	if (bo->shadow)
+		return 0;
+
+	bo->flags |= AMDGPU_GEM_CREATE_SHADOW;
+	memset(&placements, 0,
+	       (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
+
+	amdgpu_ttm_placement_init(adev, &placement,
+				  placements, AMDGPU_GEM_DOMAIN_GTT,
+				  AMDGPU_GEM_CREATE_CPU_GTT_USWC);
+
+	return amdgpu_bo_create_restricted(adev, size, byte_align, true,
+					   AMDGPU_GEM_DOMAIN_GTT,
+					   AMDGPU_GEM_CREATE_CPU_GTT_USWC,
+					   NULL, &placement,
+					   bo->tbo.resv,
+					   &bo->shadow);
+}
+
 int amdgpu_bo_create(struct amdgpu_device *adev,
 		     unsigned long size, int byte_align,
 		     bool kernel, u32 domain, u64 flags,
@@ -389,6 +415,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 {
 	struct ttm_placement placement = {0};
 	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
+	int r;
 
 	memset(&placements, 0,
 	       (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
@@ -396,9 +423,19 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 	amdgpu_ttm_placement_init(adev, &placement,
 				  placements, domain, flags);
 
-	return amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
-					   domain, flags, sg, &placement,
-					   resv, bo_ptr);
+	r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
+					domain, flags, sg, &placement,
+					resv, bo_ptr);
+	if (r)
+		return r;
+
+	if (flags & AMDGPU_GEM_CREATE_SHADOW) {
+		r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
+		if (r)
+			amdgpu_bo_unref(bo_ptr);
+	}
+
+	return r;
 }
 
 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
@@ -452,14 +489,21 @@ struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 {
 	struct ttm_buffer_object *tbo;
+	struct amdgpu_bo *shadow;
 
 	if ((*bo) == NULL)
 		return;
 
+	shadow = (*bo)->shadow;
 	tbo = &((*bo)->tbo);
 	ttm_bo_unref(&tbo);
-	if (tbo == NULL)
+	if (tbo == NULL) {
 		*bo = NULL;
+		if (shadow) {
+			tbo = &shadow->tbo;
+			ttm_bo_unref(&tbo);
+		}
+	}
 }
 
 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 8df3816..da2d3e1 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -77,6 +77,8 @@
 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC		(1 << 2)
 /* Flag that the memory should be in VRAM and cleared */
 #define AMDGPU_GEM_CREATE_VRAM_CLEARED		(1 << 3)
+/* Flag that create shadow bo(GTT) while allocating vram bo */
+#define AMDGPU_GEM_CREATE_SHADOW		(1 << 4)
 
 struct drm_amdgpu_gem_create_in  {
 	/** the requested memory size */
-- 
1.9.1

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[PATCH 02/19] drm/amdgpu: validate shadow as well when validating bo

[Chunming Zhou]

Change-Id: I64c3d8c56f7955e885cad242fd06a8676f278363
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 76 ++++++++++++++++++++--------------
 1 file changed, 46 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index e4617c4..3434098 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -288,18 +288,56 @@ static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 	return max(bytes_moved_threshold, 1024*1024ull);
 }
 
+static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
+				 struct amdgpu_bo *bo)
+{
+	u64 initial_bytes_moved;
+	uint32_t domain;
+	int r;
+
+	if (bo->pin_count)
+		return 0;
+
+	/* Avoid moving this one if we have moved too many buffers
+	 * for this IB already.
+	 *
+	 * Note that this allows moving at least one buffer of
+	 * any size, because it doesn't take the current "bo"
+	 * into account. We don't want to disallow buffer moves
+	 * completely.
+	 */
+	if (p->bytes_moved <= p->bytes_moved_threshold)
+		domain = bo->prefered_domains;
+	else
+		domain = bo->allowed_domains;
+
+retry:
+	amdgpu_ttm_placement_from_domain(bo, domain);
+	initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
+	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+	p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
+		initial_bytes_moved;
+
+	if (unlikely(r)) {
+		if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
+			domain = bo->allowed_domains;
+			goto retry;
+		}
+	}
+
+	return r;
+}
+
 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 			    struct list_head *validated)
 {
 	struct amdgpu_bo_list_entry *lobj;
-	u64 initial_bytes_moved;
 	int r;
 
 	list_for_each_entry(lobj, validated, tv.head) {
 		struct amdgpu_bo *bo = lobj->robj;
 		bool binding_userptr = false;
 		struct mm_struct *usermm;
-		uint32_t domain;
 
 		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 		if (usermm && usermm != current->mm)
@@ -314,35 +352,13 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 			binding_userptr = true;
 		}
 
-		if (bo->pin_count)
-			continue;
-
-		/* Avoid moving this one if we have moved too many buffers
-		 * for this IB already.
-		 *
-		 * Note that this allows moving at least one buffer of
-		 * any size, because it doesn't take the current "bo"
-		 * into account. We don't want to disallow buffer moves
-		 * completely.
-		 */
-		if (p->bytes_moved <= p->bytes_moved_threshold)
-			domain = bo->prefered_domains;
-		else
-			domain = bo->allowed_domains;
-
-	retry:
-		amdgpu_ttm_placement_from_domain(bo, domain);
-		initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
-		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
-		p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
-			       initial_bytes_moved;
-
-		if (unlikely(r)) {
-			if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
-				domain = bo->allowed_domains;
-				goto retry;
-			}
+		r = amdgpu_cs_bo_validate(p, bo);
+		if (r)
 			return r;
+		if (bo->shadow) {
+			r = amdgpu_cs_bo_validate(p, bo);
+			if (r)
+				return r;
 		}
 
 		if (binding_userptr) {
-- 
1.9.1

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[PATCH 03/19] drm/amdgpu: allocate shadow for pd/pt bo

[Chunming Zhou]

The pd/pt shadow bo will be used to backup page table, when gpu reset
happens, we can restore the page table by them.

Change-Id: I28e4a9178f59eccb215f7977b5475d36e593ee5f
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 38c80ea..017274c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1341,7 +1341,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 		r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
 				     AMDGPU_GPU_PAGE_SIZE, true,
 				     AMDGPU_GEM_DOMAIN_VRAM,
-				     AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
+				     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
+				     AMDGPU_GEM_CREATE_SHADOW,
 				     NULL, resv, &pt);
 		if (r)
 			goto error_free;
@@ -1540,7 +1541,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 
 	r = amdgpu_bo_create(adev, pd_size, align, true,
 			     AMDGPU_GEM_DOMAIN_VRAM,
-			     AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
+			     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
+			     AMDGPU_GEM_CREATE_SHADOW,
 			     NULL, NULL, &vm->page_directory);
 	if (r)
 		goto error_free_sched_entity;
-- 
1.9.1

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[PATCH 04/19] drm/amdgpu: add shadow flag

[Chunming Zhou]

Indicate if need to sync between bo and shadow, where sync to where.

Change-Id: I74994dfad141da5c23a3598bb2e3df1253a195f7
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8c2ac1a..53b7039 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -481,6 +481,12 @@ struct amdgpu_bo_va {
 
 #define AMDGPU_GEM_DOMAIN_MAX		0x3
 
+enum amdgpu_shadow_flag {
+	AMDGPU_SHADOW_FLAG_SYNC_TO_NONE = 0,
+	AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT,
+	AMDGPU_SHADOW_FLAG_SYNC_TO_SHADOW,
+};
+
 struct amdgpu_bo {
 	/* Protected by gem.mutex */
 	struct list_head		list;
@@ -507,6 +513,8 @@ struct amdgpu_bo {
 	struct drm_gem_object		gem_base;
 	struct amdgpu_bo		*parent;
 	struct amdgpu_bo		*shadow;
+	/* indicate if need to sync between bo and shadow */
+	u32                             shadow_flag;
 
 	struct ttm_bo_kmap_obj		dma_buf_vmap;
 	struct amdgpu_mn		*mn;
-- 
1.9.1

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[PATCH 05/19] drm/amdgpu: sync bo and shadow

[Chunming Zhou]

Use shadow flag to judge which direction to sync.

Change-Id: I9b540970d3a24c6aebeaa94c99f66a89134c663d
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 52 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  5 +++
 2 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index d6ca3dd..c0f8d91 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -438,6 +438,58 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 	return r;
 }
 
+int amdgpu_bo_sync_between_bo_and_shadow(struct amdgpu_device *adev,
+					 struct amdgpu_ring *ring,
+					 struct amdgpu_bo *bo,
+					 struct reservation_object *resv,
+					 struct fence **fence)
+
+{
+	struct amdgpu_bo *shadow = bo->shadow;
+	uint64_t bo_addr, shadow_addr;
+	int r;
+
+	if (!shadow)
+		return -EINVAL;
+
+	if (bo->shadow_flag & AMDGPU_SHADOW_FLAG_SYNC_TO_NONE) {
+		DRM_INFO("No need to sync bo and shadow\n");
+		return 0;
+	}
+	r = amdgpu_bo_pin(bo, bo->prefered_domains, &bo_addr);
+	if (r) {
+		DRM_ERROR("Failed to pin bo object\n");
+		goto err1;
+	}
+	r = amdgpu_bo_pin(bo->shadow, bo->shadow->prefered_domains, &shadow_addr);
+	if (r) {
+		DRM_ERROR("Failed to pin bo shadow object\n");
+		goto err2;
+	}
+
+	r = reservation_object_reserve_shared(bo->tbo.resv);
+	if (r)
+		goto err3;
+
+	if (bo->shadow_flag & AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT)
+		r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
+				       amdgpu_bo_size(bo), resv, fence);
+	else
+		r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
+				       amdgpu_bo_size(bo), resv, fence);
+	if (!r) {
+		amdgpu_bo_fence(bo, *fence, true);
+		bo->shadow_flag = AMDGPU_SHADOW_FLAG_SYNC_TO_NONE;
+	}
+err3:
+	amdgpu_bo_unpin(bo->shadow);
+err2:
+	amdgpu_bo_unpin(bo);
+err1:
+
+	return r;
+}
+
 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 {
 	bool is_iomem;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index d650b42..68578c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -155,6 +155,11 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
 		     bool shared);
 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
+int amdgpu_bo_sync_between_bo_and_shadow(struct amdgpu_device *adev,
+					 struct amdgpu_ring *ring,
+					 struct amdgpu_bo *bo,
+					 struct reservation_object *resv,
+					 struct fence **fence);
 
 /*
  * sub allocation
-- 
1.9.1

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[PATCH 06/19] drm/amdgpu: implement vm recovery function from shadow

[Chunming Zhou]

Change-Id: I46783043eecbe9fc9c2ce9230be1085aca3731bd
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  4 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 48 ++++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 53b7039..9cb6fda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -921,6 +921,8 @@ struct amdgpu_vm {
 
 	/* client id */
 	u64                     client_id;
+
+	struct fence            *shadow_sync_fence;
 };
 
 struct amdgpu_vm_id {
@@ -1011,6 +1013,8 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
 		       uint64_t addr);
 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 		      struct amdgpu_bo_va *bo_va);
+int amdgpu_vm_recover_page_table_from_shadow(struct amdgpu_device *adev,
+					     struct amdgpu_vm *vm);
 
 /*
  * context related structures
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 017274c..e6576c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -702,6 +702,52 @@ error_free:
 	return r;
 }
 
+int amdgpu_vm_recover_page_table_from_shadow(struct amdgpu_device *adev,
+					     struct amdgpu_vm *vm)
+{
+	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+	struct fence *fence;
+	uint64_t pt_idx;
+	int r;
+
+	if (!vm->page_directory->shadow)
+		return 0;
+
+	r = amdgpu_bo_reserve(vm->page_directory, false);
+	if (r)
+		return r;
+	vm->page_directory->shadow_flag = AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT;
+	r = amdgpu_bo_sync_between_bo_and_shadow(adev, ring,
+						 vm->page_directory,
+						 NULL, &fence);
+	if (r) {
+		DRM_ERROR("recover page table failed!\n");
+		goto err;
+	}
+	fence_put(vm->shadow_sync_fence);
+	vm->shadow_sync_fence = fence_get(fence);
+	fence_put(fence);
+	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
+		struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
+
+		if (!bo)
+			continue;
+		bo->shadow_flag = AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT;
+		r = amdgpu_bo_sync_between_bo_and_shadow(adev, ring, bo,
+							 NULL, &fence);
+		if (r) {
+			DRM_ERROR("recover page table failed!\n");
+			goto err;
+		}
+		fence_put(vm->shadow_sync_fence);
+		vm->shadow_sync_fence = fence_get(fence);
+		fence_put(fence);
+	}
+
+err:
+	amdgpu_bo_unreserve(vm->page_directory);
+	return r;
+}
 /**
  * amdgpu_vm_frag_ptes - add fragment information to PTEs
  *
@@ -1556,6 +1602,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	if (r)
 		goto error_free_page_directory;
 	vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
+	vm->shadow_sync_fence = NULL;
 
 	return 0;
 
@@ -1604,6 +1651,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 
 	amdgpu_bo_unref(&vm->page_directory);
 	fence_put(vm->page_directory_fence);
+	fence_put(vm->shadow_sync_fence);
 }
 
 /**
-- 
1.9.1

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[PATCH 07/19] drm/amdgpu: fix vm init error path

[Chunming Zhou]

Change-Id: Ie3d5440dc0d2d3a61d8e785ab08b8b91eda223db
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e6576c2..d6a2ddb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1581,7 +1581,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	r = amd_sched_entity_init(&ring->sched, &vm->entity,
 				  rq, amdgpu_sched_jobs);
 	if (r)
-		return r;
+		goto err;
 
 	vm->page_directory_fence = NULL;
 
@@ -1613,6 +1613,9 @@ error_free_page_directory:
 error_free_sched_entity:
 	amd_sched_entity_fini(&ring->sched, &vm->entity);
 
+err:
+	drm_free_large(vm->page_tables);
+
 	return r;
 }
 
-- 
1.9.1

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[PATCH 08/19] drm/amdgpu: add shadow_entity for shadow page table updates

[Chunming Zhou]

Change-Id: Id1bcb6701f1663e409b8ebe533ea9f8e7194227b
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ++++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9cb6fda..90805b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -921,7 +921,8 @@ struct amdgpu_vm {
 
 	/* client id */
 	u64                     client_id;
-
+	/* Scheduler entity for shadow page table updates */
+	struct amd_sched_entity	shadow_entity;
 	struct fence            *shadow_sync_fence;
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d6a2ddb..daf4098 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1577,11 +1577,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
 	ring_instance %= adev->vm_manager.vm_pte_num_rings;
 	ring = adev->vm_manager.vm_pte_rings[ring_instance];
+	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
+	r = amd_sched_entity_init(&ring->sched, &vm->shadow_entity,
+				  rq, amdgpu_sched_jobs);
+	if (r)
+		goto err;
+
 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 	r = amd_sched_entity_init(&ring->sched, &vm->entity,
 				  rq, amdgpu_sched_jobs);
 	if (r)
-		goto err;
+		goto err1;
 
 	vm->page_directory_fence = NULL;
 
@@ -1613,6 +1619,8 @@ error_free_page_directory:
 error_free_sched_entity:
 	amd_sched_entity_fini(&ring->sched, &vm->entity);
 
+err1:
+	amd_sched_entity_fini(&ring->sched, &vm->shadow_entity);
 err:
 	drm_free_large(vm->page_tables);
 
@@ -1633,6 +1641,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	struct amdgpu_bo_va_mapping *mapping, *tmp;
 	int i;
 
+	amd_sched_entity_fini(vm->shadow_entity.sched, &vm->shadow_entity);
 	amd_sched_entity_fini(vm->entity.sched, &vm->entity);
 
 	if (!RB_EMPTY_ROOT(&vm->va)) {
-- 
1.9.1

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[PATCH 09/19] drm/amdgpu: update pd shadow bo

[Chunming Zhou]

Change-Id: I8d0c625c9f1c9a16b8e2e915831590be5a9a5242
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 67 +++++++++++++++++++++++-----------
 2 files changed, 46 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 90805b4..c168212 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -883,6 +883,7 @@ struct amdgpu_ring {
 struct amdgpu_vm_pt {
 	struct amdgpu_bo_list_entry	entry;
 	uint64_t			addr;
+	uint64_t			shadow_addr;
 };
 
 struct amdgpu_vm {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index daf4098..8eb91a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -597,23 +597,13 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
 	return result;
 }
 
-/**
- * amdgpu_vm_update_pdes - make sure that page directory is valid
- *
- * @adev: amdgpu_device pointer
- * @vm: requested vm
- * @start: start of GPU address range
- * @end: end of GPU address range
- *
- * Allocates new page tables if necessary
- * and updates the page directory.
- * Returns 0 for success, error for failure.
- */
-int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
-				    struct amdgpu_vm *vm)
+int amdgpu_vm_update_page_directory_or_shadow(struct amdgpu_device *adev,
+					      struct amdgpu_vm *vm,
+					      bool shadow)
 {
 	struct amdgpu_ring *ring;
-	struct amdgpu_bo *pd = vm->page_directory;
+	struct amdgpu_bo *pd = shadow ? vm->page_directory->shadow :
+		vm->page_directory;
 	uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
 	uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
 	uint64_t last_pde = ~0, last_pt = ~0;
@@ -647,10 +637,17 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 		if (bo == NULL)
 			continue;
 
-		pt = amdgpu_bo_gpu_offset(bo);
-		if (vm->page_tables[pt_idx].addr == pt)
-			continue;
-		vm->page_tables[pt_idx].addr = pt;
+		if (!shadow) {
+			pt = amdgpu_bo_gpu_offset(bo);
+			if (vm->page_tables[pt_idx].addr == pt)
+				continue;
+			vm->page_tables[pt_idx].addr = pt;
+		} else {
+			pt = amdgpu_bo_gpu_offset(bo);
+			if (vm->page_tables[pt_idx].shadow_addr == pt)
+				continue;
+			vm->page_tables[pt_idx].shadow_addr = pt;
+		}
 
 		pde = pd_addr + pt_idx * 8;
 		if (((last_pde + 8 * count) != pde) ||
@@ -678,10 +675,12 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 
 	if (vm_update_params.ib->length_dw != 0) {
 		amdgpu_ring_pad_ib(ring, vm_update_params.ib);
-		amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
-				 AMDGPU_FENCE_OWNER_VM);
+		if (!shadow)
+			amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
+					 AMDGPU_FENCE_OWNER_VM);
 		WARN_ON(vm_update_params.ib->length_dw > ndw);
-		r = amdgpu_job_submit(job, ring, &vm->entity,
+		r = amdgpu_job_submit(job, ring,
+				      shadow ? &vm->shadow_entity : &vm->entity,
 				      AMDGPU_FENCE_OWNER_VM, &fence);
 		if (r)
 			goto error_free;
@@ -702,6 +701,29 @@ error_free:
 	return r;
 }
 
+/**
+ * amdgpu_vm_update_pdes - make sure that page directory is valid
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: requested vm
+ * @start: start of GPU address range
+ * @end: end of GPU address range
+ *
+ * Allocates new page tables if necessary
+ * and updates the page directory.
+ * Returns 0 for success, error for failure.
+ */
+int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
+				    struct amdgpu_vm *vm)
+{
+	int r;
+
+	r = amdgpu_vm_update_page_directory_or_shadow(adev, vm, true);
+	if (r)
+		return r;
+	return amdgpu_vm_update_page_directory_or_shadow(adev, vm, false);
+}
+
 int amdgpu_vm_recover_page_table_from_shadow(struct amdgpu_device *adev,
 					     struct amdgpu_vm *vm)
 {
@@ -1410,6 +1432,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 		entry->tv.shared = true;
 		entry->user_pages = NULL;
 		vm->page_tables[pt_idx].addr = 0;
+		vm->page_tables[pt_idx].shadow_addr = 0;
 	}
 
 	return 0;
-- 
1.9.1

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[PATCH 10/19] drm/amdgpu: update pt shadow

[Chunming Zhou]

Change-Id: I33b31cbe794c1c83b8e02e3069159c8204ac03e3
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 108 +++++++++++++++++++++------------
 1 file changed, 69 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8eb91a0..f317b09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -869,7 +869,8 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
 					*vm_update_params,
 				  struct amdgpu_vm *vm,
 				  uint64_t start, uint64_t end,
-				  uint64_t dst, uint32_t flags)
+				  uint64_t dst, uint32_t flags,
+				  bool shadow)
 {
 	const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
 
@@ -883,7 +884,8 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
 	/* initialize the variables */
 	addr = start;
 	pt_idx = addr >> amdgpu_vm_block_size;
-	pt = vm->page_tables[pt_idx].entry.robj;
+	pt = shadow ? vm->page_tables[pt_idx].entry.robj->shadow :
+		vm->page_tables[pt_idx].entry.robj;
 
 	if ((addr & ~mask) == (end & ~mask))
 		nptes = end - addr;
@@ -902,7 +904,8 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
 	/* walk over the address space and update the page tables */
 	while (addr < end) {
 		pt_idx = addr >> amdgpu_vm_block_size;
-		pt = vm->page_tables[pt_idx].entry.robj;
+		pt = shadow ? vm->page_tables[pt_idx].entry.robj->shadow :
+			vm->page_tables[pt_idx].entry.robj;
 
 		if ((addr & ~mask) == (end & ~mask))
 			nptes = end - addr;
@@ -937,31 +940,15 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
 			    cur_pe_end, cur_dst, flags);
 }
 
-/**
- * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
- *
- * @adev: amdgpu_device pointer
- * @exclusive: fence we need to sync to
- * @src: address where to copy page table entries from
- * @pages_addr: DMA addresses to use for mapping
- * @vm: requested vm
- * @start: start of mapped range
- * @last: last mapped entry
- * @flags: flags for the entries
- * @addr: addr to set the area to
- * @fence: optional resulting fence
- *
- * Fill in the page table entries between @start and @last.
- * Returns 0 for success, -EINVAL for failure.
- */
-static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
-				       struct fence *exclusive,
-				       uint64_t src,
-				       dma_addr_t *pages_addr,
-				       struct amdgpu_vm *vm,
-				       uint64_t start, uint64_t last,
-				       uint32_t flags, uint64_t addr,
-				       struct fence **fence)
+static int amdgpu_vm_bo_update_mapping_or_shadow(struct amdgpu_device *adev,
+						 struct fence *exclusive,
+						 uint64_t src,
+						 dma_addr_t *pages_addr,
+						 struct amdgpu_vm *vm,
+						 uint64_t start, uint64_t last,
+						 uint32_t flags, uint64_t addr,
+						 struct fence **fence,
+						 bool shadow)
 {
 	struct amdgpu_ring *ring;
 	void *owner = AMDGPU_FENCE_OWNER_VM;
@@ -1016,29 +1003,30 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 
 	vm_update_params.ib = &job->ibs[0];
 
-	r = amdgpu_sync_fence(adev, &job->sync, exclusive);
-	if (r)
-		goto error_free;
-
-	r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
-			     owner);
-	if (r)
-		goto error_free;
+	if (!shadow) {
+		r = amdgpu_sync_fence(adev, &job->sync, exclusive);
+		if (r)
+			goto error_free;
 
+		r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
+				     owner);
+		if (r)
+			goto error_free;
+	}
 	r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
 	if (r)
 		goto error_free;
 
 	amdgpu_vm_update_ptes(adev, &vm_update_params, vm, start,
-			      last + 1, addr, flags);
+			      last + 1, addr, flags, shadow);
 
 	amdgpu_ring_pad_ib(ring, vm_update_params.ib);
 	WARN_ON(vm_update_params.ib->length_dw > ndw);
-	r = amdgpu_job_submit(job, ring, &vm->entity,
+	r = amdgpu_job_submit(job, ring,
+			      shadow ? &vm->shadow_entity : &vm->entity,
 			      AMDGPU_FENCE_OWNER_VM, &f);
 	if (r)
 		goto error_free;
-
 	amdgpu_bo_fence(vm->page_directory, f, true);
 	if (fence) {
 		fence_put(*fence);
@@ -1053,6 +1041,48 @@ error_free:
 }
 
 /**
+ * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
+ *
+ * @adev: amdgpu_device pointer
+ * @exclusive: fence we need to sync to
+ * @src: address where to copy page table entries from
+ * @pages_addr: DMA addresses to use for mapping
+ * @vm: requested vm
+ * @start: start of mapped range
+ * @last: last mapped entry
+ * @flags: flags for the entries
+ * @addr: addr to set the area to
+ * @fence: optional resulting fence
+ *
+ * Fill in the page table entries between @start and @last.
+ * Returns 0 for success, -EINVAL for failure.
+ */
+static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
+				       struct fence *exclusive,
+				       uint64_t src,
+				       dma_addr_t *pages_addr,
+				       struct amdgpu_vm *vm,
+				       uint64_t start, uint64_t last,
+				       uint32_t flags, uint64_t addr,
+				       struct fence **fence)
+{
+	int r;
+
+	r = amdgpu_vm_bo_update_mapping_or_shadow(adev, exclusive, src,
+						  pages_addr, vm,
+						  start, last,
+						  flags, addr,
+						  fence, true);
+	if (r)
+		return r;
+	return amdgpu_vm_bo_update_mapping_or_shadow(adev, exclusive, src,
+						     pages_addr, vm,
+						     start, last,
+						     flags, addr,
+						     NULL, false);
+}
+
+/**
  * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
  *
  * @adev: amdgpu_device pointer
-- 
1.9.1

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[PATCH 11/19] drm/amd: add last fence in sched entity

[Chunming Zhou]

Change-Id: I68f67da25c482ac9dbd26e186cb953a539555a74
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 9 +++++++--
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index f96aa82..5dab231 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -134,6 +134,7 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
 	INIT_LIST_HEAD(&entity->list);
 	entity->rq = rq;
 	entity->sched = sched;
+	entity->last_fence = NULL;
 
 	spin_lock_init(&entity->queue_lock);
 	r = kfifo_alloc(&entity->job_queue, jobs * sizeof(void *), GFP_KERNEL);
@@ -219,6 +220,7 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
 
 	amd_sched_rq_remove_entity(rq, entity);
 	kfifo_free(&entity->job_queue);
+	fence_put(entity->last_fence);
 }
 
 static void amd_sched_entity_wakeup(struct fence *f, struct fence_cb *cb)
@@ -304,6 +306,7 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
 {
 	struct amd_gpu_scheduler *sched = sched_job->sched;
 	struct amd_sched_entity *entity = sched_job->s_entity;
+	struct amd_sched_fence *s_fence = sched_job->s_fence;
 	bool added, first = false;
 
 	spin_lock(&entity->queue_lock);
@@ -312,9 +315,11 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
 
 	if (added && kfifo_len(&entity->job_queue) == sizeof(sched_job))
 		first = true;
-
+	if (added) {
+		fence_put(entity->last_fence);
+		entity->last_fence = fence_get(&s_fence->finished);
+	}
 	spin_unlock(&entity->queue_lock);
-
 	/* first job wakes up scheduler */
 	if (first) {
 		/* Add the entity to the run queue */
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
index 7cbbbfb..256a851 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
@@ -49,6 +49,7 @@ struct amd_sched_entity {
 
 	atomic_t			fence_seq;
 	uint64_t                        fence_context;
+	struct fence                    *last_fence;
 
 	struct fence			*dependency;
 	struct fence_cb			cb;
-- 
1.9.1

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[PATCH 12/19] drm/amdgpu: link all vm clients

[Chunming Zhou]

Add vm client to list tail when creating it, move to head while submit to scheduler.

Change-Id: I0625092f918853303a5ee97ea2eac87fb790ed69
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 6 ++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     | 4 ++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 3 +++
 4 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c168212..16e9a79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -902,6 +902,9 @@ struct amdgpu_vm {
 	/* BO mappings freed, but not yet updated in the PT */
 	struct list_head	freed;
 
+	/* vm itself list */
+	struct list_head	list;
+
 	/* contains the page directory */
 	struct amdgpu_bo	*page_directory;
 	unsigned		max_pde_used;
@@ -2176,6 +2179,9 @@ struct amdgpu_device {
 	struct kfd_dev          *kfd;
 
 	struct amdgpu_virtualization virtualization;
+
+	/* link all vm clients */
+	struct list_head		vm_list;
 };
 
 bool amdgpu_device_is_px(struct drm_device *dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 3434098..8310853 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -860,7 +860,10 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 			    union drm_amdgpu_cs *cs)
 {
+	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
+	struct amdgpu_vm *vm = &fpriv->vm;
 	struct amdgpu_ring *ring = p->job->ring;
+	struct amdgpu_device *adev = ring->adev;
 	struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
 	struct amdgpu_job *job;
 	int r;
@@ -883,6 +886,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 
 	trace_amdgpu_cs_ioctl(job);
 	amd_sched_entity_push_job(&job->base);
+	list_move(&vm->list, &adev->vm_list);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d1dc471..ee6f682 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1559,6 +1559,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 	spin_lock_init(&adev->gc_cac_idx_lock);
 	spin_lock_init(&adev->audio_endpt_idx_lock);
 
+	INIT_LIST_HEAD(&adev->vm_list);
+
 	adev->rmmio_base = pci_resource_start(adev->pdev, 5);
 	adev->rmmio_size = pci_resource_len(adev->pdev, 5);
 	adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f317b09..d9f24a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1614,6 +1614,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	INIT_LIST_HEAD(&vm->invalidated);
 	INIT_LIST_HEAD(&vm->cleared);
 	INIT_LIST_HEAD(&vm->freed);
+	INIT_LIST_HEAD(&vm->list);
 
 	pd_size = amdgpu_vm_directory_size(adev);
 	pd_entries = amdgpu_vm_num_pdes(adev);
@@ -1662,6 +1663,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 		goto error_free_page_directory;
 	vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
 	vm->shadow_sync_fence = NULL;
+	list_add_tail(&vm->list, &adev->vm_list);
 
 	return 0;
 
@@ -1694,6 +1696,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	struct amdgpu_bo_va_mapping *mapping, *tmp;
 	int i;
 
+	list_del(&vm->list);
 	amd_sched_entity_fini(vm->shadow_entity.sched, &vm->shadow_entity);
 	amd_sched_entity_fini(vm->entity.sched, &vm->entity);
 
-- 
1.9.1

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[PATCH 13/19] drm/amdgpu: add vm_list_lock

[Chunming Zhou]

To lock adev->vm_list.

Change-Id: I74d309eca9c22d190dd4072c69d26fa7fdea8884
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     | 2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 4 ++++
 4 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 16e9a79..bd74bd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2182,6 +2182,7 @@ struct amdgpu_device {
 
 	/* link all vm clients */
 	struct list_head		vm_list;
+	spinlock_t			vm_list_lock;
 };
 
 bool amdgpu_device_is_px(struct drm_device *dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8310853..ef73883 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -886,7 +886,9 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 
 	trace_amdgpu_cs_ioctl(job);
 	amd_sched_entity_push_job(&job->base);
+	spin_lock(&adev->vm_list_lock);
 	list_move(&vm->list, &adev->vm_list);
+	spin_unlock(&adev->vm_list_lock);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ee6f682..8e90ffc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1560,6 +1560,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 	spin_lock_init(&adev->audio_endpt_idx_lock);
 
 	INIT_LIST_HEAD(&adev->vm_list);
+	spin_lock_init(&adev->vm_list_lock);
 
 	adev->rmmio_base = pci_resource_start(adev->pdev, 5);
 	adev->rmmio_size = pci_resource_len(adev->pdev, 5);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d9f24a2..6386918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1663,7 +1663,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 		goto error_free_page_directory;
 	vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
 	vm->shadow_sync_fence = NULL;
+	spin_lock(&adev->vm_list_lock);
 	list_add_tail(&vm->list, &adev->vm_list);
+	spin_unlock(&adev->vm_list_lock);
 
 	return 0;
 
@@ -1696,7 +1698,9 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	struct amdgpu_bo_va_mapping *mapping, *tmp;
 	int i;
 
+	spin_lock(&adev->vm_list_lock);
 	list_del(&vm->list);
+	spin_unlock(&adev->vm_list_lock);
 	amd_sched_entity_fini(vm->shadow_entity.sched, &vm->shadow_entity);
 	amd_sched_entity_fini(vm->entity.sched, &vm->entity);
 
-- 
1.9.1

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[PATCH 14/19] drm/amd: add block entity function

[Chunming Zhou]

Change-Id: Ia0378640962eef362569e0bbe090aea1ca083a55
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 24 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |  3 +++
 2 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index 5dab231..f750d4a 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -110,6 +110,26 @@ amd_sched_rq_select_entity(struct amd_sched_rq *rq)
 }
 
 /**
+ * block all entity of this run queue
+ *
+ * @rq		The run queue to check.
+ *
+ */
+int amd_sched_rq_block_entity(struct amd_sched_rq *rq, bool block)
+{
+	struct amd_sched_entity *entity;
+
+	spin_lock(&rq->lock);
+
+	list_for_each_entry(entity, &rq->entities, list)
+		entity->block = block;
+
+	spin_unlock(&rq->lock);
+
+	return 0;
+}
+
+/**
  * Init a context entity used by scheduler when submit to HW ring.
  *
  * @sched	The pointer to the scheduler
@@ -135,6 +155,7 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
 	entity->rq = rq;
 	entity->sched = sched;
 	entity->last_fence = NULL;
+	entity->block = false;
 
 	spin_lock_init(&entity->queue_lock);
 	r = kfifo_alloc(&entity->job_queue, jobs * sizeof(void *), GFP_KERNEL);
@@ -187,6 +208,9 @@ static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity)
  */
 static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity)
 {
+	if (entity->block)
+		return false;
+
 	if (kfifo_is_empty(&entity->job_queue))
 		return false;
 
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
index 256a851..8ea0374 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
@@ -53,6 +53,8 @@ struct amd_sched_entity {
 
 	struct fence			*dependency;
 	struct fence_cb			cb;
+
+	bool                            block;
 };
 
 /**
@@ -156,4 +158,5 @@ int amd_sched_job_init(struct amd_sched_job *job,
 		       void *owner);
 void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched);
 void amd_sched_job_recovery(struct amd_gpu_scheduler *sched);
+int amd_sched_rq_block_entity(struct amd_sched_rq *rq, bool block);
 #endif
-- 
1.9.1

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[PATCH 15/19] drm/amdgpu: add shadow fence owner

[Chunming Zhou]

Normal cs doesn't need to care shadow jobs.

Change-Id: I63f0a802438cafff336500656c5a367074e4182d
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>

Conflicts:
	drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c |  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 22 ++++++++++++++++------
 3 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bd74bd0..7e96a4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -378,6 +378,8 @@ struct amdgpu_fence_driver {
 /* some special values for the owner field */
 #define AMDGPU_FENCE_OWNER_UNDEFINED	((void*)0ul)
 #define AMDGPU_FENCE_OWNER_VM		((void*)1ul)
+/* don't need to care vm shadow fence, except eviction */
+#define AMDGPU_FENCE_OWNER_VM_SHADOW	((void*)2ul)
 
 #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 5c8d302..b7e0f3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -213,6 +213,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
 			if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
 			    fence_owner == owner)
 				continue;
+
+			if (fence_owner == AMDGPU_FENCE_OWNER_VM_SHADOW)
+				continue;
 		}
 
 		r = amdgpu_sync_fence(adev, sync, f);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6386918..664f055 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -679,9 +679,14 @@ int amdgpu_vm_update_page_directory_or_shadow(struct amdgpu_device *adev,
 			amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
 					 AMDGPU_FENCE_OWNER_VM);
 		WARN_ON(vm_update_params.ib->length_dw > ndw);
-		r = amdgpu_job_submit(job, ring,
-				      shadow ? &vm->shadow_entity : &vm->entity,
-				      AMDGPU_FENCE_OWNER_VM, &fence);
+		if (shadow)
+			r = amdgpu_job_submit(job, ring,
+					      &vm->shadow_entity,
+					      AMDGPU_FENCE_OWNER_VM_SHADOW, &fence);
+		else
+			r = amdgpu_job_submit(job, ring, &vm->entity,
+					      AMDGPU_FENCE_OWNER_VM, &fence);
+
 		if (r)
 			goto error_free;
 
@@ -1022,9 +1027,14 @@ static int amdgpu_vm_bo_update_mapping_or_shadow(struct amdgpu_device *adev,
 
 	amdgpu_ring_pad_ib(ring, vm_update_params.ib);
 	WARN_ON(vm_update_params.ib->length_dw > ndw);
-	r = amdgpu_job_submit(job, ring,
-			      shadow ? &vm->shadow_entity : &vm->entity,
-			      AMDGPU_FENCE_OWNER_VM, &f);
+	if (shadow)
+		r = amdgpu_job_submit(job, ring,
+				      &vm->shadow_entity,
+				      AMDGPU_FENCE_OWNER_VM_SHADOW, &f);
+	else
+		r = amdgpu_job_submit(job, ring, &vm->entity,
+				      AMDGPU_FENCE_OWNER_VM, &f);
+
 	if (r)
 		goto error_free;
 	amdgpu_bo_fence(vm->page_directory, f, true);
-- 
1.9.1

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[PATCH 16/19] drm/amd: block entity

[Chunming Zhou]

Change-Id: Iba210e0d007a249a90f955f5ac9c3803cc40def2
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 7 ++++++-
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index f750d4a..78d34d5 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -109,6 +109,11 @@ amd_sched_rq_select_entity(struct amd_sched_rq *rq)
 	return NULL;
 }
 
+void amd_sched_block_entity(struct amd_sched_entity *entity, bool block)
+{
+	entity->block = block;
+}
+
 /**
  * block all entity of this run queue
  *
@@ -122,7 +127,7 @@ int amd_sched_rq_block_entity(struct amd_sched_rq *rq, bool block)
 	spin_lock(&rq->lock);
 
 	list_for_each_entry(entity, &rq->entities, list)
-		entity->block = block;
+		amd_sched_block_entity(entity, block);
 
 	spin_unlock(&rq->lock);
 
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
index 8ea0374..da01051 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
@@ -159,4 +159,5 @@ int amd_sched_job_init(struct amd_sched_job *job,
 void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched);
 void amd_sched_job_recovery(struct amd_gpu_scheduler *sched);
 int amd_sched_rq_block_entity(struct amd_sched_rq *rq, bool block);
+void amd_sched_block_entity(struct amd_sched_entity *entity, bool block);
 #endif
-- 
1.9.1

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[PATCH 17/19] drm/amdgpu: recover page tables after gpu reset

[Chunming Zhou]

Change-Id: I963598ba6eb44bc8620d70e026c0175d1a1de120
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 77 +++++++++++++++++++++++++++++-
 1 file changed, 76 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8e90ffc..f669654 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2160,18 +2160,93 @@ retry:
 		amdgpu_atombios_scratch_regs_restore(adev);
 	}
 	if (!r) {
+		struct amdgpu_ring *buffer_ring = adev->mman.buffer_funcs_ring;
+
 		amdgpu_irq_gpu_reset_resume_helper(adev);
 		r = amdgpu_ib_ring_tests(adev);
 		if (r) {
 			dev_err(adev->dev, "ib ring test failed (%d).\n", r);
 			r = amdgpu_suspend(adev);
+			need_full_reset = true;
 			goto retry;
 		}
-
+		/**
+		 * recovery vm page tables, since we cannot depend on VRAM is no problem
+		 * after gpu full reset.
+		 */
+		if (need_full_reset && !(adev->flags & AMD_IS_APU)) {
+			struct amdgpu_vm *vm, *tmp;
+			struct amdgpu_ring *ring;
+			struct fence *fence = NULL;
+			int i;
+
+			DRM_INFO("recover page table from shadow\n");
+			for (i = 0; i < adev->vm_manager.vm_pte_num_rings; i++) {
+				ring = adev->vm_manager.vm_pte_rings[i];
+				amd_sched_rq_block_entity(
+					&ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL], true);
+				amd_sched_rq_block_entity(
+					&ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL], true);
+			}
+			spin_lock(&adev->vm_list_lock);
+			list_for_each_entry_safe(vm, tmp, &adev->vm_list, list) {
+				spin_unlock(&adev->vm_list_lock);
+				amd_sched_block_entity(&vm->shadow_entity, false);
+				spin_lock(&adev->vm_list_lock);
+			}
+			spin_unlock(&adev->vm_list_lock);
+			for (i = 0; i < adev->vm_manager.vm_pte_num_rings; i++) {
+				ring = adev->vm_manager.vm_pte_rings[i];
+				kthread_unpark(ring->sched.thread);
+			}
+			spin_lock(&adev->vm_list_lock);
+			list_for_each_entry_safe(vm, tmp, &adev->vm_list, list) {
+				spin_unlock(&adev->vm_list_lock);
+				/* wait for all shadow jobs finished */
+				if (vm->shadow_entity.last_fence)
+					fence_wait(vm->shadow_entity.last_fence, false);
+				spin_lock(&adev->vm_list_lock);
+			}
+			spin_unlock(&adev->vm_list_lock);
+			for (i = 0; i < adev->vm_manager.vm_pte_num_rings; i++) {
+				ring = adev->vm_manager.vm_pte_rings[i];
+				kthread_park(ring->sched.thread);
+				amd_sched_rq_block_entity(
+					&ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL], true);
+				amd_sched_rq_block_entity(
+					&ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL], true);
+			}
+			amd_sched_block_entity(&adev->mman.entity, false);
+			kthread_unpark(buffer_ring->sched.thread);
+			spin_lock(&adev->vm_list_lock);
+			list_for_each_entry_safe(vm, tmp, &adev->vm_list, list) {
+				spin_unlock(&adev->vm_list_lock);
+				amdgpu_vm_recover_page_table_from_shadow(adev, vm);
+				if (vm->shadow_sync_fence) {
+					fence_put(fence);
+					fence = fence_get(vm->shadow_sync_fence);
+				}
+				spin_lock(&adev->vm_list_lock);
+			}
+			spin_unlock(&adev->vm_list_lock);
+			if (fence)
+				fence_wait(fence, false);
+			fence_put(fence);
+			for (i = 0; i < adev->vm_manager.vm_pte_num_rings; i++) {
+				ring = adev->vm_manager.vm_pte_rings[i];
+				kthread_park(ring->sched.thread);
+				amd_sched_rq_block_entity(
+					&ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL], false);
+				amd_sched_rq_block_entity(
+					&ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL], false);
+			}
+		}
 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 			struct amdgpu_ring *ring = adev->rings[i];
 			if (!ring)
 				continue;
+
+			DRM_INFO("ring:%d recover jobs\n", ring->idx);
 			amd_sched_job_recovery(&ring->sched);
 			kthread_unpark(ring->sched.thread);
 		}
-- 
1.9.1

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[PATCH 18/19] drm/amdgpu: add need backup function

[Chunming Zhou]

Change-Id: I76e2552078c9ae11b7f2a1769025230f61733659
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7e96a4c..05b06f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2457,6 +2457,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 
 /* Common functions */
 int amdgpu_gpu_reset(struct amdgpu_device *adev);
+bool amdgpu_need_backup(struct amdgpu_device *adev);
 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
 bool amdgpu_card_posted(struct amdgpu_device *adev);
 void amdgpu_update_display_priority(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f669654..42a6193 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2083,6 +2083,14 @@ static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
 	return 0;
 }
 
+bool amdgpu_need_backup(struct amdgpu_device *adev)
+{
+	if (adev->flags & AMD_IS_APU)
+		return false;
+
+	return amdgpu_lockup_timeout > 0 ? true : false;
+}
+
 /**
  * amdgpu_gpu_reset - reset the asic
  *
-- 
1.9.1

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[PATCH 19/19] drm/amdgpu: add backup condition for vm

[Chunming Zhou]

Change-Id: I73aa32cda17cd1039232125afa4aad299b264705
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 664f055..b279e04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -723,9 +723,11 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 {
 	int r;
 
-	r = amdgpu_vm_update_page_directory_or_shadow(adev, vm, true);
-	if (r)
-		return r;
+	if (amdgpu_need_backup(adev)) {
+		r = amdgpu_vm_update_page_directory_or_shadow(adev, vm, true);
+		if (r)
+			return r;
+	}
 	return amdgpu_vm_update_page_directory_or_shadow(adev, vm, false);
 }
 
@@ -1078,13 +1080,15 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 {
 	int r;
 
-	r = amdgpu_vm_bo_update_mapping_or_shadow(adev, exclusive, src,
-						  pages_addr, vm,
-						  start, last,
-						  flags, addr,
-						  fence, true);
-	if (r)
-		return r;
+	if (amdgpu_need_backup(adev)) {
+		r = amdgpu_vm_bo_update_mapping_or_shadow(adev, exclusive, src,
+							  pages_addr, vm,
+							  start, last,
+							  flags, addr,
+							  fence, true);
+		if (r)
+			return r;
+	}
 	return amdgpu_vm_bo_update_mapping_or_shadow(adev, exclusive, src,
 						     pages_addr, vm,
 						     start, last,
@@ -1450,7 +1454,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 				     AMDGPU_GPU_PAGE_SIZE, true,
 				     AMDGPU_GEM_DOMAIN_VRAM,
 				     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
-				     AMDGPU_GEM_CREATE_SHADOW,
+				     (amdgpu_need_backup(adev) ?
+				      AMDGPU_GEM_CREATE_SHADOW : 0),
 				     NULL, resv, &pt);
 		if (r)
 			goto error_free;
@@ -1658,7 +1663,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	r = amdgpu_bo_create(adev, pd_size, align, true,
 			     AMDGPU_GEM_DOMAIN_VRAM,
 			     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
-			     AMDGPU_GEM_CREATE_SHADOW,
+			     (amdgpu_need_backup(adev) ?
+			      AMDGPU_GEM_CREATE_SHADOW : 0),
 			     NULL, NULL, &vm->page_directory);
 	if (r)
 		goto error_free_sched_entity;
-- 
1.9.1

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Re: [PATCH 00/19] shadow page table support V2

[Edward O'Callaghan]

[-- Attachment #1.1.1: Type: text/plain, Size: 2574 bytes --]



On 08/05/2016 07:38 PM, Chunming Zhou wrote:
> Since we cannot make sure VRAM is safe after gpu reset, page table backup
> is neccessary, shadow page table is sense way to recovery page talbe when
> gpu reset happens.

Hmm, bit of a nitpick but the following is perhaps a little better wording:

s/Since we cannot ensure VRAM is consistent after a GPU reset, page
table shadowing is necessary. Shadowed page tables are, in a sense, a
method to recover the consistent state of the page tables before the
reset occurred.


> We need to allocate GTT bo as the shadow of VRAM bo when creating page table,
> and make them same. After gpu reset, we will need to use SDMA to copy GTT bo
s/make them same/make them the same/

Hope this is helpful,
Kind Regards,
Edward.

> content to VRAM bo, then page table will be recoveried. 
> 
> V2:
> Shadow bo uses a shadow entity running on normal run queue, after gpu reset,
> we need to wait for all shadow jobs finished first, then recovery page table from shadow.
> 
> Chunming Zhou (19):
>   drm/amdgpu: add shadow bo support
>   drm/amdgpu: validate shadow as well when validating bo
>   drm/amdgpu: allocate shadow for pd/pt bo
>   drm/amdgpu: add shadow flag
>   drm/amdgpu: sync bo and shadow
>   drm/amdgpu: implement vm recovery function from shadow
>   drm/amdgpu: fix vm init error path
>   drm/amdgpu: add shadow_entity for shadow page table updates
>   drm/amdgpu: update pd shadow bo
>   drm/amdgpu: update pt shadow
>   drm/amd: add last fence in sched entity
>   drm/amdgpu: link all vm clients
>   drm/amdgpu: add vm_list_lock
>   drm/amd: add block entity function
>   drm/amdgpu: add shadow fence owner
>   drm/amd: block entity
>   drm/amdgpu: recover page tables after gpu reset
>   drm/amdgpu: add need backup function
>   drm/amdgpu: add backup condition for vm
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  25 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  82 +++++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  88 ++++++++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c    | 104 +++++++++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h    |   5 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c      |   3 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c        | 270 +++++++++++++++++++-------
>  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  38 +++-
>  drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |   5 +
>  include/uapi/drm/amdgpu_drm.h                 |   2 +
>  10 files changed, 519 insertions(+), 103 deletions(-)
> 


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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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Re: [PATCH 00/19] shadow page table support V2

[Christian König]

Again patch #7 looks like an unrelated fix to me. Please split that from 
the patch set, add my rb and commit it preliminary.

Apart from that patch #1:
> +	amdgpu_ttm_placement_init(adev, &placement,
> +				  placements, AMDGPU_GEM_DOMAIN_GTT,
> +				  AMDGPU_GEM_CREATE_CPU_GTT_USWC);
> +
> +	return amdgpu_bo_create_restricted(adev, size, byte_align, true,
> +					   AMDGPU_GEM_DOMAIN_GTT,
> +					   AMDGPU_GEM_CREATE_CPU_GTT_USWC,
> +					   NULL, &placement,
> +					   bo->tbo.resv,
> +					   &bo->shadow);
You need to set bo->shadow->parent to the parent BO when you use the 
reservation object here. See the VM code on how to do this, otherwise 
TTM could free the parent reservation object first and the crash when it 
wants to free the shadow.

Additional to that do we really need the placement here? That looks 
quite odd.

Patch #2, #3 is Reviewed-by: Christian König <christian.koenig@amd.com>.

Patch #4:
> +enum amdgpu_shadow_flag {
> +	AMDGPU_SHADOW_FLAG_SYNC_TO_NONE = 0,
> +	AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT,
> +	AMDGPU_SHADOW_FLAG_SYNC_TO_SHADOW,
> +};
Either use defines here.

> +	/* indicate if need to sync between bo and shadow */
> +	u32                             shadow_flag;
Or the named enum here.

I would use the named enum, cuase it doesn't make sense to combine them 
as flags. And renaming it to something like "backup_shadow" would 
probably make sense as well.

Patch #5:
> +	r = amdgpu_bo_pin(bo, bo->prefered_domains, &bo_addr);
> +	if (r) {
> +		DRM_ERROR("Failed to pin bo object\n");
> +		goto err1;
> +	}
> +	r = amdgpu_bo_pin(bo->shadow, bo->shadow->prefered_domains, &shadow_addr);
> +	if (r) {
> +		DRM_ERROR("Failed to pin bo shadow object\n");
> +		goto err2;
> +	}
Don't use pin here, just use amdgpu_bo_offset when you need the offset.

I need to work on the S3 issue again now, going to come back to this 
patch set when I have more time.

Regards,
Christian.

Am 05.08.2016 um 11:38 schrieb Chunming Zhou:
> Since we cannot make sure VRAM is safe after gpu reset, page table backup
> is neccessary, shadow page table is sense way to recovery page talbe when
> gpu reset happens.
> We need to allocate GTT bo as the shadow of VRAM bo when creating page table,
> and make them same. After gpu reset, we will need to use SDMA to copy GTT bo
> content to VRAM bo, then page table will be recoveried.
>
> V2:
> Shadow bo uses a shadow entity running on normal run queue, after gpu reset,
> we need to wait for all shadow jobs finished first, then recovery page table from shadow.
>
> Chunming Zhou (19):
>    drm/amdgpu: add shadow bo support
>    drm/amdgpu: validate shadow as well when validating bo
>    drm/amdgpu: allocate shadow for pd/pt bo
>    drm/amdgpu: add shadow flag
>    drm/amdgpu: sync bo and shadow
>    drm/amdgpu: implement vm recovery function from shadow
>    drm/amdgpu: fix vm init error path
>    drm/amdgpu: add shadow_entity for shadow page table updates
>    drm/amdgpu: update pd shadow bo
>    drm/amdgpu: update pt shadow
>    drm/amd: add last fence in sched entity
>    drm/amdgpu: link all vm clients
>    drm/amdgpu: add vm_list_lock
>    drm/amd: add block entity function
>    drm/amdgpu: add shadow fence owner
>    drm/amd: block entity
>    drm/amdgpu: recover page tables after gpu reset
>    drm/amdgpu: add need backup function
>    drm/amdgpu: add backup condition for vm
>
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  25 +++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  82 +++++---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  88 ++++++++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c    | 104 +++++++++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.h    |   5 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c      |   3 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c        | 270 +++++++++++++++++++-------
>   drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  38 +++-
>   drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |   5 +
>   include/uapi/drm/amdgpu_drm.h                 |   2 +
>   10 files changed, 519 insertions(+), 103 deletions(-)
>

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Re: [PATCH 00/19] shadow page table support V2

[zhoucm1]

On 2016年08月08日 19:04, Christian König wrote:
> Apart from that patch #1:
>> + amdgpu_ttm_placement_init(adev, &placement,
>> +                  placements, AMDGPU_GEM_DOMAIN_GTT,
>> +                  AMDGPU_GEM_CREATE_CPU_GTT_USWC);
>> +
>> +    return amdgpu_bo_create_restricted(adev, size, byte_align, true,
>> +                       AMDGPU_GEM_DOMAIN_GTT,
>> +                       AMDGPU_GEM_CREATE_CPU_GTT_USWC,
>> +                       NULL, &placement,
>> +                       bo->tbo.resv,
>> +                       &bo->shadow);
> You need to set bo->shadow->parent to the parent BO when you use the 
> reservation object here. See the VM code on how to do this, otherwise 
> TTM could free the parent reservation object first and the crash when 
> it wants to free the shadow.
I've tried to add parent for shadow bo, I trouble how to free shadow bo.
My old though is the life cycle of shadow bo is same as parent. That 
means parent bo refers shadow bo when initialization, unref shadow bo 
when BO is freeing, other people cannot refer shadow bo.

So if we set bo->shadow->parent and reference it, then the bo cannot be 
freed.

Regards,
David Zhou
>
> Additional to that do we really need the placement here? That looks 
> quite odd.

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Re: [PATCH 00/19] shadow page table support V2

[zhoucm1]

On 2016年08月08日 19:04, Christian König wrote:
> I need to work on the S3 issue again now, going to come back to this 
> patch set when I have more time.
I've addressed your previous comments, are you free? how about the other 
patches?

Thanks,
David Zhou
>
> Regards,
> Christian.

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Re: [PATCH 00/19] shadow page table support V2

[Christian König]

Am 10.08.2016 um 08:02 schrieb zhoucm1:
>
>
> On 2016年08月08日 19:04, Christian König wrote:
>> I need to work on the S3 issue again now, going to come back to this 
>> patch set when I have more time.
> I've addressed your previous comments, are you free?

Well if you figure out why the heck the UVD engine sometimes crashes 
since I changed how usage is detected I'm all yours :)

> how about the other patches?

They looked rather good to me, maybe Alex or somebody else could take a 
look as well.

What you should keep in mind is a) please try to avoid using the 
scheduler for recovery, I really don't like the idea that we start to 
mess with userspace submissions before anything else is stable again.

And b) when we use the same reservation object for two BOs we need to 
set the parent, otherwise we can run into a race which gets freed first. 
That applies even when the BOs are reference counted like your shadow 
BOs are.

>
> Thanks,
> David Zhou
>>
>> Regards,
>> Christian.
>
> _______________________________________________
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RE: [PATCH 00/19] shadow page table support V2

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Wednesday, August 10, 2016 7:14 AM
> To: Zhou, David(ChunMing); amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 00/19] shadow page table support V2
> 
> Am 10.08.2016 um 08:02 schrieb zhoucm1:
> >
> >
> > On 2016年08月08日 19:04, Christian König wrote:
> >> I need to work on the S3 issue again now, going to come back to this
> >> patch set when I have more time.
> > I've addressed your previous comments, are you free?
> 
> Well if you figure out why the heck the UVD engine sometimes crashes
> since I changed how usage is detected I'm all yours :)
> 
> > how about the other patches?
> 
> They looked rather good to me, maybe Alex or somebody else could take a
> look as well.
> 
> What you should keep in mind is a) please try to avoid using the
> scheduler for recovery, I really don't like the idea that we start to
> mess with userspace submissions before anything else is stable again.
> 
> And b) when we use the same reservation object for two BOs we need to
> set the parent, otherwise we can run into a race which gets freed first.
> That applies even when the BOs are reference counted like your shadow
> BOs are.
> 

The patches look ok to me as well.  I agree with Christian about avoiding the scheduler for recovery.

Alex

> >
> > Thanks,
> > David Zhou
> >>
> >> Regards,
> >> Christian.
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 
> 
> _______________________________________________
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Re: [PATCH 06/19] drm/amdgpu: implement vm recovery function from shadow

[Christian König]

Am 05.08.2016 um 11:38 schrieb Chunming Zhou:
> Change-Id: I46783043eecbe9fc9c2ce9230be1085aca3731bd
> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  4 +++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 48 ++++++++++++++++++++++++++++++++++
>   2 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 53b7039..9cb6fda 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -921,6 +921,8 @@ struct amdgpu_vm {
>   
>   	/* client id */
>   	u64                     client_id;
> +
> +	struct fence            *shadow_sync_fence;
>   };
>   
>   struct amdgpu_vm_id {
> @@ -1011,6 +1013,8 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
>   		       uint64_t addr);
>   void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
>   		      struct amdgpu_bo_va *bo_va);
> +int amdgpu_vm_recover_page_table_from_shadow(struct amdgpu_device *adev,
> +					     struct amdgpu_vm *vm);
>   
>   /*
>    * context related structures
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 017274c..e6576c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -702,6 +702,52 @@ error_free:
>   	return r;
>   }
>   
> +int amdgpu_vm_recover_page_table_from_shadow(struct amdgpu_device *adev,
> +					     struct amdgpu_vm *vm)
> +{
> +	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> +	struct fence *fence;
> +	uint64_t pt_idx;
> +	int r;
> +
> +	if (!vm->page_directory->shadow)
> +		return 0;
> +
> +	r = amdgpu_bo_reserve(vm->page_directory, false);
> +	if (r)
> +		return r;

I think that the caller should reserve the BOs here.

Especially during CS we only want to reserve everything once.

BTW: How do we handle swapping the PD/PTs in and out?

E.g. we don't need to copy them from VRAM to GART any more.

Regards,
Christian.

> +	vm->page_directory->shadow_flag = AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT;
> +	r = amdgpu_bo_sync_between_bo_and_shadow(adev, ring,
> +						 vm->page_directory,
> +						 NULL, &fence);
> +	if (r) {
> +		DRM_ERROR("recover page table failed!\n");
> +		goto err;
> +	}
> +	fence_put(vm->shadow_sync_fence);
> +	vm->shadow_sync_fence = fence_get(fence);
> +	fence_put(fence);
> +	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
> +		struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
> +
> +		if (!bo)
> +			continue;
> +		bo->shadow_flag = AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT;
> +		r = amdgpu_bo_sync_between_bo_and_shadow(adev, ring, bo,
> +							 NULL, &fence);
> +		if (r) {
> +			DRM_ERROR("recover page table failed!\n");
> +			goto err;
> +		}
> +		fence_put(vm->shadow_sync_fence);
> +		vm->shadow_sync_fence = fence_get(fence);
> +		fence_put(fence);
> +	}
> +
> +err:
> +	amdgpu_bo_unreserve(vm->page_directory);
> +	return r;
> +}
>   /**
>    * amdgpu_vm_frag_ptes - add fragment information to PTEs
>    *
> @@ -1556,6 +1602,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
>   	if (r)
>   		goto error_free_page_directory;
>   	vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
> +	vm->shadow_sync_fence = NULL;
>   
>   	return 0;
>   
> @@ -1604,6 +1651,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
>   
>   	amdgpu_bo_unref(&vm->page_directory);
>   	fence_put(vm->page_directory_fence);
> +	fence_put(vm->shadow_sync_fence);
>   }
>   
>   /**


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Re: [PATCH 06/19] drm/amdgpu: implement vm recovery function from shadow

[zhoucm1]

On 2016年08月11日 16:39, Christian König wrote:
> Am 05.08.2016 um 11:38 schrieb Chunming Zhou:
>> Change-Id: I46783043eecbe9fc9c2ce9230be1085aca3731bd
>> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  4 +++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 48 
>> ++++++++++++++++++++++++++++++++++
>>   2 files changed, 52 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 53b7039..9cb6fda 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -921,6 +921,8 @@ struct amdgpu_vm {
>>         /* client id */
>>       u64                     client_id;
>> +
>> +    struct fence            *shadow_sync_fence;
>>   };
>>     struct amdgpu_vm_id {
>> @@ -1011,6 +1013,8 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
>>                  uint64_t addr);
>>   void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
>>                 struct amdgpu_bo_va *bo_va);
>> +int amdgpu_vm_recover_page_table_from_shadow(struct amdgpu_device 
>> *adev,
>> +                         struct amdgpu_vm *vm);
>>     /*
>>    * context related structures
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 017274c..e6576c2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -702,6 +702,52 @@ error_free:
>>       return r;
>>   }
>>   +int amdgpu_vm_recover_page_table_from_shadow(struct amdgpu_device 
>> *adev,
>> +                         struct amdgpu_vm *vm)
>> +{
>> +    struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
>> +    struct fence *fence;
>> +    uint64_t pt_idx;
>> +    int r;
>> +
>> +    if (!vm->page_directory->shadow)
>> +        return 0;
>> +
>> +    r = amdgpu_bo_reserve(vm->page_directory, false);
>> +    if (r)
>> +        return r;
>
> I think that the caller should reserve the BOs here.
>
> Especially during CS we only want to reserve everything once.

This function is called in gpu reset, not in cs ioctl.

>
> BTW: How do we handle swapping the PD/PTs in and out?
>
> E.g. we don't need to copy them from VRAM to GART any more.

Yes, we only need to copy from GART to VRAM when gpu reset.

Regards,
David Zhou
>
> Regards,
> Christian.
>
>> +    vm->page_directory->shadow_flag = 
>> AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT;
>> +    r = amdgpu_bo_sync_between_bo_and_shadow(adev, ring,
>> +                         vm->page_directory,
>> +                         NULL, &fence);
>> +    if (r) {
>> +        DRM_ERROR("recover page table failed!\n");
>> +        goto err;
>> +    }
>> +    fence_put(vm->shadow_sync_fence);
>> +    vm->shadow_sync_fence = fence_get(fence);
>> +    fence_put(fence);
>> +    for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
>> +        struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
>> +
>> +        if (!bo)
>> +            continue;
>> +        bo->shadow_flag = AMDGPU_SHADOW_FLAG_SYNC_TO_PARENT;
>> +        r = amdgpu_bo_sync_between_bo_and_shadow(adev, ring, bo,
>> +                             NULL, &fence);
>> +        if (r) {
>> +            DRM_ERROR("recover page table failed!\n");
>> +            goto err;
>> +        }
>> +        fence_put(vm->shadow_sync_fence);
>> +        vm->shadow_sync_fence = fence_get(fence);
>> +        fence_put(fence);
>> +    }
>> +
>> +err:
>> +    amdgpu_bo_unreserve(vm->page_directory);
>> +    return r;
>> +}
>>   /**
>>    * amdgpu_vm_frag_ptes - add fragment information to PTEs
>>    *
>> @@ -1556,6 +1602,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, 
>> struct amdgpu_vm *vm)
>>       if (r)
>>           goto error_free_page_directory;
>>       vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
>> +    vm->shadow_sync_fence = NULL;
>>         return 0;
>>   @@ -1604,6 +1651,7 @@ void amdgpu_vm_fini(struct amdgpu_device 
>> *adev, struct amdgpu_vm *vm)
>>         amdgpu_bo_unref(&vm->page_directory);
>>       fence_put(vm->page_directory_fence);
>> +    fence_put(vm->shadow_sync_fence);
>>   }
>>     /**
>
>

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