Re: [PATCH v3 08/17] arm64: dts: mediatek: add mmc support for mt8365 SoC

From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@collabora.com>
To: "Alexandre Mergnat" <amergnat@baylibre.com>,
	"Wim Van Sebroeck" <wim@linux-watchdog.org>,
	"Guenter Roeck" <linux@roeck-us.net>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	"Chaotian Jing" <chaotian.jing@mediatek.com>,
	"Ulf Hansson" <ulf.hansson@linaro.org>,
	"Wenbin Mei" <wenbin.mei@mediatek.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Zhiyong Tao" <zhiyong.tao@mediatek.com>,
	"Bernhard Rosenkränzer" <bero@baylibre.com>
Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-mmc@vger.kernel.org,
	linux-gpio@vger.kernel.org,
	Alexandre Bailon <abailon@baylibre.com>,
	Fabien Parent <fparent@baylibre.com>,
	Amjad Ouled-Ameur <aouledameur@baylibre.com>
Subject: Re: [PATCH v3 08/17] arm64: dts: mediatek: add mmc support for mt8365 SoC
Date: Wed, 29 Mar 2023 15:21:09 +0200	[thread overview]
Message-ID: <c785d80f-e443-cae4-1e17-b79eb2dc385c@collabora.com> (raw)
In-Reply-To: <20230203-evk-board-support-v3-8-0003e80e0095@baylibre.com>

Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> There are three ports of MSDC (MMC and SD Controller), which are:
> - MSDC0: EMMC5.1
> - MSDC1: SD3.0/SDIO3.0
> - MSDC2: SDIO3.0+
> 
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++++++++++
>   1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index 687011353f69..a67eeca28da5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -399,6 +399,45 @@ usb_host: usb@11200000 {
>   			};
>   		};
>   
> +		mmc0: mmc@11230000 {
> +			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11230000 0 0x1000>,
> +			      <0 0x11cd0000 0 0x1000>;
> +			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&infracfg CLK_IFR_MSDC0_HCLK>,
> +				 <&infracfg CLK_IFR_MSDC0_SRC>;
> +			clock-names = "source", "hclk", "source_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@11240000 {
> +			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11240000 0 0x1000>,
> +			      <0 0x11c90000 0 0x1000>;
> +			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&infracfg CLK_IFR_MSDC1_HCLK>,
> +				 <&infracfg CLK_IFR_MSDC1_SRC>;
> +			clock-names = "source", "hclk", "source_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc2: mmc@11250000 {
> +			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11250000 0 0x1000>,
> +			      <0 0x11c60000 0 0x1000>;
> +			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
> +				 <&infracfg CLK_IFR_MSDC2_HCLK>,
> +				 <&infracfg CLK_IFR_MSDC2_SRC>,
> +				 <&infracfg CLK_IFR_MSDC2_BK>,
> +				 <&infracfg CLK_IFR_AP_MSDC0>;
> +			clock-names = "source", "hclk", "source_cg",
> +				      "bus_clk", "sys_cg";

clock-names for this do fit in one 90 columns line.

After compressing it,

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>