From: "Souza, Jose" <jose.souza@intel.com>
To: "Surendrakumar Upadhyay,
TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
Date: Fri, 16 Oct 2020 20:41:18 +0000 [thread overview]
Message-ID: <c85c1e749bf9b91787e609659000ec8c44662b95.camel@intel.com> (raw)
In-Reply-To: <20201014145914.67547-1-tejaskumarx.surendrakumar.upadhyay@intel.com>
Please fix the checkpatch errors, you can run it locally by running "dim checkpatch drm-tip/drm-tip..HEAD", search for instructions of how to fetch
and setup dim.
Also no need to CC drm-devel for patches that only touches i915, drm-devel is for drivers that don't have it's own list and for changes in drm
subsystem that affects all other drm based drivers.
On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote:
> JSL has update in vswing table for eDP.
>
> BSpec: 21257
>
> Cc: Souza Jose <jose.souza@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 87 +++++++++++++++++++++++-
> 1 file changed, 85 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bb0b9930958f..7ab694c6d8df 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
> { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
>
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> + /* NT mV Trans mV db */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> + { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> + { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> +};
> +
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> + /* NT mV Trans mV db */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */
> + { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */
> + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */
> + { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> +};
> +
> struct icl_mg_phy_ddi_buf_trans {
> u32 cri_txdeemph_override_11_6;
> u32 cri_txdeemph_override_5_0;
> @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder,
> return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> }
>
>
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> + return icl_combo_phy_ddi_translations_dp_hbr2;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + if (dev_priv->vbt.edp.low_vswing) {
> + if (crtc_state->port_clock > 270000) {
> + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> + return jsl_combo_phy_ddi_translations_edp_hbr2;
> + } else {
> + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> + return jsl_combo_phy_ddi_translations_edp_hbr;
> + }
> + }
> +
> + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
> + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> + return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
> + else
> + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> +}
> +
> static const struct cnl_ddi_buf_trans *
> tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> @@ -2363,7 +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
> else
> tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> } else if (INTEL_GEN(dev_priv) == 11) {
> - if (IS_JSL_EHL(dev_priv))
> + if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> + jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> else if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> @@ -2544,7 +2625,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>
>
> if (INTEL_GEN(dev_priv) >= 12)
> ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> - else if (IS_JSL_EHL(dev_priv))
> + else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> + ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> else
> ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: "Souza, Jose" <jose.souza@intel.com>
To: "Surendrakumar Upadhyay,
TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
Date: Fri, 16 Oct 2020 20:41:18 +0000 [thread overview]
Message-ID: <c85c1e749bf9b91787e609659000ec8c44662b95.camel@intel.com> (raw)
In-Reply-To: <20201014145914.67547-1-tejaskumarx.surendrakumar.upadhyay@intel.com>
Please fix the checkpatch errors, you can run it locally by running "dim checkpatch drm-tip/drm-tip..HEAD", search for instructions of how to fetch
and setup dim.
Also no need to CC drm-devel for patches that only touches i915, drm-devel is for drivers that don't have it's own list and for changes in drm
subsystem that affects all other drm based drivers.
On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote:
> JSL has update in vswing table for eDP.
>
> BSpec: 21257
>
> Cc: Souza Jose <jose.souza@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 87 +++++++++++++++++++++++-
> 1 file changed, 85 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bb0b9930958f..7ab694c6d8df 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
> { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
>
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> + /* NT mV Trans mV db */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> + { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> + { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> +};
> +
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> + /* NT mV Trans mV db */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */
> + { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */
> + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */
> + { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> +};
> +
> struct icl_mg_phy_ddi_buf_trans {
> u32 cri_txdeemph_override_11_6;
> u32 cri_txdeemph_override_5_0;
> @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder,
> return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> }
>
>
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> + return icl_combo_phy_ddi_translations_dp_hbr2;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + if (dev_priv->vbt.edp.low_vswing) {
> + if (crtc_state->port_clock > 270000) {
> + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> + return jsl_combo_phy_ddi_translations_edp_hbr2;
> + } else {
> + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> + return jsl_combo_phy_ddi_translations_edp_hbr;
> + }
> + }
> +
> + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
> + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> + return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
> + else
> + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> +}
> +
> static const struct cnl_ddi_buf_trans *
> tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> @@ -2363,7 +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
> else
> tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> } else if (INTEL_GEN(dev_priv) == 11) {
> - if (IS_JSL_EHL(dev_priv))
> + if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> + jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> else if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> @@ -2544,7 +2625,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>
>
> if (INTEL_GEN(dev_priv) >= 12)
> ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> - else if (IS_JSL_EHL(dev_priv))
> + else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> + ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> else
> ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-10-16 20:41 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-14 14:59 [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 Tejas Upadhyay
2020-10-14 14:59 ` [Intel-gfx] " Tejas Upadhyay
2020-10-14 15:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/edp/jsl: Update vswing table for HBR and HBR2 (rev2) Patchwork
2020-10-14 16:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-10-16 20:41 ` Souza, Jose [this message]
2020-10-16 20:41 ` [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 Souza, Jose
2020-10-19 11:08 ` Surendrakumar Upadhyay, TejaskumarX
2020-10-19 17:09 ` Souza, Jose
2020-10-19 18:13 ` Surendrakumar Upadhyay, TejaskumarX
2020-10-19 18:15 ` Souza, Jose
2020-10-20 5:47 ` Surendrakumar Upadhyay, TejaskumarX
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