From: Stefan Wahren <stefan.wahren@i2se.com>
To: Richard Schleich <rs@noreya.tech>,
robh+dt@kernel.org, nsaenz@kernel.org, f.fainelli@gmail.com,
bcm-kernel-feedback-list@broadcom.com,
devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information
Date: Tue, 28 Dec 2021 17:30:52 +0100 [thread overview]
Message-ID: <c96baba4-df6e-bab6-d1c8-10b4771cf51e@i2se.com> (raw)
In-Reply-To: <20211221224830.16746-1-rs@noreya.tech>
Am 21.12.21 um 23:48 schrieb Richard Schleich:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2711 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
I tested the patch with a Raspberry Pi 4 (arm64/defconfig) and here are
some outputs:
/sys/devices/system/cpu/cpu0/cache
./index2/number_of_sets:1024
./index2/ways_of_associativity:16
./index2/shared_cpu_list:0-3
./index2/type:Unified
./index2/size:1024K
./index2/level:2
./index2/coherency_line_size:64
./index2/shared_cpu_map:f
./index0/number_of_sets:256
./index0/ways_of_associativity:2
./index0/shared_cpu_list:0
./index0/type:Data
./index0/size:32K
./index0/level:1
./index0/coherency_line_size:64
./index0/shared_cpu_map:1
./index1/number_of_sets:256
./index1/ways_of_associativity:3
./index1/shared_cpu_list:0
./index1/type:Instruction
./index1/size:48K
./index1/level:1
./index1/coherency_line_size:64
./index1/shared_cpu_map:1
lscpu
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: ARM
Model: 3
Model name: Cortex-A72
Stepping: r0p3
CPU max MHz: 1500,0000
CPU min MHz: 600,0000
BogoMIPS: 108.00
L1d cache: 32K
L1i cache: 48K
L2 cache: 1024K
NUMA node0 CPU(s): 0-3
Flags: fp asimd evtstrm crc32 cpuid
WARNING: multiple messages have this Message-ID (diff)
From: Stefan Wahren <stefan.wahren@i2se.com>
To: Richard Schleich <rs@noreya.tech>,
robh+dt@kernel.org, nsaenz@kernel.org, f.fainelli@gmail.com,
bcm-kernel-feedback-list@broadcom.com,
devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information
Date: Tue, 28 Dec 2021 17:30:52 +0100 [thread overview]
Message-ID: <c96baba4-df6e-bab6-d1c8-10b4771cf51e@i2se.com> (raw)
In-Reply-To: <20211221224830.16746-1-rs@noreya.tech>
Am 21.12.21 um 23:48 schrieb Richard Schleich:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2711 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
I tested the patch with a Raspberry Pi 4 (arm64/defconfig) and here are
some outputs:
/sys/devices/system/cpu/cpu0/cache
./index2/number_of_sets:1024
./index2/ways_of_associativity:16
./index2/shared_cpu_list:0-3
./index2/type:Unified
./index2/size:1024K
./index2/level:2
./index2/coherency_line_size:64
./index2/shared_cpu_map:f
./index0/number_of_sets:256
./index0/ways_of_associativity:2
./index0/shared_cpu_list:0
./index0/type:Data
./index0/size:32K
./index0/level:1
./index0/coherency_line_size:64
./index0/shared_cpu_map:1
./index1/number_of_sets:256
./index1/ways_of_associativity:3
./index1/shared_cpu_list:0
./index1/type:Instruction
./index1/size:48K
./index1/level:1
./index1/coherency_line_size:64
./index1/shared_cpu_map:1
lscpu
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: ARM
Model: 3
Model name: Cortex-A72
Stepping: r0p3
CPU max MHz: 1500,0000
CPU min MHz: 600,0000
BogoMIPS: 108.00
L1d cache: 32K
L1i cache: 48K
L2 cache: 1024K
NUMA node0 CPU(s): 0-3
Flags: fp asimd evtstrm crc32 cpuid
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next prev parent reply other threads:[~2021-12-28 16:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 22:48 [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information Richard Schleich
2021-12-21 22:48 ` Richard Schleich
2021-12-28 16:30 ` Stefan Wahren [this message]
2021-12-28 16:30 ` Stefan Wahren
2022-02-01 0:36 ` Florian Fainelli
2022-02-01 0:36 ` Florian Fainelli
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