From: Tanmay Shah <tanmay.shah@xilinx.com> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, <bjorn.andersson@linaro.org>, <mathieu.poirier@linaro.org>, <robh+dt@kernel.org>, <krzk+dt@kernel.org>, <michal.simek@xilinx.com> Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH v5 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Date: Mon, 23 May 2022 14:38:52 -0700 [thread overview] Message-ID: <c97d61b0-8a38-5054-d5f1-bc7c5e7bcf61@xilinx.com> (raw) In-Reply-To: <45fea4a1-387f-9684-a90b-58b695b54172@linaro.org> Thanks for reviews Krzysztof. Please find my comments below. On 5/21/22 8:12 AM, Krzysztof Kozlowski wrote: > On 18/05/2022 21:44, Tanmay Shah wrote: >> +description: | >> + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for >> + real-time processing based on the Cortex-R5F processor core from ARM. >> + The Cortex-R5F processor implements the Arm v7-R architecture and includes a >> + floating-point unit that implements the Arm VFPv3 instruction set. >> + >> +properties: >> + compatible: >> + const: xlnx,zynqmp-r5fss >> + >> + xlnx,cluster-mode: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [0, 1, 2] >> + description: | >> + The RPU MPCore can operate in split mode(Dual-processor performance), Safety >> + lock-step mode(Both RPU cores execute the same code in lock-step, >> + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while >> + core 1 runs normally). The processor does not support dynamic configuration. >> + Switching between modes is only permitted immediately after a processor reset. >> + If set to 1 then lockstep mode and if 0 then split mode. >> + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. >> + >> +patternProperties: >> + "^r5f-[a-f0-9]+$": >> + type: object >> + description: | >> + The RPU is located in the Low Power Domain of the Processor Subsystem. >> + Each processor includes separate L1 instruction and data caches and >> + tightly coupled memories (TCM). System memory is cacheable, but the TCM >> + memory space is non-cacheable. >> + >> + Each RPU contains one 64KB memory and two 32KB memories that >> + are accessed via the TCM A and B port interfaces, for a total of 128KB >> + per processor. In lock-step mode, the processor has access to 256KB of >> + TCM memory. >> + >> + properties: >> + compatible: >> + const: xlnx,zynqmp-r5f >> + >> + power-domains: >> + description: RPU core PM domain specifier >> + maxItems: 1 >> + >> + mboxes: >> + items: >> + - description: mailbox channel to send data to RPU >> + - description: mailbox channel to receive data from RPU >> + minItems: 1 >> + >> + mbox-names: >> + items: >> + - const: tx >> + - const: rx >> + minItems: 1 >> + >> + sram: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + minItems: 1 > maxItems instead Here, I am not sure how many maxItems are really needed as TCM bindings are not defined yet. For now, I will just keep maxItems as 8. i.e. 4 OCM banks and 4 TCM banks. However, that can change once bindings are defined. Is that fine? > >> + description: | >> + phandles to one or more reserved on-chip SRAM regions. Other than TCM, >> + the RPU can execute instructions and access data from, the OCM memory, >> + the main DDR memory, and other system memories. >> + >> + The regions should be defined as child nodes of the respective SRAM >> + node, and should be defined as per the generic bindings in, >> + Documentation/devicetree/bindings/sram/sram.yaml >> + >> + memory-region: >> + description: | >> + List of phandles to the reserved memory regions associated with the >> + remoteproc device. This is variable and describes the memories shared with >> + the remote processor (e.g. remoteproc firmware and carveouts, rpmsg >> + vrings, ...). This reserved memory region will be allocated on DDR memory. >> + minItems: 1 >> + items: >> + - description: region used for RPU firmware image section >> + - description: vdev buffer >> + - description: vring0 >> + - description: vring1 >> + additionalItems: true > How did this one appear here? It does not look correct, so why do you > need it? Memory regions listed in items: field here are used for default current OpenAMP demos. However, other demos can be developed by user that can use more number of memory regions. As description says, memory-region can have variable number phandles based on user requirement. So, by additionalItems I just want to notify that user can define more number of regions. We can limit memory-regions with 'maxItems: 8'. In that case, I will add 'maxItems:' field in next revision and even, that can change in future. But, User should have flexibility to define more memory regions than what is in list of 'items:' field. I think this is similar to what is defined in ti,k3-r5 bindings. Please let me know your thoughts. >> + >> + required: >> + - compatible >> + - power-domains >> + >> + unevaluatedProperties: false >> + >> +required: >> + - compatible >> +\ > Best regards, > Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Tanmay Shah <tanmay.shah@xilinx.com> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, <bjorn.andersson@linaro.org>, <mathieu.poirier@linaro.org>, <robh+dt@kernel.org>, <krzk+dt@kernel.org>, <michal.simek@xilinx.com> Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH v5 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Date: Mon, 23 May 2022 14:38:52 -0700 [thread overview] Message-ID: <c97d61b0-8a38-5054-d5f1-bc7c5e7bcf61@xilinx.com> (raw) In-Reply-To: <45fea4a1-387f-9684-a90b-58b695b54172@linaro.org> Thanks for reviews Krzysztof. Please find my comments below. On 5/21/22 8:12 AM, Krzysztof Kozlowski wrote: > On 18/05/2022 21:44, Tanmay Shah wrote: >> +description: | >> + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for >> + real-time processing based on the Cortex-R5F processor core from ARM. >> + The Cortex-R5F processor implements the Arm v7-R architecture and includes a >> + floating-point unit that implements the Arm VFPv3 instruction set. >> + >> +properties: >> + compatible: >> + const: xlnx,zynqmp-r5fss >> + >> + xlnx,cluster-mode: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [0, 1, 2] >> + description: | >> + The RPU MPCore can operate in split mode(Dual-processor performance), Safety >> + lock-step mode(Both RPU cores execute the same code in lock-step, >> + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while >> + core 1 runs normally). The processor does not support dynamic configuration. >> + Switching between modes is only permitted immediately after a processor reset. >> + If set to 1 then lockstep mode and if 0 then split mode. >> + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. >> + >> +patternProperties: >> + "^r5f-[a-f0-9]+$": >> + type: object >> + description: | >> + The RPU is located in the Low Power Domain of the Processor Subsystem. >> + Each processor includes separate L1 instruction and data caches and >> + tightly coupled memories (TCM). System memory is cacheable, but the TCM >> + memory space is non-cacheable. >> + >> + Each RPU contains one 64KB memory and two 32KB memories that >> + are accessed via the TCM A and B port interfaces, for a total of 128KB >> + per processor. In lock-step mode, the processor has access to 256KB of >> + TCM memory. >> + >> + properties: >> + compatible: >> + const: xlnx,zynqmp-r5f >> + >> + power-domains: >> + description: RPU core PM domain specifier >> + maxItems: 1 >> + >> + mboxes: >> + items: >> + - description: mailbox channel to send data to RPU >> + - description: mailbox channel to receive data from RPU >> + minItems: 1 >> + >> + mbox-names: >> + items: >> + - const: tx >> + - const: rx >> + minItems: 1 >> + >> + sram: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + minItems: 1 > maxItems instead Here, I am not sure how many maxItems are really needed as TCM bindings are not defined yet. For now, I will just keep maxItems as 8. i.e. 4 OCM banks and 4 TCM banks. However, that can change once bindings are defined. Is that fine? > >> + description: | >> + phandles to one or more reserved on-chip SRAM regions. Other than TCM, >> + the RPU can execute instructions and access data from, the OCM memory, >> + the main DDR memory, and other system memories. >> + >> + The regions should be defined as child nodes of the respective SRAM >> + node, and should be defined as per the generic bindings in, >> + Documentation/devicetree/bindings/sram/sram.yaml >> + >> + memory-region: >> + description: | >> + List of phandles to the reserved memory regions associated with the >> + remoteproc device. This is variable and describes the memories shared with >> + the remote processor (e.g. remoteproc firmware and carveouts, rpmsg >> + vrings, ...). This reserved memory region will be allocated on DDR memory. >> + minItems: 1 >> + items: >> + - description: region used for RPU firmware image section >> + - description: vdev buffer >> + - description: vring0 >> + - description: vring1 >> + additionalItems: true > How did this one appear here? It does not look correct, so why do you > need it? Memory regions listed in items: field here are used for default current OpenAMP demos. However, other demos can be developed by user that can use more number of memory regions. As description says, memory-region can have variable number phandles based on user requirement. So, by additionalItems I just want to notify that user can define more number of regions. We can limit memory-regions with 'maxItems: 8'. In that case, I will add 'maxItems:' field in next revision and even, that can change in future. But, User should have flexibility to define more memory regions than what is in list of 'items:' field. I think this is similar to what is defined in ti,k3-r5 bindings. Please let me know your thoughts. >> + >> + required: >> + - compatible >> + - power-domains >> + >> + unevaluatedProperties: false >> + >> +required: >> + - compatible >> +\ > Best regards, > Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-23 21:39 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-18 19:44 [PATCH v5 0/6] Add Xilinx RPU subsystem support Tanmay Shah 2022-05-18 19:44 ` Tanmay Shah 2022-05-18 19:44 ` [PATCH v5 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Tanmay Shah 2022-05-18 19:44 ` Tanmay Shah 2022-05-21 15:12 ` Krzysztof Kozlowski 2022-05-21 15:12 ` Krzysztof Kozlowski 2022-05-23 21:38 ` Tanmay Shah [this message] 2022-05-23 21:38 ` Tanmay Shah 2022-05-24 9:19 ` Krzysztof Kozlowski 2022-05-24 9:19 ` Krzysztof Kozlowski 2022-05-24 15:43 ` Tanmay Shah 2022-05-24 15:43 ` Tanmay Shah 2022-05-24 17:28 ` Krzysztof Kozlowski 2022-05-24 17:28 ` Krzysztof Kozlowski 2022-05-24 18:09 ` Tanmay Shah 2022-05-24 18:09 ` Tanmay Shah 2022-05-18 19:44 ` [PATCH v5 2/6] arm64: dts: xilinx: zynqmp: Add RPU subsystem device node Tanmay Shah 2022-05-18 19:44 ` Tanmay Shah 2022-05-18 19:44 ` [PATCH v5 3/6] firmware: xilinx: Add ZynqMP firmware ioctl enums for RPU configuration Tanmay Shah 2022-05-18 19:44 ` Tanmay Shah 2022-05-18 19:44 ` [PATCH v5 4/6] firmware: xilinx: Add shutdown/wakeup APIs Tanmay Shah 2022-05-18 19:44 ` Tanmay Shah 2022-05-18 19:44 ` [PATCH v5 5/6] firmware: xilinx: Add RPU configuration APIs Tanmay Shah 2022-05-18 19:44 ` Tanmay Shah 2022-05-18 19:44 ` [PATCH v5 6/6] drivers: remoteproc: Add Xilinx r5 remoteproc driver Tanmay Shah 2022-05-18 19:44 ` Tanmay Shah 2022-05-19 10:19 ` [PATCH v5 0/6] Add Xilinx RPU subsystem support Mathieu Poirier 2022-05-19 10:19 ` Mathieu Poirier 2022-05-20 3:10 ` tanmay.shah 2022-05-20 3:10 ` tanmay.shah 2022-05-26 16:41 ` Tanmay Shah 2022-05-26 17:55 ` Mathieu Poirier 2022-05-26 18:21 ` Tanmay Shah
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