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From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro
Date: Mon, 5 Apr 2021 08:14:55 -0700	[thread overview]
Message-ID: <c99b14f5-081c-70e7-1c13-377087f7bfaa@linaro.org> (raw)
In-Reply-To: <c2a0653687bea5e932747e301112ea0507169385.1617393702.git.alistair.francis@wdc.com>

On 4/2/21 1:02 PM, Alistair Francis wrote:
> @@ -622,9 +632,15 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
>       CPUState *cs = env_cpu(env);
>       int page_fault_exceptions;
>       if (first_stage) {
> -        page_fault_exceptions =
> -            get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
> -            !pmp_violation;
> +        if (riscv_cpu_is_32bit(env)) {
> +            page_fault_exceptions =
> +                get_field(env->satp, SATP32_MODE) != VM_1_10_MBARE &&
> +                !pmp_violation;
> +        } else {
> +            page_fault_exceptions =
> +                get_field(env->satp, SATP64_MODE) != VM_1_10_MBARE &&
> +                !pmp_violation;
> +        }

Similar commentary wrt HGATP_MODE.

>       } else {
>           if (riscv_cpu_is_32bit(env)) {
>               page_fault_exceptions =
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6052b2d6e9..b0ebaa029e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -930,16 +930,31 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
>       if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
>           return 0;
>       }
> -    if (validate_vm(env, get_field(val, SATP_MODE)) &&
> -        ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
> -    {
> -        if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
> -            return -RISCV_EXCP_ILLEGAL_INST;
> -        } else {
> -            if ((val ^ env->satp) & SATP_ASID) {
> -                tlb_flush(env_cpu(env));
> +    if (riscv_cpu_is_32bit(env)) {
> +        if (validate_vm(env, get_field(val, SATP32_MODE)) &&
> +            ((val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN)))
> +        {
> +            if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
> +                return -RISCV_EXCP_ILLEGAL_INST;
> +            } else {
> +                if ((val ^ env->satp) & SATP32_ASID) {
> +                    tlb_flush(env_cpu(env));
> +                }
> +                env->satp = val;
> +            }
> +        }

I think you really don't want to be duplicating this code.
Just select the constants into local variables.


r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: Re: [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro
Date: Mon, 5 Apr 2021 08:14:55 -0700	[thread overview]
Message-ID: <c99b14f5-081c-70e7-1c13-377087f7bfaa@linaro.org> (raw)
In-Reply-To: <c2a0653687bea5e932747e301112ea0507169385.1617393702.git.alistair.francis@wdc.com>

On 4/2/21 1:02 PM, Alistair Francis wrote:
> @@ -622,9 +632,15 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
>       CPUState *cs = env_cpu(env);
>       int page_fault_exceptions;
>       if (first_stage) {
> -        page_fault_exceptions =
> -            get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
> -            !pmp_violation;
> +        if (riscv_cpu_is_32bit(env)) {
> +            page_fault_exceptions =
> +                get_field(env->satp, SATP32_MODE) != VM_1_10_MBARE &&
> +                !pmp_violation;
> +        } else {
> +            page_fault_exceptions =
> +                get_field(env->satp, SATP64_MODE) != VM_1_10_MBARE &&
> +                !pmp_violation;
> +        }

Similar commentary wrt HGATP_MODE.

>       } else {
>           if (riscv_cpu_is_32bit(env)) {
>               page_fault_exceptions =
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6052b2d6e9..b0ebaa029e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -930,16 +930,31 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
>       if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
>           return 0;
>       }
> -    if (validate_vm(env, get_field(val, SATP_MODE)) &&
> -        ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
> -    {
> -        if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
> -            return -RISCV_EXCP_ILLEGAL_INST;
> -        } else {
> -            if ((val ^ env->satp) & SATP_ASID) {
> -                tlb_flush(env_cpu(env));
> +    if (riscv_cpu_is_32bit(env)) {
> +        if (validate_vm(env, get_field(val, SATP32_MODE)) &&
> +            ((val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN)))
> +        {
> +            if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
> +                return -RISCV_EXCP_ILLEGAL_INST;
> +            } else {
> +                if ((val ^ env->satp) & SATP32_ASID) {
> +                    tlb_flush(env_cpu(env));
> +                }
> +                env->satp = val;
> +            }
> +        }

I think you really don't want to be duplicating this code.
Just select the constants into local variables.


r~


  reply	other threads:[~2021-04-05 15:23 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-02 20:02 [PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-02 20:02 ` Alistair Francis
2021-04-02 20:02 ` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-02 20:02   ` Alistair Francis
2021-04-05 14:48   ` Richard Henderson
2021-04-05 14:48     ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-12  9:10     ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-02 20:02   ` Alistair Francis
2021-04-05 14:49   ` Richard Henderson
2021-04-05 14:49     ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-12  9:10     ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-02 20:02   ` Alistair Francis
2021-04-05 14:54   ` Richard Henderson
2021-04-05 14:54     ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-02 20:02   ` Alistair Francis
2021-04-05 15:10   ` Richard Henderson
2021-04-05 15:10     ` Richard Henderson
2021-04-07 17:11     ` Alistair Francis
2021-04-07 17:11       ` Alistair Francis
2021-04-08 15:20     ` Alistair Francis
2021-04-08 15:20       ` Alistair Francis
2021-04-08 18:51       ` Richard Henderson
2021-04-08 18:51         ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-02 20:02   ` Alistair Francis
2021-04-05 15:14   ` Richard Henderson [this message]
2021-04-05 15:14     ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-02 20:02   ` Alistair Francis
2021-04-05 15:15   ` Richard Henderson
2021-04-05 15:15     ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-12  9:10     ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-02 20:02   ` Alistair Francis
2021-04-05 15:15   ` Richard Henderson
2021-04-05 15:15     ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-12  9:10     ` Bin Meng
2021-04-02 20:03 ` [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build Alistair Francis
2021-04-02 20:03   ` Alistair Francis
2021-04-06 14:57   ` Richard Henderson
2021-04-06 14:57     ` Richard Henderson

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