* [PATCH v3] target/m68k: implement rtr instruction
@ 2021-03-07 21:25 Laurent Vivier
2021-03-08 1:04 ` Richard Henderson
2021-03-09 19:44 ` Laurent Vivier
0 siblings, 2 replies; 3+ messages in thread
From: Laurent Vivier @ 2021-03-07 21:25 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland, Richard Henderson, Laurent Vivier
This is needed to boot MacOS ROM.
Pull the condition code and the program counter from the stack.
Operation:
(SP) -> CCR
SP + 2 -> SP
(SP) -> PC
SP + 4 -> SP
This operation is not privileged.
Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
Notes:
v3: put loads before state writeback
v2: update comment
SP + 4 -> SP
target/m68k/translate.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index ac936ebe8f14..200018ae6a63 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2969,6 +2969,25 @@ DISAS_INSN(rtd)
gen_jmp(s, tmp);
}
+DISAS_INSN(rtr)
+{
+ TCGv tmp;
+ TCGv ccr;
+ TCGv sp;
+
+ sp = tcg_temp_new();
+ ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
+ tcg_gen_addi_i32(sp, QREG_SP, 2);
+ tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
+ tcg_gen_addi_i32(QREG_SP, sp, 4);
+ tcg_temp_free(sp);
+
+ gen_set_sr(s, ccr, true);
+ tcg_temp_free(ccr);
+
+ gen_jmp(s, tmp);
+}
+
DISAS_INSN(rts)
{
TCGv tmp;
@@ -6015,6 +6034,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(nop, 4e71, ffff);
INSN(rtd, 4e74, ffff, RTD);
BASE(rts, 4e75, ffff);
+ INSN(rtr, 4e77, ffff, M68000);
BASE(jump, 4e80, ffc0);
BASE(jump, 4ec0, ffc0);
INSN(addsubq, 5000, f080, M68000);
--
2.29.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v3] target/m68k: implement rtr instruction
2021-03-07 21:25 [PATCH v3] target/m68k: implement rtr instruction Laurent Vivier
@ 2021-03-08 1:04 ` Richard Henderson
2021-03-09 19:44 ` Laurent Vivier
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2021-03-08 1:04 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: Mark Cave-Ayland
On 3/7/21 1:25 PM, Laurent Vivier wrote:
> This is needed to boot MacOS ROM.
>
> Pull the condition code and the program counter from the stack.
>
> Operation:
>
> (SP) -> CCR
> SP + 2 -> SP
> (SP) -> PC
> SP + 4 -> SP
>
> This operation is not privileged.
>
> Reported-by: Mark Cave-Ayland<mark.cave-ayland@ilande.co.uk>
> Tested-by: Mark Cave-Ayland<mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier<laurent@vivier.eu>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v3] target/m68k: implement rtr instruction
2021-03-07 21:25 [PATCH v3] target/m68k: implement rtr instruction Laurent Vivier
2021-03-08 1:04 ` Richard Henderson
@ 2021-03-09 19:44 ` Laurent Vivier
1 sibling, 0 replies; 3+ messages in thread
From: Laurent Vivier @ 2021-03-09 19:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland
Le 07/03/2021 à 22:25, Laurent Vivier a écrit :
> This is needed to boot MacOS ROM.
>
> Pull the condition code and the program counter from the stack.
>
> Operation:
>
> (SP) -> CCR
> SP + 2 -> SP
> (SP) -> PC
> SP + 4 -> SP
>
> This operation is not privileged.
>
> Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
>
> Notes:
> v3: put loads before state writeback
>
> v2: update comment
> SP + 4 -> SP
>
> target/m68k/translate.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index ac936ebe8f14..200018ae6a63 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -2969,6 +2969,25 @@ DISAS_INSN(rtd)
> gen_jmp(s, tmp);
> }
>
> +DISAS_INSN(rtr)
> +{
> + TCGv tmp;
> + TCGv ccr;
> + TCGv sp;
> +
> + sp = tcg_temp_new();
> + ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
> + tcg_gen_addi_i32(sp, QREG_SP, 2);
> + tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
> + tcg_gen_addi_i32(QREG_SP, sp, 4);
> + tcg_temp_free(sp);
> +
> + gen_set_sr(s, ccr, true);
> + tcg_temp_free(ccr);
> +
> + gen_jmp(s, tmp);
> +}
> +
> DISAS_INSN(rts)
> {
> TCGv tmp;
> @@ -6015,6 +6034,7 @@ void register_m68k_insns (CPUM68KState *env)
> BASE(nop, 4e71, ffff);
> INSN(rtd, 4e74, ffff, RTD);
> BASE(rts, 4e75, ffff);
> + INSN(rtr, 4e77, ffff, M68000);
> BASE(jump, 4e80, ffc0);
> BASE(jump, 4ec0, ffc0);
> INSN(addsubq, 5000, f080, M68000);
>
Applied to my m68k-for-6.0 branch
Thanks,
Laurent
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-03-09 20:22 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-07 21:25 [PATCH v3] target/m68k: implement rtr instruction Laurent Vivier
2021-03-08 1:04 ` Richard Henderson
2021-03-09 19:44 ` Laurent Vivier
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.