* [PATCH] drm/amdgpu:Replace value with defined macro
@ 2018-10-02 17:20 James Zhu
[not found] ` <1538500848-13846-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: James Zhu @ 2018-10-02 17:20 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +++++--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 12 +++++++-----
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 12a60ec..7ad352c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -309,14 +309,17 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
/* Restore */
ring = &adev->vcn.ring_jpeg;
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L);
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+ UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
ring = &adev->vcn.ring_dec;
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 78a3115b..8c53fb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -810,12 +810,12 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
for (j = 0; j < 100; ++j) {
status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
- if (status & 2)
+ if (status & UVD_STATUS__IDLE)
break;
mdelay(10);
}
r = 0;
- if (status & 2)
+ if (status & UVD_STATUS__IDLE)
break;
DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
@@ -898,12 +898,13 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
ring = &adev->vcn.ring_jpeg;
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
/* initialize wptr */
ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
@@ -1123,7 +1124,8 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
int ret_code;
/* Wait for power status to be 1 */
- SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
+ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
/* disable dynamic power gating mode */
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 1/4] drm/amdgpu:Replace value with defined macro
[not found] ` <1538500848-13846-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-02 20:35 ` James Zhu
[not found] ` <1538512551-26146-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-10-03 13:10 ` [PATCH] " Leo Liu
1 sibling, 1 reply; 4+ messages in thread
From: James Zhu @ 2018-10-02 20:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +++++--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++++++++++--------
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 12a60ec..7ad352c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -309,14 +309,17 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
/* Restore */
ring = &adev->vcn.ring_jpeg;
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L);
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+ UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
ring = &adev->vcn.ring_dec;
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 78a3115b..ceb6d52 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -810,12 +810,12 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
for (j = 0; j < 100; ++j) {
status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
- if (status & 2)
+ if (status & UVD_STATUS__IDLE)
break;
mdelay(10);
}
r = 0;
- if (status & 2)
+ if (status & UVD_STATUS__IDLE)
break;
DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
@@ -898,12 +898,13 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
ring = &adev->vcn.ring_jpeg;
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
/* initialize wptr */
ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
@@ -1122,8 +1123,9 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
{
int ret_code;
- /* Wait for power status to be 1 */
- SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
+ /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
+ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
/* disable dynamic power gating mode */
@@ -1149,7 +1151,7 @@ static bool vcn_v1_0_is_idle(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2);
+ return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
}
static int vcn_v1_0_wait_for_idle(void *handle)
@@ -1157,7 +1159,8 @@ static int vcn_v1_0_wait_for_idle(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret = 0;
- SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, 0x2, 0x2, ret);
+ SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE, ret);
return ret;
}
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu:Replace value with defined macro
[not found] ` <1538500848-13846-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-10-02 20:35 ` [PATCH v2 1/4] " James Zhu
@ 2018-10-03 13:10 ` Leo Liu
1 sibling, 0 replies; 4+ messages in thread
From: Leo Liu @ 2018-10-03 13:10 UTC (permalink / raw)
To: James Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo
On 10/02/2018 01:20 PM, James Zhu wrote:
> Replace value with defined macro to make
> code more readable
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +++++--
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 12 +++++++-----
> 2 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 12a60ec..7ad352c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -309,14 +309,17 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
> /* Restore */
> ring = &adev->vcn.ring_jpeg;
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
> - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L);
> + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> + UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
> + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
Please use same indentation like below. With that fixed, the patch is
Acked-by: Leo Liu <leo.liu@amd.com>
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
> lower_32_bits(ring->gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
> upper_32_bits(ring->gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
> - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
> + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>
> ring = &adev->vcn.ring_dec;
> WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 78a3115b..8c53fb4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -810,12 +810,12 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>
> for (j = 0; j < 100; ++j) {
> status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
> - if (status & 2)
> + if (status & UVD_STATUS__IDLE)
> break;
> mdelay(10);
> }
> r = 0;
> - if (status & 2)
> + if (status & UVD_STATUS__IDLE)
> break;
>
> DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
> @@ -898,12 +898,13 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>
> ring = &adev->vcn.ring_jpeg;
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
> - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
> + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
> + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
> - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
> + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>
> /* initialize wptr */
> ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
> @@ -1123,7 +1124,8 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
> int ret_code;
>
> /* Wait for power status to be 1 */
> - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
> + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
> + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
> UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
>
> /* disable dynamic power gating mode */
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/4] drm/amdgpu:Replace value with defined macro
[not found] ` <1538512551-26146-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-03 13:12 ` Leo Liu
0 siblings, 0 replies; 4+ messages in thread
From: Leo Liu @ 2018-10-03 13:12 UTC (permalink / raw)
To: James Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo
Same comment as for v1
Regards,
Leo
On 10/02/2018 04:35 PM, James Zhu wrote:
> Replace value with defined macro to make
> code more readable
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +++++--
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++++++++++--------
> 2 files changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 12a60ec..7ad352c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -309,14 +309,17 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
> /* Restore */
> ring = &adev->vcn.ring_jpeg;
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
> - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L);
> + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> + UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
> + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
> lower_32_bits(ring->gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
> upper_32_bits(ring->gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
> - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
> + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>
> ring = &adev->vcn.ring_dec;
> WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 78a3115b..ceb6d52 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -810,12 +810,12 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>
> for (j = 0; j < 100; ++j) {
> status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
> - if (status & 2)
> + if (status & UVD_STATUS__IDLE)
> break;
> mdelay(10);
> }
> r = 0;
> - if (status & 2)
> + if (status & UVD_STATUS__IDLE)
> break;
>
> DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
> @@ -898,12 +898,13 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>
> ring = &adev->vcn.ring_jpeg;
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
> - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
> + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
> + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
> - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
> + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>
> /* initialize wptr */
> ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
> @@ -1122,8 +1123,9 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
> {
> int ret_code;
>
> - /* Wait for power status to be 1 */
> - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
> + /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
> + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
> + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
> UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
>
> /* disable dynamic power gating mode */
> @@ -1149,7 +1151,7 @@ static bool vcn_v1_0_is_idle(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2);
> + return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
> }
>
> static int vcn_v1_0_wait_for_idle(void *handle)
> @@ -1157,7 +1159,8 @@ static int vcn_v1_0_wait_for_idle(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> int ret = 0;
>
> - SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, 0x2, 0x2, ret);
> + SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
> + UVD_STATUS__IDLE, ret);
>
> return ret;
> }
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-10-03 13:12 UTC | newest]
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-- links below jump to the message on this page --
2018-10-02 17:20 [PATCH] drm/amdgpu:Replace value with defined macro James Zhu
[not found] ` <1538500848-13846-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-10-02 20:35 ` [PATCH v2 1/4] " James Zhu
[not found] ` <1538512551-26146-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-10-03 13:12 ` Leo Liu
2018-10-03 13:10 ` [PATCH] " Leo Liu
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