From: <Conor.Dooley@microchip.com> To: <bmeng.cn@gmail.com>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <atish.patra@wdc.com>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> Cc: <bin.meng@windriver.com> Subject: Re: [PATCH] riscv: dts: microchip: Define hart clocks Date: Tue, 13 Jul 2021 15:31:02 +0000 [thread overview] Message-ID: <cd14275c-4a81-ad92-ffc7-d81ead203fad@microchip.com> (raw) In-Reply-To: <20210616062739.398790-1-bmeng.cn@gmail.com> On 16/06/2021 07:27, Bin Meng wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > From: Bin Meng <bin.meng@windriver.com> > > Declare that each hart in the DT is clocked by <&clkcfg 0>. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > --- > Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/, > this adds the same <clock> property to PolarFire SoC CPU nodes so that we can > calculate the running frequency of the hart. > > arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > index a00d9dc560d3..0659068b62f7 100644 > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > @@ -24,6 +24,7 @@ cpu@0 { > i-cache-size = <16384>; > reg = <0>; > riscv,isa = "rv64imac"; > + clocks = <&clkcfg 0>; > status = "disabled"; > > cpu0_intc: interrupt-controller { > @@ -50,6 +51,7 @@ cpu@1 { > reg = <1>; > riscv,isa = "rv64imafdc"; > tlb-split; > + clocks = <&clkcfg 0>; > status = "okay"; > > cpu1_intc: interrupt-controller { > @@ -76,6 +78,7 @@ cpu@2 { > reg = <2>; > riscv,isa = "rv64imafdc"; > tlb-split; > + clocks = <&clkcfg 0>; > status = "okay"; > > cpu2_intc: interrupt-controller { > @@ -102,6 +105,7 @@ cpu@3 { > reg = <3>; > riscv,isa = "rv64imafdc"; > tlb-split; > + clocks = <&clkcfg 0>; > status = "okay"; > > cpu3_intc: interrupt-controller { > @@ -128,6 +132,7 @@ cpu@4 { > reg = <4>; > riscv,isa = "rv64imafdc"; > tlb-split; > + clocks = <&clkcfg 0>; > status = "okay"; > cpu4_intc: interrupt-controller { > #interrupt-cells = <1>; > -- > 2.25.1 > Reviewed-by: conor dooley<conor.dooley@microchip.com> > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com> To: <bmeng.cn@gmail.com>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <atish.patra@wdc.com>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> Cc: <bin.meng@windriver.com> Subject: Re: [PATCH] riscv: dts: microchip: Define hart clocks Date: Tue, 13 Jul 2021 15:31:02 +0000 [thread overview] Message-ID: <cd14275c-4a81-ad92-ffc7-d81ead203fad@microchip.com> (raw) In-Reply-To: <20210616062739.398790-1-bmeng.cn@gmail.com> On 16/06/2021 07:27, Bin Meng wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > From: Bin Meng <bin.meng@windriver.com> > > Declare that each hart in the DT is clocked by <&clkcfg 0>. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > --- > Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/, > this adds the same <clock> property to PolarFire SoC CPU nodes so that we can > calculate the running frequency of the hart. > > arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > index a00d9dc560d3..0659068b62f7 100644 > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > @@ -24,6 +24,7 @@ cpu@0 { > i-cache-size = <16384>; > reg = <0>; > riscv,isa = "rv64imac"; > + clocks = <&clkcfg 0>; > status = "disabled"; > > cpu0_intc: interrupt-controller { > @@ -50,6 +51,7 @@ cpu@1 { > reg = <1>; > riscv,isa = "rv64imafdc"; > tlb-split; > + clocks = <&clkcfg 0>; > status = "okay"; > > cpu1_intc: interrupt-controller { > @@ -76,6 +78,7 @@ cpu@2 { > reg = <2>; > riscv,isa = "rv64imafdc"; > tlb-split; > + clocks = <&clkcfg 0>; > status = "okay"; > > cpu2_intc: interrupt-controller { > @@ -102,6 +105,7 @@ cpu@3 { > reg = <3>; > riscv,isa = "rv64imafdc"; > tlb-split; > + clocks = <&clkcfg 0>; > status = "okay"; > > cpu3_intc: interrupt-controller { > @@ -128,6 +132,7 @@ cpu@4 { > reg = <4>; > riscv,isa = "rv64imafdc"; > tlb-split; > + clocks = <&clkcfg 0>; > status = "okay"; > cpu4_intc: interrupt-controller { > #interrupt-cells = <1>; > -- > 2.25.1 > Reviewed-by: conor dooley<conor.dooley@microchip.com> > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-07-13 15:31 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-16 6:27 [PATCH] riscv: dts: microchip: Define hart clocks Bin Meng 2021-06-16 6:27 ` Bin Meng 2021-07-08 13:39 ` Bin Meng 2021-07-08 13:39 ` Bin Meng 2021-07-13 15:31 ` Conor.Dooley [this message] 2021-07-13 15:31 ` Conor.Dooley
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