* [PATCH 0/6] fsys0/1 clock support for Exynos Auto v9 SoC
[not found] <CGME20220727060612epcas2p1e3631dbc4775de76cd62554a20bae716@epcas2p1.samsung.com>
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
Lanes. Similarly, CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1,
2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also
supported as a PLL source clock provider.
Chanho Park (6):
dt-bindings: clk: exynosautov9: add fys0 clock definitions
dt-bindings: clock: exynosautov9: add fsys1 clock definitions
dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
clk: samsung: exynosautov9: add fsys0 clock support
clk: samsung: exynosautov9: add fsys1 clock support
.../clock/samsung,exynosautov9-clock.yaml | 44 +++
arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 ++
drivers/clk/samsung/clk-exynosautov9.c | 372 ++++++++++++++++++
.../dt-bindings/clock/samsung,exynosautov9.h | 68 ++++
4 files changed, 512 insertions(+)
--
2.37.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 0/6] fsys0/1 clock support for Exynos Auto v9 SoC
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
Lanes. Similarly, CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1,
2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also
supported as a PLL source clock provider.
Chanho Park (6):
dt-bindings: clk: exynosautov9: add fys0 clock definitions
dt-bindings: clock: exynosautov9: add fsys1 clock definitions
dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
clk: samsung: exynosautov9: add fsys0 clock support
clk: samsung: exynosautov9: add fsys1 clock support
.../clock/samsung,exynosautov9-clock.yaml | 44 +++
arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 ++
drivers/clk/samsung/clk-exynosautov9.c | 372 ++++++++++++++++++
.../dt-bindings/clock/samsung,exynosautov9.h | 68 ++++
4 files changed, 512 insertions(+)
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions
[not found] ` <CGME20220727060612epcas2p355e7f9ca3700cad4778e944cbdbf2d50@epcas2p3.samsung.com>
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
Add fsys0(for PCIe) clock definitions.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
.../dt-bindings/clock/samsung,exynosautov9.h | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index ea9f91b4eb1a..6305a84396ce 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -185,6 +185,49 @@
#define CORE_NR_CLK 6
+/* CMU_FSYS0 */
+#define CLK_MOUT_FSYS0_BUS_USER 1
+#define CLK_MOUT_FSYS0_PCIE_USER 2
+#define CLK_GOUT_FSYS0_BUS_PCLK 3
+
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12
+#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13
+#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14
+
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23
+#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24
+#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25
+
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34
+#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35
+#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36
+
+#define FSYS0_NR_CLK 37
+
/* CMU_FSYS2 */
#define CLK_MOUT_FSYS2_BUS_USER 1
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
--
2.37.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
Add fsys0(for PCIe) clock definitions.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
.../dt-bindings/clock/samsung,exynosautov9.h | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index ea9f91b4eb1a..6305a84396ce 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -185,6 +185,49 @@
#define CORE_NR_CLK 6
+/* CMU_FSYS0 */
+#define CLK_MOUT_FSYS0_BUS_USER 1
+#define CLK_MOUT_FSYS0_PCIE_USER 2
+#define CLK_GOUT_FSYS0_BUS_PCLK 3
+
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12
+#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13
+#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14
+
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22
+#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23
+#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24
+#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25
+
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33
+#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34
+#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35
+#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36
+
+#define FSYS0_NR_CLK 37
+
/* CMU_FSYS2 */
#define CLK_MOUT_FSYS2_BUS_USER 1
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions
[not found] ` <CGME20220727060612epcas2p34e861279ece7fbd3c7c87ce02c7d795c@epcas2p3.samsung.com>
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
Add fsys1(for usb and mmc) clock definitions.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
.../dt-bindings/clock/samsung,exynosautov9.h | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index 6305a84396ce..7e11e681da5c 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -228,6 +228,31 @@
#define FSYS0_NR_CLK 37
+/* CMU_FSYS1 */
+#define FOUT_MMC_PLL 1
+
+#define CLK_MOUT_FSYS1_BUS_USER 2
+#define CLK_MOUT_MMC_PLL 3
+#define CLK_MOUT_FSYS1_MMC_CARD_USER 4
+#define CLK_MOUT_FSYS1_USBDRD_USER 5
+#define CLK_MOUT_FSYS1_MMC_CARD 6
+
+#define CLK_DOUT_FSYS1_MMC_CARD 7
+
+#define CLK_GOUT_FSYS1_PCLK 8
+#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9
+#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10
+#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11
+#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12
+#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13
+#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14
+#define CLK_GOUT_FSYS1_USB20_0_ACLK 15
+#define CLK_GOUT_FSYS1_USB20_1_ACLK 16
+#define CLK_GOUT_FSYS1_USB30_0_ACLK 17
+#define CLK_GOUT_FSYS1_USB30_1_ACLK 18
+
+#define FSYS1_NR_CLK 19
+
/* CMU_FSYS2 */
#define CLK_MOUT_FSYS2_BUS_USER 1
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
--
2.37.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
Add fsys1(for usb and mmc) clock definitions.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
.../dt-bindings/clock/samsung,exynosautov9.h | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index 6305a84396ce..7e11e681da5c 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -228,6 +228,31 @@
#define FSYS0_NR_CLK 37
+/* CMU_FSYS1 */
+#define FOUT_MMC_PLL 1
+
+#define CLK_MOUT_FSYS1_BUS_USER 2
+#define CLK_MOUT_MMC_PLL 3
+#define CLK_MOUT_FSYS1_MMC_CARD_USER 4
+#define CLK_MOUT_FSYS1_USBDRD_USER 5
+#define CLK_MOUT_FSYS1_MMC_CARD 6
+
+#define CLK_DOUT_FSYS1_MMC_CARD 7
+
+#define CLK_GOUT_FSYS1_PCLK 8
+#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9
+#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10
+#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11
+#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12
+#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13
+#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14
+#define CLK_GOUT_FSYS1_USB20_0_ACLK 15
+#define CLK_GOUT_FSYS1_USB20_1_ACLK 16
+#define CLK_GOUT_FSYS1_USB30_0_ACLK 17
+#define CLK_GOUT_FSYS1_USB30_1_ACLK 18
+
+#define FSYS1_NR_CLK 19
+
/* CMU_FSYS2 */
#define CLK_MOUT_FSYS2_BUS_USER 1
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
[not found] ` <CGME20220727060612epcas2p4b844ea92fe11c302337a320b222947d3@epcas2p4.samsung.com>
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate
cmu_fsys0 and fsys1 for Exynos Auto v9 SoC.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
.../clock/samsung,exynosautov9-clock.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
index eafc715d2d02..2ab4642679c0 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
@@ -35,6 +35,8 @@ properties:
- samsung,exynosautov9-cmu-top
- samsung,exynosautov9-cmu-busmc
- samsung,exynosautov9-cmu-core
+ - samsung,exynosautov9-cmu-fsys0
+ - samsung,exynosautov9-cmu-fsys1
- samsung,exynosautov9-cmu-fsys2
- samsung,exynosautov9-cmu-peric0
- samsung,exynosautov9-cmu-peric1
@@ -107,6 +109,48 @@ allOf:
- const: oscclk
- const: dout_clkcmu_core_bus
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-fsys0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_FSYS0 bus clock (from CMU_TOP)
+ - description: CMU_FSYS0 pcie clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_fsys0_bus
+ - const: dout_clkcmu_fsys0_pcie
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-fsys1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_FSYS1 bus clock (from CMU_TOP)
+ - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
+ - description: CMU_FSYS1 usb clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_fsys1_bus
+ - const: dout_clkcmu_fsys1_mmc_card
+ - const: dout_clkcmu_fsys1_usbdrd
+
- if:
properties:
compatible:
--
2.37.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate
cmu_fsys0 and fsys1 for Exynos Auto v9 SoC.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
.../clock/samsung,exynosautov9-clock.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
index eafc715d2d02..2ab4642679c0 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
@@ -35,6 +35,8 @@ properties:
- samsung,exynosautov9-cmu-top
- samsung,exynosautov9-cmu-busmc
- samsung,exynosautov9-cmu-core
+ - samsung,exynosautov9-cmu-fsys0
+ - samsung,exynosautov9-cmu-fsys1
- samsung,exynosautov9-cmu-fsys2
- samsung,exynosautov9-cmu-peric0
- samsung,exynosautov9-cmu-peric1
@@ -107,6 +109,48 @@ allOf:
- const: oscclk
- const: dout_clkcmu_core_bus
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-fsys0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_FSYS0 bus clock (from CMU_TOP)
+ - description: CMU_FSYS0 pcie clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_fsys0_bus
+ - const: dout_clkcmu_fsys0_pcie
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-fsys1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_FSYS1 bus clock (from CMU_TOP)
+ - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
+ - description: CMU_FSYS1 usb clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_fsys1_bus
+ - const: dout_clkcmu_fsys1_mmc_card
+ - const: dout_clkcmu_fsys1_usbdrd
+
- if:
properties:
compatible:
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 4/6] arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
[not found] ` <CGME20220727060612epcas2p3fa8d9a1e8ab3db929b3518ac8aca770c@epcas2p3.samsung.com>
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
Add cmu_fsys0 and cmu_fsys1 for PCIe clocks and USB/MMC clocks
respectively.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 ++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
index 2013718532f3..58b3b0c5d3fc 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
@@ -207,6 +207,34 @@ cmu_peric1: clock-controller@10800000 {
"dout_clkcmu_peric1_ip";
};
+ cmu_fsys0: clock-controller@17700000 {
+ compatible = "samsung,exynosautov9-cmu-fsys0";
+ reg = <0x17700000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
+ <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
+ clock-names = "oscclk",
+ "dout_clkcmu_fsys0_bus",
+ "dout_clkcmu_fsys0_pcie";
+ };
+
+ cmu_fsys1: clock-controller@17040000 {
+ compatible = "samsung,exynosautov9-cmu-fsys1";
+ reg = <0x17040000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
+ <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
+ <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
+ clock-names = "oscclk",
+ "dout_clkcmu_fsys1_bus",
+ "gout_clkcmu_fsys1_mmc_card",
+ "dout_clkcmu_fsys1_usbdrd";
+ };
+
cmu_fsys2: clock-controller@17c00000 {
compatible = "samsung,exynosautov9-cmu-fsys2";
reg = <0x17c00000 0x8000>;
--
2.37.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 4/6] arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
Add cmu_fsys0 and cmu_fsys1 for PCIe clocks and USB/MMC clocks
respectively.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 ++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
index 2013718532f3..58b3b0c5d3fc 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
@@ -207,6 +207,34 @@ cmu_peric1: clock-controller@10800000 {
"dout_clkcmu_peric1_ip";
};
+ cmu_fsys0: clock-controller@17700000 {
+ compatible = "samsung,exynosautov9-cmu-fsys0";
+ reg = <0x17700000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
+ <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
+ clock-names = "oscclk",
+ "dout_clkcmu_fsys0_bus",
+ "dout_clkcmu_fsys0_pcie";
+ };
+
+ cmu_fsys1: clock-controller@17040000 {
+ compatible = "samsung,exynosautov9-cmu-fsys1";
+ reg = <0x17040000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
+ <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
+ <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
+ clock-names = "oscclk",
+ "dout_clkcmu_fsys1_bus",
+ "gout_clkcmu_fsys1_mmc_card",
+ "dout_clkcmu_fsys1_usbdrd";
+ };
+
cmu_fsys2: clock-controller@17c00000 {
compatible = "samsung,exynosautov9-cmu-fsys2";
reg = <0x17c00000 0x8000>;
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5/6] clk: samsung: exynosautov9: add fsys0 clock support
[not found] ` <CGME20220727060612epcas2p1e79b8d8bfb9e8a3ea351c4dbd7c42b7d@epcas2p1.samsung.com>
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
Lanes.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/samsung/clk-exynosautov9.c | 243 +++++++++++++++++++++++++
1 file changed, 243 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index d9e1f8e4a7b4..527a6837661e 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1067,6 +1067,246 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.clk_name = "dout_clkcmu_core_bus",
};
+/* ---- CMU_FSYS0 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_FSYS2 (0x17700000) */
+#define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
+
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
+
+
+static const unsigned long fsys0_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS0 */
+PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" };
+PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" };
+
+static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
+ mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user",
+ mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1),
+};
+
+static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk",
+ "mout_fsys0_bus_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+
+ /* Gen3 2L0 */
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK,
+ "gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK,
+ "gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK,
+ "gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK,
+ "gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
+ 21, 0, 0),
+
+ /* Gen3 2L1 */
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK,
+ "gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK,
+ "gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK,
+ "gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK,
+ "gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
+ 21, 0, 0),
+
+ /* Gen3 4L */
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK,
+ "gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK,
+ "gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK,
+ "gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK,
+ "gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
+ .mux_clks = fsys0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
+ .gate_clks = fsys0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
+ .nr_clk_ids = FSYS0_NR_CLK,
+ .clk_regs = fsys0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
+ .clk_name = "dout_clkcmu_fsys0_bus",
+};
+
/* ---- CMU_FSYS2 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
@@ -1701,6 +1941,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
}, {
.compatible = "samsung,exynosautov9-cmu-core",
.data = &core_cmu_info,
+ }, {
+ .compatible = "samsung,exynosautov9-cmu-fsys0",
+ .data = &fsys0_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys2",
.data = &fsys2_cmu_info,
--
2.37.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5/6] clk: samsung: exynosautov9: add fsys0 clock support
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
Lanes.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/samsung/clk-exynosautov9.c | 243 +++++++++++++++++++++++++
1 file changed, 243 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index d9e1f8e4a7b4..527a6837661e 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1067,6 +1067,246 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.clk_name = "dout_clkcmu_core_bus",
};
+/* ---- CMU_FSYS0 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_FSYS2 (0x17700000) */
+#define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
+
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
+#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
+#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
+
+
+static const unsigned long fsys0_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS0 */
+PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" };
+PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" };
+
+static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
+ mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user",
+ mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1),
+};
+
+static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk",
+ "mout_fsys0_bus_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+
+ /* Gen3 2L0 */
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK,
+ "gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK,
+ "gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK,
+ "gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK,
+ "gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
+ 21, 0, 0),
+
+ /* Gen3 2L1 */
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK,
+ "gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK,
+ "gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK,
+ "gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK,
+ "gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
+ 21, 0, 0),
+
+ /* Gen3 4L */
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK,
+ "gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK,
+ "gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK,
+ "gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK,
+ "gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK,
+ "gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
+ .mux_clks = fsys0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
+ .gate_clks = fsys0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
+ .nr_clk_ids = FSYS0_NR_CLK,
+ .clk_regs = fsys0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
+ .clk_name = "dout_clkcmu_fsys0_bus",
+};
+
/* ---- CMU_FSYS2 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
@@ -1701,6 +1941,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
}, {
.compatible = "samsung,exynosautov9-cmu-core",
.data = &core_cmu_info,
+ }, {
+ .compatible = "samsung,exynosautov9-cmu-fsys0",
+ .data = &fsys0_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys2",
.data = &fsys2_cmu_info,
--
2.37.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 6/6] clk: samsung: exynosautov9: add fsys1 clock support
[not found] ` <CGME20220727060612epcas2p47e21a2545b686d536de47518f7b5c199@epcas2p4.samsung.com>
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and
mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL
source clock provider.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/samsung/clk-exynosautov9.c | 129 +++++++++++++++++++++++++
1 file changed, 129 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index 527a6837661e..b61eec1244cc 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1307,6 +1307,132 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.clk_name = "dout_clkcmu_fsys0_bus",
};
+/* ---- CMU_FSYS1 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
+#define PLL_LOCKTIME_PLL_MMC 0x0000
+#define PLL_CON0_PLL_MMC 0x0100
+#define PLL_CON3_PLL_MMC 0x010c
+#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
+#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
+
+#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
+#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
+
+static const unsigned long fsys1_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
+};
+
+static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
+ PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
+ PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS1 */
+PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
+PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
+PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
+PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
+PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user", "mout_mmc_pll" };
+
+static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
+ mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
+ PLL_CON0_PLL_MMC, 4, 1),
+ MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
+ mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
+ 4, 1),
+ MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
+ mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
+ 4, 1),
+ MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
+ mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
+ 0, 1),
+};
+
+static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
+ DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
+ "mout_fsys1_mmc_card",
+ CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
+};
+
+static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
+ "dout_fsys1_mmc_card",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
+ 21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
+ "dout_fsys1_mmc_card",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
+ .pll_clks = fsys1_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
+ .mux_clks = fsys1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
+ .div_clks = fsys1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
+ .gate_clks = fsys1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
+ .nr_clk_ids = FSYS1_NR_CLK,
+ .clk_regs = fsys1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
+ .clk_name = "dout_clkcmu_fsys1_bus",
+};
+
/* ---- CMU_FSYS2 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
@@ -1944,6 +2070,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
}, {
.compatible = "samsung,exynosautov9-cmu-fsys0",
.data = &fsys0_cmu_info,
+ }, {
+ .compatible = "samsung,exynosautov9-cmu-fsys1",
+ .data = &fsys1_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys2",
.data = &fsys2_cmu_info,
--
2.37.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 6/6] clk: samsung: exynosautov9: add fsys1 clock support
@ 2022-07-27 6:01 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 6:01 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel, Chanho Park
CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and
mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL
source clock provider.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/samsung/clk-exynosautov9.c | 129 +++++++++++++++++++++++++
1 file changed, 129 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index 527a6837661e..b61eec1244cc 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1307,6 +1307,132 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.clk_name = "dout_clkcmu_fsys0_bus",
};
+/* ---- CMU_FSYS1 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
+#define PLL_LOCKTIME_PLL_MMC 0x0000
+#define PLL_CON0_PLL_MMC 0x0100
+#define PLL_CON3_PLL_MMC 0x010c
+#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
+#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
+
+#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
+#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
+
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
+#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
+
+static const unsigned long fsys1_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
+};
+
+static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
+ PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
+ PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS1 */
+PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
+PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
+PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
+PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
+PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user", "mout_mmc_pll" };
+
+static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
+ mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
+ PLL_CON0_PLL_MMC, 4, 1),
+ MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
+ mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
+ 4, 1),
+ MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
+ mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
+ 4, 1),
+ MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
+ mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
+ 0, 1),
+};
+
+static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
+ DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
+ "mout_fsys1_mmc_card",
+ CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
+};
+
+static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
+ "dout_fsys1_mmc_card",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
+ 21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
+ "dout_fsys1_mmc_card",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
+ "mout_fsys1_usbdrd_user",
+ CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
+ .pll_clks = fsys1_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
+ .mux_clks = fsys1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
+ .div_clks = fsys1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
+ .gate_clks = fsys1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
+ .nr_clk_ids = FSYS1_NR_CLK,
+ .clk_regs = fsys1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
+ .clk_name = "dout_clkcmu_fsys1_bus",
+};
+
/* ---- CMU_FSYS2 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
@@ -1944,6 +2070,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
}, {
.compatible = "samsung,exynosautov9-cmu-fsys0",
.data = &fsys0_cmu_info,
+ }, {
+ .compatible = "samsung,exynosautov9-cmu-fsys1",
+ .data = &fsys1_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys2",
.data = &fsys2_cmu_info,
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions
2022-07-27 6:01 ` Chanho Park
@ 2022-07-27 7:38 ` Chanwoo Choi
-1 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:38 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add fsys1(for usb and mmc) clock definitions.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> .../dt-bindings/clock/samsung,exynosautov9.h | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index 6305a84396ce..7e11e681da5c 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -228,6 +228,31 @@
>
> #define FSYS0_NR_CLK 37
>
> +/* CMU_FSYS1 */
> +#define FOUT_MMC_PLL 1
> +
> +#define CLK_MOUT_FSYS1_BUS_USER 2
> +#define CLK_MOUT_MMC_PLL 3
nitpik. This clock id doesn't have 'FSYS1' word. Is it right?
> +#define CLK_MOUT_FSYS1_MMC_CARD_USER 4
> +#define CLK_MOUT_FSYS1_USBDRD_USER 5
> +#define CLK_MOUT_FSYS1_MMC_CARD 6
> +
> +#define CLK_DOUT_FSYS1_MMC_CARD 7
> +
> +#define CLK_GOUT_FSYS1_PCLK 8
> +#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9
> +#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10
> +#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11
> +#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12
> +#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13
> +#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14
> +#define CLK_GOUT_FSYS1_USB20_0_ACLK 15
> +#define CLK_GOUT_FSYS1_USB20_1_ACLK 16
> +#define CLK_GOUT_FSYS1_USB30_0_ACLK 17
> +#define CLK_GOUT_FSYS1_USB30_1_ACLK 18
> +
> +#define FSYS1_NR_CLK 19
> +
> /* CMU_FSYS2 */
> #define CLK_MOUT_FSYS2_BUS_USER 1
> #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions
@ 2022-07-27 7:38 ` Chanwoo Choi
0 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:38 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add fsys1(for usb and mmc) clock definitions.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> .../dt-bindings/clock/samsung,exynosautov9.h | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index 6305a84396ce..7e11e681da5c 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -228,6 +228,31 @@
>
> #define FSYS0_NR_CLK 37
>
> +/* CMU_FSYS1 */
> +#define FOUT_MMC_PLL 1
> +
> +#define CLK_MOUT_FSYS1_BUS_USER 2
> +#define CLK_MOUT_MMC_PLL 3
nitpik. This clock id doesn't have 'FSYS1' word. Is it right?
> +#define CLK_MOUT_FSYS1_MMC_CARD_USER 4
> +#define CLK_MOUT_FSYS1_USBDRD_USER 5
> +#define CLK_MOUT_FSYS1_MMC_CARD 6
> +
> +#define CLK_DOUT_FSYS1_MMC_CARD 7
> +
> +#define CLK_GOUT_FSYS1_PCLK 8
> +#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9
> +#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10
> +#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11
> +#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12
> +#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13
> +#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14
> +#define CLK_GOUT_FSYS1_USB20_0_ACLK 15
> +#define CLK_GOUT_FSYS1_USB20_1_ACLK 16
> +#define CLK_GOUT_FSYS1_USB30_0_ACLK 17
> +#define CLK_GOUT_FSYS1_USB30_1_ACLK 18
> +
> +#define FSYS1_NR_CLK 19
> +
> /* CMU_FSYS2 */
> #define CLK_MOUT_FSYS2_BUS_USER 1
> #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
--
Best Regards,
Samsung Electronics
Chanwoo Choi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions
2022-07-27 6:01 ` Chanho Park
@ 2022-07-27 7:39 ` Chanwoo Choi
-1 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:39 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add fsys0(for PCIe) clock definitions.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> .../dt-bindings/clock/samsung,exynosautov9.h | 43 +++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index ea9f91b4eb1a..6305a84396ce 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -185,6 +185,49 @@
>
> #define CORE_NR_CLK 6
>
> +/* CMU_FSYS0 */
> +#define CLK_MOUT_FSYS0_BUS_USER 1
> +#define CLK_MOUT_FSYS0_PCIE_USER 2
> +#define CLK_GOUT_FSYS0_BUS_PCLK 3
> +
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12
> +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13
> +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14
> +
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23
> +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24
> +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25
> +
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34
> +#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35
> +#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36
> +
> +#define FSYS0_NR_CLK 37
> +
> /* CMU_FSYS2 */
> #define CLK_MOUT_FSYS2_BUS_USER 1
> #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions
@ 2022-07-27 7:39 ` Chanwoo Choi
0 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:39 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add fsys0(for PCIe) clock definitions.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> .../dt-bindings/clock/samsung,exynosautov9.h | 43 +++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index ea9f91b4eb1a..6305a84396ce 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -185,6 +185,49 @@
>
> #define CORE_NR_CLK 6
>
> +/* CMU_FSYS0 */
> +#define CLK_MOUT_FSYS0_BUS_USER 1
> +#define CLK_MOUT_FSYS0_PCIE_USER 2
> +#define CLK_GOUT_FSYS0_BUS_PCLK 3
> +
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12
> +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13
> +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14
> +
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23
> +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24
> +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25
> +
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33
> +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34
> +#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35
> +#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36
> +
> +#define FSYS0_NR_CLK 37
> +
> /* CMU_FSYS2 */
> #define CLK_MOUT_FSYS2_BUS_USER 1
> #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
2022-07-27 6:01 ` Chanho Park
@ 2022-07-27 7:39 ` Chanwoo Choi
-1 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:39 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate
> cmu_fsys0 and fsys1 for Exynos Auto v9 SoC.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> .../clock/samsung,exynosautov9-clock.yaml | 44 +++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
> index eafc715d2d02..2ab4642679c0 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
> @@ -35,6 +35,8 @@ properties:
> - samsung,exynosautov9-cmu-top
> - samsung,exynosautov9-cmu-busmc
> - samsung,exynosautov9-cmu-core
> + - samsung,exynosautov9-cmu-fsys0
> + - samsung,exynosautov9-cmu-fsys1
> - samsung,exynosautov9-cmu-fsys2
> - samsung,exynosautov9-cmu-peric0
> - samsung,exynosautov9-cmu-peric1
> @@ -107,6 +109,48 @@ allOf:
> - const: oscclk
> - const: dout_clkcmu_core_bus
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynosautov9-cmu-fsys0
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_FSYS0 bus clock (from CMU_TOP)
> + - description: CMU_FSYS0 pcie clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_clkcmu_fsys0_bus
> + - const: dout_clkcmu_fsys0_pcie
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynosautov9-cmu-fsys1
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_FSYS1 bus clock (from CMU_TOP)
> + - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
> + - description: CMU_FSYS1 usb clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_clkcmu_fsys1_bus
> + - const: dout_clkcmu_fsys1_mmc_card
> + - const: dout_clkcmu_fsys1_usbdrd
> +
> - if:
> properties:
> compatible:
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
@ 2022-07-27 7:39 ` Chanwoo Choi
0 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:39 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate
> cmu_fsys0 and fsys1 for Exynos Auto v9 SoC.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> .../clock/samsung,exynosautov9-clock.yaml | 44 +++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
> index eafc715d2d02..2ab4642679c0 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
> @@ -35,6 +35,8 @@ properties:
> - samsung,exynosautov9-cmu-top
> - samsung,exynosautov9-cmu-busmc
> - samsung,exynosautov9-cmu-core
> + - samsung,exynosautov9-cmu-fsys0
> + - samsung,exynosautov9-cmu-fsys1
> - samsung,exynosautov9-cmu-fsys2
> - samsung,exynosautov9-cmu-peric0
> - samsung,exynosautov9-cmu-peric1
> @@ -107,6 +109,48 @@ allOf:
> - const: oscclk
> - const: dout_clkcmu_core_bus
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynosautov9-cmu-fsys0
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_FSYS0 bus clock (from CMU_TOP)
> + - description: CMU_FSYS0 pcie clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_clkcmu_fsys0_bus
> + - const: dout_clkcmu_fsys0_pcie
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynosautov9-cmu-fsys1
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_FSYS1 bus clock (from CMU_TOP)
> + - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
> + - description: CMU_FSYS1 usb clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_clkcmu_fsys1_bus
> + - const: dout_clkcmu_fsys1_mmc_card
> + - const: dout_clkcmu_fsys1_usbdrd
> +
> - if:
> properties:
> compatible:
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 4/6] arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
2022-07-27 6:01 ` Chanho Park
@ 2022-07-27 7:40 ` Chanwoo Choi
-1 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:40 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add cmu_fsys0 and cmu_fsys1 for PCIe clocks and USB/MMC clocks
> respectively.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 ++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
> index 2013718532f3..58b3b0c5d3fc 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
> @@ -207,6 +207,34 @@ cmu_peric1: clock-controller@10800000 {
> "dout_clkcmu_peric1_ip";
> };
>
> + cmu_fsys0: clock-controller@17700000 {
> + compatible = "samsung,exynosautov9-cmu-fsys0";
> + reg = <0x17700000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&xtcxo>,
> + <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
> + <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
> + clock-names = "oscclk",
> + "dout_clkcmu_fsys0_bus",
> + "dout_clkcmu_fsys0_pcie";
> + };
> +
> + cmu_fsys1: clock-controller@17040000 {
> + compatible = "samsung,exynosautov9-cmu-fsys1";
> + reg = <0x17040000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&xtcxo>,
> + <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
> + <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
> + <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
> + clock-names = "oscclk",
> + "dout_clkcmu_fsys1_bus",
> + "gout_clkcmu_fsys1_mmc_card",
> + "dout_clkcmu_fsys1_usbdrd";
> + };
> +
> cmu_fsys2: clock-controller@17c00000 {
> compatible = "samsung,exynosautov9-cmu-fsys2";
> reg = <0x17c00000 0x8000>;
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 4/6] arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
@ 2022-07-27 7:40 ` Chanwoo Choi
0 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:40 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add cmu_fsys0 and cmu_fsys1 for PCIe clocks and USB/MMC clocks
> respectively.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 ++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
> index 2013718532f3..58b3b0c5d3fc 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
> @@ -207,6 +207,34 @@ cmu_peric1: clock-controller@10800000 {
> "dout_clkcmu_peric1_ip";
> };
>
> + cmu_fsys0: clock-controller@17700000 {
> + compatible = "samsung,exynosautov9-cmu-fsys0";
> + reg = <0x17700000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&xtcxo>,
> + <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
> + <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
> + clock-names = "oscclk",
> + "dout_clkcmu_fsys0_bus",
> + "dout_clkcmu_fsys0_pcie";
> + };
> +
> + cmu_fsys1: clock-controller@17040000 {
> + compatible = "samsung,exynosautov9-cmu-fsys1";
> + reg = <0x17040000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&xtcxo>,
> + <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
> + <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
> + <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
> + clock-names = "oscclk",
> + "dout_clkcmu_fsys1_bus",
> + "gout_clkcmu_fsys1_mmc_card",
> + "dout_clkcmu_fsys1_usbdrd";
> + };
> +
> cmu_fsys2: clock-controller@17c00000 {
> compatible = "samsung,exynosautov9-cmu-fsys2";
> reg = <0x17c00000 0x8000>;
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5/6] clk: samsung: exynosautov9: add fsys0 clock support
2022-07-27 6:01 ` Chanho Park
@ 2022-07-27 7:44 ` Chanwoo Choi
-1 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:44 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
> Lanes.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/clk/samsung/clk-exynosautov9.c | 243 +++++++++++++++++++++++++
> 1 file changed, 243 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
> index d9e1f8e4a7b4..527a6837661e 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -1067,6 +1067,246 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
> .clk_name = "dout_clkcmu_core_bus",
> };
>
> +/* ---- CMU_FSYS0 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_FSYS2 (0x17700000) */
> +#define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
> +#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
> +
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
> +
> +
> +static const unsigned long fsys0_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
> + PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_FSYS0 */
> +PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" };
> +PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" };
> +
> +static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
> + mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user",
> + mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1),
> +};
> +
> +static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk",
> + "mout_fsys0_bus_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
> + 21, CLK_IGNORE_UNUSED, 0),
> +
> + /* Gen3 2L0 */
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK,
> + "gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK,
> + "gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK,
> + "gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK,
> + "gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
> + 21, 0, 0),
> +
> + /* Gen3 2L1 */
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK,
> + "gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK,
> + "gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK,
> + "gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK,
> + "gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
> + 21, 0, 0),
> +
> + /* Gen3 4L */
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK,
> + "gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK,
> + "gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK,
> + "gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK,
> + "gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
> + .mux_clks = fsys0_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
> + .gate_clks = fsys0_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
> + .nr_clk_ids = FSYS0_NR_CLK,
> + .clk_regs = fsys0_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
> + .clk_name = "dout_clkcmu_fsys0_bus",
> +};
> +
> /* ---- CMU_FSYS2 ---------------------------------------------------------- */
>
> /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
> @@ -1701,6 +1941,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
> }, {
> .compatible = "samsung,exynosautov9-cmu-core",
> .data = &core_cmu_info,
> + }, {
> + .compatible = "samsung,exynosautov9-cmu-fsys0",
> + .data = &fsys0_cmu_info,
> }, {
> .compatible = "samsung,exynosautov9-cmu-fsys2",
> .data = &fsys2_cmu_info,
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5/6] clk: samsung: exynosautov9: add fsys0 clock support
@ 2022-07-27 7:44 ` Chanwoo Choi
0 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:44 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
> Lanes.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/clk/samsung/clk-exynosautov9.c | 243 +++++++++++++++++++++++++
> 1 file changed, 243 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
> index d9e1f8e4a7b4..527a6837661e 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -1067,6 +1067,246 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
> .clk_name = "dout_clkcmu_core_bus",
> };
>
> +/* ---- CMU_FSYS0 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_FSYS2 (0x17700000) */
> +#define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
> +#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
> +
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
> +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
> +
> +
> +static const unsigned long fsys0_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
> + PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_FSYS0 */
> +PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" };
> +PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" };
> +
> +static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
> + mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user",
> + mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1),
> +};
> +
> +static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk",
> + "mout_fsys0_bus_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
> + 21, CLK_IGNORE_UNUSED, 0),
> +
> + /* Gen3 2L0 */
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK,
> + "gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK,
> + "gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK,
> + "gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK,
> + "gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
> + 21, 0, 0),
> +
> + /* Gen3 2L1 */
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK,
> + "gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK,
> + "gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK,
> + "gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK,
> + "gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
> + 21, 0, 0),
> +
> + /* Gen3 4L */
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK,
> + "gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK,
> + "gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK,
> + "gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK,
> + "gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK,
> + "gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
> + .mux_clks = fsys0_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
> + .gate_clks = fsys0_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
> + .nr_clk_ids = FSYS0_NR_CLK,
> + .clk_regs = fsys0_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
> + .clk_name = "dout_clkcmu_fsys0_bus",
> +};
> +
> /* ---- CMU_FSYS2 ---------------------------------------------------------- */
>
> /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
> @@ -1701,6 +1941,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
> }, {
> .compatible = "samsung,exynosautov9-cmu-core",
> .data = &core_cmu_info,
> + }, {
> + .compatible = "samsung,exynosautov9-cmu-fsys0",
> + .data = &fsys0_cmu_info,
> }, {
> .compatible = "samsung,exynosautov9-cmu-fsys2",
> .data = &fsys2_cmu_info,
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 6/6] clk: samsung: exynosautov9: add fsys1 clock support
2022-07-27 6:01 ` Chanho Park
@ 2022-07-27 7:44 ` Chanwoo Choi
-1 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:44 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and
> mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL
> source clock provider.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/clk/samsung/clk-exynosautov9.c | 129 +++++++++++++++++++++++++
> 1 file changed, 129 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
> index 527a6837661e..b61eec1244cc 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -1307,6 +1307,132 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
> .clk_name = "dout_clkcmu_fsys0_bus",
> };
>
> +/* ---- CMU_FSYS1 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
> +#define PLL_LOCKTIME_PLL_MMC 0x0000
> +#define PLL_CON0_PLL_MMC 0x0100
> +#define PLL_CON3_PLL_MMC 0x010c
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
> +
> +#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
> +#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
> +
> +static const unsigned long fsys1_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
> +};
> +
> +static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
> + PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
> + PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_FSYS1 */
> +PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
> +PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
> +PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
> +PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
> +PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user", "mout_mmc_pll" };
> +
> +static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
> + mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
> + PLL_CON0_PLL_MMC, 4, 1),
> + MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
> + mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
> + 4, 1),
> + MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
> + mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
> + 4, 1),
> + MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
> + mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
> + 0, 1),
> +};
> +
> +static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
> + DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
> + "mout_fsys1_mmc_card",
> + CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
> +};
> +
> +static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
> + 21, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
> + "dout_fsys1_mmc_card",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
> + 21, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
> + "dout_fsys1_mmc_card",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
> + .pll_clks = fsys1_pll_clks,
> + .nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
> + .mux_clks = fsys1_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
> + .div_clks = fsys1_div_clks,
> + .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
> + .gate_clks = fsys1_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
> + .nr_clk_ids = FSYS1_NR_CLK,
> + .clk_regs = fsys1_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
> + .clk_name = "dout_clkcmu_fsys1_bus",
> +};
> +
> /* ---- CMU_FSYS2 ---------------------------------------------------------- */
>
> /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
> @@ -1944,6 +2070,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
> }, {
> .compatible = "samsung,exynosautov9-cmu-fsys0",
> .data = &fsys0_cmu_info,
> + }, {
> + .compatible = "samsung,exynosautov9-cmu-fsys1",
> + .data = &fsys1_cmu_info,
> }, {
> .compatible = "samsung,exynosautov9-cmu-fsys2",
> .data = &fsys2_cmu_info,
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 6/6] clk: samsung: exynosautov9: add fsys1 clock support
@ 2022-07-27 7:44 ` Chanwoo Choi
0 siblings, 0 replies; 36+ messages in thread
From: Chanwoo Choi @ 2022-07-27 7:44 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 22. 7. 27. 15:01, Chanho Park wrote:
> CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and
> mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL
> source clock provider.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/clk/samsung/clk-exynosautov9.c | 129 +++++++++++++++++++++++++
> 1 file changed, 129 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
> index 527a6837661e..b61eec1244cc 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -1307,6 +1307,132 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
> .clk_name = "dout_clkcmu_fsys0_bus",
> };
>
> +/* ---- CMU_FSYS1 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
> +#define PLL_LOCKTIME_PLL_MMC 0x0000
> +#define PLL_CON0_PLL_MMC 0x0100
> +#define PLL_CON3_PLL_MMC 0x010c
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
> +
> +#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
> +#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
> +
> +static const unsigned long fsys1_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
> +};
> +
> +static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
> + PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
> + PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_FSYS1 */
> +PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
> +PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
> +PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
> +PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
> +PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user", "mout_mmc_pll" };
> +
> +static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
> + mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
> + PLL_CON0_PLL_MMC, 4, 1),
> + MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
> + mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
> + 4, 1),
> + MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
> + mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
> + 4, 1),
> + MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
> + mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
> + 0, 1),
> +};
> +
> +static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
> + DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
> + "mout_fsys1_mmc_card",
> + CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
> +};
> +
> +static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
> + 21, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
> + "dout_fsys1_mmc_card",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
> + 21, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
> + "dout_fsys1_mmc_card",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
> + .pll_clks = fsys1_pll_clks,
> + .nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
> + .mux_clks = fsys1_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
> + .div_clks = fsys1_div_clks,
> + .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
> + .gate_clks = fsys1_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
> + .nr_clk_ids = FSYS1_NR_CLK,
> + .clk_regs = fsys1_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
> + .clk_name = "dout_clkcmu_fsys1_bus",
> +};
> +
> /* ---- CMU_FSYS2 ---------------------------------------------------------- */
>
> /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
> @@ -1944,6 +2070,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
> }, {
> .compatible = "samsung,exynosautov9-cmu-fsys0",
> .data = &fsys0_cmu_info,
> + }, {
> + .compatible = "samsung,exynosautov9-cmu-fsys1",
> + .data = &fsys1_cmu_info,
> }, {
> .compatible = "samsung,exynosautov9-cmu-fsys2",
> .data = &fsys2_cmu_info,
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions
2022-07-27 7:38 ` Chanwoo Choi
@ 2022-07-27 7:53 ` Chanho Park
-1 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 7:53 UTC (permalink / raw)
To: 'Chanwoo Choi', 'Sylwester Nawrocki',
'Tomasz Figa', 'Chanwoo Choi',
'Krzysztof Kozlowski', 'Stephen Boyd',
'Michael Turquette', 'Rob Herring',
'Krzysztof Kozlowski'
Cc: 'Sam Protsenko', 'Alim Akhtar',
linux-samsung-soc, devicetree, linux-clk, linux-arm-kernel
> Subject: Re: [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock
> definitions
>
> On 22. 7. 27. 15:01, Chanho Park wrote:
> > Add fsys1(for usb and mmc) clock definitions.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > ---
> > .../dt-bindings/clock/samsung,exynosautov9.h | 25 +++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h
> b/include/dt-bindings/clock/samsung,exynosautov9.h
> > index 6305a84396ce..7e11e681da5c 100644
> > --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> > +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> > @@ -228,6 +228,31 @@
> >
> > #define FSYS0_NR_CLK 37
> >
> > +/* CMU_FSYS1 */
> > +#define FOUT_MMC_PLL 1
> > +
> > +#define CLK_MOUT_FSYS1_BUS_USER 2
> > +#define CLK_MOUT_MMC_PLL 3
>
> nitpik. This clock id doesn't have 'FSYS1' word. Is it right?
Nice catch. I copied it from the SoC User manual but it should have the FSYS1 prefix because it's definitely included in the FSYS1 cmu block
I'll update it next patchset.
Best Regards,
Chanho Park
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions
@ 2022-07-27 7:53 ` Chanho Park
0 siblings, 0 replies; 36+ messages in thread
From: Chanho Park @ 2022-07-27 7:53 UTC (permalink / raw)
To: 'Chanwoo Choi', 'Sylwester Nawrocki',
'Tomasz Figa', 'Chanwoo Choi',
'Krzysztof Kozlowski', 'Stephen Boyd',
'Michael Turquette', 'Rob Herring',
'Krzysztof Kozlowski'
Cc: 'Sam Protsenko', 'Alim Akhtar',
linux-samsung-soc, devicetree, linux-clk, linux-arm-kernel
> Subject: Re: [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock
> definitions
>
> On 22. 7. 27. 15:01, Chanho Park wrote:
> > Add fsys1(for usb and mmc) clock definitions.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > ---
> > .../dt-bindings/clock/samsung,exynosautov9.h | 25 +++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h
> b/include/dt-bindings/clock/samsung,exynosautov9.h
> > index 6305a84396ce..7e11e681da5c 100644
> > --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> > +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> > @@ -228,6 +228,31 @@
> >
> > #define FSYS0_NR_CLK 37
> >
> > +/* CMU_FSYS1 */
> > +#define FOUT_MMC_PLL 1
> > +
> > +#define CLK_MOUT_FSYS1_BUS_USER 2
> > +#define CLK_MOUT_MMC_PLL 3
>
> nitpik. This clock id doesn't have 'FSYS1' word. Is it right?
Nice catch. I copied it from the SoC User manual but it should have the FSYS1 prefix because it's definitely included in the FSYS1 cmu block
I'll update it next patchset.
Best Regards,
Chanho Park
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions
2022-07-27 6:01 ` Chanho Park
@ 2022-07-28 8:17 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-28 8:17 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 27/07/2022 08:01, Chanho Park wrote:
> Add fsys0(for PCIe) clock definitions.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions
@ 2022-07-28 8:17 ` Krzysztof Kozlowski
0 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-28 8:17 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 27/07/2022 08:01, Chanho Park wrote:
> Add fsys0(for PCIe) clock definitions.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
2022-07-27 6:01 ` Chanho Park
@ 2022-07-28 8:18 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-28 8:18 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 27/07/2022 08:01, Chanho Park wrote:
> Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate
> cmu_fsys0 and fsys1 for Exynos Auto v9 SoC.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
@ 2022-07-28 8:18 ` Krzysztof Kozlowski
0 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-28 8:18 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 27/07/2022 08:01, Chanho Park wrote:
> Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate
> cmu_fsys0 and fsys1 for Exynos Auto v9 SoC.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5/6] clk: samsung: exynosautov9: add fsys0 clock support
2022-07-27 6:01 ` Chanho Park
@ 2022-07-28 8:19 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-28 8:19 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 27/07/2022 08:01, Chanho Park wrote:
> CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
> Lanes.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5/6] clk: samsung: exynosautov9: add fsys0 clock support
@ 2022-07-28 8:19 ` Krzysztof Kozlowski
0 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-28 8:19 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 27/07/2022 08:01, Chanho Park wrote:
> CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
> Lanes.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 6/6] clk: samsung: exynosautov9: add fsys1 clock support
2022-07-27 6:01 ` Chanho Park
@ 2022-07-28 8:20 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-28 8:20 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 27/07/2022 08:01, Chanho Park wrote:
> CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and
> mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL
> source clock provider.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 6/6] clk: samsung: exynosautov9: add fsys1 clock support
@ 2022-07-28 8:20 ` Krzysztof Kozlowski
0 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-28 8:20 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Sam Protsenko, Alim Akhtar, linux-samsung-soc, devicetree,
linux-clk, linux-arm-kernel
On 27/07/2022 08:01, Chanho Park wrote:
> CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and
> mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL
> source clock provider.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2022-07-28 8:21 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <CGME20220727060612epcas2p1e3631dbc4775de76cd62554a20bae716@epcas2p1.samsung.com>
2022-07-27 6:01 ` [PATCH 0/6] fsys0/1 clock support for Exynos Auto v9 SoC Chanho Park
2022-07-27 6:01 ` Chanho Park
[not found] ` <CGME20220727060612epcas2p355e7f9ca3700cad4778e944cbdbf2d50@epcas2p3.samsung.com>
2022-07-27 6:01 ` [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions Chanho Park
2022-07-27 6:01 ` Chanho Park
2022-07-27 7:39 ` Chanwoo Choi
2022-07-27 7:39 ` Chanwoo Choi
2022-07-28 8:17 ` Krzysztof Kozlowski
2022-07-28 8:17 ` Krzysztof Kozlowski
[not found] ` <CGME20220727060612epcas2p34e861279ece7fbd3c7c87ce02c7d795c@epcas2p3.samsung.com>
2022-07-27 6:01 ` [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 " Chanho Park
2022-07-27 6:01 ` Chanho Park
2022-07-27 7:38 ` Chanwoo Choi
2022-07-27 7:38 ` Chanwoo Choi
2022-07-27 7:53 ` Chanho Park
2022-07-27 7:53 ` Chanho Park
[not found] ` <CGME20220727060612epcas2p4b844ea92fe11c302337a320b222947d3@epcas2p4.samsung.com>
2022-07-27 6:01 ` [PATCH 3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 Chanho Park
2022-07-27 6:01 ` Chanho Park
2022-07-27 7:39 ` Chanwoo Choi
2022-07-27 7:39 ` Chanwoo Choi
2022-07-28 8:18 ` Krzysztof Kozlowski
2022-07-28 8:18 ` Krzysztof Kozlowski
[not found] ` <CGME20220727060612epcas2p3fa8d9a1e8ab3db929b3518ac8aca770c@epcas2p3.samsung.com>
2022-07-27 6:01 ` [PATCH 4/6] arm64: dts: exynosautov9: add fsys0/1 clock DT nodes Chanho Park
2022-07-27 6:01 ` Chanho Park
2022-07-27 7:40 ` Chanwoo Choi
2022-07-27 7:40 ` Chanwoo Choi
[not found] ` <CGME20220727060612epcas2p1e79b8d8bfb9e8a3ea351c4dbd7c42b7d@epcas2p1.samsung.com>
2022-07-27 6:01 ` [PATCH 5/6] clk: samsung: exynosautov9: add fsys0 clock support Chanho Park
2022-07-27 6:01 ` Chanho Park
2022-07-27 7:44 ` Chanwoo Choi
2022-07-27 7:44 ` Chanwoo Choi
2022-07-28 8:19 ` Krzysztof Kozlowski
2022-07-28 8:19 ` Krzysztof Kozlowski
[not found] ` <CGME20220727060612epcas2p47e21a2545b686d536de47518f7b5c199@epcas2p4.samsung.com>
2022-07-27 6:01 ` [PATCH 6/6] clk: samsung: exynosautov9: add fsys1 " Chanho Park
2022-07-27 6:01 ` Chanho Park
2022-07-27 7:44 ` Chanwoo Choi
2022-07-27 7:44 ` Chanwoo Choi
2022-07-28 8:20 ` Krzysztof Kozlowski
2022-07-28 8:20 ` Krzysztof Kozlowski
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