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* [PATCH 00/16] add device tree for SAM9X60 SoC and SAM9X60-EK board
@ 2020-01-08 12:55 ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

This series add device tree for SAM9X60 SoC and SAM9X60-EK board.
Allong with these, there are patches that documents some compatibles
for SAM9X60's IPs.

Claudiu Beznea (15):
  dt-bindings: at_xdmac: add entry for microchip compatibles
  dt-bindings: atmel-can: add microchip,sam9x60-can
  dt-bindings: atmel-tcb: add microchip,<chip>-tcb
  dt-bindings: atmel-isi: add microchip,sam9x60-isi
  dt-bindings: at91-sama5d2_adc: add microchip,sam9x60-adc
  dt-bindings: atmel-matrix: add microchip,sam9x60-matrix
  dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
  dt-bindings: atmel-sysreg: add microchip,sam9x60-ddramc
  dt-bindings: atmel-smc: add microchip,sam9x60-smc
  dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr
  dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
  dt-bindings: spi_atmel: add microchip,sam9x60-spi
  dt-bindings: atmel-usart: add microchip,<chip>-usart
  dt-bindings: arm: add sam9x60-ek board
  ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B

Sandeep Sheriker Mallikarjun (1):
  ARM: dts: at91: sam9x60: add device tree for soc and board

 .../devicetree/bindings/arm/atmel-at91.yaml        |   6 +
 .../devicetree/bindings/arm/atmel-sysregs.txt      |   1 +
 .../devicetree/bindings/dma/atmel-xdma.txt         |   3 +-
 .../bindings/iio/adc/at91-sama5d2_adc.txt          |   2 +-
 .../devicetree/bindings/media/atmel-isi.txt        |   2 +-
 .../devicetree/bindings/mfd/atmel-gpbr.txt         |   4 +-
 .../devicetree/bindings/mfd/atmel-matrix.txt       |   1 +
 .../devicetree/bindings/mfd/atmel-smc.txt          |   1 +
 .../devicetree/bindings/mfd/atmel-tcb.txt          |   5 +-
 .../devicetree/bindings/mfd/atmel-usart.txt        |   6 +-
 .../devicetree/bindings/mtd/atmel-nand.txt         |   1 +
 .../devicetree/bindings/net/can/atmel-can.txt      |   3 +-
 .../bindings/rtc/atmel,at91rm9200-rtc.txt          |   3 +-
 .../devicetree/bindings/spi/spi_atmel.txt          |   2 +-
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts               | 647 +++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi                     | 691 +++++++++++++++++++++
 arch/arm/configs/at91_dt_defconfig                 |   4 +
 18 files changed, 1373 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 00/16] add device tree for SAM9X60 SoC and SAM9X60-EK board
@ 2020-01-08 12:55 ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

This series add device tree for SAM9X60 SoC and SAM9X60-EK board.
Allong with these, there are patches that documents some compatibles
for SAM9X60's IPs.

Claudiu Beznea (15):
  dt-bindings: at_xdmac: add entry for microchip compatibles
  dt-bindings: atmel-can: add microchip,sam9x60-can
  dt-bindings: atmel-tcb: add microchip,<chip>-tcb
  dt-bindings: atmel-isi: add microchip,sam9x60-isi
  dt-bindings: at91-sama5d2_adc: add microchip,sam9x60-adc
  dt-bindings: atmel-matrix: add microchip,sam9x60-matrix
  dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
  dt-bindings: atmel-sysreg: add microchip,sam9x60-ddramc
  dt-bindings: atmel-smc: add microchip,sam9x60-smc
  dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr
  dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
  dt-bindings: spi_atmel: add microchip,sam9x60-spi
  dt-bindings: atmel-usart: add microchip,<chip>-usart
  dt-bindings: arm: add sam9x60-ek board
  ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B

Sandeep Sheriker Mallikarjun (1):
  ARM: dts: at91: sam9x60: add device tree for soc and board

 .../devicetree/bindings/arm/atmel-at91.yaml        |   6 +
 .../devicetree/bindings/arm/atmel-sysregs.txt      |   1 +
 .../devicetree/bindings/dma/atmel-xdma.txt         |   3 +-
 .../bindings/iio/adc/at91-sama5d2_adc.txt          |   2 +-
 .../devicetree/bindings/media/atmel-isi.txt        |   2 +-
 .../devicetree/bindings/mfd/atmel-gpbr.txt         |   4 +-
 .../devicetree/bindings/mfd/atmel-matrix.txt       |   1 +
 .../devicetree/bindings/mfd/atmel-smc.txt          |   1 +
 .../devicetree/bindings/mfd/atmel-tcb.txt          |   5 +-
 .../devicetree/bindings/mfd/atmel-usart.txt        |   6 +-
 .../devicetree/bindings/mtd/atmel-nand.txt         |   1 +
 .../devicetree/bindings/net/can/atmel-can.txt      |   3 +-
 .../bindings/rtc/atmel,at91rm9200-rtc.txt          |   3 +-
 .../devicetree/bindings/spi/spi_atmel.txt          |   2 +-
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts               | 647 +++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi                     | 691 +++++++++++++++++++++
 arch/arm/configs/at91_dt_defconfig                 |   4 +
 18 files changed, 1373 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 00/16] add device tree for SAM9X60 SoC and SAM9X60-EK board
@ 2020-01-08 12:55 ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

This series add device tree for SAM9X60 SoC and SAM9X60-EK board.
Allong with these, there are patches that documents some compatibles
for SAM9X60's IPs.

Claudiu Beznea (15):
  dt-bindings: at_xdmac: add entry for microchip compatibles
  dt-bindings: atmel-can: add microchip,sam9x60-can
  dt-bindings: atmel-tcb: add microchip,<chip>-tcb
  dt-bindings: atmel-isi: add microchip,sam9x60-isi
  dt-bindings: at91-sama5d2_adc: add microchip,sam9x60-adc
  dt-bindings: atmel-matrix: add microchip,sam9x60-matrix
  dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
  dt-bindings: atmel-sysreg: add microchip,sam9x60-ddramc
  dt-bindings: atmel-smc: add microchip,sam9x60-smc
  dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr
  dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
  dt-bindings: spi_atmel: add microchip,sam9x60-spi
  dt-bindings: atmel-usart: add microchip,<chip>-usart
  dt-bindings: arm: add sam9x60-ek board
  ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B

Sandeep Sheriker Mallikarjun (1):
  ARM: dts: at91: sam9x60: add device tree for soc and board

 .../devicetree/bindings/arm/atmel-at91.yaml        |   6 +
 .../devicetree/bindings/arm/atmel-sysregs.txt      |   1 +
 .../devicetree/bindings/dma/atmel-xdma.txt         |   3 +-
 .../bindings/iio/adc/at91-sama5d2_adc.txt          |   2 +-
 .../devicetree/bindings/media/atmel-isi.txt        |   2 +-
 .../devicetree/bindings/mfd/atmel-gpbr.txt         |   4 +-
 .../devicetree/bindings/mfd/atmel-matrix.txt       |   1 +
 .../devicetree/bindings/mfd/atmel-smc.txt          |   1 +
 .../devicetree/bindings/mfd/atmel-tcb.txt          |   5 +-
 .../devicetree/bindings/mfd/atmel-usart.txt        |   6 +-
 .../devicetree/bindings/mtd/atmel-nand.txt         |   1 +
 .../devicetree/bindings/net/can/atmel-can.txt      |   3 +-
 .../bindings/rtc/atmel,at91rm9200-rtc.txt          |   3 +-
 .../devicetree/bindings/spi/spi_atmel.txt          |   2 +-
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts               | 647 +++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi                     | 691 +++++++++++++++++++++
 arch/arm/configs/at91_dt_defconfig                 |   4 +
 18 files changed, 1373 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 00/16] add device tree for SAM9X60 SoC and SAM9X60-EK board
@ 2020-01-08 12:55 ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

This series add device tree for SAM9X60 SoC and SAM9X60-EK board.
Allong with these, there are patches that documents some compatibles
for SAM9X60's IPs.

Claudiu Beznea (15):
  dt-bindings: at_xdmac: add entry for microchip compatibles
  dt-bindings: atmel-can: add microchip,sam9x60-can
  dt-bindings: atmel-tcb: add microchip,<chip>-tcb
  dt-bindings: atmel-isi: add microchip,sam9x60-isi
  dt-bindings: at91-sama5d2_adc: add microchip,sam9x60-adc
  dt-bindings: atmel-matrix: add microchip,sam9x60-matrix
  dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
  dt-bindings: atmel-sysreg: add microchip,sam9x60-ddramc
  dt-bindings: atmel-smc: add microchip,sam9x60-smc
  dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr
  dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
  dt-bindings: spi_atmel: add microchip,sam9x60-spi
  dt-bindings: atmel-usart: add microchip,<chip>-usart
  dt-bindings: arm: add sam9x60-ek board
  ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B

Sandeep Sheriker Mallikarjun (1):
  ARM: dts: at91: sam9x60: add device tree for soc and board

 .../devicetree/bindings/arm/atmel-at91.yaml        |   6 +
 .../devicetree/bindings/arm/atmel-sysregs.txt      |   1 +
 .../devicetree/bindings/dma/atmel-xdma.txt         |   3 +-
 .../bindings/iio/adc/at91-sama5d2_adc.txt          |   2 +-
 .../devicetree/bindings/media/atmel-isi.txt        |   2 +-
 .../devicetree/bindings/mfd/atmel-gpbr.txt         |   4 +-
 .../devicetree/bindings/mfd/atmel-matrix.txt       |   1 +
 .../devicetree/bindings/mfd/atmel-smc.txt          |   1 +
 .../devicetree/bindings/mfd/atmel-tcb.txt          |   5 +-
 .../devicetree/bindings/mfd/atmel-usart.txt        |   6 +-
 .../devicetree/bindings/mtd/atmel-nand.txt         |   1 +
 .../devicetree/bindings/net/can/atmel-can.txt      |   3 +-
 .../bindings/rtc/atmel,at91rm9200-rtc.txt          |   3 +-
 .../devicetree/bindings/spi/spi_atmel.txt          |   2 +-
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts               | 647 +++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi                     | 691 +++++++++++++++++++++
 arch/arm/configs/at91_dt_defconfig                 |   4 +
 18 files changed, 1373 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 01/16] dt-bindings: at_xdmac: add entry for microchip compatibles
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add entry for microchip compatibles. This is for "microchip,sam9x60-dma"
DT binding.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/dma/atmel-xdma.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt
index 0eb2b3207e08..081a76c3db2f 100644
--- a/Documentation/devicetree/bindings/dma/atmel-xdma.txt
+++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt
@@ -2,9 +2,10 @@
 
 * XDMA Controller
 Required properties:
-- compatible: Should be "atmel,<chip>-dma".
+- compatible: Should be "atmel,<chip>-dma" or "microchip,<chip>-dma".
   <chip> compatible description:
   - sama5d4: first SoC adding the XDMAC
+  - sam9x60: Microchip SoC
 - reg: Should contain DMA registers location and length.
 - interrupts: Should contain DMA interrupt.
 - #dma-cells: Must be <1>, used to represent the number of integer cells in
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 01/16] dt-bindings: at_xdmac: add entry for microchip compatibles
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add entry for microchip compatibles. This is for "microchip,sam9x60-dma"
DT binding.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/dma/atmel-xdma.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt
index 0eb2b3207e08..081a76c3db2f 100644
--- a/Documentation/devicetree/bindings/dma/atmel-xdma.txt
+++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt
@@ -2,9 +2,10 @@
 
 * XDMA Controller
 Required properties:
-- compatible: Should be "atmel,<chip>-dma".
+- compatible: Should be "atmel,<chip>-dma" or "microchip,<chip>-dma".
   <chip> compatible description:
   - sama5d4: first SoC adding the XDMAC
+  - sam9x60: Microchip SoC
 - reg: Should contain DMA registers location and length.
 - interrupts: Should contain DMA interrupt.
 - #dma-cells: Must be <1>, used to represent the number of integer cells in
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 01/16] dt-bindings: at_xdmac: add entry for microchip compatibles
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add entry for microchip compatibles. This is for "microchip,sam9x60-dma"
DT binding.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/dma/atmel-xdma.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt
index 0eb2b3207e08..081a76c3db2f 100644
--- a/Documentation/devicetree/bindings/dma/atmel-xdma.txt
+++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt
@@ -2,9 +2,10 @@
 
 * XDMA Controller
 Required properties:
-- compatible: Should be "atmel,<chip>-dma".
+- compatible: Should be "atmel,<chip>-dma" or "microchip,<chip>-dma".
   <chip> compatible description:
   - sama5d4: first SoC adding the XDMAC
+  - sam9x60: Microchip SoC
 - reg: Should contain DMA registers location and length.
 - interrupts: Should contain DMA interrupt.
 - #dma-cells: Must be <1>, used to represent the number of integer cells in
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 01/16] dt-bindings: at_xdmac: add entry for microchip compatibles
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add entry for microchip compatibles. This is for "microchip,sam9x60-dma"
DT binding.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/dma/atmel-xdma.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt
index 0eb2b3207e08..081a76c3db2f 100644
--- a/Documentation/devicetree/bindings/dma/atmel-xdma.txt
+++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt
@@ -2,9 +2,10 @@
 
 * XDMA Controller
 Required properties:
-- compatible: Should be "atmel,<chip>-dma".
+- compatible: Should be "atmel,<chip>-dma" or "microchip,<chip>-dma".
   <chip> compatible description:
   - sama5d4: first SoC adding the XDMAC
+  - sam9x60: Microchip SoC
 - reg: Should contain DMA registers location and length.
 - interrupts: Should contain DMA interrupt.
 - #dma-cells: Must be <1>, used to represent the number of integer cells in
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 02/16] dt-bindings: atmel-can: add microchip,sam9x60-can
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-can to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/net/can/atmel-can.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/can/atmel-can.txt b/Documentation/devicetree/bindings/net/can/atmel-can.txt
index 14e52a0d86ec..218a3b3eb27e 100644
--- a/Documentation/devicetree/bindings/net/can/atmel-can.txt
+++ b/Documentation/devicetree/bindings/net/can/atmel-can.txt
@@ -1,7 +1,8 @@
 * AT91 CAN *
 
 Required properties:
-  - compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can"
+  - compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
+    "microchip,sam9x60-can"
   - reg: Should contain CAN controller registers location and length
   - interrupts: Should contain IRQ line for the CAN controller
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 02/16] dt-bindings: atmel-can: add microchip,sam9x60-can
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-can to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/net/can/atmel-can.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/can/atmel-can.txt b/Documentation/devicetree/bindings/net/can/atmel-can.txt
index 14e52a0d86ec..218a3b3eb27e 100644
--- a/Documentation/devicetree/bindings/net/can/atmel-can.txt
+++ b/Documentation/devicetree/bindings/net/can/atmel-can.txt
@@ -1,7 +1,8 @@
 * AT91 CAN *
 
 Required properties:
-  - compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can"
+  - compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
+    "microchip,sam9x60-can"
   - reg: Should contain CAN controller registers location and length
   - interrupts: Should contain IRQ line for the CAN controller
 
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 02/16] dt-bindings: atmel-can: add microchip,sam9x60-can
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-can to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/net/can/atmel-can.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/can/atmel-can.txt b/Documentation/devicetree/bindings/net/can/atmel-can.txt
index 14e52a0d86ec..218a3b3eb27e 100644
--- a/Documentation/devicetree/bindings/net/can/atmel-can.txt
+++ b/Documentation/devicetree/bindings/net/can/atmel-can.txt
@@ -1,7 +1,8 @@
 * AT91 CAN *
 
 Required properties:
-  - compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can"
+  - compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
+    "microchip,sam9x60-can"
   - reg: Should contain CAN controller registers location and length
   - interrupts: Should contain IRQ line for the CAN controller
 
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 02/16] dt-bindings: atmel-can: add microchip,sam9x60-can
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-can to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/net/can/atmel-can.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/can/atmel-can.txt b/Documentation/devicetree/bindings/net/can/atmel-can.txt
index 14e52a0d86ec..218a3b3eb27e 100644
--- a/Documentation/devicetree/bindings/net/can/atmel-can.txt
+++ b/Documentation/devicetree/bindings/net/can/atmel-can.txt
@@ -1,7 +1,8 @@
 * AT91 CAN *
 
 Required properties:
-  - compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can"
+  - compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
+    "microchip,sam9x60-can"
   - reg: Should contain CAN controller registers location and length
   - interrupts: Should contain IRQ line for the CAN controller
 
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,<chip>-tcb to DT bindings documentation. This is for
microchip,sam9x60-tcb.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
index c4a83e364cb6..e1713e41f6e0 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
@@ -1,6 +1,7 @@
 * Device tree bindings for Atmel Timer Counter Blocks
-- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
-  <chip> can be "at91rm9200" or "at91sam9x5"
+- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
+  "simple-mfd", "syscon".
+  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
 - reg: Should contain registers location and length
 - #address-cells: has to be 1
 - #size-cells: has to be 0
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,<chip>-tcb to DT bindings documentation. This is for
microchip,sam9x60-tcb.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
index c4a83e364cb6..e1713e41f6e0 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
@@ -1,6 +1,7 @@
 * Device tree bindings for Atmel Timer Counter Blocks
-- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
-  <chip> can be "at91rm9200" or "at91sam9x5"
+- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
+  "simple-mfd", "syscon".
+  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
 - reg: Should contain registers location and length
 - #address-cells: has to be 1
 - #size-cells: has to be 0
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,<chip>-tcb to DT bindings documentation. This is for
microchip,sam9x60-tcb.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
index c4a83e364cb6..e1713e41f6e0 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
@@ -1,6 +1,7 @@
 * Device tree bindings for Atmel Timer Counter Blocks
-- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
-  <chip> can be "at91rm9200" or "at91sam9x5"
+- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
+  "simple-mfd", "syscon".
+  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
 - reg: Should contain registers location and length
 - #address-cells: has to be 1
 - #size-cells: has to be 0
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,<chip>-tcb to DT bindings documentation. This is for
microchip,sam9x60-tcb.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
index c4a83e364cb6..e1713e41f6e0 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
@@ -1,6 +1,7 @@
 * Device tree bindings for Atmel Timer Counter Blocks
-- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
-  <chip> can be "at91rm9200" or "at91sam9x5"
+- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
+  "simple-mfd", "syscon".
+  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
 - reg: Should contain registers location and length
 - #address-cells: has to be 1
 - #size-cells: has to be 0
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 04/16] dt-bindings: atmel-isi: add microchip,sam9x60-isi
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-isi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/media/atmel-isi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/atmel-isi.txt b/Documentation/devicetree/bindings/media/atmel-isi.txt
index 332513a151cc..8924c7545b63 100644
--- a/Documentation/devicetree/bindings/media/atmel-isi.txt
+++ b/Documentation/devicetree/bindings/media/atmel-isi.txt
@@ -2,7 +2,7 @@ Atmel Image Sensor Interface (ISI)
 ----------------------------------
 
 Required properties for ISI:
-- compatible: must be "atmel,at91sam9g45-isi".
+- compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
 - reg: physical base address and length of the registers set for the device.
 - interrupts: should contain IRQ line for the ISI.
 - clocks: list of clock specifiers, corresponding to entries in the clock-names
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 04/16] dt-bindings: atmel-isi: add microchip,sam9x60-isi
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-isi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/media/atmel-isi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/atmel-isi.txt b/Documentation/devicetree/bindings/media/atmel-isi.txt
index 332513a151cc..8924c7545b63 100644
--- a/Documentation/devicetree/bindings/media/atmel-isi.txt
+++ b/Documentation/devicetree/bindings/media/atmel-isi.txt
@@ -2,7 +2,7 @@ Atmel Image Sensor Interface (ISI)
 ----------------------------------
 
 Required properties for ISI:
-- compatible: must be "atmel,at91sam9g45-isi".
+- compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
 - reg: physical base address and length of the registers set for the device.
 - interrupts: should contain IRQ line for the ISI.
 - clocks: list of clock specifiers, corresponding to entries in the clock-names
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 04/16] dt-bindings: atmel-isi: add microchip,sam9x60-isi
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-isi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/media/atmel-isi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/atmel-isi.txt b/Documentation/devicetree/bindings/media/atmel-isi.txt
index 332513a151cc..8924c7545b63 100644
--- a/Documentation/devicetree/bindings/media/atmel-isi.txt
+++ b/Documentation/devicetree/bindings/media/atmel-isi.txt
@@ -2,7 +2,7 @@ Atmel Image Sensor Interface (ISI)
 ----------------------------------
 
 Required properties for ISI:
-- compatible: must be "atmel,at91sam9g45-isi".
+- compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
 - reg: physical base address and length of the registers set for the device.
 - interrupts: should contain IRQ line for the ISI.
 - clocks: list of clock specifiers, corresponding to entries in the clock-names
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 04/16] dt-bindings: atmel-isi: add microchip,sam9x60-isi
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-isi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/media/atmel-isi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/atmel-isi.txt b/Documentation/devicetree/bindings/media/atmel-isi.txt
index 332513a151cc..8924c7545b63 100644
--- a/Documentation/devicetree/bindings/media/atmel-isi.txt
+++ b/Documentation/devicetree/bindings/media/atmel-isi.txt
@@ -2,7 +2,7 @@ Atmel Image Sensor Interface (ISI)
 ----------------------------------
 
 Required properties for ISI:
-- compatible: must be "atmel,at91sam9g45-isi".
+- compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
 - reg: physical base address and length of the registers set for the device.
 - interrupts: should contain IRQ line for the ISI.
 - clocks: list of clock specifiers, corresponding to entries in the clock-names
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 05/16] dt-bindings: at91-sama5d2_adc: add microchip,sam9x60-adc
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-adc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
index 4a3c1d496e1a..07c59f301b31 100644
--- a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
@@ -1,7 +1,7 @@
 * AT91 SAMA5D2 Analog to Digital Converter (ADC)
 
 Required properties:
-  - compatible: Should be "atmel,sama5d2-adc".
+  - compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
   - reg: Should contain ADC registers location and length.
   - interrupts: Should contain the IRQ line for the ADC.
   - clocks: phandle to device clock.
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 05/16] dt-bindings: at91-sama5d2_adc: add microchip,sam9x60-adc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-adc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
index 4a3c1d496e1a..07c59f301b31 100644
--- a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
@@ -1,7 +1,7 @@
 * AT91 SAMA5D2 Analog to Digital Converter (ADC)
 
 Required properties:
-  - compatible: Should be "atmel,sama5d2-adc".
+  - compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
   - reg: Should contain ADC registers location and length.
   - interrupts: Should contain the IRQ line for the ADC.
   - clocks: phandle to device clock.
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 05/16] dt-bindings: at91-sama5d2_adc: add microchip, sam9x60-adc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-adc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
index 4a3c1d496e1a..07c59f301b31 100644
--- a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
@@ -1,7 +1,7 @@
 * AT91 SAMA5D2 Analog to Digital Converter (ADC)
 
 Required properties:
-  - compatible: Should be "atmel,sama5d2-adc".
+  - compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
   - reg: Should contain ADC registers location and length.
   - interrupts: Should contain the IRQ line for the ADC.
   - clocks: phandle to device clock.
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 05/16] dt-bindings: at91-sama5d2_adc: add microchip, sam9x60-adc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-adc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
index 4a3c1d496e1a..07c59f301b31 100644
--- a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
@@ -1,7 +1,7 @@
 * AT91 SAMA5D2 Analog to Digital Converter (ADC)
 
 Required properties:
-  - compatible: Should be "atmel,sama5d2-adc".
+  - compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
   - reg: Should contain ADC registers location and length.
   - interrupts: Should contain the IRQ line for the ADC.
   - clocks: phandle to device clock.
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 06/16] dt-bindings: atmel-matrix: add microchip,sam9x60-matrix
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-matrix to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-matrix.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
index e3ef50ca02a5..89d05c64fb01 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
@@ -13,6 +13,7 @@ Required properties:
 			"atmel,at91sam9n12-matrix", "syscon"
 			"atmel,at91sam9x5-matrix", "syscon"
 			"atmel,sama5d3-matrix", "syscon"
+			"microchip,sam9x60-matrix", "syscon"
 - reg:			Contains offset/length value of the Bus Matrix
 			memory region.
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 06/16] dt-bindings: atmel-matrix: add microchip,sam9x60-matrix
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-matrix to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-matrix.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
index e3ef50ca02a5..89d05c64fb01 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
@@ -13,6 +13,7 @@ Required properties:
 			"atmel,at91sam9n12-matrix", "syscon"
 			"atmel,at91sam9x5-matrix", "syscon"
 			"atmel,sama5d3-matrix", "syscon"
+			"microchip,sam9x60-matrix", "syscon"
 - reg:			Contains offset/length value of the Bus Matrix
 			memory region.
 
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 06/16] dt-bindings: atmel-matrix: add microchip, sam9x60-matrix
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-matrix to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-matrix.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
index e3ef50ca02a5..89d05c64fb01 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
@@ -13,6 +13,7 @@ Required properties:
 			"atmel,at91sam9n12-matrix", "syscon"
 			"atmel,at91sam9x5-matrix", "syscon"
 			"atmel,sama5d3-matrix", "syscon"
+			"microchip,sam9x60-matrix", "syscon"
 - reg:			Contains offset/length value of the Bus Matrix
 			memory region.
 
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 06/16] dt-bindings: atmel-matrix: add microchip, sam9x60-matrix
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-matrix to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-matrix.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
index e3ef50ca02a5..89d05c64fb01 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
@@ -13,6 +13,7 @@ Required properties:
 			"atmel,at91sam9n12-matrix", "syscon"
 			"atmel,at91sam9x5-matrix", "syscon"
 			"atmel,sama5d3-matrix", "syscon"
+			"microchip,sam9x60-matrix", "syscon"
 - reg:			Contains offset/length value of the Bus Matrix
 			memory region.
 
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-pmecc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 68b51dc58816..3aa297c97ab6 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -57,6 +57,7 @@ Required properties:
 	"atmel,at91sam9g45-pmecc"
 	"atmel,sama5d4-pmecc"
 	"atmel,sama5d2-pmecc"
+	"microchip,sam9x60-pmecc"
 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
        block, and the second one to the PMECC_ERRLOC block.
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-pmecc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 68b51dc58816..3aa297c97ab6 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -57,6 +57,7 @@ Required properties:
 	"atmel,at91sam9g45-pmecc"
 	"atmel,sama5d4-pmecc"
 	"atmel,sama5d2-pmecc"
+	"microchip,sam9x60-pmecc"
 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
        block, and the second one to the PMECC_ERRLOC block.
 
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-pmecc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 68b51dc58816..3aa297c97ab6 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -57,6 +57,7 @@ Required properties:
 	"atmel,at91sam9g45-pmecc"
 	"atmel,sama5d4-pmecc"
 	"atmel,sama5d2-pmecc"
+	"microchip,sam9x60-pmecc"
 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
        block, and the second one to the PMECC_ERRLOC block.
 
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-pmecc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 68b51dc58816..3aa297c97ab6 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -57,6 +57,7 @@ Required properties:
 	"atmel,at91sam9g45-pmecc"
 	"atmel,sama5d4-pmecc"
 	"atmel,sama5d2-pmecc"
+	"microchip,sam9x60-pmecc"
 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
        block, and the second one to the PMECC_ERRLOC block.
 
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 08/16] dt-bindings: atmel-sysreg: add microchip,sam9x60-ddramc
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-ddramc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 9fbde401a090..b4900d3b4a7c 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -39,6 +39,7 @@ RAMC SDRAM/DDR Controller required properties:
 			"atmel,at91sam9260-sdramc",
 			"atmel,at91sam9g45-ddramc",
 			"atmel,sama5d3-ddramc",
+			"microchip,sam9x60-ddramc"
 - reg: Should contain registers location and length
 
 Examples:
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 08/16] dt-bindings: atmel-sysreg: add microchip,sam9x60-ddramc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-ddramc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 9fbde401a090..b4900d3b4a7c 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -39,6 +39,7 @@ RAMC SDRAM/DDR Controller required properties:
 			"atmel,at91sam9260-sdramc",
 			"atmel,at91sam9g45-ddramc",
 			"atmel,sama5d3-ddramc",
+			"microchip,sam9x60-ddramc"
 - reg: Should contain registers location and length
 
 Examples:
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 08/16] dt-bindings: atmel-sysreg: add microchip, sam9x60-ddramc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-ddramc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 9fbde401a090..b4900d3b4a7c 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -39,6 +39,7 @@ RAMC SDRAM/DDR Controller required properties:
 			"atmel,at91sam9260-sdramc",
 			"atmel,at91sam9g45-ddramc",
 			"atmel,sama5d3-ddramc",
+			"microchip,sam9x60-ddramc"
 - reg: Should contain registers location and length
 
 Examples:
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 08/16] dt-bindings: atmel-sysreg: add microchip, sam9x60-ddramc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-ddramc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 9fbde401a090..b4900d3b4a7c 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -39,6 +39,7 @@ RAMC SDRAM/DDR Controller required properties:
 			"atmel,at91sam9260-sdramc",
 			"atmel,at91sam9g45-ddramc",
 			"atmel,sama5d3-ddramc",
+			"microchip,sam9x60-ddramc"
 - reg: Should contain registers location and length
 
 Examples:
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 09/16] dt-bindings: atmel-smc: add microchip,sam9x60-smc
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-smc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-smc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
index 1103ce2030fb..5696d9fcb5dc 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-smc.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
@@ -9,6 +9,7 @@ Required properties:
 			"atmel,at91sam9260-smc", "syscon"
 			"atmel,sama5d3-smc", "syscon"
 			"atmel,sama5d2-smc", "syscon"
+			"microchip,sam9x60-smc", "syscon"
 - reg:			Contains offset/length value of the SMC memory
 			region.
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 09/16] dt-bindings: atmel-smc: add microchip,sam9x60-smc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-smc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-smc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
index 1103ce2030fb..5696d9fcb5dc 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-smc.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
@@ -9,6 +9,7 @@ Required properties:
 			"atmel,at91sam9260-smc", "syscon"
 			"atmel,sama5d3-smc", "syscon"
 			"atmel,sama5d2-smc", "syscon"
+			"microchip,sam9x60-smc", "syscon"
 - reg:			Contains offset/length value of the SMC memory
 			region.
 
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 09/16] dt-bindings: atmel-smc: add microchip,sam9x60-smc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-smc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-smc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
index 1103ce2030fb..5696d9fcb5dc 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-smc.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
@@ -9,6 +9,7 @@ Required properties:
 			"atmel,at91sam9260-smc", "syscon"
 			"atmel,sama5d3-smc", "syscon"
 			"atmel,sama5d2-smc", "syscon"
+			"microchip,sam9x60-smc", "syscon"
 - reg:			Contains offset/length value of the SMC memory
 			region.
 
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 09/16] dt-bindings: atmel-smc: add microchip,sam9x60-smc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-smc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-smc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
index 1103ce2030fb..5696d9fcb5dc 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-smc.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
@@ -9,6 +9,7 @@ Required properties:
 			"atmel,at91sam9260-smc", "syscon"
 			"atmel,sama5d3-smc", "syscon"
 			"atmel,sama5d2-smc", "syscon"
+			"microchip,sam9x60-smc", "syscon"
 - reg:			Contains offset/length value of the SMC memory
 			region.
 
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 10/16] dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-gpbr to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-gpbr.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
index a28569540683..e8c525569f10 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
@@ -3,7 +3,9 @@
 The GPBR are a set of battery-backed registers.
 
 Required properties:
-- compatible:		"atmel,at91sam9260-gpbr", "syscon"
+- compatible:		Should be one of the following:
+			"atmel,at91sam9260-gpbr", "syscon"
+			"microchip,sam9x60-gpbr", "syscon"
 - reg:			contains offset/length value of the GPBR memory
 			region.
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 10/16] dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-gpbr to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-gpbr.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
index a28569540683..e8c525569f10 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
@@ -3,7 +3,9 @@
 The GPBR are a set of battery-backed registers.
 
 Required properties:
-- compatible:		"atmel,at91sam9260-gpbr", "syscon"
+- compatible:		Should be one of the following:
+			"atmel,at91sam9260-gpbr", "syscon"
+			"microchip,sam9x60-gpbr", "syscon"
 - reg:			contains offset/length value of the GPBR memory
 			region.
 
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 10/16] dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-gpbr to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-gpbr.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
index a28569540683..e8c525569f10 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
@@ -3,7 +3,9 @@
 The GPBR are a set of battery-backed registers.
 
 Required properties:
-- compatible:		"atmel,at91sam9260-gpbr", "syscon"
+- compatible:		Should be one of the following:
+			"atmel,at91sam9260-gpbr", "syscon"
+			"microchip,sam9x60-gpbr", "syscon"
 - reg:			contains offset/length value of the GPBR memory
 			region.
 
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 10/16] dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-gpbr to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-gpbr.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
index a28569540683..e8c525569f10 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
@@ -3,7 +3,9 @@
 The GPBR are a set of battery-backed registers.
 
 Required properties:
-- compatible:		"atmel,at91sam9260-gpbr", "syscon"
+- compatible:		Should be one of the following:
+			"atmel,at91sam9260-gpbr", "syscon"
+			"microchip,sam9x60-gpbr", "syscon"
 - reg:			contains offset/length value of the GPBR memory
 			region.
 
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-rtc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
index 5d3791e789c6..35eab9138d0b 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -1,7 +1,8 @@
 Atmel AT91RM9200 Real Time Clock
 
 Required properties:
-- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
+- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
+  "microchip,sam9x60-rtc"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: rtc alarm/event interrupt
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-rtc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
index 5d3791e789c6..35eab9138d0b 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -1,7 +1,8 @@
 Atmel AT91RM9200 Real Time Clock
 
 Required properties:
-- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
+- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
+  "microchip,sam9x60-rtc"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: rtc alarm/event interrupt
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 11/16] dt-bindings: atmel, at91rm9200-rtc: add microchip, sam9x60-rtc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-rtc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
index 5d3791e789c6..35eab9138d0b 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -1,7 +1,8 @@
 Atmel AT91RM9200 Real Time Clock
 
 Required properties:
-- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
+- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
+  "microchip,sam9x60-rtc"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: rtc alarm/event interrupt
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 11/16] dt-bindings: atmel, at91rm9200-rtc: add microchip, sam9x60-rtc
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-rtc to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
index 5d3791e789c6..35eab9138d0b 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -1,7 +1,8 @@
 Atmel AT91RM9200 Real Time Clock
 
 Required properties:
-- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
+- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
+  "microchip,sam9x60-rtc"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: rtc alarm/event interrupt
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 12/16] dt-bindings: spi_atmel: add microchip,sam9x60-spi
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 12/16] dt-bindings: spi_atmel: add microchip,sam9x60-spi
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 12/16] dt-bindings: spi_atmel: add microchip,sam9x60-spi
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 12/16] dt-bindings: spi_atmel: add microchip,sam9x60-spi
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 13/16] dt-bindings: atmel-usart: add microchip,<chip>-usart
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,<chip>-usart to DT bindings documentation. This is for
microchip,sam9x60-usart.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-usart.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
index 699fd3c9ace8..e5c7331abe09 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
@@ -1,10 +1,12 @@
 * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
 
 Required properties for USART:
-- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
+- compatible: Should be "atmel,<chip>-usart", "microchip,<chip>-usart" or
+  "atmel,<chip>-dbgu".
   The compatible <chip> indicated will be the first SoC to support an
   additional mode or an USART new feature.
-  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
+  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart",
+  "microchip,<chip>-usart".
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt
 - clock-names: tuple listing input clock names.
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 13/16] dt-bindings: atmel-usart: add microchip,<chip>-usart
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add microchip,<chip>-usart to DT bindings documentation. This is for
microchip,sam9x60-usart.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-usart.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
index 699fd3c9ace8..e5c7331abe09 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
@@ -1,10 +1,12 @@
 * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
 
 Required properties for USART:
-- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
+- compatible: Should be "atmel,<chip>-usart", "microchip,<chip>-usart" or
+  "atmel,<chip>-dbgu".
   The compatible <chip> indicated will be the first SoC to support an
   additional mode or an USART new feature.
-  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
+  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart",
+  "microchip,<chip>-usart".
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt
 - clock-names: tuple listing input clock names.
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 13/16] dt-bindings: atmel-usart: add microchip,<chip>-usart
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,<chip>-usart to DT bindings documentation. This is for
microchip,sam9x60-usart.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-usart.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
index 699fd3c9ace8..e5c7331abe09 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
@@ -1,10 +1,12 @@
 * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
 
 Required properties for USART:
-- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
+- compatible: Should be "atmel,<chip>-usart", "microchip,<chip>-usart" or
+  "atmel,<chip>-dbgu".
   The compatible <chip> indicated will be the first SoC to support an
   additional mode or an USART new feature.
-  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
+  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart",
+  "microchip,<chip>-usart".
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt
 - clock-names: tuple listing input clock names.
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 13/16] dt-bindings: atmel-usart: add microchip,<chip>-usart
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add microchip,<chip>-usart to DT bindings documentation. This is for
microchip,sam9x60-usart.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/mfd/atmel-usart.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
index 699fd3c9ace8..e5c7331abe09 100644
--- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt
+++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
@@ -1,10 +1,12 @@
 * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
 
 Required properties for USART:
-- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
+- compatible: Should be "atmel,<chip>-usart", "microchip,<chip>-usart" or
+  "atmel,<chip>-dbgu".
   The compatible <chip> indicated will be the first SoC to support an
   additional mode or an USART new feature.
-  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
+  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart",
+  "microchip,<chip>-usart".
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt
 - clock-names: tuple listing input clock names.
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 14/16] dt-bindings: arm: add sam9x60-ek board
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add documentation for SAM9X60-EK board.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
index 6dd8be401673..bdf22891a768 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -57,6 +57,12 @@ properties:
           - const: atmel,sama5d2
           - const: atmel,sama5
 
+      - description: SAM9X60-EK board
+        items:
+          - const: microchip,sam9x60ek
+          - const: microchip,sam9x60
+          - const: atmel,at91sam9
+
       - description: Nattis v2 board with Natte v2 power board
         items:
           - const: axentia,nattis-2
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 14/16] dt-bindings: arm: add sam9x60-ek board
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Add documentation for SAM9X60-EK board.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
index 6dd8be401673..bdf22891a768 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -57,6 +57,12 @@ properties:
           - const: atmel,sama5d2
           - const: atmel,sama5
 
+      - description: SAM9X60-EK board
+        items:
+          - const: microchip,sam9x60ek
+          - const: microchip,sam9x60
+          - const: atmel,at91sam9
+
       - description: Nattis v2 board with Natte v2 power board
         items:
           - const: axentia,nattis-2
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 14/16] dt-bindings: arm: add sam9x60-ek board
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add documentation for SAM9X60-EK board.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
index 6dd8be401673..bdf22891a768 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -57,6 +57,12 @@ properties:
           - const: atmel,sama5d2
           - const: atmel,sama5
 
+      - description: SAM9X60-EK board
+        items:
+          - const: microchip,sam9x60ek
+          - const: microchip,sam9x60
+          - const: atmel,at91sam9
+
       - description: Nattis v2 board with Natte v2 power board
         items:
           - const: axentia,nattis-2
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 14/16] dt-bindings: arm: add sam9x60-ek board
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Add documentation for SAM9X60-EK board.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
index 6dd8be401673..bdf22891a768 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -57,6 +57,12 @@ properties:
           - const: atmel,sama5d2
           - const: atmel,sama5
 
+      - description: SAM9X60-EK board
+        items:
+          - const: microchip,sam9x60ek
+          - const: microchip,sam9x60
+          - const: atmel,at91sam9
+
       - description: Nattis v2 board with Natte v2 power board
         items:
           - const: axentia,nattis-2
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 15/16] ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B
  2020-01-08 12:55 ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B. These are necessary
for SAM9X60.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 5c5df8bc0074..f66bb98a5cce 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -160,6 +160,9 @@ CONFIG_USB_AT91=y
 CONFIG_USB_ATMEL_USBA=y
 CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_AT91=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
@@ -177,6 +180,7 @@ CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_AT_XDMAC=y
+CONFIG_MICROCHIP_PIT64B=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 15/16] ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Claudiu Beznea

Enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B. These are necessary
for SAM9X60.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 5c5df8bc0074..f66bb98a5cce 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -160,6 +160,9 @@ CONFIG_USB_AT91=y
 CONFIG_USB_ATMEL_USBA=y
 CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_AT91=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
@@ -177,6 +180,7 @@ CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_AT_XDMAC=y
+CONFIG_MICROCHIP_PIT64B=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 15/16] ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B. These are necessary
for SAM9X60.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 5c5df8bc0074..f66bb98a5cce 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -160,6 +160,9 @@ CONFIG_USB_AT91=y
 CONFIG_USB_ATMEL_USBA=y
 CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_AT91=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
@@ -177,6 +180,7 @@ CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_AT_XDMAC=y
+CONFIG_MICROCHIP_PIT64B=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-- 
2.7.4


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 15/16] ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

Enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B. These are necessary
for SAM9X60.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 5c5df8bc0074..f66bb98a5cce 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -160,6 +160,9 @@ CONFIG_USB_AT91=y
 CONFIG_USB_ATMEL_USBA=y
 CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_AT91=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
@@ -177,6 +180,7 @@ CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_AT_XDMAC=y
+CONFIG_MICROCHIP_PIT64B=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
  2020-01-08 12:55 ` Claudiu Beznea
                     ` (2 preceding siblings ...)
  (?)
@ 2020-01-08 12:55   ` Claudiu Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Sandeep Sheriker Mallikarjun, Claudiu Beznea, Codrin Ciubotariu

From: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>

Add device tree files for SAM9X60 SoC and SAM9X60-EK board.

Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
 arch/arm/boot/dts/Makefile           |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi       | 691 +++++++++++++++++++++++++++++++++++
 3 files changed, 1340 insertions(+)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 08011dc8c7a6..36e90f07be13 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 	at91sam9g35ek.dtb \
 	at91sam9x25ek.dtb \
 	at91sam9x35ek.dtb
+dtb-$(CONFIG_SOC_SAM9X60) += \
+	at91-sam9x60ek.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
 	at91-kizbox2-2.dtb \
 	at91-kizbox3-hs.dtb \
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
new file mode 100644
index 000000000000..9f30132d7d7b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+
+/ {
+	model = "Microchip SAM9X60-EK";
+	compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal {
+			clock-frequency = <24000000>;
+		};
+	};
+
+	regulators: regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_1v8: fixed-regulator-vdd_1v8@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd_1v5: fixed-regulator-vdd_1v5@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD1_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD2_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+		status = "okay";
+
+		sw1 {
+			label = "SW1";
+			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
+			linux,code=<0x104>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay"; /* Conflict with pwm0. */
+
+		red {
+			label = "red";
+			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		green {
+			label = "green";
+			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue {
+			label = "blue";
+			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&adc {
+	vddana-supply = <&vdd1_3v3>;
+	vref-supply = <&vdd1_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+	status = "okay";
+};
+
+&can0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can0_rx_tx>;
+	status = "disabled"; /* Conflict with dbgu. */
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_rx_tx>;
+	status = "okay";
+};
+
+&classd {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_classd_default>;
+	atmel,pwm-type = "diff";
+	atmel,non-overlap-time = <10>;
+	status = "okay";
+};
+
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+	status = "okay"; /* Conflict with can0. */
+};
+
+&ebi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+	status = "okay";
+
+	nand_controller: nand-controller {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+		status = "okay";
+
+		nand@3 {
+			reg = <0x3 0x0 0x800000>;
+			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+			nand-bus-width = <8>;
+			nand-ecc-mode = "hw";
+			nand-ecc-strength = <8>;
+			nand-ecc-step-size = <512>;
+			nand-on-flash-bbt;
+			label = "atmel_nand";
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				at91bootstrap@0 {
+					label = "at91bootstrap";
+					reg = <0x0 0x40000>;
+				};
+
+				uboot@40000 {
+					label = "u-boot";
+					reg = <0x40000 0xc0000>;
+				};
+
+				ubootenvred@100000 {
+					label = "U-Boot Env Redundant";
+					reg = <0x100000 0x40000>;
+				};
+
+				ubootenv@140000 {
+					label = "U-Boot Env";
+					reg = <0x140000 0x40000>;
+				};
+
+				dtb@180000 {
+					label = "device tree";
+					reg = <0x180000 0x80000>;
+				};
+
+				kernel@200000 {
+					label = "kernel";
+					reg = <0x200000 0x600000>;
+				};
+
+				rootfs@800000 {
+					label = "rootfs";
+					reg = <0x800000 0x1f800000>;
+				};
+			};
+		};
+	};
+};
+
+&flx0 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c0: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx0_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		eeprom@53 {
+			compatible = "atmel,24c32";
+			reg = <0x53>;
+			pagesize = <16>;
+			size = <128>;
+			status = "okay";
+		};
+	};
+};
+
+&flx4 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+	status = "disabled";
+
+	spi0: spi@400 {
+		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+		reg = <0x400 0x200>;
+		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+		clock-names = "spi_clk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx4_default>;
+		atmel,fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
+
+&flx5 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+	status = "okay";
+
+	uart1: serial@200 {
+		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+		reg = <0x200 0x200>;
+		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+		dmas = <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(10))>,
+		       <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(11))>;
+		dma-names = "tx", "rx";
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+		clock-names = "usart";
+		pinctrl-0 = <&pinctrl_flx5_default>;
+		pinctrl-names = "default";
+		atmel,use-dma-rx;
+		atmel,use-dma-tx;
+		status = "okay";
+	};
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c1: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx6_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		gpio_exp: mcp23008@20 {
+			compatible = "microchip,mcp23008";
+			reg = <0x20>;
+		};
+	};
+};
+
+&i2s {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2s_default>;
+	#sound-dai-cells = <0>;
+	status = "disabled"; /* Conflict with QSPI. */
+};
+
+&macb0 {
+	phy-mode = "rmii";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_macb0_rmii>;
+	status = "okay";
+
+	ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	atmel,mux-mask = <
+			 /*	A	B	C	*/
+			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
+			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
+			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
+			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
+			 >;
+
+	adc {
+		pinctrl_adc_default: adc_default {
+			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_adtrg_default: adtrg_default {
+			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				      AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	i2s {
+		pinctrl_i2s_default: i2s {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SCK */
+				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SWS */
+				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDIN */
+				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDOUT */
+				 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* I2SMCK */
+		};
+	};
+
+	qspi {
+		pinctrl_qspi: qspi {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	nand {
+		pinctrl_nand_oe_we: nand-oe-we-0 {
+			atmel,pins =
+				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_nand_rb: nand-rb-0 {
+			atmel,pins =
+				<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_nand_cs: nand-cs-0 {
+			atmel,pins =
+				<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	ebi {
+		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_ebi_addr_nand: ebi-addr-0 {
+			atmel,pins =
+				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx0_default: flx0_twi {
+			atmel,pins =
+				<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_flx4_default: flx4_spi {
+			atmel,pins =
+				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx5_default: flx_uart {
+			atmel,pins =
+				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
+				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx6_default: flx6_twi {
+			atmel,pins =
+				<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	classd {
+		pinctrl_classd_default: classd {
+			atmel,pins =
+				<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	can0 {
+		pinctrl_can0_rx_tx: can0_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0 */
+				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX0 */
+				 AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	can1 {
+		pinctrl_can1_rx_tx: can1_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1 RXD1 */
+				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX1 TXD1 */
+				 AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	macb0 {
+		pinctrl_macb0_rmii: macb0_rmii-0 {
+			atmel,pins =
+				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+				 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+		};
+	};
+
+	pwm0 {
+		pinctrl_pwm0_0: pwm0_0 {
+			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_1: pwm0_1 {
+			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_2: pwm0_2 {
+			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_3: pwm0_3 {
+			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+	};
+
+	sdmmc0 {
+		pinctrl_sdmmc0_default: sdmmc0 {
+			atmel,pins =
+				<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17 CK  periph A with pullup */
+				 AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD periph A with pullup */
+				 AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0 periph A */
+				 AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1 periph A with pullup */
+				 AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2 periph A with pullup */
+				 AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3 periph A with pullup */
+		};
+	};
+
+	gpio_keys {
+		pinctrl_key_gpio_default: pinctrl_key_gpio {
+			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+}; /* pinctrl */
+
+&pmc {
+	atmel,osc-bypass;
+};
+
+&pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
+	status = "disabled"; /* Conflict with leds. */
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc0_default>;
+	status = "okay";
+	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay"; /* Conflict with i2s. */
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		m25p,fast-read;
+
+		at91bootstrap@0 {
+			label = "qspi: at91bootstrap";
+			reg = <0x0 0x40000>;
+		};
+
+		bootloader@40000 {
+			label = "qspi: bootloader";
+			reg = <0x40000 0xc0000>;
+		};
+
+		bootloaderenvred@100000 {
+			label = "qspi: bootloader env redundant";
+			reg = <0x100000 0x40000>;
+		};
+
+		bootloaderenv@140000 {
+			label = "qspi: bootloader env";
+			reg = <0x140000 0x40000>;
+		};
+
+		dtb@180000 {
+			label = "qspi: device tree";
+			reg = <0x180000 0x80000>;
+		};
+
+		kernel@200000 {
+			label = "qspi: kernel";
+			reg = <0x200000 0x600000>;
+		};
+	};
+};
+
+&shutdown_controller {
+	atmel,shdwc-debouncer = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
+&tcb0 {
+	timer0: timer@0 {
+		compatible = "atmel,tcb-timer";
+		reg = <0>;
+	};
+
+	timer1: timer@1 {
+		compatible = "atmel,tcb-timer";
+		reg = <1>;
+	};
+};
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 16 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
new file mode 100644
index 000000000000..2eb92a90453b
--- /dev/null
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Microchip SAM9X60 SoC";
+	compatible = "microchip,sam9x60";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+		tcb0 = &tcb0;
+		tcb1 = &tcb1;
+	};
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x20000000 0x10000000>;
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	sram: sram@300000 {
+		compatible = "mmio-sram";
+		reg = <0x00300000 0x100000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		usb1: ohci@600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00600000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb2: ehci@700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00700000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+			clock-names = "usb_clk", "ehci_clk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
+		ebi: ebi@10000000 {
+			compatible = "microchip,sam9x60-ebi";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			atmel,smc = <&smc>;
+			microchip,sfr = <&sfr>;
+			reg = <0x10000000 0x60000000>;
+			ranges = <0x0 0x0 0x10000000 0x10000000
+				  0x1 0x0 0x20000000 0x10000000
+				  0x2 0x0 0x30000000 0x10000000
+				  0x3 0x0 0x40000000 0x10000000
+				  0x4 0x0 0x50000000 0x10000000
+				  0x5 0x0 0x60000000 0x10000000>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			status = "disabled";
+
+			nand_controller: nand-controller {
+				compatible = "microchip,sam9x60-nand-controller";
+				ecc-engine = <&pmecc>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				ranges;
+				status = "disabled";
+			};
+		};
+
+		sdmmc0: sdio-host@80000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x80000000 0x300>;
+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		sdmmc1: sdio-host@90000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x90000000 0x300>;
+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			flx4: flexcom@f0000000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0000000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0000000 0x800>;
+				status = "disabled";
+			};
+
+			flx5: flexcom@f0004000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0004000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0004000 0x800>;
+				status = "disabled";
+			};
+
+			dma0: dma-controller@f0008000 {
+				compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
+				reg = <0xf0008000 0x1000>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+				#dma-cells = <1>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+				clock-names = "dma_clk";
+			};
+
+			ssc: ssc@f0010000 {
+				compatible = "atmel,at91sam9g45-ssc";
+				reg = <0xf0010000 0x4000>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(38))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(39))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			qspi: spi@f0014000 {
+				compatible = "microchip,sam9x60-qspi";
+				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
+				reg-names = "qspi_base", "qspi_mmap";
+				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(26))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(27))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
+				clock-names = "pclk", "qspick";
+				atmel,pmc = <&pmc>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2s: i2s@f001c000 {
+				compatible = "microchip,sam9x60-i2smcc";
+				reg = <0xf001c000 0x100>;
+				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(36))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(37))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			flx11: flexcom@f0020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0020000 0x800>;
+				status = "disabled";
+			};
+
+			flx12: flexcom@f0024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0024000 0x800>;
+				status = "disabled";
+			};
+
+			pit64b: timer@f0028000 {
+				compatible = "microchip,sam9x60-pit64b";
+				reg = <0xf0028000 0x100>;
+				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+				clock-names = "pclk", "gclk";
+			};
+
+			sha: sha@f002c000 {
+				compatible = "atmel,at91sam9g46-sha";
+				reg = <0xf002c000 0x100>;
+				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(34))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+				clock-names = "sha_clk";
+				status = "okay";
+			};
+
+			trng: trng@f0030000 {
+				compatible = "microchip,sam9x60-trng";
+				reg = <0xf0030000 0x100>;
+				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+				status = "okay";
+			};
+
+			aes: aes@f0034000 {
+				compatible = "atmel,at91sam9g46-aes";
+				reg = <0xf0034000 0x100>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(32))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(33))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+				clock-names = "aes_clk";
+				status = "okay";
+			};
+
+			tdes: tdes@f0038000 {
+				compatible = "atmel,at91sam9g46-tdes";
+				reg = <0xf0038000 0x100>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(31))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(30))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+				clock-names = "tdes_clk";
+				status = "okay";
+			};
+
+			classd: classd@f003c000 {
+				compatible = "atmel,sama5d2-classd";
+				reg = <0xf003c000 0x100>;
+				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(35))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			can0: can@f8000000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8000000 0x300>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			can1: can@f8004000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8004000 0x300>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			tcb0: timer@f8008000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf8008000 0x100>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			tcb1: timer@f800c000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf800c000 0x100>;
+				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			flx6: flexcom@f8010000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8010000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8010000 0x800>;
+				status = "disabled";
+			};
+
+			flx7: flexcom@f8014000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8014000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8014000 0x800>;
+				status = "disabled";
+			};
+
+			flx8: flexcom@f8018000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8018000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8018000 0x800>;
+				status = "disabled";
+			};
+
+			flx0: flexcom@f801c000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf801c000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf801c000 0x800>;
+				status = "disabled";
+			};
+
+			flx1: flexcom@f8020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8020000 0x800>;
+				status = "disabled";
+			};
+
+			flx2: flexcom@f8024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8024000 0x800>;
+				status = "disabled";
+			};
+
+			flx3: flexcom@f8028000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8028000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8028000 0x800>;
+				status = "disabled";
+			};
+
+			macb0: ethernet@f802c000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf802c000 0x1000>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			macb1: ethernet@f8030000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf8030000 0x1000>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			pwm0: pwm@f8034000 {
+				compatible = "microchip,sam9x60-pwm";
+				reg = <0xf8034000 0x300>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+				#pwm-cells = <3>;
+				status="disabled";
+			};
+
+			hlcdc: hlcdc@f8038000 {
+				compatible = "microchip,sam9x60-hlcdc";
+				reg = <0xf8038000 0x4000>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
+				clock-names = "periph_clk","sys_clk", "slow_clk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
+				status = "disabled";
+
+				hlcdc-display-controller {
+					compatible = "atmel,hlcdc-display-controller";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						reg = <0>;
+					};
+				};
+
+				hlcdc_pwm: hlcdc-pwm {
+					compatible = "atmel,hlcdc-pwm";
+					#pwm-cells = <3>;
+				};
+			};
+
+			flx9: flexcom@f8040000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8040000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8040000 0x800>;
+				status = "disabled";
+			};
+
+			flx10: flexcom@f8044000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8044000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8044000 0x800>;
+				status = "disabled";
+			};
+
+			isi: isi@f8048000 {
+				compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
+				reg = <0xf8048000 0x100>;
+				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+				clock-names = "isi_clk";
+				status = "disabled";
+				port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			adc: adc@f804c000 {
+				compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
+				reg = <0xf804c000 0x100>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+				clock-names = "adc_clk";
+				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
+				dma-names = "rx";
+				atmel,min-sample-rate-hz = <200000>;
+				atmel,max-sample-rate-hz = <20000000>;
+				atmel,startup-time-ms = <4>;
+				atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+				#io-channel-cells = <1>;
+				status = "disabled";
+			};
+
+			sfr: sfr@f8050000 {
+				compatible = "microchip,sam9x60-sfr", "syscon";
+				reg = <0xf8050000 0x100>;
+			};
+
+			matrix: matrix@ffffde00 {
+				compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
+				reg = <0xffffde00 0x200>;
+			};
+
+			pmecc: ecc-engine@ffffe000 {
+				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+				reg = <0xffffe000 0x300>,
+				      <0xffffe600 0x100>;
+			};
+
+			mpddrc: mpddrc@ffffe800 {
+				compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
+				reg = <0xffffe800 0x200>;
+				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+				clock-names = "ddrck", "mpddr";
+			};
+
+			smc: smc@ffffea00 {
+				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+				reg = <0xffffea00 0x100>;
+			};
+
+			aic: interrupt-controller@fffff100 {
+				compatible = "microchip,sam9x60-aic";
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				reg = <0xfffff100 0x100>;
+				atmel,external-irqs = <31>;
+			};
+
+			dbgu: serial@fffff200 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xfffff200 0x200>;
+				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(28))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(29))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			pinctrl: pinctrl@fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff400 0xfffff400 0x800>;
+
+				pioA: gpio@fffff400 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <26>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+				};
+
+				pioD: gpio@fffffa00 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <22>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+				};
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "microchip,sam9x60-pmc", "syscon";
+				reg = <0xfffffc00 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				#clock-cells = <2>;
+				clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+				clock-names = "td_slck", "md_slck", "main_xtal";
+			};
+
+			reset_controller: rstc@fffffe00 {
+				compatible = "microchip,sam9x60-rstc";
+				reg = <0xfffffe00 0x10>;
+				clocks = <&clk32k 0>;
+			};
+
+			shutdown_controller: shdwc@fffffe10 {
+				compatible = "microchip,sam9x60-shdwc";
+				reg = <0xfffffe10 0x10>;
+				clocks = <&clk32k 0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				atmel,wakeup-rtc-timer;
+				atmel,wakeup-rtt-timer;
+				status = "disabled";
+			};
+
+			pit: timer@fffffe40 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffe40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			};
+
+			clk32k: sckc@fffffe50 {
+				compatible = "microchip,sam9x60-sckc";
+				reg = <0xfffffe50 0x4>;
+				clocks = <&slow_xtal>;
+				#clock-cells = <1>;
+			};
+
+			gpbr: syscon@fffffe60 {
+				compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffe60 0x10>;
+			};
+
+			rtc: rtc@fffffea8 {
+				compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
+				reg = <0xfffffea8 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k 0>;
+			};
+		};
+	};
+};
-- 
2.7.4


^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Sandeep Sheriker Mallikarjun, Claudiu Beznea, Codrin Ciubotariu

From: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>

Add device tree files for SAM9X60 SoC and SAM9X60-EK board.

Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
 arch/arm/boot/dts/Makefile           |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi       | 691 +++++++++++++++++++++++++++++++++++
 3 files changed, 1340 insertions(+)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 08011dc8c7a6..36e90f07be13 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 	at91sam9g35ek.dtb \
 	at91sam9x25ek.dtb \
 	at91sam9x35ek.dtb
+dtb-$(CONFIG_SOC_SAM9X60) += \
+	at91-sam9x60ek.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
 	at91-kizbox2-2.dtb \
 	at91-kizbox3-hs.dtb \
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
new file mode 100644
index 000000000000..9f30132d7d7b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+
+/ {
+	model = "Microchip SAM9X60-EK";
+	compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal {
+			clock-frequency = <24000000>;
+		};
+	};
+
+	regulators: regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_1v8: fixed-regulator-vdd_1v8@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd_1v5: fixed-regulator-vdd_1v5@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD1_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD2_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+		status = "okay";
+
+		sw1 {
+			label = "SW1";
+			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
+			linux,code=<0x104>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay"; /* Conflict with pwm0. */
+
+		red {
+			label = "red";
+			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		green {
+			label = "green";
+			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue {
+			label = "blue";
+			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&adc {
+	vddana-supply = <&vdd1_3v3>;
+	vref-supply = <&vdd1_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+	status = "okay";
+};
+
+&can0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can0_rx_tx>;
+	status = "disabled"; /* Conflict with dbgu. */
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_rx_tx>;
+	status = "okay";
+};
+
+&classd {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_classd_default>;
+	atmel,pwm-type = "diff";
+	atmel,non-overlap-time = <10>;
+	status = "okay";
+};
+
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+	status = "okay"; /* Conflict with can0. */
+};
+
+&ebi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+	status = "okay";
+
+	nand_controller: nand-controller {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+		status = "okay";
+
+		nand@3 {
+			reg = <0x3 0x0 0x800000>;
+			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+			nand-bus-width = <8>;
+			nand-ecc-mode = "hw";
+			nand-ecc-strength = <8>;
+			nand-ecc-step-size = <512>;
+			nand-on-flash-bbt;
+			label = "atmel_nand";
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				at91bootstrap@0 {
+					label = "at91bootstrap";
+					reg = <0x0 0x40000>;
+				};
+
+				uboot@40000 {
+					label = "u-boot";
+					reg = <0x40000 0xc0000>;
+				};
+
+				ubootenvred@100000 {
+					label = "U-Boot Env Redundant";
+					reg = <0x100000 0x40000>;
+				};
+
+				ubootenv@140000 {
+					label = "U-Boot Env";
+					reg = <0x140000 0x40000>;
+				};
+
+				dtb@180000 {
+					label = "device tree";
+					reg = <0x180000 0x80000>;
+				};
+
+				kernel@200000 {
+					label = "kernel";
+					reg = <0x200000 0x600000>;
+				};
+
+				rootfs@800000 {
+					label = "rootfs";
+					reg = <0x800000 0x1f800000>;
+				};
+			};
+		};
+	};
+};
+
+&flx0 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c0: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx0_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		eeprom@53 {
+			compatible = "atmel,24c32";
+			reg = <0x53>;
+			pagesize = <16>;
+			size = <128>;
+			status = "okay";
+		};
+	};
+};
+
+&flx4 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+	status = "disabled";
+
+	spi0: spi@400 {
+		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+		reg = <0x400 0x200>;
+		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+		clock-names = "spi_clk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx4_default>;
+		atmel,fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
+
+&flx5 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+	status = "okay";
+
+	uart1: serial@200 {
+		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+		reg = <0x200 0x200>;
+		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+		dmas = <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(10))>,
+		       <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(11))>;
+		dma-names = "tx", "rx";
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+		clock-names = "usart";
+		pinctrl-0 = <&pinctrl_flx5_default>;
+		pinctrl-names = "default";
+		atmel,use-dma-rx;
+		atmel,use-dma-tx;
+		status = "okay";
+	};
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c1: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx6_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		gpio_exp: mcp23008@20 {
+			compatible = "microchip,mcp23008";
+			reg = <0x20>;
+		};
+	};
+};
+
+&i2s {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2s_default>;
+	#sound-dai-cells = <0>;
+	status = "disabled"; /* Conflict with QSPI. */
+};
+
+&macb0 {
+	phy-mode = "rmii";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_macb0_rmii>;
+	status = "okay";
+
+	ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	atmel,mux-mask = <
+			 /*	A	B	C	*/
+			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
+			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
+			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
+			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
+			 >;
+
+	adc {
+		pinctrl_adc_default: adc_default {
+			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_adtrg_default: adtrg_default {
+			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				      AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	i2s {
+		pinctrl_i2s_default: i2s {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SCK */
+				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SWS */
+				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDIN */
+				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDOUT */
+				 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* I2SMCK */
+		};
+	};
+
+	qspi {
+		pinctrl_qspi: qspi {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	nand {
+		pinctrl_nand_oe_we: nand-oe-we-0 {
+			atmel,pins =
+				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_nand_rb: nand-rb-0 {
+			atmel,pins =
+				<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_nand_cs: nand-cs-0 {
+			atmel,pins =
+				<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	ebi {
+		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_ebi_addr_nand: ebi-addr-0 {
+			atmel,pins =
+				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx0_default: flx0_twi {
+			atmel,pins =
+				<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_flx4_default: flx4_spi {
+			atmel,pins =
+				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx5_default: flx_uart {
+			atmel,pins =
+				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
+				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx6_default: flx6_twi {
+			atmel,pins =
+				<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	classd {
+		pinctrl_classd_default: classd {
+			atmel,pins =
+				<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	can0 {
+		pinctrl_can0_rx_tx: can0_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0 */
+				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX0 */
+				 AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	can1 {
+		pinctrl_can1_rx_tx: can1_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1 RXD1 */
+				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX1 TXD1 */
+				 AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	macb0 {
+		pinctrl_macb0_rmii: macb0_rmii-0 {
+			atmel,pins =
+				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+				 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+		};
+	};
+
+	pwm0 {
+		pinctrl_pwm0_0: pwm0_0 {
+			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_1: pwm0_1 {
+			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_2: pwm0_2 {
+			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_3: pwm0_3 {
+			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+	};
+
+	sdmmc0 {
+		pinctrl_sdmmc0_default: sdmmc0 {
+			atmel,pins =
+				<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17 CK  periph A with pullup */
+				 AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD periph A with pullup */
+				 AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0 periph A */
+				 AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1 periph A with pullup */
+				 AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2 periph A with pullup */
+				 AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3 periph A with pullup */
+		};
+	};
+
+	gpio_keys {
+		pinctrl_key_gpio_default: pinctrl_key_gpio {
+			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+}; /* pinctrl */
+
+&pmc {
+	atmel,osc-bypass;
+};
+
+&pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
+	status = "disabled"; /* Conflict with leds. */
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc0_default>;
+	status = "okay";
+	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay"; /* Conflict with i2s. */
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		m25p,fast-read;
+
+		at91bootstrap@0 {
+			label = "qspi: at91bootstrap";
+			reg = <0x0 0x40000>;
+		};
+
+		bootloader@40000 {
+			label = "qspi: bootloader";
+			reg = <0x40000 0xc0000>;
+		};
+
+		bootloaderenvred@100000 {
+			label = "qspi: bootloader env redundant";
+			reg = <0x100000 0x40000>;
+		};
+
+		bootloaderenv@140000 {
+			label = "qspi: bootloader env";
+			reg = <0x140000 0x40000>;
+		};
+
+		dtb@180000 {
+			label = "qspi: device tree";
+			reg = <0x180000 0x80000>;
+		};
+
+		kernel@200000 {
+			label = "qspi: kernel";
+			reg = <0x200000 0x600000>;
+		};
+	};
+};
+
+&shutdown_controller {
+	atmel,shdwc-debouncer = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
+&tcb0 {
+	timer0: timer@0 {
+		compatible = "atmel,tcb-timer";
+		reg = <0>;
+	};
+
+	timer1: timer@1 {
+		compatible = "atmel,tcb-timer";
+		reg = <1>;
+	};
+};
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 16 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
new file mode 100644
index 000000000000..2eb92a90453b
--- /dev/null
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Microchip SAM9X60 SoC";
+	compatible = "microchip,sam9x60";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+		tcb0 = &tcb0;
+		tcb1 = &tcb1;
+	};
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x20000000 0x10000000>;
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	sram: sram@300000 {
+		compatible = "mmio-sram";
+		reg = <0x00300000 0x100000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		usb1: ohci@600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00600000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb2: ehci@700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00700000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+			clock-names = "usb_clk", "ehci_clk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
+		ebi: ebi@10000000 {
+			compatible = "microchip,sam9x60-ebi";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			atmel,smc = <&smc>;
+			microchip,sfr = <&sfr>;
+			reg = <0x10000000 0x60000000>;
+			ranges = <0x0 0x0 0x10000000 0x10000000
+				  0x1 0x0 0x20000000 0x10000000
+				  0x2 0x0 0x30000000 0x10000000
+				  0x3 0x0 0x40000000 0x10000000
+				  0x4 0x0 0x50000000 0x10000000
+				  0x5 0x0 0x60000000 0x10000000>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			status = "disabled";
+
+			nand_controller: nand-controller {
+				compatible = "microchip,sam9x60-nand-controller";
+				ecc-engine = <&pmecc>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				ranges;
+				status = "disabled";
+			};
+		};
+
+		sdmmc0: sdio-host@80000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x80000000 0x300>;
+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		sdmmc1: sdio-host@90000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x90000000 0x300>;
+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			flx4: flexcom@f0000000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0000000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0000000 0x800>;
+				status = "disabled";
+			};
+
+			flx5: flexcom@f0004000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0004000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0004000 0x800>;
+				status = "disabled";
+			};
+
+			dma0: dma-controller@f0008000 {
+				compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
+				reg = <0xf0008000 0x1000>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+				#dma-cells = <1>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+				clock-names = "dma_clk";
+			};
+
+			ssc: ssc@f0010000 {
+				compatible = "atmel,at91sam9g45-ssc";
+				reg = <0xf0010000 0x4000>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(38))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(39))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			qspi: spi@f0014000 {
+				compatible = "microchip,sam9x60-qspi";
+				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
+				reg-names = "qspi_base", "qspi_mmap";
+				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(26))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(27))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
+				clock-names = "pclk", "qspick";
+				atmel,pmc = <&pmc>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2s: i2s@f001c000 {
+				compatible = "microchip,sam9x60-i2smcc";
+				reg = <0xf001c000 0x100>;
+				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(36))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(37))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			flx11: flexcom@f0020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0020000 0x800>;
+				status = "disabled";
+			};
+
+			flx12: flexcom@f0024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0024000 0x800>;
+				status = "disabled";
+			};
+
+			pit64b: timer@f0028000 {
+				compatible = "microchip,sam9x60-pit64b";
+				reg = <0xf0028000 0x100>;
+				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+				clock-names = "pclk", "gclk";
+			};
+
+			sha: sha@f002c000 {
+				compatible = "atmel,at91sam9g46-sha";
+				reg = <0xf002c000 0x100>;
+				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(34))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+				clock-names = "sha_clk";
+				status = "okay";
+			};
+
+			trng: trng@f0030000 {
+				compatible = "microchip,sam9x60-trng";
+				reg = <0xf0030000 0x100>;
+				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+				status = "okay";
+			};
+
+			aes: aes@f0034000 {
+				compatible = "atmel,at91sam9g46-aes";
+				reg = <0xf0034000 0x100>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(32))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(33))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+				clock-names = "aes_clk";
+				status = "okay";
+			};
+
+			tdes: tdes@f0038000 {
+				compatible = "atmel,at91sam9g46-tdes";
+				reg = <0xf0038000 0x100>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(31))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(30))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+				clock-names = "tdes_clk";
+				status = "okay";
+			};
+
+			classd: classd@f003c000 {
+				compatible = "atmel,sama5d2-classd";
+				reg = <0xf003c000 0x100>;
+				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(35))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			can0: can@f8000000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8000000 0x300>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			can1: can@f8004000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8004000 0x300>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			tcb0: timer@f8008000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf8008000 0x100>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			tcb1: timer@f800c000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf800c000 0x100>;
+				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			flx6: flexcom@f8010000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8010000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8010000 0x800>;
+				status = "disabled";
+			};
+
+			flx7: flexcom@f8014000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8014000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8014000 0x800>;
+				status = "disabled";
+			};
+
+			flx8: flexcom@f8018000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8018000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8018000 0x800>;
+				status = "disabled";
+			};
+
+			flx0: flexcom@f801c000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf801c000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf801c000 0x800>;
+				status = "disabled";
+			};
+
+			flx1: flexcom@f8020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8020000 0x800>;
+				status = "disabled";
+			};
+
+			flx2: flexcom@f8024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8024000 0x800>;
+				status = "disabled";
+			};
+
+			flx3: flexcom@f8028000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8028000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8028000 0x800>;
+				status = "disabled";
+			};
+
+			macb0: ethernet@f802c000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf802c000 0x1000>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			macb1: ethernet@f8030000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf8030000 0x1000>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			pwm0: pwm@f8034000 {
+				compatible = "microchip,sam9x60-pwm";
+				reg = <0xf8034000 0x300>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+				#pwm-cells = <3>;
+				status="disabled";
+			};
+
+			hlcdc: hlcdc@f8038000 {
+				compatible = "microchip,sam9x60-hlcdc";
+				reg = <0xf8038000 0x4000>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
+				clock-names = "periph_clk","sys_clk", "slow_clk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
+				status = "disabled";
+
+				hlcdc-display-controller {
+					compatible = "atmel,hlcdc-display-controller";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						reg = <0>;
+					};
+				};
+
+				hlcdc_pwm: hlcdc-pwm {
+					compatible = "atmel,hlcdc-pwm";
+					#pwm-cells = <3>;
+				};
+			};
+
+			flx9: flexcom@f8040000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8040000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8040000 0x800>;
+				status = "disabled";
+			};
+
+			flx10: flexcom@f8044000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8044000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8044000 0x800>;
+				status = "disabled";
+			};
+
+			isi: isi@f8048000 {
+				compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
+				reg = <0xf8048000 0x100>;
+				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+				clock-names = "isi_clk";
+				status = "disabled";
+				port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			adc: adc@f804c000 {
+				compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
+				reg = <0xf804c000 0x100>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+				clock-names = "adc_clk";
+				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
+				dma-names = "rx";
+				atmel,min-sample-rate-hz = <200000>;
+				atmel,max-sample-rate-hz = <20000000>;
+				atmel,startup-time-ms = <4>;
+				atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+				#io-channel-cells = <1>;
+				status = "disabled";
+			};
+
+			sfr: sfr@f8050000 {
+				compatible = "microchip,sam9x60-sfr", "syscon";
+				reg = <0xf8050000 0x100>;
+			};
+
+			matrix: matrix@ffffde00 {
+				compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
+				reg = <0xffffde00 0x200>;
+			};
+
+			pmecc: ecc-engine@ffffe000 {
+				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+				reg = <0xffffe000 0x300>,
+				      <0xffffe600 0x100>;
+			};
+
+			mpddrc: mpddrc@ffffe800 {
+				compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
+				reg = <0xffffe800 0x200>;
+				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+				clock-names = "ddrck", "mpddr";
+			};
+
+			smc: smc@ffffea00 {
+				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+				reg = <0xffffea00 0x100>;
+			};
+
+			aic: interrupt-controller@fffff100 {
+				compatible = "microchip,sam9x60-aic";
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				reg = <0xfffff100 0x100>;
+				atmel,external-irqs = <31>;
+			};
+
+			dbgu: serial@fffff200 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xfffff200 0x200>;
+				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(28))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(29))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			pinctrl: pinctrl@fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff400 0xfffff400 0x800>;
+
+				pioA: gpio@fffff400 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <26>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+				};
+
+				pioD: gpio@fffffa00 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <22>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+				};
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "microchip,sam9x60-pmc", "syscon";
+				reg = <0xfffffc00 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				#clock-cells = <2>;
+				clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+				clock-names = "td_slck", "md_slck", "main_xtal";
+			};
+
+			reset_controller: rstc@fffffe00 {
+				compatible = "microchip,sam9x60-rstc";
+				reg = <0xfffffe00 0x10>;
+				clocks = <&clk32k 0>;
+			};
+
+			shutdown_controller: shdwc@fffffe10 {
+				compatible = "microchip,sam9x60-shdwc";
+				reg = <0xfffffe10 0x10>;
+				clocks = <&clk32k 0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				atmel,wakeup-rtc-timer;
+				atmel,wakeup-rtt-timer;
+				status = "disabled";
+			};
+
+			pit: timer@fffffe40 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffe40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			};
+
+			clk32k: sckc@fffffe50 {
+				compatible = "microchip,sam9x60-sckc";
+				reg = <0xfffffe50 0x4>;
+				clocks = <&slow_xtal>;
+				#clock-cells = <1>;
+			};
+
+			gpbr: syscon@fffffe60 {
+				compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffe60 0x10>;
+			};
+
+			rtc: rtc@fffffea8 {
+				compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
+				reg = <0xfffffea8 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k 0>;
+			};
+		};
+	};
+};
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc,
	Sandeep Sheriker Mallikarjun, Claudiu Beznea, Codrin Ciubotariu

From: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>

Add device tree files for SAM9X60 SoC and SAM9X60-EK board.

Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
 arch/arm/boot/dts/Makefile           |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi       | 691 +++++++++++++++++++++++++++++++++++
 3 files changed, 1340 insertions(+)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 08011dc8c7a6..36e90f07be13 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 	at91sam9g35ek.dtb \
 	at91sam9x25ek.dtb \
 	at91sam9x35ek.dtb
+dtb-$(CONFIG_SOC_SAM9X60) += \
+	at91-sam9x60ek.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
 	at91-kizbox2-2.dtb \
 	at91-kizbox3-hs.dtb \
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
new file mode 100644
index 000000000000..9f30132d7d7b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+
+/ {
+	model = "Microchip SAM9X60-EK";
+	compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal {
+			clock-frequency = <24000000>;
+		};
+	};
+
+	regulators: regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_1v8: fixed-regulator-vdd_1v8@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd_1v5: fixed-regulator-vdd_1v5@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD1_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD2_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+		status = "okay";
+
+		sw1 {
+			label = "SW1";
+			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
+			linux,code=<0x104>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay"; /* Conflict with pwm0. */
+
+		red {
+			label = "red";
+			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		green {
+			label = "green";
+			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue {
+			label = "blue";
+			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&adc {
+	vddana-supply = <&vdd1_3v3>;
+	vref-supply = <&vdd1_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+	status = "okay";
+};
+
+&can0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can0_rx_tx>;
+	status = "disabled"; /* Conflict with dbgu. */
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_rx_tx>;
+	status = "okay";
+};
+
+&classd {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_classd_default>;
+	atmel,pwm-type = "diff";
+	atmel,non-overlap-time = <10>;
+	status = "okay";
+};
+
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+	status = "okay"; /* Conflict with can0. */
+};
+
+&ebi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+	status = "okay";
+
+	nand_controller: nand-controller {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+		status = "okay";
+
+		nand@3 {
+			reg = <0x3 0x0 0x800000>;
+			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+			nand-bus-width = <8>;
+			nand-ecc-mode = "hw";
+			nand-ecc-strength = <8>;
+			nand-ecc-step-size = <512>;
+			nand-on-flash-bbt;
+			label = "atmel_nand";
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				at91bootstrap@0 {
+					label = "at91bootstrap";
+					reg = <0x0 0x40000>;
+				};
+
+				uboot@40000 {
+					label = "u-boot";
+					reg = <0x40000 0xc0000>;
+				};
+
+				ubootenvred@100000 {
+					label = "U-Boot Env Redundant";
+					reg = <0x100000 0x40000>;
+				};
+
+				ubootenv@140000 {
+					label = "U-Boot Env";
+					reg = <0x140000 0x40000>;
+				};
+
+				dtb@180000 {
+					label = "device tree";
+					reg = <0x180000 0x80000>;
+				};
+
+				kernel@200000 {
+					label = "kernel";
+					reg = <0x200000 0x600000>;
+				};
+
+				rootfs@800000 {
+					label = "rootfs";
+					reg = <0x800000 0x1f800000>;
+				};
+			};
+		};
+	};
+};
+
+&flx0 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c0: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx0_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		eeprom@53 {
+			compatible = "atmel,24c32";
+			reg = <0x53>;
+			pagesize = <16>;
+			size = <128>;
+			status = "okay";
+		};
+	};
+};
+
+&flx4 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+	status = "disabled";
+
+	spi0: spi@400 {
+		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+		reg = <0x400 0x200>;
+		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+		clock-names = "spi_clk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx4_default>;
+		atmel,fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
+
+&flx5 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+	status = "okay";
+
+	uart1: serial@200 {
+		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+		reg = <0x200 0x200>;
+		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+		dmas = <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(10))>,
+		       <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(11))>;
+		dma-names = "tx", "rx";
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+		clock-names = "usart";
+		pinctrl-0 = <&pinctrl_flx5_default>;
+		pinctrl-names = "default";
+		atmel,use-dma-rx;
+		atmel,use-dma-tx;
+		status = "okay";
+	};
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c1: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx6_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		gpio_exp: mcp23008@20 {
+			compatible = "microchip,mcp23008";
+			reg = <0x20>;
+		};
+	};
+};
+
+&i2s {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2s_default>;
+	#sound-dai-cells = <0>;
+	status = "disabled"; /* Conflict with QSPI. */
+};
+
+&macb0 {
+	phy-mode = "rmii";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_macb0_rmii>;
+	status = "okay";
+
+	ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	atmel,mux-mask = <
+			 /*	A	B	C	*/
+			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
+			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
+			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
+			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
+			 >;
+
+	adc {
+		pinctrl_adc_default: adc_default {
+			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_adtrg_default: adtrg_default {
+			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				      AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	i2s {
+		pinctrl_i2s_default: i2s {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SCK */
+				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SWS */
+				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDIN */
+				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDOUT */
+				 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* I2SMCK */
+		};
+	};
+
+	qspi {
+		pinctrl_qspi: qspi {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	nand {
+		pinctrl_nand_oe_we: nand-oe-we-0 {
+			atmel,pins =
+				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_nand_rb: nand-rb-0 {
+			atmel,pins =
+				<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_nand_cs: nand-cs-0 {
+			atmel,pins =
+				<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	ebi {
+		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_ebi_addr_nand: ebi-addr-0 {
+			atmel,pins =
+				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx0_default: flx0_twi {
+			atmel,pins =
+				<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_flx4_default: flx4_spi {
+			atmel,pins =
+				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx5_default: flx_uart {
+			atmel,pins =
+				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
+				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx6_default: flx6_twi {
+			atmel,pins =
+				<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	classd {
+		pinctrl_classd_default: classd {
+			atmel,pins =
+				<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	can0 {
+		pinctrl_can0_rx_tx: can0_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0 */
+				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX0 */
+				 AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	can1 {
+		pinctrl_can1_rx_tx: can1_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1 RXD1 */
+				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX1 TXD1 */
+				 AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	macb0 {
+		pinctrl_macb0_rmii: macb0_rmii-0 {
+			atmel,pins =
+				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+				 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+		};
+	};
+
+	pwm0 {
+		pinctrl_pwm0_0: pwm0_0 {
+			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_1: pwm0_1 {
+			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_2: pwm0_2 {
+			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_3: pwm0_3 {
+			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+	};
+
+	sdmmc0 {
+		pinctrl_sdmmc0_default: sdmmc0 {
+			atmel,pins =
+				<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17 CK  periph A with pullup */
+				 AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD periph A with pullup */
+				 AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0 periph A */
+				 AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1 periph A with pullup */
+				 AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2 periph A with pullup */
+				 AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3 periph A with pullup */
+		};
+	};
+
+	gpio_keys {
+		pinctrl_key_gpio_default: pinctrl_key_gpio {
+			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+}; /* pinctrl */
+
+&pmc {
+	atmel,osc-bypass;
+};
+
+&pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
+	status = "disabled"; /* Conflict with leds. */
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc0_default>;
+	status = "okay";
+	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay"; /* Conflict with i2s. */
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		m25p,fast-read;
+
+		at91bootstrap@0 {
+			label = "qspi: at91bootstrap";
+			reg = <0x0 0x40000>;
+		};
+
+		bootloader@40000 {
+			label = "qspi: bootloader";
+			reg = <0x40000 0xc0000>;
+		};
+
+		bootloaderenvred@100000 {
+			label = "qspi: bootloader env redundant";
+			reg = <0x100000 0x40000>;
+		};
+
+		bootloaderenv@140000 {
+			label = "qspi: bootloader env";
+			reg = <0x140000 0x40000>;
+		};
+
+		dtb@180000 {
+			label = "qspi: device tree";
+			reg = <0x180000 0x80000>;
+		};
+
+		kernel@200000 {
+			label = "qspi: kernel";
+			reg = <0x200000 0x600000>;
+		};
+	};
+};
+
+&shutdown_controller {
+	atmel,shdwc-debouncer = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
+&tcb0 {
+	timer0: timer@0 {
+		compatible = "atmel,tcb-timer";
+		reg = <0>;
+	};
+
+	timer1: timer@1 {
+		compatible = "atmel,tcb-timer";
+		reg = <1>;
+	};
+};
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 16 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
new file mode 100644
index 000000000000..2eb92a90453b
--- /dev/null
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Microchip SAM9X60 SoC";
+	compatible = "microchip,sam9x60";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+		tcb0 = &tcb0;
+		tcb1 = &tcb1;
+	};
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x20000000 0x10000000>;
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	sram: sram@300000 {
+		compatible = "mmio-sram";
+		reg = <0x00300000 0x100000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		usb1: ohci@600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00600000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb2: ehci@700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00700000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+			clock-names = "usb_clk", "ehci_clk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
+		ebi: ebi@10000000 {
+			compatible = "microchip,sam9x60-ebi";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			atmel,smc = <&smc>;
+			microchip,sfr = <&sfr>;
+			reg = <0x10000000 0x60000000>;
+			ranges = <0x0 0x0 0x10000000 0x10000000
+				  0x1 0x0 0x20000000 0x10000000
+				  0x2 0x0 0x30000000 0x10000000
+				  0x3 0x0 0x40000000 0x10000000
+				  0x4 0x0 0x50000000 0x10000000
+				  0x5 0x0 0x60000000 0x10000000>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			status = "disabled";
+
+			nand_controller: nand-controller {
+				compatible = "microchip,sam9x60-nand-controller";
+				ecc-engine = <&pmecc>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				ranges;
+				status = "disabled";
+			};
+		};
+
+		sdmmc0: sdio-host@80000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x80000000 0x300>;
+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		sdmmc1: sdio-host@90000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x90000000 0x300>;
+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			flx4: flexcom@f0000000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0000000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0000000 0x800>;
+				status = "disabled";
+			};
+
+			flx5: flexcom@f0004000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0004000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0004000 0x800>;
+				status = "disabled";
+			};
+
+			dma0: dma-controller@f0008000 {
+				compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
+				reg = <0xf0008000 0x1000>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+				#dma-cells = <1>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+				clock-names = "dma_clk";
+			};
+
+			ssc: ssc@f0010000 {
+				compatible = "atmel,at91sam9g45-ssc";
+				reg = <0xf0010000 0x4000>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(38))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(39))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			qspi: spi@f0014000 {
+				compatible = "microchip,sam9x60-qspi";
+				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
+				reg-names = "qspi_base", "qspi_mmap";
+				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(26))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(27))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
+				clock-names = "pclk", "qspick";
+				atmel,pmc = <&pmc>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2s: i2s@f001c000 {
+				compatible = "microchip,sam9x60-i2smcc";
+				reg = <0xf001c000 0x100>;
+				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(36))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(37))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			flx11: flexcom@f0020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0020000 0x800>;
+				status = "disabled";
+			};
+
+			flx12: flexcom@f0024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0024000 0x800>;
+				status = "disabled";
+			};
+
+			pit64b: timer@f0028000 {
+				compatible = "microchip,sam9x60-pit64b";
+				reg = <0xf0028000 0x100>;
+				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+				clock-names = "pclk", "gclk";
+			};
+
+			sha: sha@f002c000 {
+				compatible = "atmel,at91sam9g46-sha";
+				reg = <0xf002c000 0x100>;
+				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(34))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+				clock-names = "sha_clk";
+				status = "okay";
+			};
+
+			trng: trng@f0030000 {
+				compatible = "microchip,sam9x60-trng";
+				reg = <0xf0030000 0x100>;
+				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+				status = "okay";
+			};
+
+			aes: aes@f0034000 {
+				compatible = "atmel,at91sam9g46-aes";
+				reg = <0xf0034000 0x100>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(32))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(33))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+				clock-names = "aes_clk";
+				status = "okay";
+			};
+
+			tdes: tdes@f0038000 {
+				compatible = "atmel,at91sam9g46-tdes";
+				reg = <0xf0038000 0x100>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(31))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(30))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+				clock-names = "tdes_clk";
+				status = "okay";
+			};
+
+			classd: classd@f003c000 {
+				compatible = "atmel,sama5d2-classd";
+				reg = <0xf003c000 0x100>;
+				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(35))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			can0: can@f8000000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8000000 0x300>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			can1: can@f8004000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8004000 0x300>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			tcb0: timer@f8008000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf8008000 0x100>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			tcb1: timer@f800c000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf800c000 0x100>;
+				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			flx6: flexcom@f8010000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8010000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8010000 0x800>;
+				status = "disabled";
+			};
+
+			flx7: flexcom@f8014000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8014000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8014000 0x800>;
+				status = "disabled";
+			};
+
+			flx8: flexcom@f8018000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8018000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8018000 0x800>;
+				status = "disabled";
+			};
+
+			flx0: flexcom@f801c000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf801c000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf801c000 0x800>;
+				status = "disabled";
+			};
+
+			flx1: flexcom@f8020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8020000 0x800>;
+				status = "disabled";
+			};
+
+			flx2: flexcom@f8024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8024000 0x800>;
+				status = "disabled";
+			};
+
+			flx3: flexcom@f8028000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8028000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8028000 0x800>;
+				status = "disabled";
+			};
+
+			macb0: ethernet@f802c000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf802c000 0x1000>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			macb1: ethernet@f8030000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf8030000 0x1000>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			pwm0: pwm@f8034000 {
+				compatible = "microchip,sam9x60-pwm";
+				reg = <0xf8034000 0x300>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+				#pwm-cells = <3>;
+				status="disabled";
+			};
+
+			hlcdc: hlcdc@f8038000 {
+				compatible = "microchip,sam9x60-hlcdc";
+				reg = <0xf8038000 0x4000>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
+				clock-names = "periph_clk","sys_clk", "slow_clk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
+				status = "disabled";
+
+				hlcdc-display-controller {
+					compatible = "atmel,hlcdc-display-controller";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						reg = <0>;
+					};
+				};
+
+				hlcdc_pwm: hlcdc-pwm {
+					compatible = "atmel,hlcdc-pwm";
+					#pwm-cells = <3>;
+				};
+			};
+
+			flx9: flexcom@f8040000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8040000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8040000 0x800>;
+				status = "disabled";
+			};
+
+			flx10: flexcom@f8044000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8044000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8044000 0x800>;
+				status = "disabled";
+			};
+
+			isi: isi@f8048000 {
+				compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
+				reg = <0xf8048000 0x100>;
+				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+				clock-names = "isi_clk";
+				status = "disabled";
+				port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			adc: adc@f804c000 {
+				compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
+				reg = <0xf804c000 0x100>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+				clock-names = "adc_clk";
+				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
+				dma-names = "rx";
+				atmel,min-sample-rate-hz = <200000>;
+				atmel,max-sample-rate-hz = <20000000>;
+				atmel,startup-time-ms = <4>;
+				atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+				#io-channel-cells = <1>;
+				status = "disabled";
+			};
+
+			sfr: sfr@f8050000 {
+				compatible = "microchip,sam9x60-sfr", "syscon";
+				reg = <0xf8050000 0x100>;
+			};
+
+			matrix: matrix@ffffde00 {
+				compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
+				reg = <0xffffde00 0x200>;
+			};
+
+			pmecc: ecc-engine@ffffe000 {
+				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+				reg = <0xffffe000 0x300>,
+				      <0xffffe600 0x100>;
+			};
+
+			mpddrc: mpddrc@ffffe800 {
+				compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
+				reg = <0xffffe800 0x200>;
+				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+				clock-names = "ddrck", "mpddr";
+			};
+
+			smc: smc@ffffea00 {
+				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+				reg = <0xffffea00 0x100>;
+			};
+
+			aic: interrupt-controller@fffff100 {
+				compatible = "microchip,sam9x60-aic";
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				reg = <0xfffff100 0x100>;
+				atmel,external-irqs = <31>;
+			};
+
+			dbgu: serial@fffff200 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xfffff200 0x200>;
+				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(28))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(29))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			pinctrl: pinctrl@fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff400 0xfffff400 0x800>;
+
+				pioA: gpio@fffff400 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <26>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+				};
+
+				pioD: gpio@fffffa00 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <22>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+				};
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "microchip,sam9x60-pmc", "syscon";
+				reg = <0xfffffc00 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				#clock-cells = <2>;
+				clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+				clock-names = "td_slck", "md_slck", "main_xtal";
+			};
+
+			reset_controller: rstc@fffffe00 {
+				compatible = "microchip,sam9x60-rstc";
+				reg = <0xfffffe00 0x10>;
+				clocks = <&clk32k 0>;
+			};
+
+			shutdown_controller: shdwc@fffffe10 {
+				compatible = "microchip,sam9x60-shdwc";
+				reg = <0xfffffe10 0x10>;
+				clocks = <&clk32k 0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				atmel,wakeup-rtc-timer;
+				atmel,wakeup-rtt-timer;
+				status = "disabled";
+			};
+
+			pit: timer@fffffe40 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffe40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			};
+
+			clk32k: sckc@fffffe50 {
+				compatible = "microchip,sam9x60-sckc";
+				reg = <0xfffffe50 0x4>;
+				clocks = <&slow_xtal>;
+				#clock-cells = <1>;
+			};
+
+			gpbr: syscon@fffffe60 {
+				compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffe60 0x10>;
+			};
+
+			rtc: rtc@fffffea8 {
+				compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
+				reg = <0xfffffea8 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k 0>;
+			};
+		};
+	};
+};
-- 
2.7.4

^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev,
	Sandeep Sheriker Mallikarjun, linux-kernel, linux-spi, linux-mtd,
	dmaengine, Codrin Ciubotariu, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

From: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>

Add device tree files for SAM9X60 SoC and SAM9X60-EK board.

Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
 arch/arm/boot/dts/Makefile           |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi       | 691 +++++++++++++++++++++++++++++++++++
 3 files changed, 1340 insertions(+)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 08011dc8c7a6..36e90f07be13 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 	at91sam9g35ek.dtb \
 	at91sam9x25ek.dtb \
 	at91sam9x35ek.dtb
+dtb-$(CONFIG_SOC_SAM9X60) += \
+	at91-sam9x60ek.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
 	at91-kizbox2-2.dtb \
 	at91-kizbox3-hs.dtb \
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
new file mode 100644
index 000000000000..9f30132d7d7b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+
+/ {
+	model = "Microchip SAM9X60-EK";
+	compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal {
+			clock-frequency = <24000000>;
+		};
+	};
+
+	regulators: regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_1v8: fixed-regulator-vdd_1v8@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd_1v5: fixed-regulator-vdd_1v5@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD1_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD2_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+		status = "okay";
+
+		sw1 {
+			label = "SW1";
+			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
+			linux,code=<0x104>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay"; /* Conflict with pwm0. */
+
+		red {
+			label = "red";
+			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		green {
+			label = "green";
+			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue {
+			label = "blue";
+			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&adc {
+	vddana-supply = <&vdd1_3v3>;
+	vref-supply = <&vdd1_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+	status = "okay";
+};
+
+&can0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can0_rx_tx>;
+	status = "disabled"; /* Conflict with dbgu. */
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_rx_tx>;
+	status = "okay";
+};
+
+&classd {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_classd_default>;
+	atmel,pwm-type = "diff";
+	atmel,non-overlap-time = <10>;
+	status = "okay";
+};
+
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+	status = "okay"; /* Conflict with can0. */
+};
+
+&ebi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+	status = "okay";
+
+	nand_controller: nand-controller {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+		status = "okay";
+
+		nand@3 {
+			reg = <0x3 0x0 0x800000>;
+			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+			nand-bus-width = <8>;
+			nand-ecc-mode = "hw";
+			nand-ecc-strength = <8>;
+			nand-ecc-step-size = <512>;
+			nand-on-flash-bbt;
+			label = "atmel_nand";
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				at91bootstrap@0 {
+					label = "at91bootstrap";
+					reg = <0x0 0x40000>;
+				};
+
+				uboot@40000 {
+					label = "u-boot";
+					reg = <0x40000 0xc0000>;
+				};
+
+				ubootenvred@100000 {
+					label = "U-Boot Env Redundant";
+					reg = <0x100000 0x40000>;
+				};
+
+				ubootenv@140000 {
+					label = "U-Boot Env";
+					reg = <0x140000 0x40000>;
+				};
+
+				dtb@180000 {
+					label = "device tree";
+					reg = <0x180000 0x80000>;
+				};
+
+				kernel@200000 {
+					label = "kernel";
+					reg = <0x200000 0x600000>;
+				};
+
+				rootfs@800000 {
+					label = "rootfs";
+					reg = <0x800000 0x1f800000>;
+				};
+			};
+		};
+	};
+};
+
+&flx0 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c0: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx0_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		eeprom@53 {
+			compatible = "atmel,24c32";
+			reg = <0x53>;
+			pagesize = <16>;
+			size = <128>;
+			status = "okay";
+		};
+	};
+};
+
+&flx4 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+	status = "disabled";
+
+	spi0: spi@400 {
+		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+		reg = <0x400 0x200>;
+		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+		clock-names = "spi_clk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx4_default>;
+		atmel,fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
+
+&flx5 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+	status = "okay";
+
+	uart1: serial@200 {
+		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+		reg = <0x200 0x200>;
+		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+		dmas = <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(10))>,
+		       <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(11))>;
+		dma-names = "tx", "rx";
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+		clock-names = "usart";
+		pinctrl-0 = <&pinctrl_flx5_default>;
+		pinctrl-names = "default";
+		atmel,use-dma-rx;
+		atmel,use-dma-tx;
+		status = "okay";
+	};
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c1: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx6_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		gpio_exp: mcp23008@20 {
+			compatible = "microchip,mcp23008";
+			reg = <0x20>;
+		};
+	};
+};
+
+&i2s {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2s_default>;
+	#sound-dai-cells = <0>;
+	status = "disabled"; /* Conflict with QSPI. */
+};
+
+&macb0 {
+	phy-mode = "rmii";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_macb0_rmii>;
+	status = "okay";
+
+	ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	atmel,mux-mask = <
+			 /*	A	B	C	*/
+			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
+			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
+			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
+			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
+			 >;
+
+	adc {
+		pinctrl_adc_default: adc_default {
+			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_adtrg_default: adtrg_default {
+			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				      AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	i2s {
+		pinctrl_i2s_default: i2s {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SCK */
+				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SWS */
+				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDIN */
+				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDOUT */
+				 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* I2SMCK */
+		};
+	};
+
+	qspi {
+		pinctrl_qspi: qspi {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	nand {
+		pinctrl_nand_oe_we: nand-oe-we-0 {
+			atmel,pins =
+				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_nand_rb: nand-rb-0 {
+			atmel,pins =
+				<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_nand_cs: nand-cs-0 {
+			atmel,pins =
+				<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	ebi {
+		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_ebi_addr_nand: ebi-addr-0 {
+			atmel,pins =
+				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx0_default: flx0_twi {
+			atmel,pins =
+				<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_flx4_default: flx4_spi {
+			atmel,pins =
+				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx5_default: flx_uart {
+			atmel,pins =
+				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
+				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx6_default: flx6_twi {
+			atmel,pins =
+				<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	classd {
+		pinctrl_classd_default: classd {
+			atmel,pins =
+				<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	can0 {
+		pinctrl_can0_rx_tx: can0_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0 */
+				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX0 */
+				 AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	can1 {
+		pinctrl_can1_rx_tx: can1_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1 RXD1 */
+				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX1 TXD1 */
+				 AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	macb0 {
+		pinctrl_macb0_rmii: macb0_rmii-0 {
+			atmel,pins =
+				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+				 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+		};
+	};
+
+	pwm0 {
+		pinctrl_pwm0_0: pwm0_0 {
+			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_1: pwm0_1 {
+			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_2: pwm0_2 {
+			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_3: pwm0_3 {
+			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+	};
+
+	sdmmc0 {
+		pinctrl_sdmmc0_default: sdmmc0 {
+			atmel,pins =
+				<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17 CK  periph A with pullup */
+				 AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD periph A with pullup */
+				 AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0 periph A */
+				 AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1 periph A with pullup */
+				 AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2 periph A with pullup */
+				 AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3 periph A with pullup */
+		};
+	};
+
+	gpio_keys {
+		pinctrl_key_gpio_default: pinctrl_key_gpio {
+			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+}; /* pinctrl */
+
+&pmc {
+	atmel,osc-bypass;
+};
+
+&pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
+	status = "disabled"; /* Conflict with leds. */
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc0_default>;
+	status = "okay";
+	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay"; /* Conflict with i2s. */
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		m25p,fast-read;
+
+		at91bootstrap@0 {
+			label = "qspi: at91bootstrap";
+			reg = <0x0 0x40000>;
+		};
+
+		bootloader@40000 {
+			label = "qspi: bootloader";
+			reg = <0x40000 0xc0000>;
+		};
+
+		bootloaderenvred@100000 {
+			label = "qspi: bootloader env redundant";
+			reg = <0x100000 0x40000>;
+		};
+
+		bootloaderenv@140000 {
+			label = "qspi: bootloader env";
+			reg = <0x140000 0x40000>;
+		};
+
+		dtb@180000 {
+			label = "qspi: device tree";
+			reg = <0x180000 0x80000>;
+		};
+
+		kernel@200000 {
+			label = "qspi: kernel";
+			reg = <0x200000 0x600000>;
+		};
+	};
+};
+
+&shutdown_controller {
+	atmel,shdwc-debouncer = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
+&tcb0 {
+	timer0: timer@0 {
+		compatible = "atmel,tcb-timer";
+		reg = <0>;
+	};
+
+	timer1: timer@1 {
+		compatible = "atmel,tcb-timer";
+		reg = <1>;
+	};
+};
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 16 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
new file mode 100644
index 000000000000..2eb92a90453b
--- /dev/null
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Microchip SAM9X60 SoC";
+	compatible = "microchip,sam9x60";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+		tcb0 = &tcb0;
+		tcb1 = &tcb1;
+	};
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x20000000 0x10000000>;
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	sram: sram@300000 {
+		compatible = "mmio-sram";
+		reg = <0x00300000 0x100000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		usb1: ohci@600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00600000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb2: ehci@700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00700000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+			clock-names = "usb_clk", "ehci_clk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
+		ebi: ebi@10000000 {
+			compatible = "microchip,sam9x60-ebi";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			atmel,smc = <&smc>;
+			microchip,sfr = <&sfr>;
+			reg = <0x10000000 0x60000000>;
+			ranges = <0x0 0x0 0x10000000 0x10000000
+				  0x1 0x0 0x20000000 0x10000000
+				  0x2 0x0 0x30000000 0x10000000
+				  0x3 0x0 0x40000000 0x10000000
+				  0x4 0x0 0x50000000 0x10000000
+				  0x5 0x0 0x60000000 0x10000000>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			status = "disabled";
+
+			nand_controller: nand-controller {
+				compatible = "microchip,sam9x60-nand-controller";
+				ecc-engine = <&pmecc>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				ranges;
+				status = "disabled";
+			};
+		};
+
+		sdmmc0: sdio-host@80000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x80000000 0x300>;
+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		sdmmc1: sdio-host@90000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x90000000 0x300>;
+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			flx4: flexcom@f0000000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0000000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0000000 0x800>;
+				status = "disabled";
+			};
+
+			flx5: flexcom@f0004000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0004000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0004000 0x800>;
+				status = "disabled";
+			};
+
+			dma0: dma-controller@f0008000 {
+				compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
+				reg = <0xf0008000 0x1000>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+				#dma-cells = <1>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+				clock-names = "dma_clk";
+			};
+
+			ssc: ssc@f0010000 {
+				compatible = "atmel,at91sam9g45-ssc";
+				reg = <0xf0010000 0x4000>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(38))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(39))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			qspi: spi@f0014000 {
+				compatible = "microchip,sam9x60-qspi";
+				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
+				reg-names = "qspi_base", "qspi_mmap";
+				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(26))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(27))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
+				clock-names = "pclk", "qspick";
+				atmel,pmc = <&pmc>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2s: i2s@f001c000 {
+				compatible = "microchip,sam9x60-i2smcc";
+				reg = <0xf001c000 0x100>;
+				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(36))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(37))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			flx11: flexcom@f0020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0020000 0x800>;
+				status = "disabled";
+			};
+
+			flx12: flexcom@f0024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0024000 0x800>;
+				status = "disabled";
+			};
+
+			pit64b: timer@f0028000 {
+				compatible = "microchip,sam9x60-pit64b";
+				reg = <0xf0028000 0x100>;
+				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+				clock-names = "pclk", "gclk";
+			};
+
+			sha: sha@f002c000 {
+				compatible = "atmel,at91sam9g46-sha";
+				reg = <0xf002c000 0x100>;
+				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(34))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+				clock-names = "sha_clk";
+				status = "okay";
+			};
+
+			trng: trng@f0030000 {
+				compatible = "microchip,sam9x60-trng";
+				reg = <0xf0030000 0x100>;
+				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+				status = "okay";
+			};
+
+			aes: aes@f0034000 {
+				compatible = "atmel,at91sam9g46-aes";
+				reg = <0xf0034000 0x100>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(32))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(33))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+				clock-names = "aes_clk";
+				status = "okay";
+			};
+
+			tdes: tdes@f0038000 {
+				compatible = "atmel,at91sam9g46-tdes";
+				reg = <0xf0038000 0x100>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(31))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(30))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+				clock-names = "tdes_clk";
+				status = "okay";
+			};
+
+			classd: classd@f003c000 {
+				compatible = "atmel,sama5d2-classd";
+				reg = <0xf003c000 0x100>;
+				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(35))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			can0: can@f8000000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8000000 0x300>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			can1: can@f8004000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8004000 0x300>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			tcb0: timer@f8008000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf8008000 0x100>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			tcb1: timer@f800c000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf800c000 0x100>;
+				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			flx6: flexcom@f8010000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8010000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8010000 0x800>;
+				status = "disabled";
+			};
+
+			flx7: flexcom@f8014000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8014000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8014000 0x800>;
+				status = "disabled";
+			};
+
+			flx8: flexcom@f8018000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8018000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8018000 0x800>;
+				status = "disabled";
+			};
+
+			flx0: flexcom@f801c000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf801c000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf801c000 0x800>;
+				status = "disabled";
+			};
+
+			flx1: flexcom@f8020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8020000 0x800>;
+				status = "disabled";
+			};
+
+			flx2: flexcom@f8024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8024000 0x800>;
+				status = "disabled";
+			};
+
+			flx3: flexcom@f8028000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8028000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8028000 0x800>;
+				status = "disabled";
+			};
+
+			macb0: ethernet@f802c000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf802c000 0x1000>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			macb1: ethernet@f8030000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf8030000 0x1000>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			pwm0: pwm@f8034000 {
+				compatible = "microchip,sam9x60-pwm";
+				reg = <0xf8034000 0x300>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+				#pwm-cells = <3>;
+				status="disabled";
+			};
+
+			hlcdc: hlcdc@f8038000 {
+				compatible = "microchip,sam9x60-hlcdc";
+				reg = <0xf8038000 0x4000>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
+				clock-names = "periph_clk","sys_clk", "slow_clk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
+				status = "disabled";
+
+				hlcdc-display-controller {
+					compatible = "atmel,hlcdc-display-controller";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						reg = <0>;
+					};
+				};
+
+				hlcdc_pwm: hlcdc-pwm {
+					compatible = "atmel,hlcdc-pwm";
+					#pwm-cells = <3>;
+				};
+			};
+
+			flx9: flexcom@f8040000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8040000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8040000 0x800>;
+				status = "disabled";
+			};
+
+			flx10: flexcom@f8044000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8044000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8044000 0x800>;
+				status = "disabled";
+			};
+
+			isi: isi@f8048000 {
+				compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
+				reg = <0xf8048000 0x100>;
+				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+				clock-names = "isi_clk";
+				status = "disabled";
+				port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			adc: adc@f804c000 {
+				compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
+				reg = <0xf804c000 0x100>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+				clock-names = "adc_clk";
+				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
+				dma-names = "rx";
+				atmel,min-sample-rate-hz = <200000>;
+				atmel,max-sample-rate-hz = <20000000>;
+				atmel,startup-time-ms = <4>;
+				atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+				#io-channel-cells = <1>;
+				status = "disabled";
+			};
+
+			sfr: sfr@f8050000 {
+				compatible = "microchip,sam9x60-sfr", "syscon";
+				reg = <0xf8050000 0x100>;
+			};
+
+			matrix: matrix@ffffde00 {
+				compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
+				reg = <0xffffde00 0x200>;
+			};
+
+			pmecc: ecc-engine@ffffe000 {
+				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+				reg = <0xffffe000 0x300>,
+				      <0xffffe600 0x100>;
+			};
+
+			mpddrc: mpddrc@ffffe800 {
+				compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
+				reg = <0xffffe800 0x200>;
+				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+				clock-names = "ddrck", "mpddr";
+			};
+
+			smc: smc@ffffea00 {
+				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+				reg = <0xffffea00 0x100>;
+			};
+
+			aic: interrupt-controller@fffff100 {
+				compatible = "microchip,sam9x60-aic";
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				reg = <0xfffff100 0x100>;
+				atmel,external-irqs = <31>;
+			};
+
+			dbgu: serial@fffff200 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xfffff200 0x200>;
+				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(28))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(29))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			pinctrl: pinctrl@fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff400 0xfffff400 0x800>;
+
+				pioA: gpio@fffff400 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <26>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+				};
+
+				pioD: gpio@fffffa00 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <22>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+				};
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "microchip,sam9x60-pmc", "syscon";
+				reg = <0xfffffc00 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				#clock-cells = <2>;
+				clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+				clock-names = "td_slck", "md_slck", "main_xtal";
+			};
+
+			reset_controller: rstc@fffffe00 {
+				compatible = "microchip,sam9x60-rstc";
+				reg = <0xfffffe00 0x10>;
+				clocks = <&clk32k 0>;
+			};
+
+			shutdown_controller: shdwc@fffffe10 {
+				compatible = "microchip,sam9x60-shdwc";
+				reg = <0xfffffe10 0x10>;
+				clocks = <&clk32k 0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				atmel,wakeup-rtc-timer;
+				atmel,wakeup-rtt-timer;
+				status = "disabled";
+			};
+
+			pit: timer@fffffe40 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffe40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			};
+
+			clk32k: sckc@fffffe50 {
+				compatible = "microchip,sam9x60-sckc";
+				reg = <0xfffffe50 0x4>;
+				clocks = <&slow_xtal>;
+				#clock-cells = <1>;
+			};
+
+			gpbr: syscon@fffffe60 {
+				compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffe60 0x10>;
+			};
+
+			rtc: rtc@fffffea8 {
+				compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
+				reg = <0xfffffea8 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k 0>;
+			};
+		};
+	};
+};
-- 
2.7.4


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^ permalink raw reply	[flat|nested] 108+ messages in thread

* [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
@ 2020-01-08 12:55   ` Claudiu Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu Beznea @ 2020-01-08 12:55 UTC (permalink / raw)
  To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, miquel.raynal, richard, vigneshr, wg, mkl,
	a.zummo, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev,
	Sandeep Sheriker Mallikarjun, linux-kernel, linux-spi, linux-mtd,
	dmaengine, Codrin Ciubotariu, linux-can, Claudiu Beznea,
	linux-arm-kernel, linux-media

From: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>

Add device tree files for SAM9X60 SoC and SAM9X60-EK board.

Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
 arch/arm/boot/dts/Makefile           |   2 +
 arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/sam9x60.dtsi       | 691 +++++++++++++++++++++++++++++++++++
 3 files changed, 1340 insertions(+)
 create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
 create mode 100644 arch/arm/boot/dts/sam9x60.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 08011dc8c7a6..36e90f07be13 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 	at91sam9g35ek.dtb \
 	at91sam9x25ek.dtb \
 	at91sam9x35ek.dtb
+dtb-$(CONFIG_SOC_SAM9X60) += \
+	at91-sam9x60ek.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
 	at91-kizbox2-2.dtb \
 	at91-kizbox3-hs.dtb \
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
new file mode 100644
index 000000000000..9f30132d7d7b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+
+/ {
+	model = "Microchip SAM9X60-EK";
+	compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal {
+			clock-frequency = <24000000>;
+		};
+	};
+
+	regulators: regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_1v8: fixed-regulator-vdd_1v8@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd_1v5: fixed-regulator-vdd_1v5@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_1V5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD1_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+
+		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD2_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			status = "okay";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+		status = "okay";
+
+		sw1 {
+			label = "SW1";
+			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
+			linux,code=<0x104>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay"; /* Conflict with pwm0. */
+
+		red {
+			label = "red";
+			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		green {
+			label = "green";
+			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue {
+			label = "blue";
+			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&adc {
+	vddana-supply = <&vdd1_3v3>;
+	vref-supply = <&vdd1_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+	status = "okay";
+};
+
+&can0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can0_rx_tx>;
+	status = "disabled"; /* Conflict with dbgu. */
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_rx_tx>;
+	status = "okay";
+};
+
+&classd {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_classd_default>;
+	atmel,pwm-type = "diff";
+	atmel,non-overlap-time = <10>;
+	status = "okay";
+};
+
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+	status = "okay"; /* Conflict with can0. */
+};
+
+&ebi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+	status = "okay";
+
+	nand_controller: nand-controller {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+		status = "okay";
+
+		nand@3 {
+			reg = <0x3 0x0 0x800000>;
+			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+			nand-bus-width = <8>;
+			nand-ecc-mode = "hw";
+			nand-ecc-strength = <8>;
+			nand-ecc-step-size = <512>;
+			nand-on-flash-bbt;
+			label = "atmel_nand";
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				at91bootstrap@0 {
+					label = "at91bootstrap";
+					reg = <0x0 0x40000>;
+				};
+
+				uboot@40000 {
+					label = "u-boot";
+					reg = <0x40000 0xc0000>;
+				};
+
+				ubootenvred@100000 {
+					label = "U-Boot Env Redundant";
+					reg = <0x100000 0x40000>;
+				};
+
+				ubootenv@140000 {
+					label = "U-Boot Env";
+					reg = <0x140000 0x40000>;
+				};
+
+				dtb@180000 {
+					label = "device tree";
+					reg = <0x180000 0x80000>;
+				};
+
+				kernel@200000 {
+					label = "kernel";
+					reg = <0x200000 0x600000>;
+				};
+
+				rootfs@800000 {
+					label = "rootfs";
+					reg = <0x800000 0x1f800000>;
+				};
+			};
+		};
+	};
+};
+
+&flx0 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c0: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx0_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		eeprom@53 {
+			compatible = "atmel,24c32";
+			reg = <0x53>;
+			pagesize = <16>;
+			size = <128>;
+			status = "okay";
+		};
+	};
+};
+
+&flx4 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+	status = "disabled";
+
+	spi0: spi@400 {
+		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+		reg = <0x400 0x200>;
+		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+		clock-names = "spi_clk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx4_default>;
+		atmel,fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
+
+&flx5 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+	status = "okay";
+
+	uart1: serial@200 {
+		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+		reg = <0x200 0x200>;
+		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+		dmas = <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(10))>,
+		       <&dma0
+			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+			 AT91_XDMAC_DT_PERID(11))>;
+		dma-names = "tx", "rx";
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+		clock-names = "usart";
+		pinctrl-0 = <&pinctrl_flx5_default>;
+		pinctrl-names = "default";
+		atmel,use-dma-rx;
+		atmel,use-dma-tx;
+		status = "okay";
+	};
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c1: i2c@600 {
+		compatible = "microchip,sam9x60-i2c";
+		reg = <0x600 0x200>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flx6_default>;
+		atmel,fifo-size = <16>;
+		i2c-analog-filter;
+		i2c-digital-filter;
+		i2c-digital-filter-width-ns = <35>;
+		status = "okay";
+
+		gpio_exp: mcp23008@20 {
+			compatible = "microchip,mcp23008";
+			reg = <0x20>;
+		};
+	};
+};
+
+&i2s {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2s_default>;
+	#sound-dai-cells = <0>;
+	status = "disabled"; /* Conflict with QSPI. */
+};
+
+&macb0 {
+	phy-mode = "rmii";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_macb0_rmii>;
+	status = "okay";
+
+	ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	atmel,mux-mask = <
+			 /*	A	B	C	*/
+			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
+			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
+			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
+			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
+			 >;
+
+	adc {
+		pinctrl_adc_default: adc_default {
+			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_adtrg_default: adtrg_default {
+			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				      AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	i2s {
+		pinctrl_i2s_default: i2s {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SCK */
+				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SWS */
+				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDIN */
+				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE		/* I2SDOUT */
+				 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* I2SMCK */
+		};
+	};
+
+	qspi {
+		pinctrl_qspi: qspi {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+				 AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	nand {
+		pinctrl_nand_oe_we: nand-oe-we-0 {
+			atmel,pins =
+				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_nand_rb: nand-rb-0 {
+			atmel,pins =
+				<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_nand_cs: nand-cs-0 {
+			atmel,pins =
+				<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	ebi {
+		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_ebi_addr_nand: ebi-addr-0 {
+			atmel,pins =
+				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx0_default: flx0_twi {
+			atmel,pins =
+				<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_flx4_default: flx4_spi {
+			atmel,pins =
+				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx5_default: flx_uart {
+			atmel,pins =
+				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
+				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
+				 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_flx6_default: flx6_twi {
+			atmel,pins =
+				<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	classd {
+		pinctrl_classd_default: classd {
+			atmel,pins =
+				<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	can0 {
+		pinctrl_can0_rx_tx: can0_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0 */
+				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX0 */
+				 AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	can1 {
+		pinctrl_can1_rx_tx: can1_rx_tx {
+			atmel,pins =
+				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1 RXD1 */
+				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANTX1 TXD1 */
+				 AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
+				 AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
+		};
+	};
+
+	macb0 {
+		pinctrl_macb0_rmii: macb0_rmii-0 {
+			atmel,pins =
+				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+				 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+		};
+	};
+
+	pwm0 {
+		pinctrl_pwm0_0: pwm0_0 {
+			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_1: pwm0_1 {
+			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_2: pwm0_2 {
+			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+
+		pinctrl_pwm0_3: pwm0_3 {
+			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+		};
+	};
+
+	sdmmc0 {
+		pinctrl_sdmmc0_default: sdmmc0 {
+			atmel,pins =
+				<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17 CK  periph A with pullup */
+				 AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD periph A with pullup */
+				 AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0 periph A */
+				 AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1 periph A with pullup */
+				 AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2 periph A with pullup */
+				 AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3 periph A with pullup */
+		};
+	};
+
+	gpio_keys {
+		pinctrl_key_gpio_default: pinctrl_key_gpio {
+			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+}; /* pinctrl */
+
+&pmc {
+	atmel,osc-bypass;
+};
+
+&pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
+	status = "disabled"; /* Conflict with leds. */
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc0_default>;
+	status = "okay";
+	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay"; /* Conflict with i2s. */
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		m25p,fast-read;
+
+		at91bootstrap@0 {
+			label = "qspi: at91bootstrap";
+			reg = <0x0 0x40000>;
+		};
+
+		bootloader@40000 {
+			label = "qspi: bootloader";
+			reg = <0x40000 0xc0000>;
+		};
+
+		bootloaderenvred@100000 {
+			label = "qspi: bootloader env redundant";
+			reg = <0x100000 0x40000>;
+		};
+
+		bootloaderenv@140000 {
+			label = "qspi: bootloader env";
+			reg = <0x140000 0x40000>;
+		};
+
+		dtb@180000 {
+			label = "qspi: device tree";
+			reg = <0x180000 0x80000>;
+		};
+
+		kernel@200000 {
+			label = "qspi: kernel";
+			reg = <0x200000 0x600000>;
+		};
+	};
+};
+
+&shutdown_controller {
+	atmel,shdwc-debouncer = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
+&tcb0 {
+	timer0: timer@0 {
+		compatible = "atmel,tcb-timer";
+		reg = <0>;
+	};
+
+	timer1: timer@1 {
+		compatible = "atmel,tcb-timer";
+		reg = <1>;
+	};
+};
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 16 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
new file mode 100644
index 000000000000..2eb92a90453b
--- /dev/null
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Microchip SAM9X60 SoC";
+	compatible = "microchip,sam9x60";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+		tcb0 = &tcb0;
+		tcb1 = &tcb1;
+	};
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x20000000 0x10000000>;
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	sram: sram@300000 {
+		compatible = "mmio-sram";
+		reg = <0x00300000 0x100000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		usb1: ohci@600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00600000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb2: ehci@700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00700000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+			clock-names = "usb_clk", "ehci_clk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
+		ebi: ebi@10000000 {
+			compatible = "microchip,sam9x60-ebi";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			atmel,smc = <&smc>;
+			microchip,sfr = <&sfr>;
+			reg = <0x10000000 0x60000000>;
+			ranges = <0x0 0x0 0x10000000 0x10000000
+				  0x1 0x0 0x20000000 0x10000000
+				  0x2 0x0 0x30000000 0x10000000
+				  0x3 0x0 0x40000000 0x10000000
+				  0x4 0x0 0x50000000 0x10000000
+				  0x5 0x0 0x60000000 0x10000000>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			status = "disabled";
+
+			nand_controller: nand-controller {
+				compatible = "microchip,sam9x60-nand-controller";
+				ecc-engine = <&pmecc>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				ranges;
+				status = "disabled";
+			};
+		};
+
+		sdmmc0: sdio-host@80000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x80000000 0x300>;
+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		sdmmc1: sdio-host@90000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x90000000 0x300>;
+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			flx4: flexcom@f0000000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0000000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0000000 0x800>;
+				status = "disabled";
+			};
+
+			flx5: flexcom@f0004000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0004000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0004000 0x800>;
+				status = "disabled";
+			};
+
+			dma0: dma-controller@f0008000 {
+				compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
+				reg = <0xf0008000 0x1000>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+				#dma-cells = <1>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+				clock-names = "dma_clk";
+			};
+
+			ssc: ssc@f0010000 {
+				compatible = "atmel,at91sam9g45-ssc";
+				reg = <0xf0010000 0x4000>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(38))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(39))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			qspi: spi@f0014000 {
+				compatible = "microchip,sam9x60-qspi";
+				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
+				reg-names = "qspi_base", "qspi_mmap";
+				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(26))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(27))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
+				clock-names = "pclk", "qspick";
+				atmel,pmc = <&pmc>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2s: i2s@f001c000 {
+				compatible = "microchip,sam9x60-i2smcc";
+				reg = <0xf001c000 0x100>;
+				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(36))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(37))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			flx11: flexcom@f0020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0020000 0x800>;
+				status = "disabled";
+			};
+
+			flx12: flexcom@f0024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf0024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf0024000 0x800>;
+				status = "disabled";
+			};
+
+			pit64b: timer@f0028000 {
+				compatible = "microchip,sam9x60-pit64b";
+				reg = <0xf0028000 0x100>;
+				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+				clock-names = "pclk", "gclk";
+			};
+
+			sha: sha@f002c000 {
+				compatible = "atmel,at91sam9g46-sha";
+				reg = <0xf002c000 0x100>;
+				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(34))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+				clock-names = "sha_clk";
+				status = "okay";
+			};
+
+			trng: trng@f0030000 {
+				compatible = "microchip,sam9x60-trng";
+				reg = <0xf0030000 0x100>;
+				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+				status = "okay";
+			};
+
+			aes: aes@f0034000 {
+				compatible = "atmel,at91sam9g46-aes";
+				reg = <0xf0034000 0x100>;
+				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(32))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(33))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+				clock-names = "aes_clk";
+				status = "okay";
+			};
+
+			tdes: tdes@f0038000 {
+				compatible = "atmel,at91sam9g46-tdes";
+				reg = <0xf0038000 0x100>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(31))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(30))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+				clock-names = "tdes_clk";
+				status = "okay";
+			};
+
+			classd: classd@f003c000 {
+				compatible = "atmel,sama5d2-classd";
+				reg = <0xf003c000 0x100>;
+				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(35))>;
+				dma-names = "tx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+				clock-names = "pclk", "gclk";
+				status = "disabled";
+			};
+
+			can0: can@f8000000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8000000 0x300>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			can1: can@f8004000 {
+				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+				reg = <0xf8004000 0x300>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+				clock-names = "can_clk";
+				status = "disabled";
+			};
+
+			tcb0: timer@f8008000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf8008000 0x100>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			tcb1: timer@f800c000 {
+				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0xf800c000 0x100>;
+				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			flx6: flexcom@f8010000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8010000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8010000 0x800>;
+				status = "disabled";
+			};
+
+			flx7: flexcom@f8014000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8014000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8014000 0x800>;
+				status = "disabled";
+			};
+
+			flx8: flexcom@f8018000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8018000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8018000 0x800>;
+				status = "disabled";
+			};
+
+			flx0: flexcom@f801c000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf801c000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf801c000 0x800>;
+				status = "disabled";
+			};
+
+			flx1: flexcom@f8020000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8020000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8020000 0x800>;
+				status = "disabled";
+			};
+
+			flx2: flexcom@f8024000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8024000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8024000 0x800>;
+				status = "disabled";
+			};
+
+			flx3: flexcom@f8028000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8028000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8028000 0x800>;
+				status = "disabled";
+			};
+
+			macb0: ethernet@f802c000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf802c000 0x1000>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			macb1: ethernet@f8030000 {
+				compatible = "cdns,sam9x60-macb", "cdns,macb";
+				reg = <0xf8030000 0x1000>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			pwm0: pwm@f8034000 {
+				compatible = "microchip,sam9x60-pwm";
+				reg = <0xf8034000 0x300>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+				#pwm-cells = <3>;
+				status="disabled";
+			};
+
+			hlcdc: hlcdc@f8038000 {
+				compatible = "microchip,sam9x60-hlcdc";
+				reg = <0xf8038000 0x4000>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
+				clock-names = "periph_clk","sys_clk", "slow_clk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
+				status = "disabled";
+
+				hlcdc-display-controller {
+					compatible = "atmel,hlcdc-display-controller";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						reg = <0>;
+					};
+				};
+
+				hlcdc_pwm: hlcdc-pwm {
+					compatible = "atmel,hlcdc-pwm";
+					#pwm-cells = <3>;
+				};
+			};
+
+			flx9: flexcom@f8040000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8040000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8040000 0x800>;
+				status = "disabled";
+			};
+
+			flx10: flexcom@f8044000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xf8044000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xf8044000 0x800>;
+				status = "disabled";
+			};
+
+			isi: isi@f8048000 {
+				compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
+				reg = <0xf8048000 0x100>;
+				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+				clock-names = "isi_clk";
+				status = "disabled";
+				port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			adc: adc@f804c000 {
+				compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
+				reg = <0xf804c000 0x100>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+				clock-names = "adc_clk";
+				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
+				dma-names = "rx";
+				atmel,min-sample-rate-hz = <200000>;
+				atmel,max-sample-rate-hz = <20000000>;
+				atmel,startup-time-ms = <4>;
+				atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+				#io-channel-cells = <1>;
+				status = "disabled";
+			};
+
+			sfr: sfr@f8050000 {
+				compatible = "microchip,sam9x60-sfr", "syscon";
+				reg = <0xf8050000 0x100>;
+			};
+
+			matrix: matrix@ffffde00 {
+				compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
+				reg = <0xffffde00 0x200>;
+			};
+
+			pmecc: ecc-engine@ffffe000 {
+				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+				reg = <0xffffe000 0x300>,
+				      <0xffffe600 0x100>;
+			};
+
+			mpddrc: mpddrc@ffffe800 {
+				compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
+				reg = <0xffffe800 0x200>;
+				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+				clock-names = "ddrck", "mpddr";
+			};
+
+			smc: smc@ffffea00 {
+				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+				reg = <0xffffea00 0x100>;
+			};
+
+			aic: interrupt-controller@fffff100 {
+				compatible = "microchip,sam9x60-aic";
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				reg = <0xfffff100 0x100>;
+				atmel,external-irqs = <31>;
+			};
+
+			dbgu: serial@fffff200 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xfffff200 0x200>;
+				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(28))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(29))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			pinctrl: pinctrl@fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff400 0xfffff400 0x800>;
+
+				pioA: gpio@fffff400 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <26>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+				};
+
+				pioD: gpio@fffffa00 {
+					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <22>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+				};
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "microchip,sam9x60-pmc", "syscon";
+				reg = <0xfffffc00 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				#clock-cells = <2>;
+				clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+				clock-names = "td_slck", "md_slck", "main_xtal";
+			};
+
+			reset_controller: rstc@fffffe00 {
+				compatible = "microchip,sam9x60-rstc";
+				reg = <0xfffffe00 0x10>;
+				clocks = <&clk32k 0>;
+			};
+
+			shutdown_controller: shdwc@fffffe10 {
+				compatible = "microchip,sam9x60-shdwc";
+				reg = <0xfffffe10 0x10>;
+				clocks = <&clk32k 0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				atmel,wakeup-rtc-timer;
+				atmel,wakeup-rtt-timer;
+				status = "disabled";
+			};
+
+			pit: timer@fffffe40 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffe40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			};
+
+			clk32k: sckc@fffffe50 {
+				compatible = "microchip,sam9x60-sckc";
+				reg = <0xfffffe50 0x4>;
+				clocks = <&slow_xtal>;
+				#clock-cells = <1>;
+			};
+
+			gpbr: syscon@fffffe60 {
+				compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffe60 0x10>;
+			};
+
+			rtc: rtc@fffffea8 {
+				compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
+				reg = <0xfffffea8 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k 0>;
+			};
+		};
+	};
+};
-- 
2.7.4


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^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
  2020-01-08 12:55   ` Claudiu Beznea
                       ` (2 preceding siblings ...)
  (?)
@ 2020-01-09 19:16     ` Miquel Raynal
  -1 siblings, 0 replies; 108+ messages in thread
From: Miquel Raynal @ 2020-01-09 19:16 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, richard, vigneshr, wg, mkl, a.zummo, broonie,
	devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc

Hi Claudiu,

Claudiu Beznea <claudiu.beznea@microchip.com> wrote on Wed, 8 Jan 2020
14:55:14 +0200:

> Add microchip,sam9x60-pmecc to DT bindings documentation.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 68b51dc58816..3aa297c97ab6 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -57,6 +57,7 @@ Required properties:
>  	"atmel,at91sam9g45-pmecc"
>  	"atmel,sama5d4-pmecc"
>  	"atmel,sama5d2-pmecc"
> +	"microchip,sam9x60-pmecc"
>  - reg: should contain 2 register ranges. The first one is pointing to the PMECC
>         block, and the second one to the PMECC_ERRLOC block.
>  

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

Thanks,
Miquèl

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
@ 2020-01-09 19:16     ` Miquel Raynal
  0 siblings, 0 replies; 108+ messages in thread
From: Miquel Raynal @ 2020-01-09 19:16 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, richard, vigneshr, wg, mkl, a.zummo, broonie,
	devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd

Hi Claudiu,

Claudiu Beznea <claudiu.beznea@microchip.com> wrote on Wed, 8 Jan 2020
14:55:14 +0200:

> Add microchip,sam9x60-pmecc to DT bindings documentation.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 68b51dc58816..3aa297c97ab6 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -57,6 +57,7 @@ Required properties:
>  	"atmel,at91sam9g45-pmecc"
>  	"atmel,sama5d4-pmecc"
>  	"atmel,sama5d2-pmecc"
> +	"microchip,sam9x60-pmecc"
>  - reg: should contain 2 register ranges. The first one is pointing to the PMECC
>         block, and the second one to the PMECC_ERRLOC block.
>  

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

Thanks,
Miquèl

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
@ 2020-01-09 19:16     ` Miquel Raynal
  0 siblings, 0 replies; 108+ messages in thread
From: Miquel Raynal @ 2020-01-09 19:16 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni,
	ludovic.desroches, vkoul, eugen.hristev, jic23, knaack.h, lars,
	pmeerw, mchehab, lee.jones, richard.genoud, radu_nicolae.pirea,
	tudor.ambarus, richard, vigneshr, wg, mkl, a.zummo, broonie,
	devicetree, linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd

Hi Claudiu,

Claudiu Beznea <claudiu.beznea@microchip.com> wrote on Wed, 8 Jan 2020
14:55:14 +0200:

> Add microchip,sam9x60-pmecc to DT bindings documentation.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 68b51dc58816..3aa297c97ab6 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -57,6 +57,7 @@ Required properties:
>  	"atmel,at91sam9g45-pmecc"
>  	"atmel,sama5d4-pmecc"
>  	"atmel,sama5d2-pmecc"
> +	"microchip,sam9x60-pmecc"
>  - reg: should contain 2 register ranges. The first one is pointing to the PMECC
>         block, and the second one to the PMECC_ERRLOC block.
>  

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

Thanks,
Miquèl

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
@ 2020-01-09 19:16     ` Miquel Raynal
  0 siblings, 0 replies; 108+ messages in thread
From: Miquel Raynal @ 2020-01-09 19:16 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, alexandre.belloni, vigneshr, linux-iio,
	linux-kernel, linux-mtd, pmeerw, lee.jones, linux-rtc, lars,
	richard, ludovic.desroches, wg, linux-media, devicetree,
	tudor.ambarus, radu_nicolae.pirea, linux-can, broonie, mkl,
	mchehab, linux-arm-kernel, a.zummo, richard.genoud, netdev,
	nicolas.ferre, linux-spi, vkoul, robh+dt, knaack.h, dmaengine,
	eugen.hristev, jic23

Hi Claudiu,

Claudiu Beznea <claudiu.beznea@microchip.com> wrote on Wed, 8 Jan 2020
14:55:14 +0200:

> Add microchip,sam9x60-pmecc to DT bindings documentation.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 68b51dc58816..3aa297c97ab6 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -57,6 +57,7 @@ Required properties:
>  	"atmel,at91sam9g45-pmecc"
>  	"atmel,sama5d4-pmecc"
>  	"atmel,sama5d2-pmecc"
> +	"microchip,sam9x60-pmecc"
>  - reg: should contain 2 register ranges. The first one is pointing to the PMECC
>         block, and the second one to the PMECC_ERRLOC block.
>  

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

Thanks,
Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc
@ 2020-01-09 19:16     ` Miquel Raynal
  0 siblings, 0 replies; 108+ messages in thread
From: Miquel Raynal @ 2020-01-09 19:16 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, alexandre.belloni, vigneshr, linux-iio,
	linux-kernel, linux-mtd, pmeerw, lee.jones, linux-rtc, lars,
	richard, ludovic.desroches, wg, linux-media, devicetree,
	tudor.ambarus, radu_nicolae.pirea, linux-can, broonie, mkl,
	mchehab, linux-arm-kernel, a.zummo, richard.genoud, netdev,
	linux-spi, vkoul, robh+dt, knaack.h, dmaengine, eugen.hristev,
	jic23

Hi Claudiu,

Claudiu Beznea <claudiu.beznea@microchip.com> wrote on Wed, 8 Jan 2020
14:55:14 +0200:

> Add microchip,sam9x60-pmecc to DT bindings documentation.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 68b51dc58816..3aa297c97ab6 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -57,6 +57,7 @@ Required properties:
>  	"atmel,at91sam9g45-pmecc"
>  	"atmel,sama5d4-pmecc"
>  	"atmel,sama5d2-pmecc"
> +	"microchip,sam9x60-pmecc"
>  - reg: should contain 2 register ranges. The first one is pointing to the PMECC
>         block, and the second one to the PMECC_ERRLOC block.
>  

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

Thanks,
Miquèl

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Applied "dt-bindings: spi_atmel: add microchip,sam9x60-spi" to the spi tree
  2020-01-08 12:55   ` Claudiu Beznea
                       ` (2 preceding siblings ...)
  (?)
@ 2020-01-09 21:31     ` Mark Brown
  -1 siblings, 0 replies; 108+ messages in thread
From: Mark Brown @ 2020-01-09 21:31 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: alexandre.belloni, a.zummo, broonie, devicetree, dmaengine,
	eugen.hristev, jic23, knaack.h, lars, lee.jones,
	linux-arm-kernel, linux-can, linux-iio, linux-kernel,
	linux-media, linux-mtd, linux-rtc, linux-spi, ludovic.desroches,
	Mark Brown, mark.rutland, mchehab, miquel.raynal, mkl, netdev,
	nicolas.ferre, pmeerw, radu_nicolae.pirea, richard.genoud,
	richard, robh+dt, tudor.ambarus, vigneshr, vkoul, wg

The patch

   dt-bindings: spi_atmel: add microchip,sam9x60-spi

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.6

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 0a1eb761ff30cdc089bcc94e1bd540b6956487c5 Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Wed, 8 Jan 2020 14:55:19 +0200
Subject: [PATCH] dt-bindings: spi_atmel: add microchip,sam9x60-spi

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1578488123-26127-13-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.20.1


^ permalink raw reply	[flat|nested] 108+ messages in thread

* Applied "dt-bindings: spi_atmel: add microchip,sam9x60-spi" to the spi tree
@ 2020-01-09 21:31     ` Mark Brown
  0 siblings, 0 replies; 108+ messages in thread
From: Mark Brown @ 2020-01-09 21:31 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: alexandre.belloni, a.zummo, broonie, devicetree, dmaengine,
	eugen.hristev, jic23, knaack.h, lars, lee.jones,
	linux-arm-kernel, linux-can, linux-iio, linux-kernel,
	linux-media, linux-mtd, linux-rtc, linux-spi, ludovic.desroches

The patch

   dt-bindings: spi_atmel: add microchip,sam9x60-spi

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.6

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 0a1eb761ff30cdc089bcc94e1bd540b6956487c5 Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Wed, 8 Jan 2020 14:55:19 +0200
Subject: [PATCH] dt-bindings: spi_atmel: add microchip,sam9x60-spi

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1578488123-26127-13-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.20.1

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Applied "dt-bindings: spi_atmel: add microchip,sam9x60-spi" to the spi tree
@ 2020-01-09 21:31     ` Mark Brown
  0 siblings, 0 replies; 108+ messages in thread
From: Mark Brown @ 2020-01-09 21:31 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: alexandre.belloni, a.zummo, broonie, devicetree, dmaengine,
	eugen.hristev, jic23, knaack.h, lars, lee.jones,
	linux-arm-kernel, linux-can, linux-iio, linux-kernel,
	linux-media, linux-mtd, linux-rtc, linux-spi, ludovic.desroches,
	Mark Brown, mark.rutland, mchehab, miquel.raynal, mkl, netdev,
	nicolas.ferre, pmeerw, radu_nicolae.pirea, richard.genoud,
	richard, robh+dt, t

The patch

   dt-bindings: spi_atmel: add microchip,sam9x60-spi

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.6

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 0a1eb761ff30cdc089bcc94e1bd540b6956487c5 Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Wed, 8 Jan 2020 14:55:19 +0200
Subject: [PATCH] dt-bindings: spi_atmel: add microchip,sam9x60-spi

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1578488123-26127-13-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.20.1

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Applied "dt-bindings: spi_atmel: add microchip, sam9x60-spi" to the spi tree
@ 2020-01-09 21:31     ` Mark Brown
  0 siblings, 0 replies; 108+ messages in thread
From: Mark Brown @ 2020-01-09 21:31 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, alexandre.belloni, vigneshr, linux-iio,
	nicolas.ferre, linux-mtd, pmeerw, miquel.raynal, lee.jones,
	linux-rtc, lars, richard, ludovic.desroches, wg, linux-media,
	devicetree, tudor.ambarus, radu_nicolae.pirea, linux-can,
	Mark Brown, mkl, mchehab, linux-arm-kernel, a.zummo,
	richard.genoud, netdev, linux-kernel, linux-spi, vkoul, robh+dt,
	knaack.h, dmaengine, eugen.hristev, jic23

The patch

   dt-bindings: spi_atmel: add microchip,sam9x60-spi

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.6

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 0a1eb761ff30cdc089bcc94e1bd540b6956487c5 Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Wed, 8 Jan 2020 14:55:19 +0200
Subject: [PATCH] dt-bindings: spi_atmel: add microchip,sam9x60-spi

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1578488123-26127-13-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.20.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Applied "dt-bindings: spi_atmel: add microchip, sam9x60-spi" to the spi tree
@ 2020-01-09 21:31     ` Mark Brown
  0 siblings, 0 replies; 108+ messages in thread
From: Mark Brown @ 2020-01-09 21:31 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, alexandre.belloni, vigneshr, linux-iio, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	ludovic.desroches, wg, linux-media, devicetree, tudor.ambarus,
	radu_nicolae.pirea, linux-can, Mark Brown, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, linux-kernel,
	linux-spi, vkoul, robh+dt, knaack.h, dmaengine, eugen.hristev,
	jic23

The patch

   dt-bindings: spi_atmel: add microchip,sam9x60-spi

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.6

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 0a1eb761ff30cdc089bcc94e1bd540b6956487c5 Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Wed, 8 Jan 2020 14:55:19 +0200
Subject: [PATCH] dt-bindings: spi_atmel: add microchip,sam9x60-spi

Add microchip,sam9x60-spi to DT bindings documentation.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1578488123-26127-13-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/spi/spi_atmel.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index f99c733d75c1..5bb4a8f1df7a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -1,7 +1,7 @@
 Atmel SPI device
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-spi".
+- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 13:40     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 13:40 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: robh+dt, mark.rutland, nicolas.ferre, ludovic.desroches, vkoul,
	eugen.hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, tudor.ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc

On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
> Add microchip,<chip>-tcb to DT bindings documentation. This is for
> microchip,sam9x60-tcb.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> index c4a83e364cb6..e1713e41f6e0 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> @@ -1,6 +1,7 @@
>  * Device tree bindings for Atmel Timer Counter Blocks
> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
> -  <chip> can be "at91rm9200" or "at91sam9x5"
> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
> +  "simple-mfd", "syscon".
> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"

atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
are not allowed and the documentation should reflect that.

It would probably be easier to do that on top of the yaml conversion
here:
https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 13:40     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 13:40 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	nicolas.ferre-UWL1GkI3JZL3oGB3hsPCZA,
	ludovic.desroches-UWL1GkI3JZL3oGB3hsPCZA,
	vkoul-DgEjT+Ai2ygdnm+yROfE0A,
	eugen.hristev-UWL1GkI3JZL3oGB3hsPCZA,
	jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
	lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
	mchehab-DgEjT+Ai2ygdnm+yROfE0A, lee.jones-QSEj5FYQhm4dnm+yROfE0A,
	richard.genoud-Re5JQEeQqe8AvxtiuMwx3w,
	radu_nicolae.pirea-8LCfxC+Vs8U,
	tudor.ambarus-UWL1GkI3JZL3oGB3hsPCZA,
	miquel.raynal-LDxbnhwyfcJBDgjK7y7TUQ, richard-/L3Ra7n9ekc,
	vigneshr-l0cyMroinI0, wg-5Yr1BZd7O62+XT7JhA+gdA,
	mkl-bIcnvbaLZ9MEGnE8C9+IrQ, a.zummo-BfzFCNDTiLLj+vYz1yj4TQ,
	broonie-DgEjT+Ai2ygdnm+yROfE0A,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	dmaengine-u79uwXL29TY76Z2rM5mHXA,
	linux-iio-u79uwXL29TY76Z2rM5mHXA,
	linux-media-u79uwXL29TY76Z2rM5mHXA,
	linux-spi-u79uwXL29TY76Z2rM5mHXA,
	linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-can-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
	linux-rtc-fy+rA21nqHI

On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
> Add microchip,<chip>-tcb to DT bindings documentation. This is for
> microchip,sam9x60-tcb.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> index c4a83e364cb6..e1713e41f6e0 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> @@ -1,6 +1,7 @@
>  * Device tree bindings for Atmel Timer Counter Blocks
> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
> -  <chip> can be "at91rm9200" or "at91sam9x5"
> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
> +  "simple-mfd", "syscon".
> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"

atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
are not allowed and the documentation should reflect that.

It would probably be easier to do that on top of the yaml conversion
here:
https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org/

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 13:40     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 13:40 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	ludovic.desroches, wg, linux-media, devicetree, tudor.ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, nicolas.ferre,
	linux-spi, vkoul, broonie, knaack.h, dmaengine, eugen.hristev,
	jic23

On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
> Add microchip,<chip>-tcb to DT bindings documentation. This is for
> microchip,sam9x60-tcb.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> index c4a83e364cb6..e1713e41f6e0 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> @@ -1,6 +1,7 @@
>  * Device tree bindings for Atmel Timer Counter Blocks
> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
> -  <chip> can be "at91rm9200" or "at91sam9x5"
> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
> +  "simple-mfd", "syscon".
> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"

atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
are not allowed and the documentation should reflect that.

It would probably be easier to do that on top of the yaml conversion
here:
https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 13:40     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 13:40 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	ludovic.desroches, wg, linux-media, devicetree, tudor.ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, linux-spi,
	vkoul, broonie, knaack.h, dmaengine, eugen.hristev, jic23

On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
> Add microchip,<chip>-tcb to DT bindings documentation. This is for
> microchip,sam9x60-tcb.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> index c4a83e364cb6..e1713e41f6e0 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> @@ -1,6 +1,7 @@
>  * Device tree bindings for Atmel Timer Counter Blocks
> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
> -  <chip> can be "at91rm9200" or "at91sam9x5"
> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
> +  "simple-mfd", "syscon".
> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"

atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
are not allowed and the documentation should reflect that.

It would probably be easier to do that on top of the yaml conversion
here:
https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
  2020-01-10 13:40     ` Alexandre Belloni
                         ` (2 preceding siblings ...)
  (?)
@ 2020-01-10 14:29       ` Claudiu.Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 14:29 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, vkoul,
	Eugen.Hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, Tudor.Ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc



On 10.01.2020 15:40, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
>> Add microchip,<chip>-tcb to DT bindings documentation. This is for
>> microchip,sam9x60-tcb.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> index c4a83e364cb6..e1713e41f6e0 100644
>> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> @@ -1,6 +1,7 @@
>>  * Device tree bindings for Atmel Timer Counter Blocks
>> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
>> -  <chip> can be "at91rm9200" or "at91sam9x5"
>> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
>> +  "simple-mfd", "syscon".
>> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> 
> atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> are not allowed and the documentation should reflect that.

OK! I'll double check it.

> 
> It would probably be easier to do that on top of the yaml conversion
> here:
> https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/

I don't see this integrated in next-20200110. Am I looking at the wrong branch?

> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 14:29       ` Claudiu.Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 14:29 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, vkoul,
	Eugen.Hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, Tudor.Ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd



On 10.01.2020 15:40, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
>> Add microchip,<chip>-tcb to DT bindings documentation. This is for
>> microchip,sam9x60-tcb.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> index c4a83e364cb6..e1713e41f6e0 100644
>> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> @@ -1,6 +1,7 @@
>>  * Device tree bindings for Atmel Timer Counter Blocks
>> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
>> -  <chip> can be "at91rm9200" or "at91sam9x5"
>> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
>> +  "simple-mfd", "syscon".
>> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> 
> atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> are not allowed and the documentation should reflect that.

OK! I'll double check it.

> 
> It would probably be easier to do that on top of the yaml conversion
> here:
> https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/

I don't see this integrated in next-20200110. Am I looking at the wrong branch?

> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 14:29       ` Claudiu.Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 14:29 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, vkoul,
	Eugen.Hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, Tudor.Ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd



On 10.01.2020 15:40, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
>> Add microchip,<chip>-tcb to DT bindings documentation. This is for
>> microchip,sam9x60-tcb.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> index c4a83e364cb6..e1713e41f6e0 100644
>> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> @@ -1,6 +1,7 @@
>>  * Device tree bindings for Atmel Timer Counter Blocks
>> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
>> -  <chip> can be "at91rm9200" or "at91sam9x5"
>> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
>> +  "simple-mfd", "syscon".
>> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> 
> atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> are not allowed and the documentation should reflect that.

OK! I'll double check it.

> 
> It would probably be easier to do that on top of the yaml conversion
> here:
> https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/

I don't see this integrated in next-20200110. Am I looking at the wrong branch?

> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 14:29       ` Claudiu.Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 14:29 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	Ludovic.Desroches, wg, linux-media, devicetree, Tudor.Ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, Nicolas.Ferre,
	linux-spi, vkoul, broonie, knaack.h, dmaengine, Eugen.Hristev,
	jic23



On 10.01.2020 15:40, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
>> Add microchip,<chip>-tcb to DT bindings documentation. This is for
>> microchip,sam9x60-tcb.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> index c4a83e364cb6..e1713e41f6e0 100644
>> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> @@ -1,6 +1,7 @@
>>  * Device tree bindings for Atmel Timer Counter Blocks
>> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
>> -  <chip> can be "at91rm9200" or "at91sam9x5"
>> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
>> +  "simple-mfd", "syscon".
>> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> 
> atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> are not allowed and the documentation should reflect that.

OK! I'll double check it.

> 
> It would probably be easier to do that on top of the yaml conversion
> here:
> https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/

I don't see this integrated in next-20200110. Am I looking at the wrong branch?

> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 14:29       ` Claudiu.Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 14:29 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	Ludovic.Desroches, wg, linux-media, devicetree, Tudor.Ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, linux-spi,
	vkoul, broonie, knaack.h, dmaengine, Eugen.Hristev, jic23



On 10.01.2020 15:40, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
>> Add microchip,<chip>-tcb to DT bindings documentation. This is for
>> microchip,sam9x60-tcb.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> index c4a83e364cb6..e1713e41f6e0 100644
>> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>> @@ -1,6 +1,7 @@
>>  * Device tree bindings for Atmel Timer Counter Blocks
>> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
>> -  <chip> can be "at91rm9200" or "at91sam9x5"
>> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
>> +  "simple-mfd", "syscon".
>> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> 
> atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> are not allowed and the documentation should reflect that.

OK! I'll double check it.

> 
> It would probably be easier to do that on top of the yaml conversion
> here:
> https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/

I don't see this integrated in next-20200110. Am I looking at the wrong branch?

> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
  2020-01-08 12:55   ` [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc Claudiu Beznea
  (?)
  (?)
@ 2020-01-10 14:30     ` Alexandre Belloni
  -1 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:30 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: robh+dt, mark.rutland, nicolas.ferre, ludovic.desroches, vkoul,
	eugen.hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, tudor.ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc

Hi,

On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
> Add microchip,sam9x60-rtc to DT bindings documentation.

This will have to be rebased on top of
https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> index 5d3791e789c6..35eab9138d0b 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> @@ -1,7 +1,8 @@
>  Atmel AT91RM9200 Real Time Clock
>  
>  Required properties:
> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
> +  "microchip,sam9x60-rtc"
>  - reg: physical base address of the controller and length of memory mapped
>    region.
>  - interrupts: rtc alarm/event interrupt
> -- 
> 2.7.4
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
@ 2020-01-10 14:30     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:30 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: robh+dt, mark.rutland, nicolas.ferre, ludovic.desroches, vkoul,
	eugen.hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, tudor.ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc

Hi,

On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
> Add microchip,sam9x60-rtc to DT bindings documentation.

This will have to be rebased on top of
https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> index 5d3791e789c6..35eab9138d0b 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> @@ -1,7 +1,8 @@
>  Atmel AT91RM9200 Real Time Clock
>  
>  Required properties:
> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
> +  "microchip,sam9x60-rtc"
>  - reg: physical base address of the controller and length of memory mapped
>    region.
>  - interrupts: rtc alarm/event interrupt
> -- 
> 2.7.4
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
@ 2020-01-10 14:30     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:30 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	ludovic.desroches, wg, linux-media, devicetree, tudor.ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, nicolas.ferre,
	linux-spi, vkoul, broonie, knaack.h, dmaengine, eugen.hristev,
	jic23

Hi,

On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
> Add microchip,sam9x60-rtc to DT bindings documentation.

This will have to be rebased on top of
https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> index 5d3791e789c6..35eab9138d0b 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> @@ -1,7 +1,8 @@
>  Atmel AT91RM9200 Real Time Clock
>  
>  Required properties:
> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
> +  "microchip,sam9x60-rtc"
>  - reg: physical base address of the controller and length of memory mapped
>    region.
>  - interrupts: rtc alarm/event interrupt
> -- 
> 2.7.4
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
@ 2020-01-10 14:30     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:30 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	ludovic.desroches, wg, linux-media, devicetree, tudor.ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, linux-spi,
	vkoul, broonie, knaack.h, dmaengine, eugen.hristev, jic23

Hi,

On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
> Add microchip,sam9x60-rtc to DT bindings documentation.

This will have to be rebased on top of
https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> index 5d3791e789c6..35eab9138d0b 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
> @@ -1,7 +1,8 @@
>  Atmel AT91RM9200 Real Time Clock
>  
>  Required properties:
> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
> +  "microchip,sam9x60-rtc"
>  - reg: physical base address of the controller and length of memory mapped
>    region.
>  - interrupts: rtc alarm/event interrupt
> -- 
> 2.7.4
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 13/16] dt-bindings: atmel-usart: add microchip,<chip>-usart
  2020-01-08 12:55   ` Claudiu Beznea
  (?)
@ 2020-01-10 14:31     ` Alexandre Belloni
  -1 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:31 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: robh+dt, mark.rutland, nicolas.ferre, ludovic.desroches, vkoul,
	eugen.hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, tudor.ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc

On 08/01/2020 14:55:20+0200, Claudiu Beznea wrote:
> Add microchip,<chip>-usart to DT bindings documentation. This is for
> microchip,sam9x60-usart.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mfd/atmel-usart.txt | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> index 699fd3c9ace8..e5c7331abe09 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> +++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> @@ -1,10 +1,12 @@
>  * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
>  
>  Required properties for USART:
> -- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
> +- compatible: Should be "atmel,<chip>-usart", "microchip,<chip>-usart" or
> +  "atmel,<chip>-dbgu".
>    The compatible <chip> indicated will be the first SoC to support an
>    additional mode or an USART new feature.
> -  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
> +  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart",
> +  "microchip,<chip>-usart".

The wildcard here should be eliminated because all the combinations are
not allowed. This would also make it clearer that this change is to
introduce a new IP instead of renamed atmel to microchip.

>  - reg: Should contain registers location and length
>  - interrupts: Should contain interrupt
>  - clock-names: tuple listing input clock names.
> -- 
> 2.7.4
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 13/16] dt-bindings: atmel-usart: add microchip,<chip>-usart
@ 2020-01-10 14:31     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:31 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	ludovic.desroches, wg, linux-media, devicetree, tudor.ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, nicolas.ferre,
	linux-spi, vkoul, broonie, knaack.h, dmaengine, eugen.hristev,
	jic23

On 08/01/2020 14:55:20+0200, Claudiu Beznea wrote:
> Add microchip,<chip>-usart to DT bindings documentation. This is for
> microchip,sam9x60-usart.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mfd/atmel-usart.txt | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> index 699fd3c9ace8..e5c7331abe09 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> +++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> @@ -1,10 +1,12 @@
>  * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
>  
>  Required properties for USART:
> -- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
> +- compatible: Should be "atmel,<chip>-usart", "microchip,<chip>-usart" or
> +  "atmel,<chip>-dbgu".
>    The compatible <chip> indicated will be the first SoC to support an
>    additional mode or an USART new feature.
> -  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
> +  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart",
> +  "microchip,<chip>-usart".

The wildcard here should be eliminated because all the combinations are
not allowed. This would also make it clearer that this change is to
introduce a new IP instead of renamed atmel to microchip.

>  - reg: Should contain registers location and length
>  - interrupts: Should contain interrupt
>  - clock-names: tuple listing input clock names.
> -- 
> 2.7.4
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 13/16] dt-bindings: atmel-usart: add microchip,<chip>-usart
@ 2020-01-10 14:31     ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:31 UTC (permalink / raw)
  To: Claudiu Beznea
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	ludovic.desroches, wg, linux-media, devicetree, tudor.ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, linux-spi,
	vkoul, broonie, knaack.h, dmaengine, eugen.hristev, jic23

On 08/01/2020 14:55:20+0200, Claudiu Beznea wrote:
> Add microchip,<chip>-usart to DT bindings documentation. This is for
> microchip,sam9x60-usart.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  Documentation/devicetree/bindings/mfd/atmel-usart.txt | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> index 699fd3c9ace8..e5c7331abe09 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> +++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
> @@ -1,10 +1,12 @@
>  * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
>  
>  Required properties for USART:
> -- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
> +- compatible: Should be "atmel,<chip>-usart", "microchip,<chip>-usart" or
> +  "atmel,<chip>-dbgu".
>    The compatible <chip> indicated will be the first SoC to support an
>    additional mode or an USART new feature.
> -  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
> +  For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart",
> +  "microchip,<chip>-usart".

The wildcard here should be eliminated because all the combinations are
not allowed. This would also make it clearer that this change is to
introduce a new IP instead of renamed atmel to microchip.

>  - reg: Should contain registers location and length
>  - interrupts: Should contain interrupt
>  - clock-names: tuple listing input clock names.
> -- 
> 2.7.4
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 14:32         ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:32 UTC (permalink / raw)
  To: Claudiu.Beznea
  Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, vkoul,
	Eugen.Hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, Tudor.Ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc

On 10/01/2020 14:29:27+0000, Claudiu.Beznea@microchip.com wrote:
> 
> 
> On 10.01.2020 15:40, Alexandre Belloni wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
> >> Add microchip,<chip>-tcb to DT bindings documentation. This is for
> >> microchip,sam9x60-tcb.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> >> ---
> >>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
> >>  1 file changed, 3 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> index c4a83e364cb6..e1713e41f6e0 100644
> >> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> @@ -1,6 +1,7 @@
> >>  * Device tree bindings for Atmel Timer Counter Blocks
> >> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
> >> -  <chip> can be "at91rm9200" or "at91sam9x5"
> >> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
> >> +  "simple-mfd", "syscon".
> >> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> > 
> > atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> > are not allowed and the documentation should reflect that.
> 
> OK! I'll double check it.
> 
> > 
> > It would probably be easier to do that on top of the yaml conversion
> > here:
> > https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/
> 
> I don't see this integrated in next-20200110. Am I looking at the wrong branch?
> 

I had a few comments and I need to resend.

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 14:32         ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:32 UTC (permalink / raw)
  To: Claudiu.Beznea-UWL1GkI3JZL3oGB3hsPCZA
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	Nicolas.Ferre-UWL1GkI3JZL3oGB3hsPCZA,
	Ludovic.Desroches-UWL1GkI3JZL3oGB3hsPCZA,
	vkoul-DgEjT+Ai2ygdnm+yROfE0A,
	Eugen.Hristev-UWL1GkI3JZL3oGB3hsPCZA,
	jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
	lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
	mchehab-DgEjT+Ai2ygdnm+yROfE0A, lee.jones-QSEj5FYQhm4dnm+yROfE0A,
	richard.genoud-Re5JQEeQqe8AvxtiuMwx3w,
	radu_nicolae.pirea-8LCfxC+Vs8U,
	Tudor.Ambarus-UWL1GkI3JZL3oGB3hsPCZA,
	miquel.raynal-LDxbnhwyfcJBDgjK7y7TUQ, richard-/L3Ra7n9ekc,
	vigneshr-l0cyMroinI0, wg-5Yr1BZd7O62+XT7JhA+gdA,
	mkl-bIcnvbaLZ9MEGnE8C9+IrQ, a.zummo-BfzFCNDTiLLj+vYz1yj4TQ,
	broonie-DgEjT+Ai2ygdnm+yROfE0A,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	dmaengine-u79uwXL29TY76Z2rM5mHXA,
	linux-iio-u79uwXL29TY76Z2rM5mHXA,
	linux-media-u79uwXL29TY76Z2rM5mHXA,
	linux-spi-u79uwXL29TY76Z2rM5mHXA,
	linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-can-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
	linux-rtc-fy+rA21nqHI

On 10/01/2020 14:29:27+0000, Claudiu.Beznea-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org wrote:
> 
> 
> On 10.01.2020 15:40, Alexandre Belloni wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
> >> Add microchip,<chip>-tcb to DT bindings documentation. This is for
> >> microchip,sam9x60-tcb.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> >> ---
> >>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
> >>  1 file changed, 3 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> index c4a83e364cb6..e1713e41f6e0 100644
> >> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> @@ -1,6 +1,7 @@
> >>  * Device tree bindings for Atmel Timer Counter Blocks
> >> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
> >> -  <chip> can be "at91rm9200" or "at91sam9x5"
> >> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
> >> +  "simple-mfd", "syscon".
> >> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> > 
> > atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> > are not allowed and the documentation should reflect that.
> 
> OK! I'll double check it.
> 
> > 
> > It would probably be easier to do that on top of the yaml conversion
> > here:
> > https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org/
> 
> I don't see this integrated in next-20200110. Am I looking at the wrong branch?
> 

I had a few comments and I need to resend.

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 14:32         ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:32 UTC (permalink / raw)
  To: Claudiu.Beznea
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	Ludovic.Desroches, wg, linux-media, devicetree, Tudor.Ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, Nicolas.Ferre,
	linux-spi, vkoul, broonie, knaack.h, dmaengine, Eugen.Hristev,
	jic23

On 10/01/2020 14:29:27+0000, Claudiu.Beznea@microchip.com wrote:
> 
> 
> On 10.01.2020 15:40, Alexandre Belloni wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
> >> Add microchip,<chip>-tcb to DT bindings documentation. This is for
> >> microchip,sam9x60-tcb.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> >> ---
> >>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
> >>  1 file changed, 3 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> index c4a83e364cb6..e1713e41f6e0 100644
> >> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> @@ -1,6 +1,7 @@
> >>  * Device tree bindings for Atmel Timer Counter Blocks
> >> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
> >> -  <chip> can be "at91rm9200" or "at91sam9x5"
> >> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
> >> +  "simple-mfd", "syscon".
> >> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> > 
> > atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> > are not allowed and the documentation should reflect that.
> 
> OK! I'll double check it.
> 
> > 
> > It would probably be easier to do that on top of the yaml conversion
> > here:
> > https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/
> 
> I don't see this integrated in next-20200110. Am I looking at the wrong branch?
> 

I had a few comments and I need to resend.

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb
@ 2020-01-10 14:32         ` Alexandre Belloni
  0 siblings, 0 replies; 108+ messages in thread
From: Alexandre Belloni @ 2020-01-10 14:32 UTC (permalink / raw)
  To: Claudiu.Beznea
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	Ludovic.Desroches, wg, linux-media, devicetree, Tudor.Ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, linux-spi,
	vkoul, broonie, knaack.h, dmaengine, Eugen.Hristev, jic23

On 10/01/2020 14:29:27+0000, Claudiu.Beznea@microchip.com wrote:
> 
> 
> On 10.01.2020 15:40, Alexandre Belloni wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 08/01/2020 14:55:10+0200, Claudiu Beznea wrote:
> >> Add microchip,<chip>-tcb to DT bindings documentation. This is for
> >> microchip,sam9x60-tcb.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> >> ---
> >>  Documentation/devicetree/bindings/mfd/atmel-tcb.txt | 5 +++--
> >>  1 file changed, 3 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> index c4a83e364cb6..e1713e41f6e0 100644
> >> --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> +++ b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> >> @@ -1,6 +1,7 @@
> >>  * Device tree bindings for Atmel Timer Counter Blocks
> >> -- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
> >> -  <chip> can be "at91rm9200" or "at91sam9x5"
> >> +- compatible: Should be "atmel,<chip>-tcb", "microchip,<chip>-tcb",
> >> +  "simple-mfd", "syscon".
> >> +  <chip> can be "at91rm9200", "at91sam9x5" or "sam9x60"
> > 
> > atmel,sam9x60-tcb, microchip,at91rm9200-tcb and microchip,at91sam9x5-tcb
> > are not allowed and the documentation should reflect that.
> 
> OK! I'll double check it.
> 
> > 
> > It would probably be easier to do that on top of the yaml conversion
> > here:
> > https://lore.kernel.org/lkml/20191009224006.5021-2-alexandre.belloni@bootlin.com/
> 
> I don't see this integrated in next-20200110. Am I looking at the wrong branch?
> 

I had a few comments and I need to resend.

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
  2020-01-10 14:30     ` Alexandre Belloni
                         ` (2 preceding siblings ...)
  (?)
@ 2020-01-10 15:02       ` Claudiu.Beznea
  -1 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 15:02 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, vkoul,
	Eugen.Hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, Tudor.Ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd, linux-can, netdev, linux-rtc



On 10.01.2020 16:30, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi,
> 
> On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
>> Add microchip,sam9x60-rtc to DT bindings documentation.
> 
> This will have to be rebased on top of
> https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

This is also not integrated in latest next. Will this postpone the
acceptance of the device tree, until the yaml conversion is accepted?

> 
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> index 5d3791e789c6..35eab9138d0b 100644
>> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> @@ -1,7 +1,8 @@
>>  Atmel AT91RM9200 Real Time Clock
>>
>>  Required properties:
>> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
>> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
>> +  "microchip,sam9x60-rtc"
>>  - reg: physical base address of the controller and length of memory mapped
>>    region.
>>  - interrupts: rtc alarm/event interrupt
>> --
>> 2.7.4
>>
> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
@ 2020-01-10 15:02       ` Claudiu.Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 15:02 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, vkoul,
	Eugen.Hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, Tudor.Ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd



On 10.01.2020 16:30, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi,
> 
> On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
>> Add microchip,sam9x60-rtc to DT bindings documentation.
> 
> This will have to be rebased on top of
> https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

This is also not integrated in latest next. Will this postpone the
acceptance of the device tree, until the yaml conversion is accepted?

> 
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> index 5d3791e789c6..35eab9138d0b 100644
>> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> @@ -1,7 +1,8 @@
>>  Atmel AT91RM9200 Real Time Clock
>>
>>  Required properties:
>> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
>> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
>> +  "microchip,sam9x60-rtc"
>>  - reg: physical base address of the controller and length of memory mapped
>>    region.
>>  - interrupts: rtc alarm/event interrupt
>> --
>> 2.7.4
>>
> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
@ 2020-01-10 15:02       ` Claudiu.Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 15:02 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, vkoul,
	Eugen.Hristev, jic23, knaack.h, lars, pmeerw, mchehab, lee.jones,
	richard.genoud, radu_nicolae.pirea, Tudor.Ambarus, miquel.raynal,
	richard, vigneshr, wg, mkl, a.zummo, broonie, devicetree,
	linux-arm-kernel, linux-kernel, dmaengine, linux-iio,
	linux-media, linux-spi, linux-mtd



On 10.01.2020 16:30, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi,
> 
> On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
>> Add microchip,sam9x60-rtc to DT bindings documentation.
> 
> This will have to be rebased on top of
> https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

This is also not integrated in latest next. Will this postpone the
acceptance of the device tree, until the yaml conversion is accepted?

> 
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> index 5d3791e789c6..35eab9138d0b 100644
>> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> @@ -1,7 +1,8 @@
>>  Atmel AT91RM9200 Real Time Clock
>>
>>  Required properties:
>> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
>> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
>> +  "microchip,sam9x60-rtc"
>>  - reg: physical base address of the controller and length of memory mapped
>>    region.
>>  - interrupts: rtc alarm/event interrupt
>> --
>> 2.7.4
>>
> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
@ 2020-01-10 15:02       ` Claudiu.Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 15:02 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	Ludovic.Desroches, wg, linux-media, devicetree, Tudor.Ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, Nicolas.Ferre,
	linux-spi, vkoul, broonie, knaack.h, dmaengine, Eugen.Hristev,
	jic23



On 10.01.2020 16:30, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi,
> 
> On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
>> Add microchip,sam9x60-rtc to DT bindings documentation.
> 
> This will have to be rebased on top of
> https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

This is also not integrated in latest next. Will this postpone the
acceptance of the device tree, until the yaml conversion is accepted?

> 
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> index 5d3791e789c6..35eab9138d0b 100644
>> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> @@ -1,7 +1,8 @@
>>  Atmel AT91RM9200 Real Time Clock
>>
>>  Required properties:
>> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
>> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
>> +  "microchip,sam9x60-rtc"
>>  - reg: physical base address of the controller and length of memory mapped
>>    region.
>>  - interrupts: rtc alarm/event interrupt
>> --
>> 2.7.4
>>
> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc
@ 2020-01-10 15:02       ` Claudiu.Beznea
  0 siblings, 0 replies; 108+ messages in thread
From: Claudiu.Beznea @ 2020-01-10 15:02 UTC (permalink / raw)
  To: alexandre.belloni
  Cc: mark.rutland, vigneshr, linux-iio, linux-kernel, linux-mtd,
	pmeerw, miquel.raynal, lee.jones, linux-rtc, lars, richard,
	Ludovic.Desroches, wg, linux-media, devicetree, Tudor.Ambarus,
	radu_nicolae.pirea, linux-can, robh+dt, mkl, mchehab,
	linux-arm-kernel, a.zummo, richard.genoud, netdev, linux-spi,
	vkoul, broonie, knaack.h, dmaengine, Eugen.Hristev, jic23



On 10.01.2020 16:30, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi,
> 
> On 08/01/2020 14:55:18+0200, Claudiu Beznea wrote:
>> Add microchip,sam9x60-rtc to DT bindings documentation.
> 
> This will have to be rebased on top of
> https://lore.kernel.org/linux-rtc/20191229204421.337612-2-alexandre.belloni@bootlin.com/

This is also not integrated in latest next. Will this postpone the
acceptance of the device tree, until the yaml conversion is accepted?

> 
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> index 5d3791e789c6..35eab9138d0b 100644
>> --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
>> @@ -1,7 +1,8 @@
>>  Atmel AT91RM9200 Real Time Clock
>>
>>  Required properties:
>> -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
>> +- compatible: should be: "atmel,at91rm9200-rtc", "atmel,at91sam9x5-rtc" or
>> +  "microchip,sam9x60-rtc"
>>  - reg: physical base address of the controller and length of memory mapped
>>    region.
>>  - interrupts: rtc alarm/event interrupt
>> --
>> 2.7.4
>>
> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
> 
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
  2020-01-08 12:55   ` Claudiu Beznea
  (?)
  (?)
@ 2020-01-10 16:37     ` Nicolas.Ferre
  -1 siblings, 0 replies; 108+ messages in thread
From: Nicolas.Ferre @ 2020-01-10 16:37 UTC (permalink / raw)
  To: miquel.raynal, knaack.h, pmeerw, Claudiu.Beznea, richard.genoud,
	radu_nicolae.pirea, mchehab, Tudor.Ambarus, lars,
	alexandre.belloni, vkoul, a.zummo, Ludovic.Desroches, wg,
	richard, mark.rutland, robh+dt, jic23, Eugen.Hristev, mkl,
	lee.jones, vigneshr, broonie
  Cc: dmaengine, linux-media, linux-spi, linux-iio, devicetree,
	linux-can, linux-kernel, linux-rtc, linux-arm-kernel, netdev,
	linux-mtd, Sandeep.Sheriker, Codrin.Ciubotariu

Le mercredi 08 janvier 2020 à 14:55 +0200, Claudiu Beznea a écrit :
> From: Sandeep Sheriker Mallikarjun <
> sandeepsheriker.mallikarjun@microchip.com>
> 
> Add device tree files for SAM9X60 SoC and SAM9X60-EK board.
> 
> Signed-off-by: Sandeep Sheriker Mallikarjun <
> sandeepsheriker.mallikarjun@microchip.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

> ---
>  arch/arm/boot/dts/Makefile           |   2 +
>  arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/sam9x60.dtsi       | 691
> +++++++++++++++++++++++++++++++++++
>  3 files changed, 1340 insertions(+)
>  create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
>  create mode 100644 arch/arm/boot/dts/sam9x60.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 08011dc8c7a6..36e90f07be13 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>  	at91sam9g35ek.dtb \
>  	at91sam9x25ek.dtb \
>  	at91sam9x35ek.dtb
> +dtb-$(CONFIG_SOC_SAM9X60) += \
> +	at91-sam9x60ek.dtb
>  dtb-$(CONFIG_SOC_SAM_V7) += \
>  	at91-kizbox2-2.dtb \
>  	at91-kizbox3-hs.dtb \
> diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-
> sam9x60ek.dts
> new file mode 100644
> index 000000000000..9f30132d7d7b
> --- /dev/null
> +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
> @@ -0,0 +1,647 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
> + *
> + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
> + */
> +/dts-v1/;
> +#include "sam9x60.dtsi"
> +
> +/ {
> +	model = "Microchip SAM9X60-EK";
> +	compatible = "microchip,sam9x60ek", "microchip,sam9x60",
> "atmel,at91sam9";
> +
> +	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		serial1 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	clocks {
> +		slow_xtal {
> +			clock-frequency = <32768>;
> +		};
> +
> +		main_xtal {
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	regulators: regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		vdd_1v8: fixed-regulator-vdd_1v8@0 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD_1V8";
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd_1v5: fixed-regulator-vdd_1v5@1 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD_1V5";
> +			regulator-min-microvolt = <1500000>;
> +			regulator-max-microvolt = <1500000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD1_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD2_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +	};
> +
> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_key_gpio_default>;
> +		status = "okay";
> +
> +		sw1 {
> +			label = "SW1";
> +			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
> +			linux,code=<0x104>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		status = "okay"; /* Conflict with pwm0. */
> +
> +		red {
> +			label = "red";
> +			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		green {
> +			label = "green";
> +			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		blue {
> +			label = "blue";
> +			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +};
> +
> +&adc {
> +	vddana-supply = <&vdd1_3v3>;
> +	vref-supply = <&vdd1_3v3>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
> +	status = "okay";
> +};
> +
> +&can0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_can0_rx_tx>;
> +	status = "disabled"; /* Conflict with dbgu. */
> +};
> +
> +&can1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_can1_rx_tx>;
> +	status = "okay";
> +};
> +
> +&classd {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_classd_default>;
> +	atmel,pwm-type = "diff";
> +	atmel,non-overlap-time = <10>;
> +	status = "okay";
> +};
> +
> +&dbgu {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_dbgu>;
> +	status = "okay"; /* Conflict with can0. */
> +};
> +
> +&ebi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
> +	status = "okay";
> +
> +	nand_controller: nand-controller {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs
> &pinctrl_nand_rb>;
> +		status = "okay";
> +
> +		nand@3 {
> +			reg = <0x3 0x0 0x800000>;
> +			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
> +			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
> +			nand-bus-width = <8>;
> +			nand-ecc-mode = "hw";
> +			nand-ecc-strength = <8>;
> +			nand-ecc-step-size = <512>;
> +			nand-on-flash-bbt;
> +			label = "atmel_nand";
> +
> +			partitions {
> +				compatible = "fixed-partitions";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				at91bootstrap@0 {
> +					label = "at91bootstrap";
> +					reg = <0x0 0x40000>;
> +				};
> +
> +				uboot@40000 {
> +					label = "u-boot";
> +					reg = <0x40000 0xc0000>;
> +				};
> +
> +				ubootenvred@100000 {
> +					label = "U-Boot Env Redundant";
> +					reg = <0x100000 0x40000>;
> +				};
> +
> +				ubootenv@140000 {
> +					label = "U-Boot Env";
> +					reg = <0x140000 0x40000>;
> +				};
> +
> +				dtb@180000 {
> +					label = "device tree";
> +					reg = <0x180000 0x80000>;
> +				};
> +
> +				kernel@200000 {
> +					label = "kernel";
> +					reg = <0x200000 0x600000>;
> +				};
> +
> +				rootfs@800000 {
> +					label = "rootfs";
> +					reg = <0x800000 0x1f800000>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&flx0 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +
> +	i2c0: i2c@600 {
> +		compatible = "microchip,sam9x60-i2c";
> +		reg = <0x600 0x200>;
> +		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx0_default>;
> +		atmel,fifo-size = <16>;
> +		i2c-analog-filter;
> +		i2c-digital-filter;
> +		i2c-digital-filter-width-ns = <35>;
> +		status = "okay";
> +
> +		eeprom@53 {
> +			compatible = "atmel,24c32";
> +			reg = <0x53>;
> +			pagesize = <16>;
> +			size = <128>;
> +			status = "okay";
> +		};
> +	};
> +};
> +
> +&flx4 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
> +	status = "disabled";
> +
> +	spi0: spi@400 {
> +		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +		reg = <0x400 0x200>;
> +		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +		clock-names = "spi_clk";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx4_default>;
> +		atmel,fifo-size = <16>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +};
> +
> +&flx5 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
> +	status = "okay";
> +
> +	uart1: serial@200 {
> +		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-
> usart";
> +		reg = <0x200 0x200>;
> +		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +		dmas = <&dma0
> +			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +			 AT91_XDMAC_DT_PERID(10))>,
> +		       <&dma0
> +			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +			 AT91_XDMAC_DT_PERID(11))>;
> +		dma-names = "tx", "rx";
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +		clock-names = "usart";
> +		pinctrl-0 = <&pinctrl_flx5_default>;
> +		pinctrl-names = "default";
> +		atmel,use-dma-rx;
> +		atmel,use-dma-tx;
> +		status = "okay";
> +	};
> +};
> +
> +&flx6 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +
> +	i2c1: i2c@600 {
> +		compatible = "microchip,sam9x60-i2c";
> +		reg = <0x600 0x200>;
> +		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx6_default>;
> +		atmel,fifo-size = <16>;
> +		i2c-analog-filter;
> +		i2c-digital-filter;
> +		i2c-digital-filter-width-ns = <35>;
> +		status = "okay";
> +
> +		gpio_exp: mcp23008@20 {
> +			compatible = "microchip,mcp23008";
> +			reg = <0x20>;
> +		};
> +	};
> +};
> +
> +&i2s {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2s_default>;
> +	#sound-dai-cells = <0>;
> +	status = "disabled"; /* Conflict with QSPI. */
> +};
> +
> +&macb0 {
> +	phy-mode = "rmii";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_macb0_rmii>;
> +	status = "okay";
> +
> +	ethernet-phy@0 {
> +		reg = <0x0>;
> +	};
> +};
> +
> +&pinctrl {
> +	atmel,mux-mask = <
> +			 /*	A	B	C	*/
> +			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
> +			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
> +			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
> +			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
> +			 >;
> +
> +	adc {
> +		pinctrl_adc_default: adc_default {
> +			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_adtrg_default: adtrg_default {
> +			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	dbgu {
> +		pinctrl_dbgu: dbgu-0 {
> +			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				      AT91_PIOA 10 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	i2s {
> +		pinctrl_i2s_default: i2s {
> +			atmel,pins =
> +				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SCK */
> +				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SWS */
> +				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SDIN */
> +				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SDOUT */
> +				 AT91_PIOB 23 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;		/* I2SMCK */
> +		};
> +	};
> +
> +	qspi {
> +		pinctrl_qspi: qspi {
> +			atmel,pins =
> +				<AT91_PIOB 19 AT91_PERIPH_A
> AT91_PINCTRL_SLEWRATE_DIS
> +				 AT91_PIOB 20 AT91_PERIPH_A
> AT91_PINCTRL_SLEWRATE_DIS
> +				 AT91_PIOB 21 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 22 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 23 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 24 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +	};
> +
> +	nand {
> +		pinctrl_nand_oe_we: nand-oe-we-0 {
> +			atmel,pins =
> +				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +
> +		pinctrl_nand_rb: nand-rb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 5 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_UP>;
> +		};
> +
> +		pinctrl_nand_cs: nand-cs-0 {
> +			atmel,pins =
> +				<AT91_PIOD 4 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	ebi {
> +		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +
> +		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 21 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_ebi_addr_nand: ebi-addr-0 {
> +			atmel,pins =
> +				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +	};
> +
> +	flexcom {
> +		pinctrl_flx0_default: flx0_twi {
> +			atmel,pins =
> +				<AT91_PIOA 0 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 1 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;
> +		};
> +
> +		pinctrl_flx4_default: flx4_spi {
> +			atmel,pins =
> +				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 14 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_flx5_default: flx_uart {
> +			atmel,pins =
> +				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
> +				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
> +				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
> +				 AT91_PIOA 22 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_flx6_default: flx6_twi {
> +			atmel,pins =
> +				<AT91_PIOA 30 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 31 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	classd {
> +		pinctrl_classd_default: classd {
> +			atmel,pins =
> +				<AT91_PIOA 24 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 25 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 26 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 27 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	can0 {
> +		pinctrl_can0_rx_tx: can0_rx_tx {
> +			atmel,pins =
> +				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANRX0 */
> +				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANTX0 */
> +				 AT91_PIOD 20 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
> +				 AT91_PIOD 21 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
> +		};
> +	};
> +
> +	can1 {
> +		pinctrl_can1_rx_tx: can1_rx_tx {
> +			atmel,pins =
> +				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANRX1 RXD1 */
> +				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANTX1 TXD1 */
> +				 AT91_PIOD 19 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
> +				 AT91_PIOD 21 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
> +		};
> +	};
> +
> +	macb0 {
> +		pinctrl_macb0_rmii: macb0_rmii-0 {
> +			atmel,pins =
> +				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB0 periph A */
> +				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB1 periph A */
> +				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB2 periph A */
> +				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB3 periph A */
> +				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB4 periph A */
> +				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB5 periph A */
> +				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB6 periph A */
> +				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB7 periph A */
> +				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB9 periph A */
> +				 AT91_PIOB 10 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;	/* PB10 periph A */
> +		};
> +	};
> +
> +	pwm0 {
> +		pinctrl_pwm0_0: pwm0_0 {
> +			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_1: pwm0_1 {
> +			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_2: pwm0_2 {
> +			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_3: pwm0_3 {
> +			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	sdmmc0 {
> +		pinctrl_sdmmc0_default: sdmmc0 {
> +			atmel,pins =
> +				<AT91_PIOA 17 AT91_PERIPH_A
> (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17
> CK  periph A with pullup */
> +				 AT91_PIOA 16 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD
> periph A with pullup */
> +				 AT91_PIOA 15 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0
> periph A */
> +				 AT91_PIOA 18 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1
> periph A with pullup */
> +				 AT91_PIOA 19 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2
> periph A with pullup */
> +				 AT91_PIOA 20 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3
> periph A with pullup */
> +		};
> +	};
> +
> +	gpio_keys {
> +		pinctrl_key_gpio_default: pinctrl_key_gpio {
> +			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +}; /* pinctrl */
> +
> +&pmc {
> +	atmel,osc-bypass;
> +};
> +
> +&pwm0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2
> &pinctrl_pwm0_3>;
> +	status = "disabled"; /* Conflict with leds. */
> +};
> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sdmmc0_default>;
> +	status = "okay";
> +	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +};
> +
> +&qspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_qspi>;
> +	status = "okay"; /* Conflict with i2s. */
> +
> +	flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <80000000>;
> +		m25p,fast-read;
> +
> +		at91bootstrap@0 {
> +			label = "qspi: at91bootstrap";
> +			reg = <0x0 0x40000>;
> +		};
> +
> +		bootloader@40000 {
> +			label = "qspi: bootloader";
> +			reg = <0x40000 0xc0000>;
> +		};
> +
> +		bootloaderenvred@100000 {
> +			label = "qspi: bootloader env redundant";
> +			reg = <0x100000 0x40000>;
> +		};
> +
> +		bootloaderenv@140000 {
> +			label = "qspi: bootloader env";
> +			reg = <0x140000 0x40000>;
> +		};
> +
> +		dtb@180000 {
> +			label = "qspi: device tree";
> +			reg = <0x180000 0x80000>;
> +		};
> +
> +		kernel@200000 {
> +			label = "qspi: kernel";
> +			reg = <0x200000 0x600000>;
> +		};
> +	};
> +};
> +
> +&shutdown_controller {
> +	atmel,shdwc-debouncer = <976>;
> +	status = "okay";
> +
> +	input@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +&tcb0 {
> +	timer0: timer@0 {
> +		compatible = "atmel,tcb-timer";
> +		reg = <0>;
> +	};
> +
> +	timer1: timer@1 {
> +		compatible = "atmel,tcb-timer";
> +		reg = <1>;
> +	};
> +};
> +
> +&usb1 {
> +	num-ports = <3>;
> +	atmel,vbus-gpio = <0
> +			   &pioD 15 GPIO_ACTIVE_HIGH
> +			   &pioD 16 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usb2 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
> new file mode 100644
> index 000000000000..2eb92a90453b
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x60.dtsi
> @@ -0,0 +1,691 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
> + *
> + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
> + */
> +
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Microchip SAM9X60 SoC";
> +	compatible = "microchip,sam9x60";
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +		tcb0 = &tcb0;
> +		tcb1 = &tcb1;
> +	};
> +
> +	cpus {
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x20000000 0x10000000>;
> +	};
> +
> +	clocks {
> +		slow_xtal: slow_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: main_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00300000 0x100000>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		usb1: ohci@600000 {
> +			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> +			reg = <0x00600000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc
> PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> +			clock-names = "ohci_clk", "hclk", "uhpck";
> +			status = "disabled";
> +		};
> +
> +		usb2: ehci@700000 {
> +			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> +			reg = <0x00700000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc
> PMC_TYPE_PERIPHERAL 22>;
> +			clock-names = "usb_clk", "ehci_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		ebi: ebi@10000000 {
> +			compatible = "microchip,sam9x60-ebi";
> +			#address-cells = <2>;
> +			#size-cells = <1>;
> +			atmel,smc = <&smc>;
> +			microchip,sfr = <&sfr>;
> +			reg = <0x10000000 0x60000000>;
> +			ranges = <0x0 0x0 0x10000000 0x10000000
> +				  0x1 0x0 0x20000000 0x10000000
> +				  0x2 0x0 0x30000000 0x10000000
> +				  0x3 0x0 0x40000000 0x10000000
> +				  0x4 0x0 0x50000000 0x10000000
> +				  0x5 0x0 0x60000000 0x10000000>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			status = "disabled";
> +
> +			nand_controller: nand-controller {
> +				compatible = "microchip,sam9x60-nand-
> controller";
> +				ecc-engine = <&pmecc>;
> +				#address-cells = <2>;
> +				#size-cells = <1>;
> +				ranges;
> +				status = "disabled";
> +			};
> +		};
> +
> +		sdmmc0: sdio-host@80000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc
> PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: sdio-host@90000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x90000000 0x300>;
> +			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc
> PMC_TYPE_GCK 26>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		apb {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			flx4: flexcom@f0000000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0000000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0000000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx5: flexcom@f0004000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0004000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0004000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			dma0: dma-controller@f0008000 {
> +				compatible = "microchip,sam9x60-dma",
> "atmel,sama5d4-dma";
> +				reg = <0xf0008000 0x1000>;
> +				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> +				#dma-cells = <1>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> +				clock-names = "dma_clk";
> +			};
> +
> +			ssc: ssc@f0010000 {
> +				compatible = "atmel,at91sam9g45-ssc";
> +				reg = <0xf0010000 0x4000>;
> +				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(38))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(39))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> +				clock-names = "pclk";
> +				status = "disabled";
> +			};
> +
> +			qspi: spi@f0014000 {
> +				compatible = "microchip,sam9x60-qspi";
> +				reg = <0xf0014000 0x100>, <0x70000000
> 0x10000000>;
> +				reg-names = "qspi_base", "qspi_mmap";
> +				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(26))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(27))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc
> PMC_TYPE_SYSTEM 19>;
> +				clock-names = "pclk", "qspick";
> +				atmel,pmc = <&pmc>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2s: i2s@f001c000 {
> +				compatible = "microchip,sam9x60-i2smcc";
> +				reg = <0xf001c000 0x100>;
> +				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(36))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(37))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc
> PMC_TYPE_GCK 34>;
> +				clock-names = "pclk", "gclk";
> +				status = "disabled";
> +			};
> +
> +			flx11: flexcom@f0020000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0020000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0020000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx12: flexcom@f0024000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0024000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0024000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			pit64b: timer@f0028000 {
> +				compatible = "microchip,sam9x60-pit64b";
> +				reg = <0xf0028000 0x100>;
> +				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc
> PMC_TYPE_GCK 37>;
> +				clock-names = "pclk", "gclk";
> +			};
> +
> +			sha: sha@f002c000 {
> +				compatible = "atmel,at91sam9g46-sha";
> +				reg = <0xf002c000 0x100>;
> +				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(34))>;
> +				dma-names = "tx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> +				clock-names = "sha_clk";
> +				status = "okay";
> +			};
> +
> +			trng: trng@f0030000 {
> +				compatible = "microchip,sam9x60-trng";
> +				reg = <0xf0030000 0x100>;
> +				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> +				status = "okay";
> +			};
> +
> +			aes: aes@f0034000 {
> +				compatible = "atmel,at91sam9g46-aes";
> +				reg = <0xf0034000 0x100>;
> +				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(32))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(33))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> +				clock-names = "aes_clk";
> +				status = "okay";
> +			};
> +
> +			tdes: tdes@f0038000 {
> +				compatible = "atmel,at91sam9g46-tdes";
> +				reg = <0xf0038000 0x100>;
> +				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(31))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(30))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
> +				clock-names = "tdes_clk";
> +				status = "okay";
> +			};
> +
> +			classd: classd@f003c000 {
> +				compatible = "atmel,sama5d2-classd";
> +				reg = <0xf003c000 0x100>;
> +				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(35))>;
> +				dma-names = "tx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc
> PMC_TYPE_GCK 42>;
> +				clock-names = "pclk", "gclk";
> +				status = "disabled";
> +			};
> +
> +			can0: can@f8000000 {
> +				compatible = "microchip,sam9x60-can",
> "atmel,at91sam9x5-can";
> +				reg = <0xf8000000 0x300>;
> +				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
> +				clock-names = "can_clk";
> +				status = "disabled";
> +			};
> +
> +			can1: can@f8004000 {
> +				compatible = "microchip,sam9x60-can",
> "atmel,at91sam9x5-can";
> +				reg = <0xf8004000 0x300>;
> +				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
> +				clock-names = "can_clk";
> +				status = "disabled";
> +			};
> +
> +			tcb0: timer@f8008000 {
> +				compatible = "microchip,sam9x60-tcb",
> "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0xf8008000 0x100>;
> +				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>,
> <&clk32k 0>;
> +				clock-names = "t0_clk", "slow_clk";
> +			};
> +
> +			tcb1: timer@f800c000 {
> +				compatible = "microchip,sam9x60-tcb",
> "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0xf800c000 0x100>;
> +				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>,
> <&clk32k 0>;
> +				clock-names = "t0_clk", "slow_clk";
> +			};
> +
> +			flx6: flexcom@f8010000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8010000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8010000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx7: flexcom@f8014000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8014000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8014000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx8: flexcom@f8018000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8018000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8018000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx0: flexcom@f801c000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf801c000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf801c000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx1: flexcom@f8020000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8020000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8020000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx2: flexcom@f8024000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8024000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8024000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx3: flexcom@f8028000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8028000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8028000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			macb0: ethernet@f802c000 {
> +				compatible = "cdns,sam9x60-macb", "cdns,macb";
> +				reg = <0xf802c000 0x1000>;
> +				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc
> PMC_TYPE_PERIPHERAL 24>;
> +				clock-names = "hclk", "pclk";
> +				status = "disabled";
> +			};
> +
> +			macb1: ethernet@f8030000 {
> +				compatible = "cdns,sam9x60-macb", "cdns,macb";
> +				reg = <0xf8030000 0x1000>;
> +				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc
> PMC_TYPE_PERIPHERAL 27>;
> +				clock-names = "hclk", "pclk";
> +				status = "disabled";
> +			};
> +
> +			pwm0: pwm@f8034000 {
> +				compatible = "microchip,sam9x60-pwm";
> +				reg = <0xf8034000 0x300>;
> +				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
> +				#pwm-cells = <3>;
> +				status="disabled";
> +			};
> +
> +			hlcdc: hlcdc@f8038000 {
> +				compatible = "microchip,sam9x60-hlcdc";
> +				reg = <0xf8038000 0x4000>;
> +				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc
> PMC_TYPE_GCK 25>, <&clk32k 1>;
> +				clock-names = "periph_clk","sys_clk",
> "slow_clk";
> +				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
> +				assigned-clock-parents = <&pmc PMC_TYPE_CORE
> PMC_MCK>;
> +				status = "disabled";
> +
> +				hlcdc-display-controller {
> +					compatible = "atmel,hlcdc-display-
> controller";
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						#address-cells = <1>;
> +						#size-cells = <0>;
> +						reg = <0>;
> +					};
> +				};
> +
> +				hlcdc_pwm: hlcdc-pwm {
> +					compatible = "atmel,hlcdc-pwm";
> +					#pwm-cells = <3>;
> +				};
> +			};
> +
> +			flx9: flexcom@f8040000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8040000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8040000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx10: flexcom@f8044000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8044000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8044000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			isi: isi@f8048000 {
> +				compatible = "microchip,sam9x60-isi",
> "atmel,at91sam9g45-isi";
> +				reg = <0xf8048000 0x100>;
> +				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
> +				clock-names = "isi_clk";
> +				status = "disabled";
> +				port {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +			};
> +
> +			adc: adc@f804c000 {
> +				compatible = "microchip,sam9x60-adc",
> "atmel,sama5d2-adc";
> +				reg = <0xf804c000 0x100>;
> +				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
> +				clock-names = "adc_clk";
> +				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
> +				dma-names = "rx";
> +				atmel,min-sample-rate-hz = <200000>;
> +				atmel,max-sample-rate-hz = <20000000>;
> +				atmel,startup-time-ms = <4>;
> +				atmel,trigger-edge-type =
> <IRQ_TYPE_EDGE_RISING>;
> +				#io-channel-cells = <1>;
> +				status = "disabled";
> +			};
> +
> +			sfr: sfr@f8050000 {
> +				compatible = "microchip,sam9x60-sfr",
> "syscon";
> +				reg = <0xf8050000 0x100>;
> +			};
> +
> +			matrix: matrix@ffffde00 {
> +				compatible = "microchip,sam9x60-matrix",
> "atmel,at91sam9x5-matrix", "syscon";
> +				reg = <0xffffde00 0x200>;
> +			};
> +
> +			pmecc: ecc-engine@ffffe000 {
> +				compatible = "microchip,sam9x60-pmecc",
> "atmel,at91sam9g45-pmecc";
> +				reg = <0xffffe000 0x300>,
> +				      <0xffffe600 0x100>;
> +			};
> +
> +			mpddrc: mpddrc@ffffe800 {
> +				compatible = "microchip,sam9x60-ddramc",
> "atmel,sama5d3-ddramc";
> +				reg = <0xffffe800 0x200>;
> +				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc
> PMC_TYPE_CORE PMC_MCK>;
> +				clock-names = "ddrck", "mpddr";
> +			};
> +
> +			smc: smc@ffffea00 {
> +				compatible = "microchip,sam9x60-smc",
> "atmel,at91sam9260-smc", "syscon";
> +				reg = <0xffffea00 0x100>;
> +			};
> +
> +			aic: interrupt-controller@fffff100 {
> +				compatible = "microchip,sam9x60-aic";
> +				#interrupt-cells = <3>;
> +				interrupt-controller;
> +				reg = <0xfffff100 0x100>;
> +				atmel,external-irqs = <31>;
> +			};
> +
> +			dbgu: serial@fffff200 {
> +				compatible = "atmel,at91sam9260-dbgu",
> "atmel,at91sam9260-usart";
> +				reg = <0xfffff200 0x200>;
> +				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(28))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(29))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
> +				clock-names = "usart";
> +				status = "disabled";
> +			};
> +
> +			pinctrl: pinctrl@fffff400 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				compatible = "microchip,sam9x60-pinctrl",
> "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
> +				ranges = <0xfffff400 0xfffff400 0x800>;
> +
> +				pioA: gpio@fffff400 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <2 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
> +				};
> +
> +				pioB: gpio@fffff600 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <3 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					#gpio-lines = <26>;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
> +				};
> +
> +				pioC: gpio@fffff800 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <4 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
> +				};
> +
> +				pioD: gpio@fffffa00 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffffa00 0x200>;
> +					interrupts = <44 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					#gpio-lines = <22>;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL
> 44>;
> +				};
> +			};
> +
> +			pmc: pmc@fffffc00 {
> +				compatible = "microchip,sam9x60-pmc",
> "syscon";
> +				reg = <0xfffffc00 0x200>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				#clock-cells = <2>;
> +				clocks = <&clk32k 1>, <&clk32k 0>,
> <&main_xtal>;
> +				clock-names = "td_slck", "md_slck",
> "main_xtal";
> +			};
> +
> +			reset_controller: rstc@fffffe00 {
> +				compatible = "microchip,sam9x60-rstc";
> +				reg = <0xfffffe00 0x10>;
> +				clocks = <&clk32k 0>;
> +			};
> +
> +			shutdown_controller: shdwc@fffffe10 {
> +				compatible = "microchip,sam9x60-shdwc";
> +				reg = <0xfffffe10 0x10>;
> +				clocks = <&clk32k 0>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				atmel,wakeup-rtc-timer;
> +				atmel,wakeup-rtt-timer;
> +				status = "disabled";
> +			};
> +
> +			pit: timer@fffffe40 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffe40 0x10>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			};
> +
> +			clk32k: sckc@fffffe50 {
> +				compatible = "microchip,sam9x60-sckc";
> +				reg = <0xfffffe50 0x4>;
> +				clocks = <&slow_xtal>;
> +				#clock-cells = <1>;
> +			};
> +
> +			gpbr: syscon@fffffe60 {
> +				compatible = "microchip,sam9x60-gpbr",
> "atmel,at91sam9260-gpbr", "syscon";
> +				reg = <0xfffffe60 0x10>;
> +			};
> +
> +			rtc: rtc@fffffea8 {
> +				compatible = "microchip,sam9x60-rtc",
> "atmel,at91sam9x5-rtc";
> +				reg = <0xfffffea8 0x100>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&clk32k 0>;
> +			};
> +		};
> +	};
> +};

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
@ 2020-01-10 16:37     ` Nicolas.Ferre
  0 siblings, 0 replies; 108+ messages in thread
From: Nicolas.Ferre @ 2020-01-10 16:37 UTC (permalink / raw)
  To: miquel.raynal, knaack.h, pmeerw, Claudiu.Beznea, richard.genoud,
	radu_nicolae.pirea, mchehab, Tudor.Ambarus, lars,
	alexandre.belloni, vkoul, a.zummo, Ludovic.Desroches, wg,
	richard, mark.rutland, robh+dt, jic23, Eugen.Hristev, mkl,
	lee.jones, vigneshr, broonie
  Cc: dmaengine, linux-media, linux-spi, linux-iio, devicetree,
	linux-can, linux-kernel, linux-rtc, linux-arm-kernel, netdev,
	linux-mtd, Sandeep.Sheriker, Codrin.Ciubotariu

Le mercredi 08 janvier 2020 à 14:55 +0200, Claudiu Beznea a écrit :
> From: Sandeep Sheriker Mallikarjun <
> sandeepsheriker.mallikarjun@microchip.com>
> 
> Add device tree files for SAM9X60 SoC and SAM9X60-EK board.
> 
> Signed-off-by: Sandeep Sheriker Mallikarjun <
> sandeepsheriker.mallikarjun@microchip.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

> ---
>  arch/arm/boot/dts/Makefile           |   2 +
>  arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/sam9x60.dtsi       | 691
> +++++++++++++++++++++++++++++++++++
>  3 files changed, 1340 insertions(+)
>  create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
>  create mode 100644 arch/arm/boot/dts/sam9x60.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 08011dc8c7a6..36e90f07be13 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>  	at91sam9g35ek.dtb \
>  	at91sam9x25ek.dtb \
>  	at91sam9x35ek.dtb
> +dtb-$(CONFIG_SOC_SAM9X60) += \
> +	at91-sam9x60ek.dtb
>  dtb-$(CONFIG_SOC_SAM_V7) += \
>  	at91-kizbox2-2.dtb \
>  	at91-kizbox3-hs.dtb \
> diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-
> sam9x60ek.dts
> new file mode 100644
> index 000000000000..9f30132d7d7b
> --- /dev/null
> +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
> @@ -0,0 +1,647 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
> + *
> + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
> + */
> +/dts-v1/;
> +#include "sam9x60.dtsi"
> +
> +/ {
> +	model = "Microchip SAM9X60-EK";
> +	compatible = "microchip,sam9x60ek", "microchip,sam9x60",
> "atmel,at91sam9";
> +
> +	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		serial1 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	clocks {
> +		slow_xtal {
> +			clock-frequency = <32768>;
> +		};
> +
> +		main_xtal {
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	regulators: regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		vdd_1v8: fixed-regulator-vdd_1v8@0 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD_1V8";
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd_1v5: fixed-regulator-vdd_1v5@1 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD_1V5";
> +			regulator-min-microvolt = <1500000>;
> +			regulator-max-microvolt = <1500000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD1_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD2_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +	};
> +
> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_key_gpio_default>;
> +		status = "okay";
> +
> +		sw1 {
> +			label = "SW1";
> +			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
> +			linux,code=<0x104>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		status = "okay"; /* Conflict with pwm0. */
> +
> +		red {
> +			label = "red";
> +			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		green {
> +			label = "green";
> +			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		blue {
> +			label = "blue";
> +			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +};
> +
> +&adc {
> +	vddana-supply = <&vdd1_3v3>;
> +	vref-supply = <&vdd1_3v3>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
> +	status = "okay";
> +};
> +
> +&can0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_can0_rx_tx>;
> +	status = "disabled"; /* Conflict with dbgu. */
> +};
> +
> +&can1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_can1_rx_tx>;
> +	status = "okay";
> +};
> +
> +&classd {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_classd_default>;
> +	atmel,pwm-type = "diff";
> +	atmel,non-overlap-time = <10>;
> +	status = "okay";
> +};
> +
> +&dbgu {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_dbgu>;
> +	status = "okay"; /* Conflict with can0. */
> +};
> +
> +&ebi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
> +	status = "okay";
> +
> +	nand_controller: nand-controller {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs
> &pinctrl_nand_rb>;
> +		status = "okay";
> +
> +		nand@3 {
> +			reg = <0x3 0x0 0x800000>;
> +			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
> +			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
> +			nand-bus-width = <8>;
> +			nand-ecc-mode = "hw";
> +			nand-ecc-strength = <8>;
> +			nand-ecc-step-size = <512>;
> +			nand-on-flash-bbt;
> +			label = "atmel_nand";
> +
> +			partitions {
> +				compatible = "fixed-partitions";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				at91bootstrap@0 {
> +					label = "at91bootstrap";
> +					reg = <0x0 0x40000>;
> +				};
> +
> +				uboot@40000 {
> +					label = "u-boot";
> +					reg = <0x40000 0xc0000>;
> +				};
> +
> +				ubootenvred@100000 {
> +					label = "U-Boot Env Redundant";
> +					reg = <0x100000 0x40000>;
> +				};
> +
> +				ubootenv@140000 {
> +					label = "U-Boot Env";
> +					reg = <0x140000 0x40000>;
> +				};
> +
> +				dtb@180000 {
> +					label = "device tree";
> +					reg = <0x180000 0x80000>;
> +				};
> +
> +				kernel@200000 {
> +					label = "kernel";
> +					reg = <0x200000 0x600000>;
> +				};
> +
> +				rootfs@800000 {
> +					label = "rootfs";
> +					reg = <0x800000 0x1f800000>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&flx0 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +
> +	i2c0: i2c@600 {
> +		compatible = "microchip,sam9x60-i2c";
> +		reg = <0x600 0x200>;
> +		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx0_default>;
> +		atmel,fifo-size = <16>;
> +		i2c-analog-filter;
> +		i2c-digital-filter;
> +		i2c-digital-filter-width-ns = <35>;
> +		status = "okay";
> +
> +		eeprom@53 {
> +			compatible = "atmel,24c32";
> +			reg = <0x53>;
> +			pagesize = <16>;
> +			size = <128>;
> +			status = "okay";
> +		};
> +	};
> +};
> +
> +&flx4 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
> +	status = "disabled";
> +
> +	spi0: spi@400 {
> +		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +		reg = <0x400 0x200>;
> +		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +		clock-names = "spi_clk";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx4_default>;
> +		atmel,fifo-size = <16>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +};
> +
> +&flx5 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
> +	status = "okay";
> +
> +	uart1: serial@200 {
> +		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-
> usart";
> +		reg = <0x200 0x200>;
> +		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +		dmas = <&dma0
> +			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +			 AT91_XDMAC_DT_PERID(10))>,
> +		       <&dma0
> +			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +			 AT91_XDMAC_DT_PERID(11))>;
> +		dma-names = "tx", "rx";
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +		clock-names = "usart";
> +		pinctrl-0 = <&pinctrl_flx5_default>;
> +		pinctrl-names = "default";
> +		atmel,use-dma-rx;
> +		atmel,use-dma-tx;
> +		status = "okay";
> +	};
> +};
> +
> +&flx6 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +
> +	i2c1: i2c@600 {
> +		compatible = "microchip,sam9x60-i2c";
> +		reg = <0x600 0x200>;
> +		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx6_default>;
> +		atmel,fifo-size = <16>;
> +		i2c-analog-filter;
> +		i2c-digital-filter;
> +		i2c-digital-filter-width-ns = <35>;
> +		status = "okay";
> +
> +		gpio_exp: mcp23008@20 {
> +			compatible = "microchip,mcp23008";
> +			reg = <0x20>;
> +		};
> +	};
> +};
> +
> +&i2s {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2s_default>;
> +	#sound-dai-cells = <0>;
> +	status = "disabled"; /* Conflict with QSPI. */
> +};
> +
> +&macb0 {
> +	phy-mode = "rmii";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_macb0_rmii>;
> +	status = "okay";
> +
> +	ethernet-phy@0 {
> +		reg = <0x0>;
> +	};
> +};
> +
> +&pinctrl {
> +	atmel,mux-mask = <
> +			 /*	A	B	C	*/
> +			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
> +			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
> +			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
> +			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
> +			 >;
> +
> +	adc {
> +		pinctrl_adc_default: adc_default {
> +			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_adtrg_default: adtrg_default {
> +			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	dbgu {
> +		pinctrl_dbgu: dbgu-0 {
> +			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				      AT91_PIOA 10 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	i2s {
> +		pinctrl_i2s_default: i2s {
> +			atmel,pins =
> +				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SCK */
> +				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SWS */
> +				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SDIN */
> +				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SDOUT */
> +				 AT91_PIOB 23 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;		/* I2SMCK */
> +		};
> +	};
> +
> +	qspi {
> +		pinctrl_qspi: qspi {
> +			atmel,pins =
> +				<AT91_PIOB 19 AT91_PERIPH_A
> AT91_PINCTRL_SLEWRATE_DIS
> +				 AT91_PIOB 20 AT91_PERIPH_A
> AT91_PINCTRL_SLEWRATE_DIS
> +				 AT91_PIOB 21 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 22 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 23 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 24 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +	};
> +
> +	nand {
> +		pinctrl_nand_oe_we: nand-oe-we-0 {
> +			atmel,pins =
> +				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +
> +		pinctrl_nand_rb: nand-rb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 5 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_UP>;
> +		};
> +
> +		pinctrl_nand_cs: nand-cs-0 {
> +			atmel,pins =
> +				<AT91_PIOD 4 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	ebi {
> +		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +
> +		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 21 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_ebi_addr_nand: ebi-addr-0 {
> +			atmel,pins =
> +				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +	};
> +
> +	flexcom {
> +		pinctrl_flx0_default: flx0_twi {
> +			atmel,pins =
> +				<AT91_PIOA 0 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 1 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;
> +		};
> +
> +		pinctrl_flx4_default: flx4_spi {
> +			atmel,pins =
> +				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 14 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_flx5_default: flx_uart {
> +			atmel,pins =
> +				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
> +				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
> +				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
> +				 AT91_PIOA 22 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_flx6_default: flx6_twi {
> +			atmel,pins =
> +				<AT91_PIOA 30 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 31 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	classd {
> +		pinctrl_classd_default: classd {
> +			atmel,pins =
> +				<AT91_PIOA 24 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 25 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 26 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 27 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	can0 {
> +		pinctrl_can0_rx_tx: can0_rx_tx {
> +			atmel,pins =
> +				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANRX0 */
> +				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANTX0 */
> +				 AT91_PIOD 20 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
> +				 AT91_PIOD 21 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
> +		};
> +	};
> +
> +	can1 {
> +		pinctrl_can1_rx_tx: can1_rx_tx {
> +			atmel,pins =
> +				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANRX1 RXD1 */
> +				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANTX1 TXD1 */
> +				 AT91_PIOD 19 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
> +				 AT91_PIOD 21 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
> +		};
> +	};
> +
> +	macb0 {
> +		pinctrl_macb0_rmii: macb0_rmii-0 {
> +			atmel,pins =
> +				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB0 periph A */
> +				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB1 periph A */
> +				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB2 periph A */
> +				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB3 periph A */
> +				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB4 periph A */
> +				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB5 periph A */
> +				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB6 periph A */
> +				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB7 periph A */
> +				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB9 periph A */
> +				 AT91_PIOB 10 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;	/* PB10 periph A */
> +		};
> +	};
> +
> +	pwm0 {
> +		pinctrl_pwm0_0: pwm0_0 {
> +			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_1: pwm0_1 {
> +			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_2: pwm0_2 {
> +			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_3: pwm0_3 {
> +			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	sdmmc0 {
> +		pinctrl_sdmmc0_default: sdmmc0 {
> +			atmel,pins =
> +				<AT91_PIOA 17 AT91_PERIPH_A
> (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17
> CK  periph A with pullup */
> +				 AT91_PIOA 16 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD
> periph A with pullup */
> +				 AT91_PIOA 15 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0
> periph A */
> +				 AT91_PIOA 18 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1
> periph A with pullup */
> +				 AT91_PIOA 19 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2
> periph A with pullup */
> +				 AT91_PIOA 20 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3
> periph A with pullup */
> +		};
> +	};
> +
> +	gpio_keys {
> +		pinctrl_key_gpio_default: pinctrl_key_gpio {
> +			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +}; /* pinctrl */
> +
> +&pmc {
> +	atmel,osc-bypass;
> +};
> +
> +&pwm0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2
> &pinctrl_pwm0_3>;
> +	status = "disabled"; /* Conflict with leds. */
> +};
> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sdmmc0_default>;
> +	status = "okay";
> +	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +};
> +
> +&qspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_qspi>;
> +	status = "okay"; /* Conflict with i2s. */
> +
> +	flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <80000000>;
> +		m25p,fast-read;
> +
> +		at91bootstrap@0 {
> +			label = "qspi: at91bootstrap";
> +			reg = <0x0 0x40000>;
> +		};
> +
> +		bootloader@40000 {
> +			label = "qspi: bootloader";
> +			reg = <0x40000 0xc0000>;
> +		};
> +
> +		bootloaderenvred@100000 {
> +			label = "qspi: bootloader env redundant";
> +			reg = <0x100000 0x40000>;
> +		};
> +
> +		bootloaderenv@140000 {
> +			label = "qspi: bootloader env";
> +			reg = <0x140000 0x40000>;
> +		};
> +
> +		dtb@180000 {
> +			label = "qspi: device tree";
> +			reg = <0x180000 0x80000>;
> +		};
> +
> +		kernel@200000 {
> +			label = "qspi: kernel";
> +			reg = <0x200000 0x600000>;
> +		};
> +	};
> +};
> +
> +&shutdown_controller {
> +	atmel,shdwc-debouncer = <976>;
> +	status = "okay";
> +
> +	input@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +&tcb0 {
> +	timer0: timer@0 {
> +		compatible = "atmel,tcb-timer";
> +		reg = <0>;
> +	};
> +
> +	timer1: timer@1 {
> +		compatible = "atmel,tcb-timer";
> +		reg = <1>;
> +	};
> +};
> +
> +&usb1 {
> +	num-ports = <3>;
> +	atmel,vbus-gpio = <0
> +			   &pioD 15 GPIO_ACTIVE_HIGH
> +			   &pioD 16 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usb2 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
> new file mode 100644
> index 000000000000..2eb92a90453b
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x60.dtsi
> @@ -0,0 +1,691 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
> + *
> + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
> + */
> +
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Microchip SAM9X60 SoC";
> +	compatible = "microchip,sam9x60";
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +		tcb0 = &tcb0;
> +		tcb1 = &tcb1;
> +	};
> +
> +	cpus {
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x20000000 0x10000000>;
> +	};
> +
> +	clocks {
> +		slow_xtal: slow_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: main_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00300000 0x100000>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		usb1: ohci@600000 {
> +			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> +			reg = <0x00600000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc
> PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> +			clock-names = "ohci_clk", "hclk", "uhpck";
> +			status = "disabled";
> +		};
> +
> +		usb2: ehci@700000 {
> +			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> +			reg = <0x00700000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc
> PMC_TYPE_PERIPHERAL 22>;
> +			clock-names = "usb_clk", "ehci_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		ebi: ebi@10000000 {
> +			compatible = "microchip,sam9x60-ebi";
> +			#address-cells = <2>;
> +			#size-cells = <1>;
> +			atmel,smc = <&smc>;
> +			microchip,sfr = <&sfr>;
> +			reg = <0x10000000 0x60000000>;
> +			ranges = <0x0 0x0 0x10000000 0x10000000
> +				  0x1 0x0 0x20000000 0x10000000
> +				  0x2 0x0 0x30000000 0x10000000
> +				  0x3 0x0 0x40000000 0x10000000
> +				  0x4 0x0 0x50000000 0x10000000
> +				  0x5 0x0 0x60000000 0x10000000>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			status = "disabled";
> +
> +			nand_controller: nand-controller {
> +				compatible = "microchip,sam9x60-nand-
> controller";
> +				ecc-engine = <&pmecc>;
> +				#address-cells = <2>;
> +				#size-cells = <1>;
> +				ranges;
> +				status = "disabled";
> +			};
> +		};
> +
> +		sdmmc0: sdio-host@80000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc
> PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: sdio-host@90000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x90000000 0x300>;
> +			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc
> PMC_TYPE_GCK 26>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		apb {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			flx4: flexcom@f0000000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0000000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0000000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx5: flexcom@f0004000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0004000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0004000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			dma0: dma-controller@f0008000 {
> +				compatible = "microchip,sam9x60-dma",
> "atmel,sama5d4-dma";
> +				reg = <0xf0008000 0x1000>;
> +				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> +				#dma-cells = <1>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> +				clock-names = "dma_clk";
> +			};
> +
> +			ssc: ssc@f0010000 {
> +				compatible = "atmel,at91sam9g45-ssc";
> +				reg = <0xf0010000 0x4000>;
> +				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(38))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(39))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> +				clock-names = "pclk";
> +				status = "disabled";
> +			};
> +
> +			qspi: spi@f0014000 {
> +				compatible = "microchip,sam9x60-qspi";
> +				reg = <0xf0014000 0x100>, <0x70000000
> 0x10000000>;
> +				reg-names = "qspi_base", "qspi_mmap";
> +				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(26))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(27))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc
> PMC_TYPE_SYSTEM 19>;
> +				clock-names = "pclk", "qspick";
> +				atmel,pmc = <&pmc>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2s: i2s@f001c000 {
> +				compatible = "microchip,sam9x60-i2smcc";
> +				reg = <0xf001c000 0x100>;
> +				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(36))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(37))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc
> PMC_TYPE_GCK 34>;
> +				clock-names = "pclk", "gclk";
> +				status = "disabled";
> +			};
> +
> +			flx11: flexcom@f0020000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0020000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0020000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx12: flexcom@f0024000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0024000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0024000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			pit64b: timer@f0028000 {
> +				compatible = "microchip,sam9x60-pit64b";
> +				reg = <0xf0028000 0x100>;
> +				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc
> PMC_TYPE_GCK 37>;
> +				clock-names = "pclk", "gclk";
> +			};
> +
> +			sha: sha@f002c000 {
> +				compatible = "atmel,at91sam9g46-sha";
> +				reg = <0xf002c000 0x100>;
> +				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(34))>;
> +				dma-names = "tx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> +				clock-names = "sha_clk";
> +				status = "okay";
> +			};
> +
> +			trng: trng@f0030000 {
> +				compatible = "microchip,sam9x60-trng";
> +				reg = <0xf0030000 0x100>;
> +				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> +				status = "okay";
> +			};
> +
> +			aes: aes@f0034000 {
> +				compatible = "atmel,at91sam9g46-aes";
> +				reg = <0xf0034000 0x100>;
> +				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(32))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(33))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> +				clock-names = "aes_clk";
> +				status = "okay";
> +			};
> +
> +			tdes: tdes@f0038000 {
> +				compatible = "atmel,at91sam9g46-tdes";
> +				reg = <0xf0038000 0x100>;
> +				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(31))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(30))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
> +				clock-names = "tdes_clk";
> +				status = "okay";
> +			};
> +
> +			classd: classd@f003c000 {
> +				compatible = "atmel,sama5d2-classd";
> +				reg = <0xf003c000 0x100>;
> +				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(35))>;
> +				dma-names = "tx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc
> PMC_TYPE_GCK 42>;
> +				clock-names = "pclk", "gclk";
> +				status = "disabled";
> +			};
> +
> +			can0: can@f8000000 {
> +				compatible = "microchip,sam9x60-can",
> "atmel,at91sam9x5-can";
> +				reg = <0xf8000000 0x300>;
> +				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
> +				clock-names = "can_clk";
> +				status = "disabled";
> +			};
> +
> +			can1: can@f8004000 {
> +				compatible = "microchip,sam9x60-can",
> "atmel,at91sam9x5-can";
> +				reg = <0xf8004000 0x300>;
> +				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
> +				clock-names = "can_clk";
> +				status = "disabled";
> +			};
> +
> +			tcb0: timer@f8008000 {
> +				compatible = "microchip,sam9x60-tcb",
> "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0xf8008000 0x100>;
> +				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>,
> <&clk32k 0>;
> +				clock-names = "t0_clk", "slow_clk";
> +			};
> +
> +			tcb1: timer@f800c000 {
> +				compatible = "microchip,sam9x60-tcb",
> "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0xf800c000 0x100>;
> +				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>,
> <&clk32k 0>;
> +				clock-names = "t0_clk", "slow_clk";
> +			};
> +
> +			flx6: flexcom@f8010000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8010000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8010000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx7: flexcom@f8014000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8014000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8014000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx8: flexcom@f8018000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8018000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8018000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx0: flexcom@f801c000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf801c000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf801c000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx1: flexcom@f8020000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8020000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8020000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx2: flexcom@f8024000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8024000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8024000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx3: flexcom@f8028000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8028000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8028000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			macb0: ethernet@f802c000 {
> +				compatible = "cdns,sam9x60-macb", "cdns,macb";
> +				reg = <0xf802c000 0x1000>;
> +				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc
> PMC_TYPE_PERIPHERAL 24>;
> +				clock-names = "hclk", "pclk";
> +				status = "disabled";
> +			};
> +
> +			macb1: ethernet@f8030000 {
> +				compatible = "cdns,sam9x60-macb", "cdns,macb";
> +				reg = <0xf8030000 0x1000>;
> +				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc
> PMC_TYPE_PERIPHERAL 27>;
> +				clock-names = "hclk", "pclk";
> +				status = "disabled";
> +			};
> +
> +			pwm0: pwm@f8034000 {
> +				compatible = "microchip,sam9x60-pwm";
> +				reg = <0xf8034000 0x300>;
> +				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
> +				#pwm-cells = <3>;
> +				status="disabled";
> +			};
> +
> +			hlcdc: hlcdc@f8038000 {
> +				compatible = "microchip,sam9x60-hlcdc";
> +				reg = <0xf8038000 0x4000>;
> +				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc
> PMC_TYPE_GCK 25>, <&clk32k 1>;
> +				clock-names = "periph_clk","sys_clk",
> "slow_clk";
> +				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
> +				assigned-clock-parents = <&pmc PMC_TYPE_CORE
> PMC_MCK>;
> +				status = "disabled";
> +
> +				hlcdc-display-controller {
> +					compatible = "atmel,hlcdc-display-
> controller";
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						#address-cells = <1>;
> +						#size-cells = <0>;
> +						reg = <0>;
> +					};
> +				};
> +
> +				hlcdc_pwm: hlcdc-pwm {
> +					compatible = "atmel,hlcdc-pwm";
> +					#pwm-cells = <3>;
> +				};
> +			};
> +
> +			flx9: flexcom@f8040000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8040000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8040000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx10: flexcom@f8044000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8044000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8044000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			isi: isi@f8048000 {
> +				compatible = "microchip,sam9x60-isi",
> "atmel,at91sam9g45-isi";
> +				reg = <0xf8048000 0x100>;
> +				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
> +				clock-names = "isi_clk";
> +				status = "disabled";
> +				port {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +			};
> +
> +			adc: adc@f804c000 {
> +				compatible = "microchip,sam9x60-adc",
> "atmel,sama5d2-adc";
> +				reg = <0xf804c000 0x100>;
> +				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
> +				clock-names = "adc_clk";
> +				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
> +				dma-names = "rx";
> +				atmel,min-sample-rate-hz = <200000>;
> +				atmel,max-sample-rate-hz = <20000000>;
> +				atmel,startup-time-ms = <4>;
> +				atmel,trigger-edge-type =
> <IRQ_TYPE_EDGE_RISING>;
> +				#io-channel-cells = <1>;
> +				status = "disabled";
> +			};
> +
> +			sfr: sfr@f8050000 {
> +				compatible = "microchip,sam9x60-sfr",
> "syscon";
> +				reg = <0xf8050000 0x100>;
> +			};
> +
> +			matrix: matrix@ffffde00 {
> +				compatible = "microchip,sam9x60-matrix",
> "atmel,at91sam9x5-matrix", "syscon";
> +				reg = <0xffffde00 0x200>;
> +			};
> +
> +			pmecc: ecc-engine@ffffe000 {
> +				compatible = "microchip,sam9x60-pmecc",
> "atmel,at91sam9g45-pmecc";
> +				reg = <0xffffe000 0x300>,
> +				      <0xffffe600 0x100>;
> +			};
> +
> +			mpddrc: mpddrc@ffffe800 {
> +				compatible = "microchip,sam9x60-ddramc",
> "atmel,sama5d3-ddramc";
> +				reg = <0xffffe800 0x200>;
> +				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc
> PMC_TYPE_CORE PMC_MCK>;
> +				clock-names = "ddrck", "mpddr";
> +			};
> +
> +			smc: smc@ffffea00 {
> +				compatible = "microchip,sam9x60-smc",
> "atmel,at91sam9260-smc", "syscon";
> +				reg = <0xffffea00 0x100>;
> +			};
> +
> +			aic: interrupt-controller@fffff100 {
> +				compatible = "microchip,sam9x60-aic";
> +				#interrupt-cells = <3>;
> +				interrupt-controller;
> +				reg = <0xfffff100 0x100>;
> +				atmel,external-irqs = <31>;
> +			};
> +
> +			dbgu: serial@fffff200 {
> +				compatible = "atmel,at91sam9260-dbgu",
> "atmel,at91sam9260-usart";
> +				reg = <0xfffff200 0x200>;
> +				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(28))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(29))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
> +				clock-names = "usart";
> +				status = "disabled";
> +			};
> +
> +			pinctrl: pinctrl@fffff400 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				compatible = "microchip,sam9x60-pinctrl",
> "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
> +				ranges = <0xfffff400 0xfffff400 0x800>;
> +
> +				pioA: gpio@fffff400 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <2 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
> +				};
> +
> +				pioB: gpio@fffff600 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <3 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					#gpio-lines = <26>;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
> +				};
> +
> +				pioC: gpio@fffff800 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <4 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
> +				};
> +
> +				pioD: gpio@fffffa00 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffffa00 0x200>;
> +					interrupts = <44 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					#gpio-lines = <22>;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL
> 44>;
> +				};
> +			};
> +
> +			pmc: pmc@fffffc00 {
> +				compatible = "microchip,sam9x60-pmc",
> "syscon";
> +				reg = <0xfffffc00 0x200>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				#clock-cells = <2>;
> +				clocks = <&clk32k 1>, <&clk32k 0>,
> <&main_xtal>;
> +				clock-names = "td_slck", "md_slck",
> "main_xtal";
> +			};
> +
> +			reset_controller: rstc@fffffe00 {
> +				compatible = "microchip,sam9x60-rstc";
> +				reg = <0xfffffe00 0x10>;
> +				clocks = <&clk32k 0>;
> +			};
> +
> +			shutdown_controller: shdwc@fffffe10 {
> +				compatible = "microchip,sam9x60-shdwc";
> +				reg = <0xfffffe10 0x10>;
> +				clocks = <&clk32k 0>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				atmel,wakeup-rtc-timer;
> +				atmel,wakeup-rtt-timer;
> +				status = "disabled";
> +			};
> +
> +			pit: timer@fffffe40 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffe40 0x10>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			};
> +
> +			clk32k: sckc@fffffe50 {
> +				compatible = "microchip,sam9x60-sckc";
> +				reg = <0xfffffe50 0x4>;
> +				clocks = <&slow_xtal>;
> +				#clock-cells = <1>;
> +			};
> +
> +			gpbr: syscon@fffffe60 {
> +				compatible = "microchip,sam9x60-gpbr",
> "atmel,at91sam9260-gpbr", "syscon";
> +				reg = <0xfffffe60 0x10>;
> +			};
> +
> +			rtc: rtc@fffffea8 {
> +				compatible = "microchip,sam9x60-rtc",
> "atmel,at91sam9x5-rtc";
> +				reg = <0xfffffea8 0x100>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&clk32k 0>;
> +			};
> +		};
> +	};
> +};

^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
@ 2020-01-10 16:37     ` Nicolas.Ferre
  0 siblings, 0 replies; 108+ messages in thread
From: Nicolas.Ferre @ 2020-01-10 16:37 UTC (permalink / raw)
  To: miquel.raynal, knaack.h, pmeerw, Claudiu.Beznea, richard.genoud,
	radu_nicolae.pirea, mchehab, Tudor.Ambarus, lars,
	alexandre.belloni, vkoul, a.zummo, Ludovic.Desroches, wg,
	richard, mark.rutland, robh+dt, jic23, Eugen.Hristev, mkl,
	lee.jones, vigneshr, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, Sandeep.Sheriker, linux-can,
	Codrin.Ciubotariu, linux-arm-kernel, linux-media

Le mercredi 08 janvier 2020 à 14:55 +0200, Claudiu Beznea a écrit :
> From: Sandeep Sheriker Mallikarjun <
> sandeepsheriker.mallikarjun@microchip.com>
> 
> Add device tree files for SAM9X60 SoC and SAM9X60-EK board.
> 
> Signed-off-by: Sandeep Sheriker Mallikarjun <
> sandeepsheriker.mallikarjun@microchip.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

> ---
>  arch/arm/boot/dts/Makefile           |   2 +
>  arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/sam9x60.dtsi       | 691
> +++++++++++++++++++++++++++++++++++
>  3 files changed, 1340 insertions(+)
>  create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
>  create mode 100644 arch/arm/boot/dts/sam9x60.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 08011dc8c7a6..36e90f07be13 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>  	at91sam9g35ek.dtb \
>  	at91sam9x25ek.dtb \
>  	at91sam9x35ek.dtb
> +dtb-$(CONFIG_SOC_SAM9X60) += \
> +	at91-sam9x60ek.dtb
>  dtb-$(CONFIG_SOC_SAM_V7) += \
>  	at91-kizbox2-2.dtb \
>  	at91-kizbox3-hs.dtb \
> diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-
> sam9x60ek.dts
> new file mode 100644
> index 000000000000..9f30132d7d7b
> --- /dev/null
> +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
> @@ -0,0 +1,647 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
> + *
> + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
> + */
> +/dts-v1/;
> +#include "sam9x60.dtsi"
> +
> +/ {
> +	model = "Microchip SAM9X60-EK";
> +	compatible = "microchip,sam9x60ek", "microchip,sam9x60",
> "atmel,at91sam9";
> +
> +	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		serial1 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	clocks {
> +		slow_xtal {
> +			clock-frequency = <32768>;
> +		};
> +
> +		main_xtal {
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	regulators: regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		vdd_1v8: fixed-regulator-vdd_1v8@0 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD_1V8";
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd_1v5: fixed-regulator-vdd_1v5@1 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD_1V5";
> +			regulator-min-microvolt = <1500000>;
> +			regulator-max-microvolt = <1500000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD1_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD2_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +	};
> +
> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_key_gpio_default>;
> +		status = "okay";
> +
> +		sw1 {
> +			label = "SW1";
> +			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
> +			linux,code=<0x104>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		status = "okay"; /* Conflict with pwm0. */
> +
> +		red {
> +			label = "red";
> +			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		green {
> +			label = "green";
> +			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		blue {
> +			label = "blue";
> +			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +};
> +
> +&adc {
> +	vddana-supply = <&vdd1_3v3>;
> +	vref-supply = <&vdd1_3v3>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
> +	status = "okay";
> +};
> +
> +&can0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_can0_rx_tx>;
> +	status = "disabled"; /* Conflict with dbgu. */
> +};
> +
> +&can1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_can1_rx_tx>;
> +	status = "okay";
> +};
> +
> +&classd {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_classd_default>;
> +	atmel,pwm-type = "diff";
> +	atmel,non-overlap-time = <10>;
> +	status = "okay";
> +};
> +
> +&dbgu {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_dbgu>;
> +	status = "okay"; /* Conflict with can0. */
> +};
> +
> +&ebi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
> +	status = "okay";
> +
> +	nand_controller: nand-controller {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs
> &pinctrl_nand_rb>;
> +		status = "okay";
> +
> +		nand@3 {
> +			reg = <0x3 0x0 0x800000>;
> +			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
> +			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
> +			nand-bus-width = <8>;
> +			nand-ecc-mode = "hw";
> +			nand-ecc-strength = <8>;
> +			nand-ecc-step-size = <512>;
> +			nand-on-flash-bbt;
> +			label = "atmel_nand";
> +
> +			partitions {
> +				compatible = "fixed-partitions";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				at91bootstrap@0 {
> +					label = "at91bootstrap";
> +					reg = <0x0 0x40000>;
> +				};
> +
> +				uboot@40000 {
> +					label = "u-boot";
> +					reg = <0x40000 0xc0000>;
> +				};
> +
> +				ubootenvred@100000 {
> +					label = "U-Boot Env Redundant";
> +					reg = <0x100000 0x40000>;
> +				};
> +
> +				ubootenv@140000 {
> +					label = "U-Boot Env";
> +					reg = <0x140000 0x40000>;
> +				};
> +
> +				dtb@180000 {
> +					label = "device tree";
> +					reg = <0x180000 0x80000>;
> +				};
> +
> +				kernel@200000 {
> +					label = "kernel";
> +					reg = <0x200000 0x600000>;
> +				};
> +
> +				rootfs@800000 {
> +					label = "rootfs";
> +					reg = <0x800000 0x1f800000>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&flx0 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +
> +	i2c0: i2c@600 {
> +		compatible = "microchip,sam9x60-i2c";
> +		reg = <0x600 0x200>;
> +		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx0_default>;
> +		atmel,fifo-size = <16>;
> +		i2c-analog-filter;
> +		i2c-digital-filter;
> +		i2c-digital-filter-width-ns = <35>;
> +		status = "okay";
> +
> +		eeprom@53 {
> +			compatible = "atmel,24c32";
> +			reg = <0x53>;
> +			pagesize = <16>;
> +			size = <128>;
> +			status = "okay";
> +		};
> +	};
> +};
> +
> +&flx4 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
> +	status = "disabled";
> +
> +	spi0: spi@400 {
> +		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +		reg = <0x400 0x200>;
> +		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +		clock-names = "spi_clk";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx4_default>;
> +		atmel,fifo-size = <16>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +};
> +
> +&flx5 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
> +	status = "okay";
> +
> +	uart1: serial@200 {
> +		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-
> usart";
> +		reg = <0x200 0x200>;
> +		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +		dmas = <&dma0
> +			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +			 AT91_XDMAC_DT_PERID(10))>,
> +		       <&dma0
> +			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +			 AT91_XDMAC_DT_PERID(11))>;
> +		dma-names = "tx", "rx";
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +		clock-names = "usart";
> +		pinctrl-0 = <&pinctrl_flx5_default>;
> +		pinctrl-names = "default";
> +		atmel,use-dma-rx;
> +		atmel,use-dma-tx;
> +		status = "okay";
> +	};
> +};
> +
> +&flx6 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +
> +	i2c1: i2c@600 {
> +		compatible = "microchip,sam9x60-i2c";
> +		reg = <0x600 0x200>;
> +		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx6_default>;
> +		atmel,fifo-size = <16>;
> +		i2c-analog-filter;
> +		i2c-digital-filter;
> +		i2c-digital-filter-width-ns = <35>;
> +		status = "okay";
> +
> +		gpio_exp: mcp23008@20 {
> +			compatible = "microchip,mcp23008";
> +			reg = <0x20>;
> +		};
> +	};
> +};
> +
> +&i2s {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2s_default>;
> +	#sound-dai-cells = <0>;
> +	status = "disabled"; /* Conflict with QSPI. */
> +};
> +
> +&macb0 {
> +	phy-mode = "rmii";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_macb0_rmii>;
> +	status = "okay";
> +
> +	ethernet-phy@0 {
> +		reg = <0x0>;
> +	};
> +};
> +
> +&pinctrl {
> +	atmel,mux-mask = <
> +			 /*	A	B	C	*/
> +			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
> +			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
> +			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
> +			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
> +			 >;
> +
> +	adc {
> +		pinctrl_adc_default: adc_default {
> +			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_adtrg_default: adtrg_default {
> +			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	dbgu {
> +		pinctrl_dbgu: dbgu-0 {
> +			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				      AT91_PIOA 10 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	i2s {
> +		pinctrl_i2s_default: i2s {
> +			atmel,pins =
> +				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SCK */
> +				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SWS */
> +				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SDIN */
> +				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SDOUT */
> +				 AT91_PIOB 23 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;		/* I2SMCK */
> +		};
> +	};
> +
> +	qspi {
> +		pinctrl_qspi: qspi {
> +			atmel,pins =
> +				<AT91_PIOB 19 AT91_PERIPH_A
> AT91_PINCTRL_SLEWRATE_DIS
> +				 AT91_PIOB 20 AT91_PERIPH_A
> AT91_PINCTRL_SLEWRATE_DIS
> +				 AT91_PIOB 21 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 22 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 23 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 24 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +	};
> +
> +	nand {
> +		pinctrl_nand_oe_we: nand-oe-we-0 {
> +			atmel,pins =
> +				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +
> +		pinctrl_nand_rb: nand-rb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 5 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_UP>;
> +		};
> +
> +		pinctrl_nand_cs: nand-cs-0 {
> +			atmel,pins =
> +				<AT91_PIOD 4 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	ebi {
> +		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +
> +		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 21 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_ebi_addr_nand: ebi-addr-0 {
> +			atmel,pins =
> +				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +	};
> +
> +	flexcom {
> +		pinctrl_flx0_default: flx0_twi {
> +			atmel,pins =
> +				<AT91_PIOA 0 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 1 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;
> +		};
> +
> +		pinctrl_flx4_default: flx4_spi {
> +			atmel,pins =
> +				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 14 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_flx5_default: flx_uart {
> +			atmel,pins =
> +				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
> +				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
> +				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
> +				 AT91_PIOA 22 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_flx6_default: flx6_twi {
> +			atmel,pins =
> +				<AT91_PIOA 30 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 31 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	classd {
> +		pinctrl_classd_default: classd {
> +			atmel,pins =
> +				<AT91_PIOA 24 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 25 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 26 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 27 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	can0 {
> +		pinctrl_can0_rx_tx: can0_rx_tx {
> +			atmel,pins =
> +				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANRX0 */
> +				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANTX0 */
> +				 AT91_PIOD 20 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
> +				 AT91_PIOD 21 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
> +		};
> +	};
> +
> +	can1 {
> +		pinctrl_can1_rx_tx: can1_rx_tx {
> +			atmel,pins =
> +				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANRX1 RXD1 */
> +				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANTX1 TXD1 */
> +				 AT91_PIOD 19 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
> +				 AT91_PIOD 21 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
> +		};
> +	};
> +
> +	macb0 {
> +		pinctrl_macb0_rmii: macb0_rmii-0 {
> +			atmel,pins =
> +				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB0 periph A */
> +				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB1 periph A */
> +				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB2 periph A */
> +				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB3 periph A */
> +				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB4 periph A */
> +				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB5 periph A */
> +				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB6 periph A */
> +				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB7 periph A */
> +				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB9 periph A */
> +				 AT91_PIOB 10 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;	/* PB10 periph A */
> +		};
> +	};
> +
> +	pwm0 {
> +		pinctrl_pwm0_0: pwm0_0 {
> +			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_1: pwm0_1 {
> +			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_2: pwm0_2 {
> +			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_3: pwm0_3 {
> +			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	sdmmc0 {
> +		pinctrl_sdmmc0_default: sdmmc0 {
> +			atmel,pins =
> +				<AT91_PIOA 17 AT91_PERIPH_A
> (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17
> CK  periph A with pullup */
> +				 AT91_PIOA 16 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD
> periph A with pullup */
> +				 AT91_PIOA 15 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0
> periph A */
> +				 AT91_PIOA 18 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1
> periph A with pullup */
> +				 AT91_PIOA 19 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2
> periph A with pullup */
> +				 AT91_PIOA 20 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3
> periph A with pullup */
> +		};
> +	};
> +
> +	gpio_keys {
> +		pinctrl_key_gpio_default: pinctrl_key_gpio {
> +			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +}; /* pinctrl */
> +
> +&pmc {
> +	atmel,osc-bypass;
> +};
> +
> +&pwm0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2
> &pinctrl_pwm0_3>;
> +	status = "disabled"; /* Conflict with leds. */
> +};
> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sdmmc0_default>;
> +	status = "okay";
> +	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +};
> +
> +&qspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_qspi>;
> +	status = "okay"; /* Conflict with i2s. */
> +
> +	flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <80000000>;
> +		m25p,fast-read;
> +
> +		at91bootstrap@0 {
> +			label = "qspi: at91bootstrap";
> +			reg = <0x0 0x40000>;
> +		};
> +
> +		bootloader@40000 {
> +			label = "qspi: bootloader";
> +			reg = <0x40000 0xc0000>;
> +		};
> +
> +		bootloaderenvred@100000 {
> +			label = "qspi: bootloader env redundant";
> +			reg = <0x100000 0x40000>;
> +		};
> +
> +		bootloaderenv@140000 {
> +			label = "qspi: bootloader env";
> +			reg = <0x140000 0x40000>;
> +		};
> +
> +		dtb@180000 {
> +			label = "qspi: device tree";
> +			reg = <0x180000 0x80000>;
> +		};
> +
> +		kernel@200000 {
> +			label = "qspi: kernel";
> +			reg = <0x200000 0x600000>;
> +		};
> +	};
> +};
> +
> +&shutdown_controller {
> +	atmel,shdwc-debouncer = <976>;
> +	status = "okay";
> +
> +	input@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +&tcb0 {
> +	timer0: timer@0 {
> +		compatible = "atmel,tcb-timer";
> +		reg = <0>;
> +	};
> +
> +	timer1: timer@1 {
> +		compatible = "atmel,tcb-timer";
> +		reg = <1>;
> +	};
> +};
> +
> +&usb1 {
> +	num-ports = <3>;
> +	atmel,vbus-gpio = <0
> +			   &pioD 15 GPIO_ACTIVE_HIGH
> +			   &pioD 16 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usb2 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
> new file mode 100644
> index 000000000000..2eb92a90453b
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x60.dtsi
> @@ -0,0 +1,691 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
> + *
> + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
> + */
> +
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Microchip SAM9X60 SoC";
> +	compatible = "microchip,sam9x60";
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +		tcb0 = &tcb0;
> +		tcb1 = &tcb1;
> +	};
> +
> +	cpus {
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x20000000 0x10000000>;
> +	};
> +
> +	clocks {
> +		slow_xtal: slow_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: main_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00300000 0x100000>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		usb1: ohci@600000 {
> +			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> +			reg = <0x00600000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc
> PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> +			clock-names = "ohci_clk", "hclk", "uhpck";
> +			status = "disabled";
> +		};
> +
> +		usb2: ehci@700000 {
> +			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> +			reg = <0x00700000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc
> PMC_TYPE_PERIPHERAL 22>;
> +			clock-names = "usb_clk", "ehci_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		ebi: ebi@10000000 {
> +			compatible = "microchip,sam9x60-ebi";
> +			#address-cells = <2>;
> +			#size-cells = <1>;
> +			atmel,smc = <&smc>;
> +			microchip,sfr = <&sfr>;
> +			reg = <0x10000000 0x60000000>;
> +			ranges = <0x0 0x0 0x10000000 0x10000000
> +				  0x1 0x0 0x20000000 0x10000000
> +				  0x2 0x0 0x30000000 0x10000000
> +				  0x3 0x0 0x40000000 0x10000000
> +				  0x4 0x0 0x50000000 0x10000000
> +				  0x5 0x0 0x60000000 0x10000000>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			status = "disabled";
> +
> +			nand_controller: nand-controller {
> +				compatible = "microchip,sam9x60-nand-
> controller";
> +				ecc-engine = <&pmecc>;
> +				#address-cells = <2>;
> +				#size-cells = <1>;
> +				ranges;
> +				status = "disabled";
> +			};
> +		};
> +
> +		sdmmc0: sdio-host@80000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc
> PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: sdio-host@90000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x90000000 0x300>;
> +			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc
> PMC_TYPE_GCK 26>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		apb {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			flx4: flexcom@f0000000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0000000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0000000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx5: flexcom@f0004000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0004000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0004000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			dma0: dma-controller@f0008000 {
> +				compatible = "microchip,sam9x60-dma",
> "atmel,sama5d4-dma";
> +				reg = <0xf0008000 0x1000>;
> +				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> +				#dma-cells = <1>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> +				clock-names = "dma_clk";
> +			};
> +
> +			ssc: ssc@f0010000 {
> +				compatible = "atmel,at91sam9g45-ssc";
> +				reg = <0xf0010000 0x4000>;
> +				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(38))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(39))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> +				clock-names = "pclk";
> +				status = "disabled";
> +			};
> +
> +			qspi: spi@f0014000 {
> +				compatible = "microchip,sam9x60-qspi";
> +				reg = <0xf0014000 0x100>, <0x70000000
> 0x10000000>;
> +				reg-names = "qspi_base", "qspi_mmap";
> +				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(26))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(27))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc
> PMC_TYPE_SYSTEM 19>;
> +				clock-names = "pclk", "qspick";
> +				atmel,pmc = <&pmc>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2s: i2s@f001c000 {
> +				compatible = "microchip,sam9x60-i2smcc";
> +				reg = <0xf001c000 0x100>;
> +				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(36))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(37))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc
> PMC_TYPE_GCK 34>;
> +				clock-names = "pclk", "gclk";
> +				status = "disabled";
> +			};
> +
> +			flx11: flexcom@f0020000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0020000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0020000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx12: flexcom@f0024000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0024000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0024000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			pit64b: timer@f0028000 {
> +				compatible = "microchip,sam9x60-pit64b";
> +				reg = <0xf0028000 0x100>;
> +				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc
> PMC_TYPE_GCK 37>;
> +				clock-names = "pclk", "gclk";
> +			};
> +
> +			sha: sha@f002c000 {
> +				compatible = "atmel,at91sam9g46-sha";
> +				reg = <0xf002c000 0x100>;
> +				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(34))>;
> +				dma-names = "tx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> +				clock-names = "sha_clk";
> +				status = "okay";
> +			};
> +
> +			trng: trng@f0030000 {
> +				compatible = "microchip,sam9x60-trng";
> +				reg = <0xf0030000 0x100>;
> +				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> +				status = "okay";
> +			};
> +
> +			aes: aes@f0034000 {
> +				compatible = "atmel,at91sam9g46-aes";
> +				reg = <0xf0034000 0x100>;
> +				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(32))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(33))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> +				clock-names = "aes_clk";
> +				status = "okay";
> +			};
> +
> +			tdes: tdes@f0038000 {
> +				compatible = "atmel,at91sam9g46-tdes";
> +				reg = <0xf0038000 0x100>;
> +				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(31))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(30))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
> +				clock-names = "tdes_clk";
> +				status = "okay";
> +			};
> +
> +			classd: classd@f003c000 {
> +				compatible = "atmel,sama5d2-classd";
> +				reg = <0xf003c000 0x100>;
> +				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(35))>;
> +				dma-names = "tx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc
> PMC_TYPE_GCK 42>;
> +				clock-names = "pclk", "gclk";
> +				status = "disabled";
> +			};
> +
> +			can0: can@f8000000 {
> +				compatible = "microchip,sam9x60-can",
> "atmel,at91sam9x5-can";
> +				reg = <0xf8000000 0x300>;
> +				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
> +				clock-names = "can_clk";
> +				status = "disabled";
> +			};
> +
> +			can1: can@f8004000 {
> +				compatible = "microchip,sam9x60-can",
> "atmel,at91sam9x5-can";
> +				reg = <0xf8004000 0x300>;
> +				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
> +				clock-names = "can_clk";
> +				status = "disabled";
> +			};
> +
> +			tcb0: timer@f8008000 {
> +				compatible = "microchip,sam9x60-tcb",
> "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0xf8008000 0x100>;
> +				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>,
> <&clk32k 0>;
> +				clock-names = "t0_clk", "slow_clk";
> +			};
> +
> +			tcb1: timer@f800c000 {
> +				compatible = "microchip,sam9x60-tcb",
> "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0xf800c000 0x100>;
> +				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>,
> <&clk32k 0>;
> +				clock-names = "t0_clk", "slow_clk";
> +			};
> +
> +			flx6: flexcom@f8010000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8010000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8010000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx7: flexcom@f8014000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8014000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8014000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx8: flexcom@f8018000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8018000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8018000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx0: flexcom@f801c000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf801c000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf801c000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx1: flexcom@f8020000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8020000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8020000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx2: flexcom@f8024000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8024000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8024000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx3: flexcom@f8028000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8028000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8028000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			macb0: ethernet@f802c000 {
> +				compatible = "cdns,sam9x60-macb", "cdns,macb";
> +				reg = <0xf802c000 0x1000>;
> +				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc
> PMC_TYPE_PERIPHERAL 24>;
> +				clock-names = "hclk", "pclk";
> +				status = "disabled";
> +			};
> +
> +			macb1: ethernet@f8030000 {
> +				compatible = "cdns,sam9x60-macb", "cdns,macb";
> +				reg = <0xf8030000 0x1000>;
> +				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc
> PMC_TYPE_PERIPHERAL 27>;
> +				clock-names = "hclk", "pclk";
> +				status = "disabled";
> +			};
> +
> +			pwm0: pwm@f8034000 {
> +				compatible = "microchip,sam9x60-pwm";
> +				reg = <0xf8034000 0x300>;
> +				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
> +				#pwm-cells = <3>;
> +				status="disabled";
> +			};
> +
> +			hlcdc: hlcdc@f8038000 {
> +				compatible = "microchip,sam9x60-hlcdc";
> +				reg = <0xf8038000 0x4000>;
> +				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc
> PMC_TYPE_GCK 25>, <&clk32k 1>;
> +				clock-names = "periph_clk","sys_clk",
> "slow_clk";
> +				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
> +				assigned-clock-parents = <&pmc PMC_TYPE_CORE
> PMC_MCK>;
> +				status = "disabled";
> +
> +				hlcdc-display-controller {
> +					compatible = "atmel,hlcdc-display-
> controller";
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						#address-cells = <1>;
> +						#size-cells = <0>;
> +						reg = <0>;
> +					};
> +				};
> +
> +				hlcdc_pwm: hlcdc-pwm {
> +					compatible = "atmel,hlcdc-pwm";
> +					#pwm-cells = <3>;
> +				};
> +			};
> +
> +			flx9: flexcom@f8040000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8040000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8040000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx10: flexcom@f8044000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8044000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8044000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			isi: isi@f8048000 {
> +				compatible = "microchip,sam9x60-isi",
> "atmel,at91sam9g45-isi";
> +				reg = <0xf8048000 0x100>;
> +				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
> +				clock-names = "isi_clk";
> +				status = "disabled";
> +				port {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +			};
> +
> +			adc: adc@f804c000 {
> +				compatible = "microchip,sam9x60-adc",
> "atmel,sama5d2-adc";
> +				reg = <0xf804c000 0x100>;
> +				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
> +				clock-names = "adc_clk";
> +				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
> +				dma-names = "rx";
> +				atmel,min-sample-rate-hz = <200000>;
> +				atmel,max-sample-rate-hz = <20000000>;
> +				atmel,startup-time-ms = <4>;
> +				atmel,trigger-edge-type =
> <IRQ_TYPE_EDGE_RISING>;
> +				#io-channel-cells = <1>;
> +				status = "disabled";
> +			};
> +
> +			sfr: sfr@f8050000 {
> +				compatible = "microchip,sam9x60-sfr",
> "syscon";
> +				reg = <0xf8050000 0x100>;
> +			};
> +
> +			matrix: matrix@ffffde00 {
> +				compatible = "microchip,sam9x60-matrix",
> "atmel,at91sam9x5-matrix", "syscon";
> +				reg = <0xffffde00 0x200>;
> +			};
> +
> +			pmecc: ecc-engine@ffffe000 {
> +				compatible = "microchip,sam9x60-pmecc",
> "atmel,at91sam9g45-pmecc";
> +				reg = <0xffffe000 0x300>,
> +				      <0xffffe600 0x100>;
> +			};
> +
> +			mpddrc: mpddrc@ffffe800 {
> +				compatible = "microchip,sam9x60-ddramc",
> "atmel,sama5d3-ddramc";
> +				reg = <0xffffe800 0x200>;
> +				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc
> PMC_TYPE_CORE PMC_MCK>;
> +				clock-names = "ddrck", "mpddr";
> +			};
> +
> +			smc: smc@ffffea00 {
> +				compatible = "microchip,sam9x60-smc",
> "atmel,at91sam9260-smc", "syscon";
> +				reg = <0xffffea00 0x100>;
> +			};
> +
> +			aic: interrupt-controller@fffff100 {
> +				compatible = "microchip,sam9x60-aic";
> +				#interrupt-cells = <3>;
> +				interrupt-controller;
> +				reg = <0xfffff100 0x100>;
> +				atmel,external-irqs = <31>;
> +			};
> +
> +			dbgu: serial@fffff200 {
> +				compatible = "atmel,at91sam9260-dbgu",
> "atmel,at91sam9260-usart";
> +				reg = <0xfffff200 0x200>;
> +				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(28))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(29))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
> +				clock-names = "usart";
> +				status = "disabled";
> +			};
> +
> +			pinctrl: pinctrl@fffff400 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				compatible = "microchip,sam9x60-pinctrl",
> "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
> +				ranges = <0xfffff400 0xfffff400 0x800>;
> +
> +				pioA: gpio@fffff400 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <2 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
> +				};
> +
> +				pioB: gpio@fffff600 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <3 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					#gpio-lines = <26>;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
> +				};
> +
> +				pioC: gpio@fffff800 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <4 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
> +				};
> +
> +				pioD: gpio@fffffa00 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffffa00 0x200>;
> +					interrupts = <44 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					#gpio-lines = <22>;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL
> 44>;
> +				};
> +			};
> +
> +			pmc: pmc@fffffc00 {
> +				compatible = "microchip,sam9x60-pmc",
> "syscon";
> +				reg = <0xfffffc00 0x200>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				#clock-cells = <2>;
> +				clocks = <&clk32k 1>, <&clk32k 0>,
> <&main_xtal>;
> +				clock-names = "td_slck", "md_slck",
> "main_xtal";
> +			};
> +
> +			reset_controller: rstc@fffffe00 {
> +				compatible = "microchip,sam9x60-rstc";
> +				reg = <0xfffffe00 0x10>;
> +				clocks = <&clk32k 0>;
> +			};
> +
> +			shutdown_controller: shdwc@fffffe10 {
> +				compatible = "microchip,sam9x60-shdwc";
> +				reg = <0xfffffe10 0x10>;
> +				clocks = <&clk32k 0>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				atmel,wakeup-rtc-timer;
> +				atmel,wakeup-rtt-timer;
> +				status = "disabled";
> +			};
> +
> +			pit: timer@fffffe40 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffe40 0x10>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			};
> +
> +			clk32k: sckc@fffffe50 {
> +				compatible = "microchip,sam9x60-sckc";
> +				reg = <0xfffffe50 0x4>;
> +				clocks = <&slow_xtal>;
> +				#clock-cells = <1>;
> +			};
> +
> +			gpbr: syscon@fffffe60 {
> +				compatible = "microchip,sam9x60-gpbr",
> "atmel,at91sam9260-gpbr", "syscon";
> +				reg = <0xfffffe60 0x10>;
> +			};
> +
> +			rtc: rtc@fffffea8 {
> +				compatible = "microchip,sam9x60-rtc",
> "atmel,at91sam9x5-rtc";
> +				reg = <0xfffffea8 0x100>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&clk32k 0>;
> +			};
> +		};
> +	};
> +};
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^ permalink raw reply	[flat|nested] 108+ messages in thread

* Re: [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board
@ 2020-01-10 16:37     ` Nicolas.Ferre
  0 siblings, 0 replies; 108+ messages in thread
From: Nicolas.Ferre @ 2020-01-10 16:37 UTC (permalink / raw)
  To: miquel.raynal, knaack.h, pmeerw, Claudiu.Beznea, richard.genoud,
	radu_nicolae.pirea, mchehab, Tudor.Ambarus, lars,
	alexandre.belloni, vkoul, a.zummo, Ludovic.Desroches, wg,
	richard, mark.rutland, robh+dt, jic23, Eugen.Hristev, mkl,
	lee.jones, vigneshr, broonie
  Cc: linux-rtc, devicetree, linux-iio, netdev, linux-kernel,
	linux-spi, linux-mtd, dmaengine, Sandeep.Sheriker, linux-can,
	Codrin.Ciubotariu, linux-arm-kernel, linux-media

Le mercredi 08 janvier 2020 à 14:55 +0200, Claudiu Beznea a écrit :
> From: Sandeep Sheriker Mallikarjun <
> sandeepsheriker.mallikarjun@microchip.com>
> 
> Add device tree files for SAM9X60 SoC and SAM9X60-EK board.
> 
> Signed-off-by: Sandeep Sheriker Mallikarjun <
> sandeepsheriker.mallikarjun@microchip.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

> ---
>  arch/arm/boot/dts/Makefile           |   2 +
>  arch/arm/boot/dts/at91-sam9x60ek.dts | 647 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/sam9x60.dtsi       | 691
> +++++++++++++++++++++++++++++++++++
>  3 files changed, 1340 insertions(+)
>  create mode 100644 arch/arm/boot/dts/at91-sam9x60ek.dts
>  create mode 100644 arch/arm/boot/dts/sam9x60.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 08011dc8c7a6..36e90f07be13 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -44,6 +44,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>  	at91sam9g35ek.dtb \
>  	at91sam9x25ek.dtb \
>  	at91sam9x35ek.dtb
> +dtb-$(CONFIG_SOC_SAM9X60) += \
> +	at91-sam9x60ek.dtb
>  dtb-$(CONFIG_SOC_SAM_V7) += \
>  	at91-kizbox2-2.dtb \
>  	at91-kizbox3-hs.dtb \
> diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-
> sam9x60ek.dts
> new file mode 100644
> index 000000000000..9f30132d7d7b
> --- /dev/null
> +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
> @@ -0,0 +1,647 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
> + *
> + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
> + */
> +/dts-v1/;
> +#include "sam9x60.dtsi"
> +
> +/ {
> +	model = "Microchip SAM9X60-EK";
> +	compatible = "microchip,sam9x60ek", "microchip,sam9x60",
> "atmel,at91sam9";
> +
> +	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		serial1 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	clocks {
> +		slow_xtal {
> +			clock-frequency = <32768>;
> +		};
> +
> +		main_xtal {
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	regulators: regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		vdd_1v8: fixed-regulator-vdd_1v8@0 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD_1V8";
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd_1v5: fixed-regulator-vdd_1v5@1 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD_1V5";
> +			regulator-min-microvolt = <1500000>;
> +			regulator-max-microvolt = <1500000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD1_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +
> +		vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "VDD2_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +			status = "okay";
> +		};
> +	};
> +
> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_key_gpio_default>;
> +		status = "okay";
> +
> +		sw1 {
> +			label = "SW1";
> +			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
> +			linux,code=<0x104>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		status = "okay"; /* Conflict with pwm0. */
> +
> +		red {
> +			label = "red";
> +			gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		green {
> +			label = "green";
> +			gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		blue {
> +			label = "blue";
> +			gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +};
> +
> +&adc {
> +	vddana-supply = <&vdd1_3v3>;
> +	vref-supply = <&vdd1_3v3>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
> +	status = "okay";
> +};
> +
> +&can0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_can0_rx_tx>;
> +	status = "disabled"; /* Conflict with dbgu. */
> +};
> +
> +&can1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_can1_rx_tx>;
> +	status = "okay";
> +};
> +
> +&classd {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_classd_default>;
> +	atmel,pwm-type = "diff";
> +	atmel,non-overlap-time = <10>;
> +	status = "okay";
> +};
> +
> +&dbgu {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_dbgu>;
> +	status = "okay"; /* Conflict with can0. */
> +};
> +
> +&ebi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
> +	status = "okay";
> +
> +	nand_controller: nand-controller {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs
> &pinctrl_nand_rb>;
> +		status = "okay";
> +
> +		nand@3 {
> +			reg = <0x3 0x0 0x800000>;
> +			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
> +			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
> +			nand-bus-width = <8>;
> +			nand-ecc-mode = "hw";
> +			nand-ecc-strength = <8>;
> +			nand-ecc-step-size = <512>;
> +			nand-on-flash-bbt;
> +			label = "atmel_nand";
> +
> +			partitions {
> +				compatible = "fixed-partitions";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				at91bootstrap@0 {
> +					label = "at91bootstrap";
> +					reg = <0x0 0x40000>;
> +				};
> +
> +				uboot@40000 {
> +					label = "u-boot";
> +					reg = <0x40000 0xc0000>;
> +				};
> +
> +				ubootenvred@100000 {
> +					label = "U-Boot Env Redundant";
> +					reg = <0x100000 0x40000>;
> +				};
> +
> +				ubootenv@140000 {
> +					label = "U-Boot Env";
> +					reg = <0x140000 0x40000>;
> +				};
> +
> +				dtb@180000 {
> +					label = "device tree";
> +					reg = <0x180000 0x80000>;
> +				};
> +
> +				kernel@200000 {
> +					label = "kernel";
> +					reg = <0x200000 0x600000>;
> +				};
> +
> +				rootfs@800000 {
> +					label = "rootfs";
> +					reg = <0x800000 0x1f800000>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&flx0 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +
> +	i2c0: i2c@600 {
> +		compatible = "microchip,sam9x60-i2c";
> +		reg = <0x600 0x200>;
> +		interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx0_default>;
> +		atmel,fifo-size = <16>;
> +		i2c-analog-filter;
> +		i2c-digital-filter;
> +		i2c-digital-filter-width-ns = <35>;
> +		status = "okay";
> +
> +		eeprom@53 {
> +			compatible = "atmel,24c32";
> +			reg = <0x53>;
> +			pagesize = <16>;
> +			size = <128>;
> +			status = "okay";
> +		};
> +	};
> +};
> +
> +&flx4 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
> +	status = "disabled";
> +
> +	spi0: spi@400 {
> +		compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +		reg = <0x400 0x200>;
> +		interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +		clock-names = "spi_clk";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx4_default>;
> +		atmel,fifo-size = <16>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +};
> +
> +&flx5 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
> +	status = "okay";
> +
> +	uart1: serial@200 {
> +		compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-
> usart";
> +		reg = <0x200 0x200>;
> +		interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +		dmas = <&dma0
> +			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +			 AT91_XDMAC_DT_PERID(10))>,
> +		       <&dma0
> +			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +			 AT91_XDMAC_DT_PERID(11))>;
> +		dma-names = "tx", "rx";
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +		clock-names = "usart";
> +		pinctrl-0 = <&pinctrl_flx5_default>;
> +		pinctrl-names = "default";
> +		atmel,use-dma-rx;
> +		atmel,use-dma-tx;
> +		status = "okay";
> +	};
> +};
> +
> +&flx6 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +
> +	i2c1: i2c@600 {
> +		compatible = "microchip,sam9x60-i2c";
> +		reg = <0x600 0x200>;
> +		interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_flx6_default>;
> +		atmel,fifo-size = <16>;
> +		i2c-analog-filter;
> +		i2c-digital-filter;
> +		i2c-digital-filter-width-ns = <35>;
> +		status = "okay";
> +
> +		gpio_exp: mcp23008@20 {
> +			compatible = "microchip,mcp23008";
> +			reg = <0x20>;
> +		};
> +	};
> +};
> +
> +&i2s {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2s_default>;
> +	#sound-dai-cells = <0>;
> +	status = "disabled"; /* Conflict with QSPI. */
> +};
> +
> +&macb0 {
> +	phy-mode = "rmii";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_macb0_rmii>;
> +	status = "okay";
> +
> +	ethernet-phy@0 {
> +		reg = <0x0>;
> +	};
> +};
> +
> +&pinctrl {
> +	atmel,mux-mask = <
> +			 /*	A	B	C	*/
> +			 0xFFFFFE7F 0xC0E0397F 0xEF00019D	/* pioA */
> +			 0x03FFFFFF 0x02FC7E68 0x00780000	/* pioB */
> +			 0xffffffff 0xF83FFFFF 0xB800F3FC	/* pioC */
> +			 0x003FFFFF 0x003F8000 0x00000000	/* pioD */
> +			 >;
> +
> +	adc {
> +		pinctrl_adc_default: adc_default {
> +			atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_adtrg_default: adtrg_default {
> +			atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	dbgu {
> +		pinctrl_dbgu: dbgu-0 {
> +			atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				      AT91_PIOA 10 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	i2s {
> +		pinctrl_i2s_default: i2s {
> +			atmel,pins =
> +				<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SCK */
> +				 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SWS */
> +				 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SDIN */
> +				 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE	
> 	/* I2SDOUT */
> +				 AT91_PIOB 23 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;		/* I2SMCK */
> +		};
> +	};
> +
> +	qspi {
> +		pinctrl_qspi: qspi {
> +			atmel,pins =
> +				<AT91_PIOB 19 AT91_PERIPH_A
> AT91_PINCTRL_SLEWRATE_DIS
> +				 AT91_PIOB 20 AT91_PERIPH_A
> AT91_PINCTRL_SLEWRATE_DIS
> +				 AT91_PIOB 21 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 22 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 23 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOB 24 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +	};
> +
> +	nand {
> +		pinctrl_nand_oe_we: nand-oe-we-0 {
> +			atmel,pins =
> +				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +
> +		pinctrl_nand_rb: nand-rb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 5 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_UP>;
> +		};
> +
> +		pinctrl_nand_cs: nand-cs-0 {
> +			atmel,pins =
> +				<AT91_PIOD 4 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	ebi {
> +		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +
> +		pinctrl_ebi_data_0_15: ebi-data-msb-0 {
> +			atmel,pins =
> +				<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOD 21 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_ebi_addr_nand: ebi-addr-0 {
> +			atmel,pins =
> +				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)
> +				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE
> | AT91_PINCTRL_SLEWRATE_DIS)>;
> +		};
> +	};
> +
> +	flexcom {
> +		pinctrl_flx0_default: flx0_twi {
> +			atmel,pins =
> +				<AT91_PIOA 0 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 1 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;
> +		};
> +
> +		pinctrl_flx4_default: flx4_spi {
> +			atmel,pins =
> +				<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
> +				 AT91_PIOA 14 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_flx5_default: flx_uart {
> +			atmel,pins =
> +				<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
> +				 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
> +				 AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
> +				 AT91_PIOA 22 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_flx6_default: flx6_twi {
> +			atmel,pins =
> +				<AT91_PIOA 30 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 31 AT91_PERIPH_A
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	classd {
> +		pinctrl_classd_default: classd {
> +			atmel,pins =
> +				<AT91_PIOA 24 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 25 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 26 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 27 AT91_PERIPH_C
> AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	can0 {
> +		pinctrl_can0_rx_tx: can0_rx_tx {
> +			atmel,pins =
> +				<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANRX0 */
> +				 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANTX0 */
> +				 AT91_PIOD 20 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN	/* Enable CAN0 mux */
> +				 AT91_PIOD 21 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
> +		};
> +	};
> +
> +	can1 {
> +		pinctrl_can1_rx_tx: can1_rx_tx {
> +			atmel,pins =
> +				<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANRX1 RXD1 */
> +				 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE	
> /* CANTX1 TXD1 */
> +				 AT91_PIOD 19 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN	/* Enable CAN1 mux */
> +				 AT91_PIOD 21 AT91_PERIPH_GPIO
> AT91_PINCTRL_PULL_DOWN>;	/* Enable CAN Transceivers */
> +		};
> +	};
> +
> +	macb0 {
> +		pinctrl_macb0_rmii: macb0_rmii-0 {
> +			atmel,pins =
> +				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB0 periph A */
> +				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB1 periph A */
> +				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB2 periph A */
> +				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB3 periph A */
> +				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB4 periph A */
> +				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB5 periph A */
> +				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB6 periph A */
> +				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB7 periph A */
> +				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	
> /* PB9 periph A */
> +				 AT91_PIOB 10 AT91_PERIPH_A
> AT91_PINCTRL_NONE>;	/* PB10 periph A */
> +		};
> +	};
> +
> +	pwm0 {
> +		pinctrl_pwm0_0: pwm0_0 {
> +			atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_1: pwm0_1 {
> +			atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_2: pwm0_2 {
> +			atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +
> +		pinctrl_pwm0_3: pwm0_3 {
> +			atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	sdmmc0 {
> +		pinctrl_sdmmc0_default: sdmmc0 {
> +			atmel,pins =
> +				<AT91_PIOA 17 AT91_PERIPH_A
> (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA17
> CK  periph A with pullup */
> +				 AT91_PIOA 16 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA16 CMD
> periph A with pullup */
> +				 AT91_PIOA 15 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA15 DAT0
> periph A */
> +				 AT91_PIOA 18 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA18 DAT1
> periph A with pullup */
> +				 AT91_PIOA 19 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA19 DAT2
> periph A with pullup */
> +				 AT91_PIOA 20 AT91_PERIPH_A
> (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA20 DAT3
> periph A with pullup */
> +		};
> +	};
> +
> +	gpio_keys {
> +		pinctrl_key_gpio_default: pinctrl_key_gpio {
> +			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO
> AT91_PINCTRL_NONE>;
> +		};
> +	};
> +}; /* pinctrl */
> +
> +&pmc {
> +	atmel,osc-bypass;
> +};
> +
> +&pwm0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2
> &pinctrl_pwm0_3>;
> +	status = "disabled"; /* Conflict with leds. */
> +};
> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sdmmc0_default>;
> +	status = "okay";
> +	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +};
> +
> +&qspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_qspi>;
> +	status = "okay"; /* Conflict with i2s. */
> +
> +	flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <80000000>;
> +		m25p,fast-read;
> +
> +		at91bootstrap@0 {
> +			label = "qspi: at91bootstrap";
> +			reg = <0x0 0x40000>;
> +		};
> +
> +		bootloader@40000 {
> +			label = "qspi: bootloader";
> +			reg = <0x40000 0xc0000>;
> +		};
> +
> +		bootloaderenvred@100000 {
> +			label = "qspi: bootloader env redundant";
> +			reg = <0x100000 0x40000>;
> +		};
> +
> +		bootloaderenv@140000 {
> +			label = "qspi: bootloader env";
> +			reg = <0x140000 0x40000>;
> +		};
> +
> +		dtb@180000 {
> +			label = "qspi: device tree";
> +			reg = <0x180000 0x80000>;
> +		};
> +
> +		kernel@200000 {
> +			label = "qspi: kernel";
> +			reg = <0x200000 0x600000>;
> +		};
> +	};
> +};
> +
> +&shutdown_controller {
> +	atmel,shdwc-debouncer = <976>;
> +	status = "okay";
> +
> +	input@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +&tcb0 {
> +	timer0: timer@0 {
> +		compatible = "atmel,tcb-timer";
> +		reg = <0>;
> +	};
> +
> +	timer1: timer@1 {
> +		compatible = "atmel,tcb-timer";
> +		reg = <1>;
> +	};
> +};
> +
> +&usb1 {
> +	num-ports = <3>;
> +	atmel,vbus-gpio = <0
> +			   &pioD 15 GPIO_ACTIVE_HIGH
> +			   &pioD 16 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usb2 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
> new file mode 100644
> index 000000000000..2eb92a90453b
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x60.dtsi
> @@ -0,0 +1,691 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
> + *
> + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
> + */
> +
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Microchip SAM9X60 SoC";
> +	compatible = "microchip,sam9x60";
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +		tcb0 = &tcb0;
> +		tcb1 = &tcb1;
> +	};
> +
> +	cpus {
> +		#address-cells = <0>;
> +		#size-cells = <0>;
> +
> +		cpu {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x20000000 0x10000000>;
> +	};
> +
> +	clocks {
> +		slow_xtal: slow_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: main_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00300000 0x100000>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		usb1: ohci@600000 {
> +			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> +			reg = <0x00600000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc
> PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> +			clock-names = "ohci_clk", "hclk", "uhpck";
> +			status = "disabled";
> +		};
> +
> +		usb2: ehci@700000 {
> +			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> +			reg = <0x00700000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc
> PMC_TYPE_PERIPHERAL 22>;
> +			clock-names = "usb_clk", "ehci_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		ebi: ebi@10000000 {
> +			compatible = "microchip,sam9x60-ebi";
> +			#address-cells = <2>;
> +			#size-cells = <1>;
> +			atmel,smc = <&smc>;
> +			microchip,sfr = <&sfr>;
> +			reg = <0x10000000 0x60000000>;
> +			ranges = <0x0 0x0 0x10000000 0x10000000
> +				  0x1 0x0 0x20000000 0x10000000
> +				  0x2 0x0 0x30000000 0x10000000
> +				  0x3 0x0 0x40000000 0x10000000
> +				  0x4 0x0 0x50000000 0x10000000
> +				  0x5 0x0 0x60000000 0x10000000>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			status = "disabled";
> +
> +			nand_controller: nand-controller {
> +				compatible = "microchip,sam9x60-nand-
> controller";
> +				ecc-engine = <&pmecc>;
> +				#address-cells = <2>;
> +				#size-cells = <1>;
> +				ranges;
> +				status = "disabled";
> +			};
> +		};
> +
> +		sdmmc0: sdio-host@80000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc
> PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: sdio-host@90000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x90000000 0x300>;
> +			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc
> PMC_TYPE_GCK 26>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		apb {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			flx4: flexcom@f0000000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0000000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0000000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx5: flexcom@f0004000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0004000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0004000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			dma0: dma-controller@f0008000 {
> +				compatible = "microchip,sam9x60-dma",
> "atmel,sama5d4-dma";
> +				reg = <0xf0008000 0x1000>;
> +				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> +				#dma-cells = <1>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> +				clock-names = "dma_clk";
> +			};
> +
> +			ssc: ssc@f0010000 {
> +				compatible = "atmel,at91sam9g45-ssc";
> +				reg = <0xf0010000 0x4000>;
> +				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(38))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(39))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> +				clock-names = "pclk";
> +				status = "disabled";
> +			};
> +
> +			qspi: spi@f0014000 {
> +				compatible = "microchip,sam9x60-qspi";
> +				reg = <0xf0014000 0x100>, <0x70000000
> 0x10000000>;
> +				reg-names = "qspi_base", "qspi_mmap";
> +				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(26))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(27))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc
> PMC_TYPE_SYSTEM 19>;
> +				clock-names = "pclk", "qspick";
> +				atmel,pmc = <&pmc>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2s: i2s@f001c000 {
> +				compatible = "microchip,sam9x60-i2smcc";
> +				reg = <0xf001c000 0x100>;
> +				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(36))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(37))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc
> PMC_TYPE_GCK 34>;
> +				clock-names = "pclk", "gclk";
> +				status = "disabled";
> +			};
> +
> +			flx11: flexcom@f0020000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0020000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0020000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx12: flexcom@f0024000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf0024000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf0024000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			pit64b: timer@f0028000 {
> +				compatible = "microchip,sam9x60-pit64b";
> +				reg = <0xf0028000 0x100>;
> +				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc
> PMC_TYPE_GCK 37>;
> +				clock-names = "pclk", "gclk";
> +			};
> +
> +			sha: sha@f002c000 {
> +				compatible = "atmel,at91sam9g46-sha";
> +				reg = <0xf002c000 0x100>;
> +				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(34))>;
> +				dma-names = "tx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> +				clock-names = "sha_clk";
> +				status = "okay";
> +			};
> +
> +			trng: trng@f0030000 {
> +				compatible = "microchip,sam9x60-trng";
> +				reg = <0xf0030000 0x100>;
> +				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> +				status = "okay";
> +			};
> +
> +			aes: aes@f0034000 {
> +				compatible = "atmel,at91sam9g46-aes";
> +				reg = <0xf0034000 0x100>;
> +				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(32))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(33))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> +				clock-names = "aes_clk";
> +				status = "okay";
> +			};
> +
> +			tdes: tdes@f0038000 {
> +				compatible = "atmel,at91sam9g46-tdes";
> +				reg = <0xf0038000 0x100>;
> +				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(31))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(30))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
> +				clock-names = "tdes_clk";
> +				status = "okay";
> +			};
> +
> +			classd: classd@f003c000 {
> +				compatible = "atmel,sama5d2-classd";
> +				reg = <0xf003c000 0x100>;
> +				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(35))>;
> +				dma-names = "tx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc
> PMC_TYPE_GCK 42>;
> +				clock-names = "pclk", "gclk";
> +				status = "disabled";
> +			};
> +
> +			can0: can@f8000000 {
> +				compatible = "microchip,sam9x60-can",
> "atmel,at91sam9x5-can";
> +				reg = <0xf8000000 0x300>;
> +				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
> +				clock-names = "can_clk";
> +				status = "disabled";
> +			};
> +
> +			can1: can@f8004000 {
> +				compatible = "microchip,sam9x60-can",
> "atmel,at91sam9x5-can";
> +				reg = <0xf8004000 0x300>;
> +				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
> +				clock-names = "can_clk";
> +				status = "disabled";
> +			};
> +
> +			tcb0: timer@f8008000 {
> +				compatible = "microchip,sam9x60-tcb",
> "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0xf8008000 0x100>;
> +				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>,
> <&clk32k 0>;
> +				clock-names = "t0_clk", "slow_clk";
> +			};
> +
> +			tcb1: timer@f800c000 {
> +				compatible = "microchip,sam9x60-tcb",
> "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0xf800c000 0x100>;
> +				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>,
> <&clk32k 0>;
> +				clock-names = "t0_clk", "slow_clk";
> +			};
> +
> +			flx6: flexcom@f8010000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8010000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8010000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx7: flexcom@f8014000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8014000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8014000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx8: flexcom@f8018000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8018000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8018000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx0: flexcom@f801c000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf801c000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf801c000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx1: flexcom@f8020000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8020000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8020000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx2: flexcom@f8024000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8024000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8024000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx3: flexcom@f8028000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8028000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8028000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			macb0: ethernet@f802c000 {
> +				compatible = "cdns,sam9x60-macb", "cdns,macb";
> +				reg = <0xf802c000 0x1000>;
> +				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc
> PMC_TYPE_PERIPHERAL 24>;
> +				clock-names = "hclk", "pclk";
> +				status = "disabled";
> +			};
> +
> +			macb1: ethernet@f8030000 {
> +				compatible = "cdns,sam9x60-macb", "cdns,macb";
> +				reg = <0xf8030000 0x1000>;
> +				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc
> PMC_TYPE_PERIPHERAL 27>;
> +				clock-names = "hclk", "pclk";
> +				status = "disabled";
> +			};
> +
> +			pwm0: pwm@f8034000 {
> +				compatible = "microchip,sam9x60-pwm";
> +				reg = <0xf8034000 0x300>;
> +				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
> +				#pwm-cells = <3>;
> +				status="disabled";
> +			};
> +
> +			hlcdc: hlcdc@f8038000 {
> +				compatible = "microchip,sam9x60-hlcdc";
> +				reg = <0xf8038000 0x4000>;
> +				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc
> PMC_TYPE_GCK 25>, <&clk32k 1>;
> +				clock-names = "periph_clk","sys_clk",
> "slow_clk";
> +				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
> +				assigned-clock-parents = <&pmc PMC_TYPE_CORE
> PMC_MCK>;
> +				status = "disabled";
> +
> +				hlcdc-display-controller {
> +					compatible = "atmel,hlcdc-display-
> controller";
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						#address-cells = <1>;
> +						#size-cells = <0>;
> +						reg = <0>;
> +					};
> +				};
> +
> +				hlcdc_pwm: hlcdc-pwm {
> +					compatible = "atmel,hlcdc-pwm";
> +					#pwm-cells = <3>;
> +				};
> +			};
> +
> +			flx9: flexcom@f8040000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8040000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8040000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			flx10: flexcom@f8044000 {
> +				compatible = "atmel,sama5d2-flexcom";
> +				reg = <0xf8044000 0x200>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0x0 0xf8044000 0x800>;
> +				status = "disabled";
> +			};
> +
> +			isi: isi@f8048000 {
> +				compatible = "microchip,sam9x60-isi",
> "atmel,at91sam9g45-isi";
> +				reg = <0xf8048000 0x100>;
> +				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
> +				clock-names = "isi_clk";
> +				status = "disabled";
> +				port {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +			};
> +
> +			adc: adc@f804c000 {
> +				compatible = "microchip,sam9x60-adc",
> "atmel,sama5d2-adc";
> +				reg = <0xf804c000 0x100>;
> +				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
> +				clock-names = "adc_clk";
> +				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
> +				dma-names = "rx";
> +				atmel,min-sample-rate-hz = <200000>;
> +				atmel,max-sample-rate-hz = <20000000>;
> +				atmel,startup-time-ms = <4>;
> +				atmel,trigger-edge-type =
> <IRQ_TYPE_EDGE_RISING>;
> +				#io-channel-cells = <1>;
> +				status = "disabled";
> +			};
> +
> +			sfr: sfr@f8050000 {
> +				compatible = "microchip,sam9x60-sfr",
> "syscon";
> +				reg = <0xf8050000 0x100>;
> +			};
> +
> +			matrix: matrix@ffffde00 {
> +				compatible = "microchip,sam9x60-matrix",
> "atmel,at91sam9x5-matrix", "syscon";
> +				reg = <0xffffde00 0x200>;
> +			};
> +
> +			pmecc: ecc-engine@ffffe000 {
> +				compatible = "microchip,sam9x60-pmecc",
> "atmel,at91sam9g45-pmecc";
> +				reg = <0xffffe000 0x300>,
> +				      <0xffffe600 0x100>;
> +			};
> +
> +			mpddrc: mpddrc@ffffe800 {
> +				compatible = "microchip,sam9x60-ddramc",
> "atmel,sama5d3-ddramc";
> +				reg = <0xffffe800 0x200>;
> +				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc
> PMC_TYPE_CORE PMC_MCK>;
> +				clock-names = "ddrck", "mpddr";
> +			};
> +
> +			smc: smc@ffffea00 {
> +				compatible = "microchip,sam9x60-smc",
> "atmel,at91sam9260-smc", "syscon";
> +				reg = <0xffffea00 0x100>;
> +			};
> +
> +			aic: interrupt-controller@fffff100 {
> +				compatible = "microchip,sam9x60-aic";
> +				#interrupt-cells = <3>;
> +				interrupt-controller;
> +				reg = <0xfffff100 0x100>;
> +				atmel,external-irqs = <31>;
> +			};
> +
> +			dbgu: serial@fffff200 {
> +				compatible = "atmel,at91sam9260-dbgu",
> "atmel,at91sam9260-usart";
> +				reg = <0xfffff200 0x200>;
> +				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(28))>,
> +				       <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(29))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
> +				clock-names = "usart";
> +				status = "disabled";
> +			};
> +
> +			pinctrl: pinctrl@fffff400 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				compatible = "microchip,sam9x60-pinctrl",
> "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
> +				ranges = <0xfffff400 0xfffff400 0x800>;
> +
> +				pioA: gpio@fffff400 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <2 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
> +				};
> +
> +				pioB: gpio@fffff600 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <3 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					#gpio-lines = <26>;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
> +				};
> +
> +				pioC: gpio@fffff800 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <4 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
> +				};
> +
> +				pioD: gpio@fffffa00 {
> +					compatible = "microchip,sam9x60-gpio", 
> "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffffa00 0x200>;
> +					interrupts = <44 IRQ_TYPE_LEVEL_HIGH
> 1>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					#gpio-lines = <22>;
> +					interrupt-controller;
> +					#interrupt-cells = <2>;
> +					clocks = <&pmc PMC_TYPE_PERIPHERAL
> 44>;
> +				};
> +			};
> +
> +			pmc: pmc@fffffc00 {
> +				compatible = "microchip,sam9x60-pmc",
> "syscon";
> +				reg = <0xfffffc00 0x200>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				#clock-cells = <2>;
> +				clocks = <&clk32k 1>, <&clk32k 0>,
> <&main_xtal>;
> +				clock-names = "td_slck", "md_slck",
> "main_xtal";
> +			};
> +
> +			reset_controller: rstc@fffffe00 {
> +				compatible = "microchip,sam9x60-rstc";
> +				reg = <0xfffffe00 0x10>;
> +				clocks = <&clk32k 0>;
> +			};
> +
> +			shutdown_controller: shdwc@fffffe10 {
> +				compatible = "microchip,sam9x60-shdwc";
> +				reg = <0xfffffe10 0x10>;
> +				clocks = <&clk32k 0>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				atmel,wakeup-rtc-timer;
> +				atmel,wakeup-rtt-timer;
> +				status = "disabled";
> +			};
> +
> +			pit: timer@fffffe40 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffe40 0x10>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			};
> +
> +			clk32k: sckc@fffffe50 {
> +				compatible = "microchip,sam9x60-sckc";
> +				reg = <0xfffffe50 0x4>;
> +				clocks = <&slow_xtal>;
> +				#clock-cells = <1>;
> +			};
> +
> +			gpbr: syscon@fffffe60 {
> +				compatible = "microchip,sam9x60-gpbr",
> "atmel,at91sam9260-gpbr", "syscon";
> +				reg = <0xfffffe60 0x10>;
> +			};
> +
> +			rtc: rtc@fffffea8 {
> +				compatible = "microchip,sam9x60-rtc",
> "atmel,at91sam9x5-rtc";
> +				reg = <0xfffffea8 0x100>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&clk32k 0>;
> +			};
> +		};
> +	};
> +};
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^ permalink raw reply	[flat|nested] 108+ messages in thread

end of thread, other threads:[~2020-01-10 16:38 UTC | newest]

Thread overview: 108+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-08 12:55 [PATCH 00/16] add device tree for SAM9X60 SoC and SAM9X60-EK board Claudiu Beznea
2020-01-08 12:55 ` Claudiu Beznea
2020-01-08 12:55 ` Claudiu Beznea
2020-01-08 12:55 ` Claudiu Beznea
2020-01-08 12:55 ` [PATCH 01/16] dt-bindings: at_xdmac: add entry for microchip compatibles Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55 ` [PATCH 02/16] dt-bindings: atmel-can: add microchip,sam9x60-can Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55 ` [PATCH 03/16] dt-bindings: atmel-tcb: add microchip,<chip>-tcb Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-10 13:40   ` Alexandre Belloni
2020-01-10 13:40     ` Alexandre Belloni
2020-01-10 13:40     ` Alexandre Belloni
2020-01-10 13:40     ` Alexandre Belloni
2020-01-10 14:29     ` Claudiu.Beznea
2020-01-10 14:29       ` Claudiu.Beznea
2020-01-10 14:29       ` Claudiu.Beznea
2020-01-10 14:29       ` Claudiu.Beznea
2020-01-10 14:29       ` Claudiu.Beznea
2020-01-10 14:32       ` Alexandre Belloni
2020-01-10 14:32         ` Alexandre Belloni
2020-01-10 14:32         ` Alexandre Belloni
2020-01-10 14:32         ` Alexandre Belloni
2020-01-08 12:55 ` [PATCH 04/16] dt-bindings: atmel-isi: add microchip,sam9x60-isi Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55 ` [PATCH 05/16] dt-bindings: at91-sama5d2_adc: add microchip,sam9x60-adc Claudiu Beznea
2020-01-08 12:55   ` [PATCH 05/16] dt-bindings: at91-sama5d2_adc: add microchip, sam9x60-adc Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` [PATCH 05/16] dt-bindings: at91-sama5d2_adc: add microchip,sam9x60-adc Claudiu Beznea
2020-01-08 12:55 ` [PATCH 06/16] dt-bindings: atmel-matrix: add microchip,sam9x60-matrix Claudiu Beznea
2020-01-08 12:55   ` [PATCH 06/16] dt-bindings: atmel-matrix: add microchip, sam9x60-matrix Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` [PATCH 06/16] dt-bindings: atmel-matrix: add microchip,sam9x60-matrix Claudiu Beznea
2020-01-08 12:55 ` [PATCH 07/16] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-09 19:16   ` Miquel Raynal
2020-01-09 19:16     ` Miquel Raynal
2020-01-09 19:16     ` Miquel Raynal
2020-01-09 19:16     ` Miquel Raynal
2020-01-09 19:16     ` Miquel Raynal
2020-01-08 12:55 ` [PATCH 08/16] dt-bindings: atmel-sysreg: add microchip,sam9x60-ddramc Claudiu Beznea
2020-01-08 12:55   ` [PATCH 08/16] dt-bindings: atmel-sysreg: add microchip, sam9x60-ddramc Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` [PATCH 08/16] dt-bindings: atmel-sysreg: add microchip,sam9x60-ddramc Claudiu Beznea
2020-01-08 12:55 ` [PATCH 09/16] dt-bindings: atmel-smc: add microchip,sam9x60-smc Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55 ` [PATCH 10/16] dt-bindings: atmel-gpbr: add microchip,sam9x60-gpbr Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55 ` [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc Claudiu Beznea
2020-01-08 12:55   ` [PATCH 11/16] dt-bindings: atmel, at91rm9200-rtc: add microchip, sam9x60-rtc Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` [PATCH 11/16] dt-bindings: atmel,at91rm9200-rtc: add microchip,sam9x60-rtc Claudiu Beznea
2020-01-10 14:30   ` Alexandre Belloni
2020-01-10 14:30     ` Alexandre Belloni
2020-01-10 14:30     ` Alexandre Belloni
2020-01-10 14:30     ` Alexandre Belloni
2020-01-10 15:02     ` Claudiu.Beznea
2020-01-10 15:02       ` Claudiu.Beznea
2020-01-10 15:02       ` Claudiu.Beznea
2020-01-10 15:02       ` Claudiu.Beznea
2020-01-10 15:02       ` Claudiu.Beznea
2020-01-08 12:55 ` [PATCH 12/16] dt-bindings: spi_atmel: add microchip,sam9x60-spi Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-09 21:31   ` Applied "dt-bindings: spi_atmel: add microchip,sam9x60-spi" to the spi tree Mark Brown
2020-01-09 21:31     ` Applied "dt-bindings: spi_atmel: add microchip, sam9x60-spi" " Mark Brown
2020-01-09 21:31     ` Mark Brown
2020-01-09 21:31     ` Applied "dt-bindings: spi_atmel: add microchip,sam9x60-spi" " Mark Brown
2020-01-09 21:31     ` Mark Brown
2020-01-08 12:55 ` [PATCH 13/16] dt-bindings: atmel-usart: add microchip,<chip>-usart Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-10 14:31   ` Alexandre Belloni
2020-01-10 14:31     ` Alexandre Belloni
2020-01-10 14:31     ` Alexandre Belloni
2020-01-08 12:55 ` [PATCH 14/16] dt-bindings: arm: add sam9x60-ek board Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55 ` [PATCH 15/16] ARM: at91/defconfig: enable MMC_SDHCI_OF_AT91 and MICROCHIP_PIT64B Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55 ` [PATCH 16/16] ARM: dts: at91: sam9x60: add device tree for soc and board Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-08 12:55   ` Claudiu Beznea
2020-01-10 16:37   ` Nicolas.Ferre
2020-01-10 16:37     ` Nicolas.Ferre
2020-01-10 16:37     ` Nicolas.Ferre
2020-01-10 16:37     ` Nicolas.Ferre

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