[PATCH] drm/i915: Fix MST oops due to MSA changes

[PATCH] drm/i915: Fix MST oops due to MSA changes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The MSA MISC computation now depends on the connector state, and
we do it from the DDI .pre_enable() hook. All that is fine for
DP SST but with MST we don't actually pass the connector state
to the dig port's .pre_enable() hook which leads to an oops.

Need to think more how to solve this in a cleaner fashion, but
for now let's just add a NULL check to stop the oopsing.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 80f8e2698be0..4c81449ec144 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 	 * of Color Encoding Format and Content Color Gamut] while sending
 	 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 	 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+	 *
+	 * FIXME MST doesn't pass in the conn_state
 	 */
-	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+	if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 		temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 
 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
-- 
2.21.0

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✗ Fi.CI.BAT: failure for drm/i915: Fix MST oops due to MSA changes

[Patchwork]

== Series Details ==

Series: drm/i915: Fix MST oops due to MSA changes
URL   : https://patchwork.freedesktop.org/series/68053/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14819
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14819 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14819, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14819:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-8109u:       [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html

  
Known issues
------------

  Here are the changes found in Patchwork_14819 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_basic@bad-close:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_basic@bad-close.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-u3/igt@gem_basic@bad-close.html

  * igt@i915_selftest@live_coherency:
    - fi-glk-dsi:         [PASS][5] -> [TIMEOUT][6] ([fdo#111944])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-glk-dsi/igt@i915_selftest@live_coherency.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-glk-dsi/igt@i915_selftest@live_coherency.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-kbl-x1275:       [PASS][7] -> [INCOMPLETE][8] ([fdo#112002])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - {fi-tgl-u}:         [INCOMPLETE][9] -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u/igt@debugfs_test@read_all_entries.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-tgl-u/igt@debugfs_test@read_all_entries.html

  * igt@gem_basic@bad-close:
    - fi-skl-6770hq:      [DMESG-WARN][11] ([fdo#105541]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-skl-6770hq/igt@gem_basic@bad-close.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-skl-6770hq/igt@gem_basic@bad-close.html

  * igt@gem_ctx_switch@legacy-render:
    - fi-bxt-dsi:         [INCOMPLETE][13] ([fdo#103927] / [fdo#111381]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

  * igt@gem_ringfill@basic-default-fd:
    - fi-icl-u3:          [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_ringfill@basic-default-fd.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-u3/igt@gem_ringfill@basic-default-fd.html

  * igt@gem_wait@basic-busy-all:
    - {fi-tgl-u2}:        [INCOMPLETE][17] -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u2/igt@gem_wait@basic-busy-all.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-tgl-u2/igt@gem_wait@basic-busy-all.html

  * igt@i915_selftest@live_gem_contexts:
    - {fi-icl-dsi}:       [DMESG-FAIL][19] -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_busy@basic-flip-a:
    - fi-icl-u2:          [TIMEOUT][21] ([fdo#111800]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u2/igt@kms_busy@basic-flip-a.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-u2/igt@kms_busy@basic-flip-a.html

  * igt@prime_self_import@basic-llseek-bad:
    - {fi-icl-dsi}:       [DMESG-WARN][23] ([fdo#106107]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@prime_self_import@basic-llseek-bad.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-dsi/igt@prime_self_import@basic-llseek-bad.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
  [fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944
  [fdo#112002]: https://bugs.freedesktop.org/show_bug.cgi?id=112002


Participating hosts (52 -> 46)
------------------------------

  Additional (1): fi-hsw-peppy 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7099 -> Patchwork_14819

  CI-20190529: 20190529
  CI_DRM_7099: fccd0abc9c05536751c60aabe5710c173fb8ffa6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14819: 68a6ce1869bdb2cea69459d4a550110179605ae1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

68a6ce1869bd drm/i915: Fix MST oops due to MSA changes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/index.html
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Re: [PATCH] drm/i915: Fix MST oops due to MSA changes

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala <ville.syrjala@linux.intel.com>
>Sent: Wednesday, October 16, 2019 12:36 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Shankar, Uma
><uma.shankar@intel.com>
>Subject: [PATCH] drm/i915: Fix MST oops due to MSA changes
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The MSA MISC computation now depends on the connector state, and we do it from
>the DDI .pre_enable() hook. All that is fine for DP SST but with MST we don't actually
>pass the connector state to the dig port's .pre_enable() hook which leads to an oops.
>
>Need to think more how to solve this in a cleaner fashion, but for now let's just add a
>NULL check to stop the oopsing.

Looks good to me. We will have to handle colorspaces for MST properly. But that can be
done later. Thanks for identifying and fixing this.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>Cc: Uma Shankar <uma.shankar@intel.com>
>Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA")
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 80f8e2698be0..4c81449ec144 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state
>*crtc_state,
> 	 * of Color Encoding Format and Content Color Gamut] while sending
> 	 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
> 	 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
>+	 *
>+	 * FIXME MST doesn't pass in the conn_state
> 	 */
>-	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
>+	if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> 		temp |= DP_MSA_MISC_COLOR_VSC_SDP;
>
> 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
>--
>2.21.0

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Re: [PATCH] drm/i915: Fix MST oops due to MSA changes

[Mun, Gwan-gyeong]

On Tue, 2019-10-15 at 22:05 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The MSA MISC computation now depends on the connector state, and
> we do it from the DDI .pre_enable() hook. All that is fine for
> DP SST but with MST we don't actually pass the connector state
> to the dig port's .pre_enable() hook which leads to an oops.
> 
> Need to think more how to solve this in a cleaner fashion, but
> for now let's just add a NULL check to stop the oopsing.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry
> to DP MSA")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 80f8e2698be0..4c81449ec144 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct
> intel_crtc_state *crtc_state,
>  	 * of Color Encoding Format and Content Color Gamut] while
> sending
>  	 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1
> fields
>  	 * which indicate VSC SDP for the Pixel Encoding/Colorimetry
> Format.
> +	 *
> +	 * FIXME MST doesn't pass in the conn_state
>  	 */
> -	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> +	if (conn_state && intel_dp_needs_vsc_sdp(crtc_state,
> conn_state))
>  		temp |= DP_MSA_MISC_COLOR_VSC_SDP;
>  
>  	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);

Sorry for making of a regression with my commit.
And thank you for fixing oops.
For now this seems good to me for without flow changing of setting of
MSA register.
But as you comments, as a next step we need to think more how to solve
this in a cleaner fashion on SST and MST.

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
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Re: [PATCH] drm/i915: Fix MST oops due to MSA changes

[Ville Syrjälä]

On Wed, Oct 16, 2019 at 02:59:45PM +0000, Shankar, Uma wrote:
> 
> 
> >-----Original Message-----
> >From: Ville Syrjala <ville.syrjala@linux.intel.com>
> >Sent: Wednesday, October 16, 2019 12:36 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Shankar, Uma
> ><uma.shankar@intel.com>
> >Subject: [PATCH] drm/i915: Fix MST oops due to MSA changes
> >
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >The MSA MISC computation now depends on the connector state, and we do it from
> >the DDI .pre_enable() hook. All that is fine for DP SST but with MST we don't actually
> >pass the connector state to the dig port's .pre_enable() hook which leads to an oops.
> >
> >Need to think more how to solve this in a cleaner fashion, but for now let's just add a
> >NULL check to stop the oopsing.
> 
> Looks good to me. We will have to handle colorspaces for MST properly.

Yeah, in fact just realized that this is a transcoder register so we're
no longer configuring MSA MISC for anything but the first MST stream.
The other streams will leave TRANS_MSA_MISC untouched. So I guess we
need to move this into the MST code proper, and if it needs to be left
in ddi_pre_enable() for SST we probably want to exclude it getting
programming there for MST there. Any volunteers?

Pushed. Thanks for the reviews.

> But that can be
> done later. Thanks for identifying and fixing this.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> >Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> >Cc: Uma Shankar <uma.shankar@intel.com>
> >Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA")
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> >b/drivers/gpu/drm/i915/display/intel_ddi.c
> >index 80f8e2698be0..4c81449ec144 100644
> >--- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >@@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state
> >*crtc_state,
> > 	 * of Color Encoding Format and Content Color Gamut] while sending
> > 	 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
> > 	 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
> >+	 *
> >+	 * FIXME MST doesn't pass in the conn_state
> > 	 */
> >-	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> >+	if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> > 		temp |= DP_MSA_MISC_COLOR_VSC_SDP;
> >
> > 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> >--
> >2.21.0
> 

-- 
Ville Syrjälä
Intel
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