[PATCH v2 0/3] target/arm: Restrict v7A TCG cpus to TCG accel

[PATCH v2 0/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Philippe Mathieu-Daudé]

KVM requires the target cpu to be at least ARMv8 architecture.

Restrict the last ARMv7 CPUs (A-profile) to TCG.

Series almost fully reviewed (missing review is trivial code style).

Since v1: Only include patches which don't depends on  previous series

Philippe Mathieu-Daudé (3):
  target/arm: Restrict v8M IDAU to TCG
  target/arm/cpu: Update coding style to make checkpatch.pl happy
  target/arm: Restrict v7A TCG cpus to TCG accel

 target/arm/cpu.c     | 334 -------------------------------------------
 target/arm/cpu_tcg.c | 322 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 322 insertions(+), 334 deletions(-)

-- 
2.26.2

[PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Philippe Mathieu-Daudé]

IDAU is specific to M-profile. KVM only supports A-profile.
Restrict this interface to TCG, as it is pointless (and
confusing) on a KVM-only build.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/cpu.c     | 7 -------
 target/arm/cpu_tcg.c | 8 ++++++++
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..a772fd4926f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
     .class_init = arm_cpu_class_init,
 };
 
-static const TypeInfo idau_interface_type_info = {
-    .name = TYPE_IDAU_INTERFACE,
-    .parent = TYPE_INTERFACE,
-    .class_size = sizeof(IDAUInterfaceClass),
-};
-
 static void arm_cpu_register_types(void)
 {
     const size_t cpu_count = ARRAY_SIZE(arm_cpus);
@@ -2399,7 +2393,6 @@ static void arm_cpu_register_types(void)
     if (cpu_count) {
         size_t i;
 
-        type_register_static(&idau_interface_type_info);
         for (i = 0; i < cpu_count; ++i) {
             arm_cpu_register(&arm_cpus[i]);
         }
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index c29b434c60d..fb07a336939 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -14,6 +14,7 @@
 #include "hw/core/tcg-cpu-ops.h"
 #endif /* CONFIG_TCG */
 #include "internals.h"
+#include "target/arm/idau.h"
 
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
@@ -739,10 +740,17 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 };
 
+static const TypeInfo idau_interface_type_info = {
+    .name = TYPE_IDAU_INTERFACE,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(IDAUInterfaceClass),
+};
+
 static void arm_tcg_cpu_register_types(void)
 {
     size_t i;
 
+    type_register_static(&idau_interface_type_info);
     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
         arm_cpu_register(&arm_tcg_cpus[i]);
     }
-- 
2.26.2

Re: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Claudio Fontana]

On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
> IDAU is specific to M-profile. KVM only supports A-profile.
> Restrict this interface to TCG, as it is pointless (and
> confusing) on a KVM-only build.
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


This one breaks the KVM tests hard though (most of them).

I will try to figure out why.

Ciao,

Claudio


> ---
>  target/arm/cpu.c     | 7 -------
>  target/arm/cpu_tcg.c | 8 ++++++++
>  2 files changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index b8bc89e71fc..a772fd4926f 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
>      .class_init = arm_cpu_class_init,
>  };
>  
> -static const TypeInfo idau_interface_type_info = {
> -    .name = TYPE_IDAU_INTERFACE,
> -    .parent = TYPE_INTERFACE,
> -    .class_size = sizeof(IDAUInterfaceClass),
> -};
> -
>  static void arm_cpu_register_types(void)
>  {
>      const size_t cpu_count = ARRAY_SIZE(arm_cpus);
> @@ -2399,7 +2393,6 @@ static void arm_cpu_register_types(void)
>      if (cpu_count) {
>          size_t i;
>  
> -        type_register_static(&idau_interface_type_info);
>          for (i = 0; i < cpu_count; ++i) {
>              arm_cpu_register(&arm_cpus[i]);
>          }
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index c29b434c60d..fb07a336939 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -14,6 +14,7 @@
>  #include "hw/core/tcg-cpu-ops.h"
>  #endif /* CONFIG_TCG */
>  #include "internals.h"
> +#include "target/arm/idau.h"
>  
>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
> @@ -739,10 +740,17 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
>  };
>  
> +static const TypeInfo idau_interface_type_info = {
> +    .name = TYPE_IDAU_INTERFACE,
> +    .parent = TYPE_INTERFACE,
> +    .class_size = sizeof(IDAUInterfaceClass),
> +};
> +
>  static void arm_tcg_cpu_register_types(void)
>  {
>      size_t i;
>  
> +    type_register_static(&idau_interface_type_info);
>      for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
>          arm_cpu_register(&arm_tcg_cpus[i]);
>      }
> 

Re: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Philippe Mathieu-Daudé]

On 3/9/21 2:41 PM, Claudio Fontana wrote:
> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>> IDAU is specific to M-profile. KVM only supports A-profile.
>> Restrict this interface to TCG, as it is pointless (and
>> confusing) on a KVM-only build.
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> 
> This one breaks the KVM tests hard though (most of them).
> 
> I will try to figure out why.
> 
> Ciao,
> 
> Claudio
> 
> 
>> ---
>>  target/arm/cpu.c     | 7 -------
>>  target/arm/cpu_tcg.c | 8 ++++++++
>>  2 files changed, 8 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>> index b8bc89e71fc..a772fd4926f 100644
>> --- a/target/arm/cpu.c
>> +++ b/target/arm/cpu.c
>> @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
>>      .class_init = arm_cpu_class_init,
>>  };
>>  
>> -static const TypeInfo idau_interface_type_info = {
>> -    .name = TYPE_IDAU_INTERFACE,
>> -    .parent = TYPE_INTERFACE,

Hmm this is an interface...

Is a CPU/machine trying to resolve it?

>> -    .class_size = sizeof(IDAUInterfaceClass),
>> -};
>> -
>>  static void arm_cpu_register_types(void)
>>  {
>>      const size_t cpu_count = ARRAY_SIZE(arm_cpus);
>> @@ -2399,7 +2393,6 @@ static void arm_cpu_register_types(void)
>>      if (cpu_count) {
>>          size_t i;
>>  
>> -        type_register_static(&idau_interface_type_info);
>>          for (i = 0; i < cpu_count; ++i) {
>>              arm_cpu_register(&arm_cpus[i]);
>>          }
>> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
>> index c29b434c60d..fb07a336939 100644
>> --- a/target/arm/cpu_tcg.c
>> +++ b/target/arm/cpu_tcg.c
>> @@ -14,6 +14,7 @@
>>  #include "hw/core/tcg-cpu-ops.h"
>>  #endif /* CONFIG_TCG */
>>  #include "internals.h"
>> +#include "target/arm/idau.h"
>>  
>>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>> @@ -739,10 +740,17 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>>      { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
>>  };
>>  
>> +static const TypeInfo idau_interface_type_info = {
>> +    .name = TYPE_IDAU_INTERFACE,
>> +    .parent = TYPE_INTERFACE,
>> +    .class_size = sizeof(IDAUInterfaceClass),
>> +};
>> +
>>  static void arm_tcg_cpu_register_types(void)
>>  {
>>      size_t i;
>>  
>> +    type_register_static(&idau_interface_type_info);
>>      for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
>>          arm_cpu_register(&arm_tcg_cpus[i]);
>>      }
>>
> 
> 

Re: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Claudio Fontana]

On 3/9/21 3:18 PM, Philippe Mathieu-Daudé wrote:
> On 3/9/21 2:41 PM, Claudio Fontana wrote:
>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>> IDAU is specific to M-profile. KVM only supports A-profile.
>>> Restrict this interface to TCG, as it is pointless (and
>>> confusing) on a KVM-only build.
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>>
>> This one breaks the KVM tests hard though (most of them).
>>
>> I will try to figure out why.
>>
>> Ciao,
>>
>> Claudio
>>
>>
>>> ---
>>>  target/arm/cpu.c     | 7 -------
>>>  target/arm/cpu_tcg.c | 8 ++++++++
>>>  2 files changed, 8 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>>> index b8bc89e71fc..a772fd4926f 100644
>>> --- a/target/arm/cpu.c
>>> +++ b/target/arm/cpu.c
>>> @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
>>>      .class_init = arm_cpu_class_init,
>>>  };
>>>  
>>> -static const TypeInfo idau_interface_type_info = {
>>> -    .name = TYPE_IDAU_INTERFACE,
>>> -    .parent = TYPE_INTERFACE,
> 
> Hmm this is an interface...
> 
> Is a CPU/machine trying to resolve it?

I think that qtests assume the interface to be there.

device-introspection-test for sure, but apparently many others too..

RFC v5 is out now,

Ciao,

Claudio

> 
>>> -    .class_size = sizeof(IDAUInterfaceClass),
>>> -};
>>> -
>>>  static void arm_cpu_register_types(void)
>>>  {
>>>      const size_t cpu_count = ARRAY_SIZE(arm_cpus);
>>> @@ -2399,7 +2393,6 @@ static void arm_cpu_register_types(void)
>>>      if (cpu_count) {
>>>          size_t i;
>>>  
>>> -        type_register_static(&idau_interface_type_info);
>>>          for (i = 0; i < cpu_count; ++i) {
>>>              arm_cpu_register(&arm_cpus[i]);
>>>          }
>>> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
>>> index c29b434c60d..fb07a336939 100644
>>> --- a/target/arm/cpu_tcg.c
>>> +++ b/target/arm/cpu_tcg.c
>>> @@ -14,6 +14,7 @@
>>>  #include "hw/core/tcg-cpu-ops.h"
>>>  #endif /* CONFIG_TCG */
>>>  #include "internals.h"
>>> +#include "target/arm/idau.h"
>>>  
>>>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>>>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>>> @@ -739,10 +740,17 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>>>      { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
>>>  };
>>>  
>>> +static const TypeInfo idau_interface_type_info = {
>>> +    .name = TYPE_IDAU_INTERFACE,
>>> +    .parent = TYPE_INTERFACE,
>>> +    .class_size = sizeof(IDAUInterfaceClass),
>>> +};
>>> +
>>>  static void arm_tcg_cpu_register_types(void)
>>>  {
>>>      size_t i;
>>>  
>>> +    type_register_static(&idau_interface_type_info);
>>>      for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
>>>          arm_cpu_register(&arm_tcg_cpus[i]);
>>>      }
>>>
>>
>>
> 

Re: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Claudio Fontana]

On 3/9/21 3:18 PM, Philippe Mathieu-Daudé wrote:
> On 3/9/21 2:41 PM, Claudio Fontana wrote:
>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>> IDAU is specific to M-profile. KVM only supports A-profile.
>>> Restrict this interface to TCG, as it is pointless (and
>>> confusing) on a KVM-only build.
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>>
>> This one breaks the KVM tests hard though (most of them).
>>
>> I will try to figure out why.
>>
>> Ciao,
>>
>> Claudio
>>
>>
>>> ---
>>>  target/arm/cpu.c     | 7 -------
>>>  target/arm/cpu_tcg.c | 8 ++++++++
>>>  2 files changed, 8 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>>> index b8bc89e71fc..a772fd4926f 100644
>>> --- a/target/arm/cpu.c
>>> +++ b/target/arm/cpu.c
>>> @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
>>>      .class_init = arm_cpu_class_init,
>>>  };
>>>  
>>> -static const TypeInfo idau_interface_type_info = {
>>> -    .name = TYPE_IDAU_INTERFACE,
>>> -    .parent = TYPE_INTERFACE,
> 
> Hmm this is an interface...
> 
> Is a CPU/machine trying to resolve it?

Well, this fails horribly at any qemu-system-aarch64 startup for the kvm-only build:

in my view we cannot remove the idau interface until we have removed all the TCG-only boards fronm the build.

When calling qemu_init(), and we get into select_machine(),

the object_class_get_list() tries to initialize all machine types.

When it does that, it tries to initialize the IDAU interface, and fails.

#0  0x0000ffffb9e51828 in raise () at /lib64/libc.so.6
#1  0x0000ffffb9e52e4c in abort () at /lib64/libc.so.6
#2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
#3  0x0000aaaae042c06c in object_class_foreach_tramp (key=0xaaaaf0cb3940, value=0xaaaaf0cb37c0, opaque=0xfffff9f2bac8)
    at ../qom/object.c:1069
#4  0x0000ffffbb3d4248 in g_hash_table_foreach () at /usr/lib64/libglib-2.0.so.0
#5  0x0000aaaae042c180 in object_class_foreach (fn=
    0xaaaae042c324 <object_class_get_list_tramp>, implements_type=0xaaaae089cc90 "machine", include_abstract=false, opaque=0xfffff9f2bb10)
    at ../qom/object.c:1091
#6  0x0000aaaae042c3a8 in object_class_get_list (implements_type=0xaaaae089cc90 "machine", include_abstract=false) at ../qom/object.c:1148
#7  0x0000aaaae03863d8 in select_machine () at ../softmmu/vl.c:1607
#8  0x0000aaaae038ad74 in qemu_init (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/vl.c:3489
#9  0x0000aaaadfdcf5a0 in main (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/main.c:49


(gdb) frame 2
#2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
333                     abort();
(gdb) p ti[0]
$1 = {name = 0xaaaaf0cb3940 "mps2tz", class_size = 408, instance_size = 202224, instance_align = 0, class_init = 
    0xaaaae0273408 <mps2tz_class_init>, class_base_init = 0x0, class_data = 0x0, instance_init = 0x0, instance_post_init = 0x0, 
  instance_finalize = 0x0, abstract = true, parent = 0xaaaaf0cb3960 "machine", parent_type = 0xaaaaf0cad860, class = 0xaaaaf0d0d830, 
  num_interfaces = 1, interfaces = {{typename = 0xaaaaf0cb3980 "idau-interface"}, {typename = 0x0} <repeats 31 times>}}


In my view we should revert this until all incompatible boards are disabled

In this case, the one failing is MPS2, so the offender is

devices/arm-softmmu.mak:CONFIG_MPS2=y

from the point of view of the kvm-only build.

What I'd suggest is (but I am open to alternatives):

* revert this one
* complete my arm cleanup series, with now all tests passing
* disable the non-KVM boards for KVM-only builds (basically your series)
* apply the accelerator classes specializations to ARM



> 
>>> -    .class_size = sizeof(IDAUInterfaceClass),
>>> -};
>>> -
>>>  static void arm_cpu_register_types(void)
>>>  {
>>>      const size_t cpu_count = ARRAY_SIZE(arm_cpus);
>>> @@ -2399,7 +2393,6 @@ static void arm_cpu_register_types(void)
>>>      if (cpu_count) {
>>>          size_t i;
>>>  
>>> -        type_register_static(&idau_interface_type_info);
>>>          for (i = 0; i < cpu_count; ++i) {
>>>              arm_cpu_register(&arm_cpus[i]);
>>>          }
>>> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
>>> index c29b434c60d..fb07a336939 100644
>>> --- a/target/arm/cpu_tcg.c
>>> +++ b/target/arm/cpu_tcg.c
>>> @@ -14,6 +14,7 @@
>>>  #include "hw/core/tcg-cpu-ops.h"
>>>  #endif /* CONFIG_TCG */
>>>  #include "internals.h"
>>> +#include "target/arm/idau.h"
>>>  
>>>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>>>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>>> @@ -739,10 +740,17 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>>>      { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
>>>  };
>>>  
>>> +static const TypeInfo idau_interface_type_info = {
>>> +    .name = TYPE_IDAU_INTERFACE,
>>> +    .parent = TYPE_INTERFACE,
>>> +    .class_size = sizeof(IDAUInterfaceClass),
>>> +};
>>> +
>>>  static void arm_tcg_cpu_register_types(void)
>>>  {
>>>      size_t i;
>>>  
>>> +    type_register_static(&idau_interface_type_info);
>>>      for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
>>>          arm_cpu_register(&arm_tcg_cpus[i]);
>>>      }
>>>
>>
>>

Re: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Philippe Mathieu-Daudé]

On 3/10/21 12:46 PM, Claudio Fontana wrote:
> On 3/9/21 3:18 PM, Philippe Mathieu-Daudé wrote:
>> On 3/9/21 2:41 PM, Claudio Fontana wrote:
>>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>>> IDAU is specific to M-profile. KVM only supports A-profile.
>>>> Restrict this interface to TCG, as it is pointless (and
>>>> confusing) on a KVM-only build.
>>>>
>>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>
>>>
>>> This one breaks the KVM tests hard though (most of them).
>>>
>>> I will try to figure out why.
>>>
>>> Ciao,
>>>
>>> Claudio
>>>
>>>
>>>> ---
>>>>  target/arm/cpu.c     | 7 -------
>>>>  target/arm/cpu_tcg.c | 8 ++++++++
>>>>  2 files changed, 8 insertions(+), 7 deletions(-)
>>>>
>>>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>>>> index b8bc89e71fc..a772fd4926f 100644
>>>> --- a/target/arm/cpu.c
>>>> +++ b/target/arm/cpu.c
>>>> @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
>>>>      .class_init = arm_cpu_class_init,
>>>>  };
>>>>  
>>>> -static const TypeInfo idau_interface_type_info = {
>>>> -    .name = TYPE_IDAU_INTERFACE,
>>>> -    .parent = TYPE_INTERFACE,
>>
>> Hmm this is an interface...
>>
>> Is a CPU/machine trying to resolve it?
> 
> Well, this fails horribly at any qemu-system-aarch64 startup for the kvm-only build:
> 
> in my view we cannot remove the idau interface until we have removed all the TCG-only boards fronm the build.

Yes, this is a similar bug to the one fixed by commit 8d0bceba24c
("hw/nvram: Always register FW_CFG_DATA_GENERATOR_INTERFACE").

> 
> When calling qemu_init(), and we get into select_machine(),
> 
> the object_class_get_list() tries to initialize all machine types.
> 
> When it does that, it tries to initialize the IDAU interface, and fails.
> 
> #0  0x0000ffffb9e51828 in raise () at /lib64/libc.so.6
> #1  0x0000ffffb9e52e4c in abort () at /lib64/libc.so.6
> #2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
> #3  0x0000aaaae042c06c in object_class_foreach_tramp (key=0xaaaaf0cb3940, value=0xaaaaf0cb37c0, opaque=0xfffff9f2bac8)
>     at ../qom/object.c:1069
> #4  0x0000ffffbb3d4248 in g_hash_table_foreach () at /usr/lib64/libglib-2.0.so.0
> #5  0x0000aaaae042c180 in object_class_foreach (fn=
>     0xaaaae042c324 <object_class_get_list_tramp>, implements_type=0xaaaae089cc90 "machine", include_abstract=false, opaque=0xfffff9f2bb10)
>     at ../qom/object.c:1091
> #6  0x0000aaaae042c3a8 in object_class_get_list (implements_type=0xaaaae089cc90 "machine", include_abstract=false) at ../qom/object.c:1148
> #7  0x0000aaaae03863d8 in select_machine () at ../softmmu/vl.c:1607
> #8  0x0000aaaae038ad74 in qemu_init (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/vl.c:3489
> #9  0x0000aaaadfdcf5a0 in main (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/main.c:49
> 
> 
> (gdb) frame 2
> #2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
> 333                     abort();
> (gdb) p ti[0]
> $1 = {name = 0xaaaaf0cb3940 "mps2tz", class_size = 408, instance_size = 202224, instance_align = 0, class_init = 
>     0xaaaae0273408 <mps2tz_class_init>, class_base_init = 0x0, class_data = 0x0, instance_init = 0x0, instance_post_init = 0x0, 
>   instance_finalize = 0x0, abstract = true, parent = 0xaaaaf0cb3960 "machine", parent_type = 0xaaaaf0cad860, class = 0xaaaaf0d0d830, 
>   num_interfaces = 1, interfaces = {{typename = 0xaaaaf0cb3980 "idau-interface"}, {typename = 0x0} <repeats 31 times>}}
> 
> 
> In my view we should revert this until all incompatible boards are disabled

My view is this is a QOM design problem. Others might hit the
same issue. It is hard to debug. It should be fixed upfront.

> In this case, the one failing is MPS2, so the offender is
> 
> devices/arm-softmmu.mak:CONFIG_MPS2=y
> 
> from the point of view of the kvm-only build.
> 
> What I'd suggest is (but I am open to alternatives):
> 
> * revert this one
> * complete my arm cleanup series, with now all tests passing
> * disable the non-KVM boards for KVM-only builds (basically your series)
> * apply the accelerator classes specializations to ARM

MPS2TZ uses a Cortex-M33 which is requires TCG.
The machine shouldn't be present if TCG is not built-in.

Previous attempt which you acked :)
"target/arm: Restrict ARMv7 M-profile cpus to TCG accel"
https://www.mail-archive.com/qemu-block@nongnu.org/msg79943.html

Re: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Claudio Fontana]

On 3/10/21 2:42 PM, Philippe Mathieu-Daudé wrote:
> On 3/10/21 12:46 PM, Claudio Fontana wrote:
>> On 3/9/21 3:18 PM, Philippe Mathieu-Daudé wrote:
>>> On 3/9/21 2:41 PM, Claudio Fontana wrote:
>>>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>>>> IDAU is specific to M-profile. KVM only supports A-profile.
>>>>> Restrict this interface to TCG, as it is pointless (and
>>>>> confusing) on a KVM-only build.
>>>>>
>>>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>>
>>>>
>>>> This one breaks the KVM tests hard though (most of them).
>>>>
>>>> I will try to figure out why.
>>>>
>>>> Ciao,
>>>>
>>>> Claudio
>>>>
>>>>
>>>>> ---
>>>>>  target/arm/cpu.c     | 7 -------
>>>>>  target/arm/cpu_tcg.c | 8 ++++++++
>>>>>  2 files changed, 8 insertions(+), 7 deletions(-)
>>>>>
>>>>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>>>>> index b8bc89e71fc..a772fd4926f 100644
>>>>> --- a/target/arm/cpu.c
>>>>> +++ b/target/arm/cpu.c
>>>>> @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
>>>>>      .class_init = arm_cpu_class_init,
>>>>>  };
>>>>>  
>>>>> -static const TypeInfo idau_interface_type_info = {
>>>>> -    .name = TYPE_IDAU_INTERFACE,
>>>>> -    .parent = TYPE_INTERFACE,
>>>
>>> Hmm this is an interface...
>>>
>>> Is a CPU/machine trying to resolve it?
>>
>> Well, this fails horribly at any qemu-system-aarch64 startup for the kvm-only build:
>>
>> in my view we cannot remove the idau interface until we have removed all the TCG-only boards fronm the build.
> 
> Yes, this is a similar bug to the one fixed by commit 8d0bceba24c
> ("hw/nvram: Always register FW_CFG_DATA_GENERATOR_INTERFACE").
> 
>>
>> When calling qemu_init(), and we get into select_machine(),
>>
>> the object_class_get_list() tries to initialize all machine types.
>>
>> When it does that, it tries to initialize the IDAU interface, and fails.
>>
>> #0  0x0000ffffb9e51828 in raise () at /lib64/libc.so.6
>> #1  0x0000ffffb9e52e4c in abort () at /lib64/libc.so.6
>> #2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
>> #3  0x0000aaaae042c06c in object_class_foreach_tramp (key=0xaaaaf0cb3940, value=0xaaaaf0cb37c0, opaque=0xfffff9f2bac8)
>>     at ../qom/object.c:1069
>> #4  0x0000ffffbb3d4248 in g_hash_table_foreach () at /usr/lib64/libglib-2.0.so.0
>> #5  0x0000aaaae042c180 in object_class_foreach (fn=
>>     0xaaaae042c324 <object_class_get_list_tramp>, implements_type=0xaaaae089cc90 "machine", include_abstract=false, opaque=0xfffff9f2bb10)
>>     at ../qom/object.c:1091
>> #6  0x0000aaaae042c3a8 in object_class_get_list (implements_type=0xaaaae089cc90 "machine", include_abstract=false) at ../qom/object.c:1148
>> #7  0x0000aaaae03863d8 in select_machine () at ../softmmu/vl.c:1607
>> #8  0x0000aaaae038ad74 in qemu_init (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/vl.c:3489
>> #9  0x0000aaaadfdcf5a0 in main (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/main.c:49
>>
>>
>> (gdb) frame 2
>> #2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
>> 333                     abort();
>> (gdb) p ti[0]
>> $1 = {name = 0xaaaaf0cb3940 "mps2tz", class_size = 408, instance_size = 202224, instance_align = 0, class_init = 
>>     0xaaaae0273408 <mps2tz_class_init>, class_base_init = 0x0, class_data = 0x0, instance_init = 0x0, instance_post_init = 0x0, 
>>   instance_finalize = 0x0, abstract = true, parent = 0xaaaaf0cb3960 "machine", parent_type = 0xaaaaf0cad860, class = 0xaaaaf0d0d830, 
>>   num_interfaces = 1, interfaces = {{typename = 0xaaaaf0cb3980 "idau-interface"}, {typename = 0x0} <repeats 31 times>}}
>>
>>
>> In my view we should revert this until all incompatible boards are disabled
> 
> My view is this is a QOM design problem. Others might hit the
> same issue. It is hard to debug. It should be fixed upfront.
> 
>> In this case, the one failing is MPS2, so the offender is
>>
>> devices/arm-softmmu.mak:CONFIG_MPS2=y
>>
>> from the point of view of the kvm-only build.
>>
>> What I'd suggest is (but I am open to alternatives):
>>
>> * revert this one
>> * complete my arm cleanup series, with now all tests passing
>> * disable the non-KVM boards for KVM-only builds (basically your series)
>> * apply the accelerator classes specializations to ARM
> 
> MPS2TZ uses a Cortex-M33 which is requires TCG.
> The machine shouldn't be present if TCG is not built-in.
> 
> Previous attempt which you acked :)
> "target/arm: Restrict ARMv7 M-profile cpus to TCG accel"
> https://www.mail-archive.com/qemu-block@nongnu.org/msg79943.html
> 

Yes, I would absolutely like to proceed with all of this,

and have only the right configuration for KVM be built,

but I am a bit lost with all these different series.

Ciao,

CLaudio

Re: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Claudio Fontana]

On 3/10/21 2:45 PM, Claudio Fontana wrote:
> On 3/10/21 2:42 PM, Philippe Mathieu-Daudé wrote:
>> On 3/10/21 12:46 PM, Claudio Fontana wrote:
>>> On 3/9/21 3:18 PM, Philippe Mathieu-Daudé wrote:
>>>> On 3/9/21 2:41 PM, Claudio Fontana wrote:
>>>>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>>>>> IDAU is specific to M-profile. KVM only supports A-profile.
>>>>>> Restrict this interface to TCG, as it is pointless (and
>>>>>> confusing) on a KVM-only build.
>>>>>>
>>>>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>>>
>>>>>
>>>>> This one breaks the KVM tests hard though (most of them).
>>>>>
>>>>> I will try to figure out why.
>>>>>
>>>>> Ciao,
>>>>>
>>>>> Claudio
>>>>>
>>>>>
>>>>>> ---
>>>>>>  target/arm/cpu.c     | 7 -------
>>>>>>  target/arm/cpu_tcg.c | 8 ++++++++
>>>>>>  2 files changed, 8 insertions(+), 7 deletions(-)
>>>>>>
>>>>>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>>>>>> index b8bc89e71fc..a772fd4926f 100644
>>>>>> --- a/target/arm/cpu.c
>>>>>> +++ b/target/arm/cpu.c
>>>>>> @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
>>>>>>      .class_init = arm_cpu_class_init,
>>>>>>  };
>>>>>>  
>>>>>> -static const TypeInfo idau_interface_type_info = {
>>>>>> -    .name = TYPE_IDAU_INTERFACE,
>>>>>> -    .parent = TYPE_INTERFACE,
>>>>
>>>> Hmm this is an interface...
>>>>
>>>> Is a CPU/machine trying to resolve it?
>>>
>>> Well, this fails horribly at any qemu-system-aarch64 startup for the kvm-only build:
>>>
>>> in my view we cannot remove the idau interface until we have removed all the TCG-only boards fronm the build.
>>
>> Yes, this is a similar bug to the one fixed by commit 8d0bceba24c
>> ("hw/nvram: Always register FW_CFG_DATA_GENERATOR_INTERFACE").
>>
>>>
>>> When calling qemu_init(), and we get into select_machine(),
>>>
>>> the object_class_get_list() tries to initialize all machine types.
>>>
>>> When it does that, it tries to initialize the IDAU interface, and fails.
>>>
>>> #0  0x0000ffffb9e51828 in raise () at /lib64/libc.so.6
>>> #1  0x0000ffffb9e52e4c in abort () at /lib64/libc.so.6
>>> #2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
>>> #3  0x0000aaaae042c06c in object_class_foreach_tramp (key=0xaaaaf0cb3940, value=0xaaaaf0cb37c0, opaque=0xfffff9f2bac8)
>>>     at ../qom/object.c:1069
>>> #4  0x0000ffffbb3d4248 in g_hash_table_foreach () at /usr/lib64/libglib-2.0.so.0
>>> #5  0x0000aaaae042c180 in object_class_foreach (fn=
>>>     0xaaaae042c324 <object_class_get_list_tramp>, implements_type=0xaaaae089cc90 "machine", include_abstract=false, opaque=0xfffff9f2bb10)
>>>     at ../qom/object.c:1091
>>> #6  0x0000aaaae042c3a8 in object_class_get_list (implements_type=0xaaaae089cc90 "machine", include_abstract=false) at ../qom/object.c:1148
>>> #7  0x0000aaaae03863d8 in select_machine () at ../softmmu/vl.c:1607
>>> #8  0x0000aaaae038ad74 in qemu_init (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/vl.c:3489
>>> #9  0x0000aaaadfdcf5a0 in main (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/main.c:49
>>>
>>>
>>> (gdb) frame 2
>>> #2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
>>> 333                     abort();
>>> (gdb) p ti[0]
>>> $1 = {name = 0xaaaaf0cb3940 "mps2tz", class_size = 408, instance_size = 202224, instance_align = 0, class_init = 
>>>     0xaaaae0273408 <mps2tz_class_init>, class_base_init = 0x0, class_data = 0x0, instance_init = 0x0, instance_post_init = 0x0, 
>>>   instance_finalize = 0x0, abstract = true, parent = 0xaaaaf0cb3960 "machine", parent_type = 0xaaaaf0cad860, class = 0xaaaaf0d0d830, 
>>>   num_interfaces = 1, interfaces = {{typename = 0xaaaaf0cb3980 "idau-interface"}, {typename = 0x0} <repeats 31 times>}}
>>>
>>>
>>> In my view we should revert this until all incompatible boards are disabled
>>
>> My view is this is a QOM design problem. Others might hit the
>> same issue. It is hard to debug. It should be fixed upfront.

What is the QOM design problem to fix exactly?

And in any case, I think this small change "target/arm: Restrict v8M IDAU to TCG",
when applied on its own, does not get us any closer to the goal, it actually hinders us, as we do not have a working buildable and testable kvm-only build to base on.

That is why I added a revert of this to my series.

My suggestion is just to postpone your change to later on,
when we have the other pieces in place (ie after we can disable incompabile boards).

A working kvm-only build is a good starting point I think.

After we are able to disable incompatible boards,
we can reapply "target/arm: Restrict v8M IDAU to TCG",
and we can also remove a lot of additional stubs and V7M-only code and such from the KVM-only build.

But I'd rather have a functional, make check-able starting point..

Ciao,

CLaudio


>>
>>> In this case, the one failing is MPS2, so the offender is
>>>
>>> devices/arm-softmmu.mak:CONFIG_MPS2=y
>>>
>>> from the point of view of the kvm-only build.
>>>
>>> What I'd suggest is (but I am open to alternatives):
>>>
>>> * revert this one
>>> * complete my arm cleanup series, with now all tests passing
>>> * disable the non-KVM boards for KVM-only builds (basically your series)
>>> * apply the accelerator classes specializations to ARM
>>
>> MPS2TZ uses a Cortex-M33 which is requires TCG.
>> The machine shouldn't be present if TCG is not built-in.
>>
>> Previous attempt which you acked :)
>> "target/arm: Restrict ARMv7 M-profile cpus to TCG accel"
>> https://www.mail-archive.com/qemu-block@nongnu.org/msg79943.html
>>
> 
> Yes, I would absolutely like to proceed with all of this,
> 
> and have only the right configuration for KVM be built,
> 
> but I am a bit lost with all these different series.
> 
> Ciao,
> 
> CLaudio
> 

Re: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG

[Philippe Mathieu-Daudé]

On 3/10/21 3:00 PM, Claudio Fontana wrote:
> On 3/10/21 2:45 PM, Claudio Fontana wrote:
>> On 3/10/21 2:42 PM, Philippe Mathieu-Daudé wrote:
>>> On 3/10/21 12:46 PM, Claudio Fontana wrote:
>>>> On 3/9/21 3:18 PM, Philippe Mathieu-Daudé wrote:
>>>>> On 3/9/21 2:41 PM, Claudio Fontana wrote:
>>>>>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>>>>>> IDAU is specific to M-profile. KVM only supports A-profile.
>>>>>>> Restrict this interface to TCG, as it is pointless (and
>>>>>>> confusing) on a KVM-only build.
>>>>>>>
>>>>>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>>>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>>>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>>>>
>>>>>>
>>>>>> This one breaks the KVM tests hard though (most of them).
>>>>>>
>>>>>> I will try to figure out why.
>>>>>>
>>>>>> Ciao,
>>>>>>
>>>>>> Claudio
>>>>>>
>>>>>>
>>>>>>> ---
>>>>>>>  target/arm/cpu.c     | 7 -------
>>>>>>>  target/arm/cpu_tcg.c | 8 ++++++++
>>>>>>>  2 files changed, 8 insertions(+), 7 deletions(-)
>>>>>>>
>>>>>>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>>>>>>> index b8bc89e71fc..a772fd4926f 100644
>>>>>>> --- a/target/arm/cpu.c
>>>>>>> +++ b/target/arm/cpu.c
>>>>>>> @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info = {
>>>>>>>      .class_init = arm_cpu_class_init,
>>>>>>>  };
>>>>>>>  
>>>>>>> -static const TypeInfo idau_interface_type_info = {
>>>>>>> -    .name = TYPE_IDAU_INTERFACE,
>>>>>>> -    .parent = TYPE_INTERFACE,
>>>>>
>>>>> Hmm this is an interface...
>>>>>
>>>>> Is a CPU/machine trying to resolve it?
>>>>
>>>> Well, this fails horribly at any qemu-system-aarch64 startup for the kvm-only build:
>>>>
>>>> in my view we cannot remove the idau interface until we have removed all the TCG-only boards fronm the build.
>>>
>>> Yes, this is a similar bug to the one fixed by commit 8d0bceba24c
>>> ("hw/nvram: Always register FW_CFG_DATA_GENERATOR_INTERFACE").
>>>
>>>>
>>>> When calling qemu_init(), and we get into select_machine(),
>>>>
>>>> the object_class_get_list() tries to initialize all machine types.
>>>>
>>>> When it does that, it tries to initialize the IDAU interface, and fails.
>>>>
>>>> #0  0x0000ffffb9e51828 in raise () at /lib64/libc.so.6
>>>> #1  0x0000ffffb9e52e4c in abort () at /lib64/libc.so.6
>>>> #2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
>>>> #3  0x0000aaaae042c06c in object_class_foreach_tramp (key=0xaaaaf0cb3940, value=0xaaaaf0cb37c0, opaque=0xfffff9f2bac8)
>>>>     at ../qom/object.c:1069
>>>> #4  0x0000ffffbb3d4248 in g_hash_table_foreach () at /usr/lib64/libglib-2.0.so.0
>>>> #5  0x0000aaaae042c180 in object_class_foreach (fn=
>>>>     0xaaaae042c324 <object_class_get_list_tramp>, implements_type=0xaaaae089cc90 "machine", include_abstract=false, opaque=0xfffff9f2bb10)
>>>>     at ../qom/object.c:1091
>>>> #6  0x0000aaaae042c3a8 in object_class_get_list (implements_type=0xaaaae089cc90 "machine", include_abstract=false) at ../qom/object.c:1148
>>>> #7  0x0000aaaae03863d8 in select_machine () at ../softmmu/vl.c:1607
>>>> #8  0x0000aaaae038ad74 in qemu_init (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/vl.c:3489
>>>> #9  0x0000aaaadfdcf5a0 in main (argc=15, argv=0xfffff9f2be08, envp=0xfffff9f2be88) at ../softmmu/main.c:49
>>>>
>>>>
>>>> (gdb) frame 2
>>>> #2  0x0000aaaae042a484 in type_initialize (ti=0xaaaaf0cb37c0) at ../qom/object.c:333
>>>> 333                     abort();
>>>> (gdb) p ti[0]
>>>> $1 = {name = 0xaaaaf0cb3940 "mps2tz", class_size = 408, instance_size = 202224, instance_align = 0, class_init = 
>>>>     0xaaaae0273408 <mps2tz_class_init>, class_base_init = 0x0, class_data = 0x0, instance_init = 0x0, instance_post_init = 0x0, 
>>>>   instance_finalize = 0x0, abstract = true, parent = 0xaaaaf0cb3960 "machine", parent_type = 0xaaaaf0cad860, class = 0xaaaaf0d0d830, 
>>>>   num_interfaces = 1, interfaces = {{typename = 0xaaaaf0cb3980 "idau-interface"}, {typename = 0x0} <repeats 31 times>}}
>>>>
>>>>
>>>> In my view we should revert this until all incompatible boards are disabled
>>>
>>> My view is this is a QOM design problem. Others might hit the
>>> same issue. It is hard to debug. It should be fixed upfront.
> 
> What is the QOM design problem to fix exactly?

It is hard to follow where interface types are registered,
they can be easily removed from a binary by deselecting options
with Kconfig.

There is an strict Implementation -> Interface QOM dependency
which is hard to match with Kconfig and modularized builds.

> And in any case, I think this small change "target/arm: Restrict v8M IDAU to TCG",
> when applied on its own, does not get us any closer to the goal, it actually hinders us, as we do not have a working buildable and testable kvm-only build to base on.
> 
> That is why I added a revert of this to my series.

No problem with that!

> My suggestion is just to postpone your change to later on,
> when we have the other pieces in place (ie after we can disable incompabile boards).
> 
> A working kvm-only build is a good starting point I think.
> 
> After we are able to disable incompatible boards,
> we can reapply "target/arm: Restrict v8M IDAU to TCG",
> and we can also remove a lot of additional stubs and V7M-only code and such from the KVM-only build.
> 
> But I'd rather have a functional, make check-able starting point..

At least you have tests ;)

[PATCH v2 2/3] target/arm/cpu: Update coding style to make checkpatch.pl happy

[Philippe Mathieu-Daudé]

We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a772fd4926f..6865ea76466 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1972,7 +1972,8 @@ static void cortex_a8_initfn(Object *obj)
 }
 
 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
-    /* power_control should be set to maximum latency. Again,
+    /*
+     * power_control should be set to maximum latency. Again,
      * default to 0 and set by private hook
      */
     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
@@ -2009,7 +2010,8 @@ static void cortex_a9_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
-    /* Note that A9 supports the MP extensions even for
+    /*
+     * Note that A9 supports the MP extensions even for
      * A9UP and single-core A9MP (which are both different
      * and valid configurations; we don't model A9UP).
      */
@@ -2046,7 +2048,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     MachineState *ms = MACHINE(qdev_get_machine());
 
-    /* Linux wants the number of processors from here.
+    /*
+     * Linux wants the number of processors from here.
      * Might as well set the interrupt-controller bit too.
      */
     return ((ms->smp.cpus - 1) << 24) | (1 << 23);
@@ -2093,7 +2096,8 @@ static void cortex_a7_initfn(Object *obj)
     cpu->isar.id_mmfr1 = 0x40000000;
     cpu->isar.id_mmfr2 = 0x01240000;
     cpu->isar.id_mmfr3 = 0x02102211;
-    /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
+    /*
+     * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
      * table 4-41 gives 0x02101110, which includes the arm div insns.
      */
     cpu->isar.id_isar0 = 0x02101110;
-- 
2.26.2

[PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Philippe Mathieu-Daudé]

KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").

A KVM-only build won't be able to run TCG cpus, move the
v7A CPU definitions to cpu_tcg.c.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/cpu.c     | 331 -------------------------------------------
 target/arm/cpu_tcg.c | 314 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 314 insertions(+), 331 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 6865ea76466..ae04884408c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1922,327 +1922,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
     return oc;
 }
 
-/* CPU models. These are not needed for the AArch64 linux-user build. */
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-
-static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
-    { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
-};
-
-static void cortex_a8_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a8";
-    set_feature(&cpu->env, ARM_FEATURE_V7);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
-    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    cpu->midr = 0x410fc080;
-    cpu->reset_fpsid = 0x410330c0;
-    cpu->isar.mvfr0 = 0x11110222;
-    cpu->isar.mvfr1 = 0x00011111;
-    cpu->ctr = 0x82048004;
-    cpu->reset_sctlr = 0x00c50078;
-    cpu->isar.id_pfr0 = 0x1031;
-    cpu->isar.id_pfr1 = 0x11;
-    cpu->isar.id_dfr0 = 0x400;
-    cpu->id_afr0 = 0;
-    cpu->isar.id_mmfr0 = 0x31100003;
-    cpu->isar.id_mmfr1 = 0x20000000;
-    cpu->isar.id_mmfr2 = 0x01202000;
-    cpu->isar.id_mmfr3 = 0x11;
-    cpu->isar.id_isar0 = 0x00101111;
-    cpu->isar.id_isar1 = 0x12112111;
-    cpu->isar.id_isar2 = 0x21232031;
-    cpu->isar.id_isar3 = 0x11112131;
-    cpu->isar.id_isar4 = 0x00111142;
-    cpu->isar.dbgdidr = 0x15141000;
-    cpu->clidr = (1 << 27) | (2 << 24) | 3;
-    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
-    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
-    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
-    cpu->reset_auxcr = 2;
-    define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
-}
-
-static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
-    /*
-     * power_control should be set to maximum latency. Again,
-     * default to 0 and set by private hook
-     */
-    { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
-      .access = PL1_RW, .resetvalue = 0,
-      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
-    { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
-      .access = PL1_RW, .resetvalue = 0,
-      .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
-    { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
-      .access = PL1_RW, .resetvalue = 0,
-      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
-    { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
-      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-    /* TLB lockdown control */
-    { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
-      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
-    { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
-      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
-    { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
-      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-    { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
-      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-    { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
-      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-    REGINFO_SENTINEL
-};
-
-static void cortex_a9_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a9";
-    set_feature(&cpu->env, ARM_FEATURE_V7);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    /*
-     * Note that A9 supports the MP extensions even for
-     * A9UP and single-core A9MP (which are both different
-     * and valid configurations; we don't model A9UP).
-     */
-    set_feature(&cpu->env, ARM_FEATURE_V7MP);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR);
-    cpu->midr = 0x410fc090;
-    cpu->reset_fpsid = 0x41033090;
-    cpu->isar.mvfr0 = 0x11110222;
-    cpu->isar.mvfr1 = 0x01111111;
-    cpu->ctr = 0x80038003;
-    cpu->reset_sctlr = 0x00c50078;
-    cpu->isar.id_pfr0 = 0x1031;
-    cpu->isar.id_pfr1 = 0x11;
-    cpu->isar.id_dfr0 = 0x000;
-    cpu->id_afr0 = 0;
-    cpu->isar.id_mmfr0 = 0x00100103;
-    cpu->isar.id_mmfr1 = 0x20000000;
-    cpu->isar.id_mmfr2 = 0x01230000;
-    cpu->isar.id_mmfr3 = 0x00002111;
-    cpu->isar.id_isar0 = 0x00101111;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232041;
-    cpu->isar.id_isar3 = 0x11112131;
-    cpu->isar.id_isar4 = 0x00111142;
-    cpu->isar.dbgdidr = 0x35141000;
-    cpu->clidr = (1 << 27) | (1 << 24) | 3;
-    cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
-    cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
-    define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
-}
-
-#ifndef CONFIG_USER_ONLY
-static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
-    MachineState *ms = MACHINE(qdev_get_machine());
-
-    /*
-     * Linux wants the number of processors from here.
-     * Might as well set the interrupt-controller bit too.
-     */
-    return ((ms->smp.cpus - 1) << 24) | (1 << 23);
-}
-#endif
-
-static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
-#ifndef CONFIG_USER_ONLY
-    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
-      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
-      .writefn = arm_cp_write_ignore, },
-#endif
-    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
-};
-
-static void cortex_a7_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a7";
-    set_feature(&cpu->env, ARM_FEATURE_V7VE);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
-    cpu->midr = 0x410fc075;
-    cpu->reset_fpsid = 0x41023075;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x11111111;
-    cpu->ctr = 0x84448003;
-    cpu->reset_sctlr = 0x00c50078;
-    cpu->isar.id_pfr0 = 0x00001131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x02010555;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10101105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01240000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    /*
-     * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
-     * table 4-41 gives 0x02101110, which includes the arm div insns.
-     */
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232041;
-    cpu->isar.id_isar3 = 0x11112131;
-    cpu->isar.id_isar4 = 0x10011142;
-    cpu->isar.dbgdidr = 0x3515f005;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
-    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
-    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
-    define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
-}
-
-static void cortex_a15_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a15";
-    set_feature(&cpu->env, ARM_FEATURE_V7VE);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
-    cpu->midr = 0x412fc0f1;
-    cpu->reset_fpsid = 0x410430f0;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x11111111;
-    cpu->ctr = 0x8444c004;
-    cpu->reset_sctlr = 0x00c50078;
-    cpu->isar.id_pfr0 = 0x00001131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x02010555;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10201105;
-    cpu->isar.id_mmfr1 = 0x20000000;
-    cpu->isar.id_mmfr2 = 0x01240000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232041;
-    cpu->isar.id_isar3 = 0x11112131;
-    cpu->isar.id_isar4 = 0x10011142;
-    cpu->isar.dbgdidr = 0x3515f021;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
-    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
-    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
-    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
-}
-
-#ifndef TARGET_AARCH64
-/*
- * -cpu max: a CPU with as many features enabled as our emulation supports.
- * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
- * this only needs to handle 32 bits, and need not care about KVM.
- */
-static void arm_max_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cortex_a15_initfn(obj);
-
-    /* old-style VFP short-vector support */
-    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
-
-#ifdef CONFIG_USER_ONLY
-    /*
-     * We don't set these in system emulation mode for the moment,
-     * since we don't correctly set (all of) the ID registers to
-     * advertise them.
-     */
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    {
-        uint32_t t;
-
-        t = cpu->isar.id_isar5;
-        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-        cpu->isar.id_isar5 = t;
-
-        t = cpu->isar.id_isar6;
-        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-        cpu->isar.id_isar6 = t;
-
-        t = cpu->isar.mvfr1;
-        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-        cpu->isar.mvfr1 = t;
-
-        t = cpu->isar.mvfr2;
-        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-        cpu->isar.mvfr2 = t;
-
-        t = cpu->isar.id_mmfr3;
-        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-        cpu->isar.id_mmfr3 = t;
-
-        t = cpu->isar.id_mmfr4;
-        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-        cpu->isar.id_mmfr4 = t;
-
-        t = cpu->isar.id_pfr0;
-        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-        cpu->isar.id_pfr0 = t;
-    }
-#endif
-}
-#endif
-
-#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
-
-static const ARMCPUInfo arm_cpus[] = {
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-    { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
-    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
-    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
-    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
-#ifndef TARGET_AARCH64
-    { .name = "max",         .initfn = arm_max_initfn },
-#endif
-#ifdef CONFIG_USER_ONLY
-    { .name = "any",         .initfn = arm_max_initfn },
-#endif
-#endif
-};
-
 static Property arm_cpu_properties[] = {
     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
     DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
@@ -2386,21 +2065,11 @@ static const TypeInfo arm_cpu_type_info = {
 
 static void arm_cpu_register_types(void)
 {
-    const size_t cpu_count = ARRAY_SIZE(arm_cpus);
-
     type_register_static(&arm_cpu_type_info);
 
 #ifdef CONFIG_KVM
     type_register_static(&host_arm_cpu_type_info);
 #endif
-
-    if (cpu_count) {
-        size_t i;
-
-        for (i = 0; i < cpu_count; ++i) {
-            arm_cpu_register(&arm_cpus[i]);
-        }
-    }
 }
 
 type_init(arm_cpu_register_types)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index fb07a336939..b420c8c555c 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -15,6 +15,9 @@
 #endif /* CONFIG_TCG */
 #include "internals.h"
 #include "target/arm/idau.h"
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/boards.h"
+#endif
 
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
@@ -255,6 +258,236 @@ static void arm11mpcore_initfn(Object *obj)
     cpu->reset_auxcr = 1;
 }
 
+static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
+    { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    REGINFO_SENTINEL
+};
+
+static void cortex_a8_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a8";
+    set_feature(&cpu->env, ARM_FEATURE_V7);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    cpu->midr = 0x410fc080;
+    cpu->reset_fpsid = 0x410330c0;
+    cpu->isar.mvfr0 = 0x11110222;
+    cpu->isar.mvfr1 = 0x00011111;
+    cpu->ctr = 0x82048004;
+    cpu->reset_sctlr = 0x00c50078;
+    cpu->isar.id_pfr0 = 0x1031;
+    cpu->isar.id_pfr1 = 0x11;
+    cpu->isar.id_dfr0 = 0x400;
+    cpu->id_afr0 = 0;
+    cpu->isar.id_mmfr0 = 0x31100003;
+    cpu->isar.id_mmfr1 = 0x20000000;
+    cpu->isar.id_mmfr2 = 0x01202000;
+    cpu->isar.id_mmfr3 = 0x11;
+    cpu->isar.id_isar0 = 0x00101111;
+    cpu->isar.id_isar1 = 0x12112111;
+    cpu->isar.id_isar2 = 0x21232031;
+    cpu->isar.id_isar3 = 0x11112131;
+    cpu->isar.id_isar4 = 0x00111142;
+    cpu->isar.dbgdidr = 0x15141000;
+    cpu->clidr = (1 << 27) | (2 << 24) | 3;
+    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
+    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
+    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
+    cpu->reset_auxcr = 2;
+    define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
+}
+
+static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
+    /*
+     * power_control should be set to maximum latency. Again,
+     * default to 0 and set by private hook
+     */
+    { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
+      .access = PL1_RW, .resetvalue = 0,
+      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
+    { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
+      .access = PL1_RW, .resetvalue = 0,
+      .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
+    { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
+      .access = PL1_RW, .resetvalue = 0,
+      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
+    { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
+      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+    /* TLB lockdown control */
+    { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
+      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
+    { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
+      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
+    { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
+      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+    { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
+      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+    { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
+      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+    REGINFO_SENTINEL
+};
+
+static void cortex_a9_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a9";
+    set_feature(&cpu->env, ARM_FEATURE_V7);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    /*
+     * Note that A9 supports the MP extensions even for
+     * A9UP and single-core A9MP (which are both different
+     * and valid configurations; we don't model A9UP).
+     */
+    set_feature(&cpu->env, ARM_FEATURE_V7MP);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR);
+    cpu->midr = 0x410fc090;
+    cpu->reset_fpsid = 0x41033090;
+    cpu->isar.mvfr0 = 0x11110222;
+    cpu->isar.mvfr1 = 0x01111111;
+    cpu->ctr = 0x80038003;
+    cpu->reset_sctlr = 0x00c50078;
+    cpu->isar.id_pfr0 = 0x1031;
+    cpu->isar.id_pfr1 = 0x11;
+    cpu->isar.id_dfr0 = 0x000;
+    cpu->id_afr0 = 0;
+    cpu->isar.id_mmfr0 = 0x00100103;
+    cpu->isar.id_mmfr1 = 0x20000000;
+    cpu->isar.id_mmfr2 = 0x01230000;
+    cpu->isar.id_mmfr3 = 0x00002111;
+    cpu->isar.id_isar0 = 0x00101111;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232041;
+    cpu->isar.id_isar3 = 0x11112131;
+    cpu->isar.id_isar4 = 0x00111142;
+    cpu->isar.dbgdidr = 0x35141000;
+    cpu->clidr = (1 << 27) | (1 << 24) | 3;
+    cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
+    cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
+    define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
+}
+
+#ifndef CONFIG_USER_ONLY
+static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    MachineState *ms = MACHINE(qdev_get_machine());
+
+    /*
+     * Linux wants the number of processors from here.
+     * Might as well set the interrupt-controller bit too.
+     */
+    return ((ms->smp.cpus - 1) << 24) | (1 << 23);
+}
+#endif
+
+static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
+#ifndef CONFIG_USER_ONLY
+    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
+      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
+      .writefn = arm_cp_write_ignore, },
+#endif
+    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    REGINFO_SENTINEL
+};
+
+static void cortex_a7_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a7";
+    set_feature(&cpu->env, ARM_FEATURE_V7VE);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
+    cpu->midr = 0x410fc075;
+    cpu->reset_fpsid = 0x41023075;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x11111111;
+    cpu->ctr = 0x84448003;
+    cpu->reset_sctlr = 0x00c50078;
+    cpu->isar.id_pfr0 = 0x00001131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x02010555;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01240000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    /*
+     * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
+     * table 4-41 gives 0x02101110, which includes the arm div insns.
+     */
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232041;
+    cpu->isar.id_isar3 = 0x11112131;
+    cpu->isar.id_isar4 = 0x10011142;
+    cpu->isar.dbgdidr = 0x3515f005;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+    define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
+}
+
+static void cortex_a15_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a15";
+    set_feature(&cpu->env, ARM_FEATURE_V7VE);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
+    cpu->midr = 0x412fc0f1;
+    cpu->reset_fpsid = 0x410430f0;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x11111111;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50078;
+    cpu->isar.id_pfr0 = 0x00001131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x02010555;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x20000000;
+    cpu->isar.id_mmfr2 = 0x01240000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232041;
+    cpu->isar.id_isar3 = 0x11112131;
+    cpu->isar.id_isar4 = 0x10011142;
+    cpu->isar.dbgdidr = 0x3515f021;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
+}
+
 static void cortex_m0_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -695,6 +928,77 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
     cc->gdb_core_xml_file = "arm-m-profile.xml";
 }
 
+#ifndef TARGET_AARCH64
+/*
+ * -cpu max: a CPU with as many features enabled as our emulation supports.
+ * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
+ * this only needs to handle 32 bits, and need not care about KVM.
+ */
+static void arm_max_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cortex_a15_initfn(obj);
+
+    /* old-style VFP short-vector support */
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+
+#ifdef CONFIG_USER_ONLY
+    /*
+     * We don't set these in system emulation mode for the moment,
+     * since we don't correctly set (all of) the ID registers to
+     * advertise them.
+     */
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    {
+        uint32_t t;
+
+        t = cpu->isar.id_isar5;
+        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+        cpu->isar.id_isar5 = t;
+
+        t = cpu->isar.id_isar6;
+        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+        cpu->isar.id_isar6 = t;
+
+        t = cpu->isar.mvfr1;
+        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+        cpu->isar.mvfr1 = t;
+
+        t = cpu->isar.mvfr2;
+        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+        cpu->isar.mvfr2 = t;
+
+        t = cpu->isar.id_mmfr3;
+        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+        cpu->isar.id_mmfr3 = t;
+
+        t = cpu->isar.id_mmfr4;
+        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+        cpu->isar.id_mmfr4 = t;
+
+        t = cpu->isar.id_pfr0;
+        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+        cpu->isar.id_pfr0 = t;
+    }
+#endif /* CONFIG_USER_ONLY */
+}
+#endif /* !TARGET_AARCH64 */
+
 static const ARMCPUInfo arm_tcg_cpus[] = {
     { .name = "arm926",      .initfn = arm926_initfn },
     { .name = "arm946",      .initfn = arm946_initfn },
@@ -708,6 +1012,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
     { .name = "arm1136",     .initfn = arm1136_initfn },
     { .name = "arm1176",     .initfn = arm1176_initfn },
     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
+    { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
+    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
+    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
+    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
                              .class_init = arm_v7m_class_init },
     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
@@ -738,6 +1046,12 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
+#ifndef TARGET_AARCH64
+    { .name = "max",         .initfn = arm_max_initfn },
+#endif
+#ifdef CONFIG_USER_ONLY
+    { .name = "any",         .initfn = arm_max_initfn },
+#endif
 };
 
 static const TypeInfo idau_interface_type_info = {
-- 
2.26.2

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Claudio Fontana]

On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
> 
> A KVM-only build won't be able to run TCG cpus, move the
> v7A CPU definitions to cpu_tcg.c.
> 
> Reported-by: Peter Maydell <peter.maydell@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


Here I think it's better to keep the "a15" cpu around,
until we fix the board configuration situation.

I added a patch that does that into my KVM-only build series, to avoid the resulting breakages.

Thanks,

Claudio


> ---
>  target/arm/cpu.c     | 331 -------------------------------------------
>  target/arm/cpu_tcg.c | 314 ++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 314 insertions(+), 331 deletions(-)
> 
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 6865ea76466..ae04884408c 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1922,327 +1922,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
>      return oc;
>  }
>  
> -/* CPU models. These are not needed for the AArch64 linux-user build. */
> -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
> -
> -static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
> -    { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
> -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> -    { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
> -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> -    REGINFO_SENTINEL
> -};
> -
> -static void cortex_a8_initfn(Object *obj)
> -{
> -    ARMCPU *cpu = ARM_CPU(obj);
> -
> -    cpu->dtb_compatible = "arm,cortex-a8";
> -    set_feature(&cpu->env, ARM_FEATURE_V7);
> -    set_feature(&cpu->env, ARM_FEATURE_NEON);
> -    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> -    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> -    set_feature(&cpu->env, ARM_FEATURE_EL3);
> -    cpu->midr = 0x410fc080;
> -    cpu->reset_fpsid = 0x410330c0;
> -    cpu->isar.mvfr0 = 0x11110222;
> -    cpu->isar.mvfr1 = 0x00011111;
> -    cpu->ctr = 0x82048004;
> -    cpu->reset_sctlr = 0x00c50078;
> -    cpu->isar.id_pfr0 = 0x1031;
> -    cpu->isar.id_pfr1 = 0x11;
> -    cpu->isar.id_dfr0 = 0x400;
> -    cpu->id_afr0 = 0;
> -    cpu->isar.id_mmfr0 = 0x31100003;
> -    cpu->isar.id_mmfr1 = 0x20000000;
> -    cpu->isar.id_mmfr2 = 0x01202000;
> -    cpu->isar.id_mmfr3 = 0x11;
> -    cpu->isar.id_isar0 = 0x00101111;
> -    cpu->isar.id_isar1 = 0x12112111;
> -    cpu->isar.id_isar2 = 0x21232031;
> -    cpu->isar.id_isar3 = 0x11112131;
> -    cpu->isar.id_isar4 = 0x00111142;
> -    cpu->isar.dbgdidr = 0x15141000;
> -    cpu->clidr = (1 << 27) | (2 << 24) | 3;
> -    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
> -    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
> -    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
> -    cpu->reset_auxcr = 2;
> -    define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
> -}
> -
> -static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
> -    /*
> -     * power_control should be set to maximum latency. Again,
> -     * default to 0 and set by private hook
> -     */
> -    { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW, .resetvalue = 0,
> -      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
> -    { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
> -      .access = PL1_RW, .resetvalue = 0,
> -      .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
> -    { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
> -      .access = PL1_RW, .resetvalue = 0,
> -      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
> -    { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
> -    /* TLB lockdown control */
> -    { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
> -      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
> -    { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
> -      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
> -    { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
> -      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
> -    { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
> -      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
> -    { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
> -      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
> -    REGINFO_SENTINEL
> -};
> -
> -static void cortex_a9_initfn(Object *obj)
> -{
> -    ARMCPU *cpu = ARM_CPU(obj);
> -
> -    cpu->dtb_compatible = "arm,cortex-a9";
> -    set_feature(&cpu->env, ARM_FEATURE_V7);
> -    set_feature(&cpu->env, ARM_FEATURE_NEON);
> -    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> -    set_feature(&cpu->env, ARM_FEATURE_EL3);
> -    /*
> -     * Note that A9 supports the MP extensions even for
> -     * A9UP and single-core A9MP (which are both different
> -     * and valid configurations; we don't model A9UP).
> -     */
> -    set_feature(&cpu->env, ARM_FEATURE_V7MP);
> -    set_feature(&cpu->env, ARM_FEATURE_CBAR);
> -    cpu->midr = 0x410fc090;
> -    cpu->reset_fpsid = 0x41033090;
> -    cpu->isar.mvfr0 = 0x11110222;
> -    cpu->isar.mvfr1 = 0x01111111;
> -    cpu->ctr = 0x80038003;
> -    cpu->reset_sctlr = 0x00c50078;
> -    cpu->isar.id_pfr0 = 0x1031;
> -    cpu->isar.id_pfr1 = 0x11;
> -    cpu->isar.id_dfr0 = 0x000;
> -    cpu->id_afr0 = 0;
> -    cpu->isar.id_mmfr0 = 0x00100103;
> -    cpu->isar.id_mmfr1 = 0x20000000;
> -    cpu->isar.id_mmfr2 = 0x01230000;
> -    cpu->isar.id_mmfr3 = 0x00002111;
> -    cpu->isar.id_isar0 = 0x00101111;
> -    cpu->isar.id_isar1 = 0x13112111;
> -    cpu->isar.id_isar2 = 0x21232041;
> -    cpu->isar.id_isar3 = 0x11112131;
> -    cpu->isar.id_isar4 = 0x00111142;
> -    cpu->isar.dbgdidr = 0x35141000;
> -    cpu->clidr = (1 << 27) | (1 << 24) | 3;
> -    cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
> -    cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
> -    define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
> -}
> -
> -#ifndef CONFIG_USER_ONLY
> -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> -{
> -    MachineState *ms = MACHINE(qdev_get_machine());
> -
> -    /*
> -     * Linux wants the number of processors from here.
> -     * Might as well set the interrupt-controller bit too.
> -     */
> -    return ((ms->smp.cpus - 1) << 24) | (1 << 23);
> -}
> -#endif
> -
> -static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
> -#ifndef CONFIG_USER_ONLY
> -    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
> -      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
> -      .writefn = arm_cp_write_ignore, },
> -#endif
> -    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
> -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> -    REGINFO_SENTINEL
> -};
> -
> -static void cortex_a7_initfn(Object *obj)
> -{
> -    ARMCPU *cpu = ARM_CPU(obj);
> -
> -    cpu->dtb_compatible = "arm,cortex-a7";
> -    set_feature(&cpu->env, ARM_FEATURE_V7VE);
> -    set_feature(&cpu->env, ARM_FEATURE_NEON);
> -    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> -    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> -    set_feature(&cpu->env, ARM_FEATURE_EL2);
> -    set_feature(&cpu->env, ARM_FEATURE_EL3);
> -    set_feature(&cpu->env, ARM_FEATURE_PMU);
> -    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
> -    cpu->midr = 0x410fc075;
> -    cpu->reset_fpsid = 0x41023075;
> -    cpu->isar.mvfr0 = 0x10110222;
> -    cpu->isar.mvfr1 = 0x11111111;
> -    cpu->ctr = 0x84448003;
> -    cpu->reset_sctlr = 0x00c50078;
> -    cpu->isar.id_pfr0 = 0x00001131;
> -    cpu->isar.id_pfr1 = 0x00011011;
> -    cpu->isar.id_dfr0 = 0x02010555;
> -    cpu->id_afr0 = 0x00000000;
> -    cpu->isar.id_mmfr0 = 0x10101105;
> -    cpu->isar.id_mmfr1 = 0x40000000;
> -    cpu->isar.id_mmfr2 = 0x01240000;
> -    cpu->isar.id_mmfr3 = 0x02102211;
> -    /*
> -     * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
> -     * table 4-41 gives 0x02101110, which includes the arm div insns.
> -     */
> -    cpu->isar.id_isar0 = 0x02101110;
> -    cpu->isar.id_isar1 = 0x13112111;
> -    cpu->isar.id_isar2 = 0x21232041;
> -    cpu->isar.id_isar3 = 0x11112131;
> -    cpu->isar.id_isar4 = 0x10011142;
> -    cpu->isar.dbgdidr = 0x3515f005;
> -    cpu->clidr = 0x0a200023;
> -    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
> -    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
> -    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
> -    define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
> -}
> -
> -static void cortex_a15_initfn(Object *obj)
> -{
> -    ARMCPU *cpu = ARM_CPU(obj);
> -
> -    cpu->dtb_compatible = "arm,cortex-a15";
> -    set_feature(&cpu->env, ARM_FEATURE_V7VE);
> -    set_feature(&cpu->env, ARM_FEATURE_NEON);
> -    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> -    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> -    set_feature(&cpu->env, ARM_FEATURE_EL2);
> -    set_feature(&cpu->env, ARM_FEATURE_EL3);
> -    set_feature(&cpu->env, ARM_FEATURE_PMU);
> -    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
> -    cpu->midr = 0x412fc0f1;
> -    cpu->reset_fpsid = 0x410430f0;
> -    cpu->isar.mvfr0 = 0x10110222;
> -    cpu->isar.mvfr1 = 0x11111111;
> -    cpu->ctr = 0x8444c004;
> -    cpu->reset_sctlr = 0x00c50078;
> -    cpu->isar.id_pfr0 = 0x00001131;
> -    cpu->isar.id_pfr1 = 0x00011011;
> -    cpu->isar.id_dfr0 = 0x02010555;
> -    cpu->id_afr0 = 0x00000000;
> -    cpu->isar.id_mmfr0 = 0x10201105;
> -    cpu->isar.id_mmfr1 = 0x20000000;
> -    cpu->isar.id_mmfr2 = 0x01240000;
> -    cpu->isar.id_mmfr3 = 0x02102211;
> -    cpu->isar.id_isar0 = 0x02101110;
> -    cpu->isar.id_isar1 = 0x13112111;
> -    cpu->isar.id_isar2 = 0x21232041;
> -    cpu->isar.id_isar3 = 0x11112131;
> -    cpu->isar.id_isar4 = 0x10011142;
> -    cpu->isar.dbgdidr = 0x3515f021;
> -    cpu->clidr = 0x0a200023;
> -    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
> -    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
> -    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
> -    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
> -}
> -
> -#ifndef TARGET_AARCH64
> -/*
> - * -cpu max: a CPU with as many features enabled as our emulation supports.
> - * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
> - * this only needs to handle 32 bits, and need not care about KVM.
> - */
> -static void arm_max_initfn(Object *obj)
> -{
> -    ARMCPU *cpu = ARM_CPU(obj);
> -
> -    cortex_a15_initfn(obj);
> -
> -    /* old-style VFP short-vector support */
> -    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
> -
> -#ifdef CONFIG_USER_ONLY
> -    /*
> -     * We don't set these in system emulation mode for the moment,
> -     * since we don't correctly set (all of) the ID registers to
> -     * advertise them.
> -     */
> -    set_feature(&cpu->env, ARM_FEATURE_V8);
> -    {
> -        uint32_t t;
> -
> -        t = cpu->isar.id_isar5;
> -        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
> -        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
> -        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
> -        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
> -        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
> -        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
> -        cpu->isar.id_isar5 = t;
> -
> -        t = cpu->isar.id_isar6;
> -        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
> -        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
> -        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
> -        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
> -        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
> -        cpu->isar.id_isar6 = t;
> -
> -        t = cpu->isar.mvfr1;
> -        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
> -        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
> -        cpu->isar.mvfr1 = t;
> -
> -        t = cpu->isar.mvfr2;
> -        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
> -        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
> -        cpu->isar.mvfr2 = t;
> -
> -        t = cpu->isar.id_mmfr3;
> -        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
> -        cpu->isar.id_mmfr3 = t;
> -
> -        t = cpu->isar.id_mmfr4;
> -        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
> -        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
> -        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
> -        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
> -        cpu->isar.id_mmfr4 = t;
> -
> -        t = cpu->isar.id_pfr0;
> -        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
> -        cpu->isar.id_pfr0 = t;
> -    }
> -#endif
> -}
> -#endif
> -
> -#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
> -
> -static const ARMCPUInfo arm_cpus[] = {
> -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
> -    { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
> -    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
> -    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
> -    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
> -#ifndef TARGET_AARCH64
> -    { .name = "max",         .initfn = arm_max_initfn },
> -#endif
> -#ifdef CONFIG_USER_ONLY
> -    { .name = "any",         .initfn = arm_max_initfn },
> -#endif
> -#endif
> -};
> -
>  static Property arm_cpu_properties[] = {
>      DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
>      DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
> @@ -2386,21 +2065,11 @@ static const TypeInfo arm_cpu_type_info = {
>  
>  static void arm_cpu_register_types(void)
>  {
> -    const size_t cpu_count = ARRAY_SIZE(arm_cpus);
> -
>      type_register_static(&arm_cpu_type_info);
>  
>  #ifdef CONFIG_KVM
>      type_register_static(&host_arm_cpu_type_info);
>  #endif
> -
> -    if (cpu_count) {
> -        size_t i;
> -
> -        for (i = 0; i < cpu_count; ++i) {
> -            arm_cpu_register(&arm_cpus[i]);
> -        }
> -    }
>  }
>  
>  type_init(arm_cpu_register_types)
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index fb07a336939..b420c8c555c 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -15,6 +15,9 @@
>  #endif /* CONFIG_TCG */
>  #include "internals.h"
>  #include "target/arm/idau.h"
> +#if !defined(CONFIG_USER_ONLY)
> +#include "hw/boards.h"
> +#endif
>  
>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
> @@ -255,6 +258,236 @@ static void arm11mpcore_initfn(Object *obj)
>      cpu->reset_auxcr = 1;
>  }
>  
> +static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
> +    { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
> +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
> +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    REGINFO_SENTINEL
> +};
> +
> +static void cortex_a8_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    cpu->dtb_compatible = "arm,cortex-a8";
> +    set_feature(&cpu->env, ARM_FEATURE_V7);
> +    set_feature(&cpu->env, ARM_FEATURE_NEON);
> +    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> +    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> +    set_feature(&cpu->env, ARM_FEATURE_EL3);
> +    cpu->midr = 0x410fc080;
> +    cpu->reset_fpsid = 0x410330c0;
> +    cpu->isar.mvfr0 = 0x11110222;
> +    cpu->isar.mvfr1 = 0x00011111;
> +    cpu->ctr = 0x82048004;
> +    cpu->reset_sctlr = 0x00c50078;
> +    cpu->isar.id_pfr0 = 0x1031;
> +    cpu->isar.id_pfr1 = 0x11;
> +    cpu->isar.id_dfr0 = 0x400;
> +    cpu->id_afr0 = 0;
> +    cpu->isar.id_mmfr0 = 0x31100003;
> +    cpu->isar.id_mmfr1 = 0x20000000;
> +    cpu->isar.id_mmfr2 = 0x01202000;
> +    cpu->isar.id_mmfr3 = 0x11;
> +    cpu->isar.id_isar0 = 0x00101111;
> +    cpu->isar.id_isar1 = 0x12112111;
> +    cpu->isar.id_isar2 = 0x21232031;
> +    cpu->isar.id_isar3 = 0x11112131;
> +    cpu->isar.id_isar4 = 0x00111142;
> +    cpu->isar.dbgdidr = 0x15141000;
> +    cpu->clidr = (1 << 27) | (2 << 24) | 3;
> +    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
> +    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
> +    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
> +    cpu->reset_auxcr = 2;
> +    define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
> +}
> +
> +static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
> +    /*
> +     * power_control should be set to maximum latency. Again,
> +     * default to 0 and set by private hook
> +     */
> +    { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
> +      .access = PL1_RW, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
> +    { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
> +      .access = PL1_RW, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
> +    { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
> +      .access = PL1_RW, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
> +    { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
> +      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
> +    /* TLB lockdown control */
> +    { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
> +      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
> +    { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
> +      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
> +    { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
> +      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
> +    { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
> +      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
> +    { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
> +      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
> +    REGINFO_SENTINEL
> +};
> +
> +static void cortex_a9_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    cpu->dtb_compatible = "arm,cortex-a9";
> +    set_feature(&cpu->env, ARM_FEATURE_V7);
> +    set_feature(&cpu->env, ARM_FEATURE_NEON);
> +    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> +    set_feature(&cpu->env, ARM_FEATURE_EL3);
> +    /*
> +     * Note that A9 supports the MP extensions even for
> +     * A9UP and single-core A9MP (which are both different
> +     * and valid configurations; we don't model A9UP).
> +     */
> +    set_feature(&cpu->env, ARM_FEATURE_V7MP);
> +    set_feature(&cpu->env, ARM_FEATURE_CBAR);
> +    cpu->midr = 0x410fc090;
> +    cpu->reset_fpsid = 0x41033090;
> +    cpu->isar.mvfr0 = 0x11110222;
> +    cpu->isar.mvfr1 = 0x01111111;
> +    cpu->ctr = 0x80038003;
> +    cpu->reset_sctlr = 0x00c50078;
> +    cpu->isar.id_pfr0 = 0x1031;
> +    cpu->isar.id_pfr1 = 0x11;
> +    cpu->isar.id_dfr0 = 0x000;
> +    cpu->id_afr0 = 0;
> +    cpu->isar.id_mmfr0 = 0x00100103;
> +    cpu->isar.id_mmfr1 = 0x20000000;
> +    cpu->isar.id_mmfr2 = 0x01230000;
> +    cpu->isar.id_mmfr3 = 0x00002111;
> +    cpu->isar.id_isar0 = 0x00101111;
> +    cpu->isar.id_isar1 = 0x13112111;
> +    cpu->isar.id_isar2 = 0x21232041;
> +    cpu->isar.id_isar3 = 0x11112131;
> +    cpu->isar.id_isar4 = 0x00111142;
> +    cpu->isar.dbgdidr = 0x35141000;
> +    cpu->clidr = (1 << 27) | (1 << 24) | 3;
> +    cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
> +    cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
> +    define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
> +}
> +
> +#ifndef CONFIG_USER_ONLY
> +static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> +    MachineState *ms = MACHINE(qdev_get_machine());
> +
> +    /*
> +     * Linux wants the number of processors from here.
> +     * Might as well set the interrupt-controller bit too.
> +     */
> +    return ((ms->smp.cpus - 1) << 24) | (1 << 23);
> +}
> +#endif
> +
> +static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
> +#ifndef CONFIG_USER_ONLY
> +    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
> +      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
> +      .writefn = arm_cp_write_ignore, },
> +#endif
> +    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
> +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    REGINFO_SENTINEL
> +};
> +
> +static void cortex_a7_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    cpu->dtb_compatible = "arm,cortex-a7";
> +    set_feature(&cpu->env, ARM_FEATURE_V7VE);
> +    set_feature(&cpu->env, ARM_FEATURE_NEON);
> +    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> +    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> +    set_feature(&cpu->env, ARM_FEATURE_EL2);
> +    set_feature(&cpu->env, ARM_FEATURE_EL3);
> +    set_feature(&cpu->env, ARM_FEATURE_PMU);
> +    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
> +    cpu->midr = 0x410fc075;
> +    cpu->reset_fpsid = 0x41023075;
> +    cpu->isar.mvfr0 = 0x10110222;
> +    cpu->isar.mvfr1 = 0x11111111;
> +    cpu->ctr = 0x84448003;
> +    cpu->reset_sctlr = 0x00c50078;
> +    cpu->isar.id_pfr0 = 0x00001131;
> +    cpu->isar.id_pfr1 = 0x00011011;
> +    cpu->isar.id_dfr0 = 0x02010555;
> +    cpu->id_afr0 = 0x00000000;
> +    cpu->isar.id_mmfr0 = 0x10101105;
> +    cpu->isar.id_mmfr1 = 0x40000000;
> +    cpu->isar.id_mmfr2 = 0x01240000;
> +    cpu->isar.id_mmfr3 = 0x02102211;
> +    /*
> +     * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
> +     * table 4-41 gives 0x02101110, which includes the arm div insns.
> +     */
> +    cpu->isar.id_isar0 = 0x02101110;
> +    cpu->isar.id_isar1 = 0x13112111;
> +    cpu->isar.id_isar2 = 0x21232041;
> +    cpu->isar.id_isar3 = 0x11112131;
> +    cpu->isar.id_isar4 = 0x10011142;
> +    cpu->isar.dbgdidr = 0x3515f005;
> +    cpu->clidr = 0x0a200023;
> +    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
> +    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
> +    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
> +    define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
> +}
> +
> +static void cortex_a15_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    cpu->dtb_compatible = "arm,cortex-a15";
> +    set_feature(&cpu->env, ARM_FEATURE_V7VE);
> +    set_feature(&cpu->env, ARM_FEATURE_NEON);
> +    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> +    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
> +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> +    set_feature(&cpu->env, ARM_FEATURE_EL2);
> +    set_feature(&cpu->env, ARM_FEATURE_EL3);
> +    set_feature(&cpu->env, ARM_FEATURE_PMU);
> +    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
> +    cpu->midr = 0x412fc0f1;
> +    cpu->reset_fpsid = 0x410430f0;
> +    cpu->isar.mvfr0 = 0x10110222;
> +    cpu->isar.mvfr1 = 0x11111111;
> +    cpu->ctr = 0x8444c004;
> +    cpu->reset_sctlr = 0x00c50078;
> +    cpu->isar.id_pfr0 = 0x00001131;
> +    cpu->isar.id_pfr1 = 0x00011011;
> +    cpu->isar.id_dfr0 = 0x02010555;
> +    cpu->id_afr0 = 0x00000000;
> +    cpu->isar.id_mmfr0 = 0x10201105;
> +    cpu->isar.id_mmfr1 = 0x20000000;
> +    cpu->isar.id_mmfr2 = 0x01240000;
> +    cpu->isar.id_mmfr3 = 0x02102211;
> +    cpu->isar.id_isar0 = 0x02101110;
> +    cpu->isar.id_isar1 = 0x13112111;
> +    cpu->isar.id_isar2 = 0x21232041;
> +    cpu->isar.id_isar3 = 0x11112131;
> +    cpu->isar.id_isar4 = 0x10011142;
> +    cpu->isar.dbgdidr = 0x3515f021;
> +    cpu->clidr = 0x0a200023;
> +    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
> +    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
> +    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
> +    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
> +}
> +
>  static void cortex_m0_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -695,6 +928,77 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
>      cc->gdb_core_xml_file = "arm-m-profile.xml";
>  }
>  
> +#ifndef TARGET_AARCH64
> +/*
> + * -cpu max: a CPU with as many features enabled as our emulation supports.
> + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
> + * this only needs to handle 32 bits, and need not care about KVM.
> + */
> +static void arm_max_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    cortex_a15_initfn(obj);
> +
> +    /* old-style VFP short-vector support */
> +    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
> +
> +#ifdef CONFIG_USER_ONLY
> +    /*
> +     * We don't set these in system emulation mode for the moment,
> +     * since we don't correctly set (all of) the ID registers to
> +     * advertise them.
> +     */
> +    set_feature(&cpu->env, ARM_FEATURE_V8);
> +    {
> +        uint32_t t;
> +
> +        t = cpu->isar.id_isar5;
> +        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
> +        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
> +        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
> +        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
> +        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
> +        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
> +        cpu->isar.id_isar5 = t;
> +
> +        t = cpu->isar.id_isar6;
> +        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
> +        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
> +        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
> +        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
> +        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
> +        cpu->isar.id_isar6 = t;
> +
> +        t = cpu->isar.mvfr1;
> +        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
> +        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
> +        cpu->isar.mvfr1 = t;
> +
> +        t = cpu->isar.mvfr2;
> +        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
> +        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
> +        cpu->isar.mvfr2 = t;
> +
> +        t = cpu->isar.id_mmfr3;
> +        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
> +        cpu->isar.id_mmfr3 = t;
> +
> +        t = cpu->isar.id_mmfr4;
> +        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
> +        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
> +        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
> +        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
> +        cpu->isar.id_mmfr4 = t;
> +
> +        t = cpu->isar.id_pfr0;
> +        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
> +        cpu->isar.id_pfr0 = t;
> +    }
> +#endif /* CONFIG_USER_ONLY */
> +}
> +#endif /* !TARGET_AARCH64 */
> +
>  static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "arm926",      .initfn = arm926_initfn },
>      { .name = "arm946",      .initfn = arm946_initfn },
> @@ -708,6 +1012,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "arm1136",     .initfn = arm1136_initfn },
>      { .name = "arm1176",     .initfn = arm1176_initfn },
>      { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
> +    { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
> +    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
> +    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
> +    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
>      { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
>                               .class_init = arm_v7m_class_init },
>      { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
> @@ -738,6 +1046,12 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
>      { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
>      { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
> +#ifndef TARGET_AARCH64
> +    { .name = "max",         .initfn = arm_max_initfn },
> +#endif
> +#ifdef CONFIG_USER_ONLY
> +    { .name = "any",         .initfn = arm_max_initfn },
> +#endif
>  };
>  
>  static const TypeInfo idau_interface_type_info = {
> 

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Philippe Mathieu-Daudé]

Hi Peter,

On 3/11/21 11:43 AM, Claudio Fontana wrote:
> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>> KVM requires the target cpu to be at least ARMv8 architecture
>> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
>> "target/arm: Remove KVM support for 32-bit Arm hosts").
>>
>> A KVM-only build won't be able to run TCG cpus, move the
>> v7A CPU definitions to cpu_tcg.c.
>>
>> Reported-by: Peter Maydell <peter.maydell@linaro.org>
>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> 
> Here I think it's better to keep the "a15" cpu around,
> until we fix the board configuration situation.
> 
> I added a patch that does that into my KVM-only build series, to avoid the resulting breakages.

Actually I got a downstream report that this break migration from QEMU
5.2 to QEMU 6.0.

I first thought it was on an old kernel (with 32-bit KVM enabled),
but not, it is for Aarch64 VMs on recent KVM (without 32-bit support)
but the 'virt' machines were started with default Cortex-A15 CPU...

    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");

I'm not sure upstream should care about this case, but I though
maybe you could give me hints about the best way to keep old VMs
working, as this likely affects any distribution. Obviously not
upgrading QEMU is not a solution :)

The simplest seems to revert 82bf7ae84ce and this patch, but I
doubt this will be enough.

Maybe there is some clever thing to do before reverting 82bf7ae84ce,
that could also benefit upstream, by doing something with versioned
machines? I have no idea (yet) how that work and if it could work.

Thanks,

Phil.

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Claudio Fontana]

On 3/18/21 10:47 AM, Philippe Mathieu-Daudé wrote:
> Hi Peter,
> 
> On 3/11/21 11:43 AM, Claudio Fontana wrote:
>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>> KVM requires the target cpu to be at least ARMv8 architecture
>>> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
>>> "target/arm: Remove KVM support for 32-bit Arm hosts").
>>>
>>> A KVM-only build won't be able to run TCG cpus, move the
>>> v7A CPU definitions to cpu_tcg.c.
>>>
>>> Reported-by: Peter Maydell <peter.maydell@linaro.org>
>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>>
>> Here I think it's better to keep the "a15" cpu around,
>> until we fix the board configuration situation.
>>
>> I added a patch that does that into my KVM-only build series, to avoid the resulting breakages.
> 
> Actually I got a downstream report that this break migration from QEMU
> 5.2 to QEMU 6.0.
> 
> I first thought it was on an old kernel (with 32-bit KVM enabled),
> but not, it is for Aarch64 VMs on recent KVM (without 32-bit support)
> but the 'virt' machines were started with default Cortex-A15 CPU...
> 
>     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
> 
> I'm not sure upstream should care about this case, but I though
> maybe you could give me hints about the best way to keep old VMs
> working, as this likely affects any distribution. Obviously not
> upgrading QEMU is not a solution :)
> 
> The simplest seems to revert 82bf7ae84ce and this patch, but I
> doubt this will be enough.
> 
> Maybe there is some clever thing to do before reverting 82bf7ae84ce,
> that could also benefit upstream, by doing something with versioned
> machines? I have no idea (yet) how that work and if it could work.

Does just applying my series fix it?

https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg06463.html

Ie, I have resurrected specifically the a15 to keep things working for "virt".

Patch 22/50. Maybe I am missing something though?

https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg06494.html

Ciao,

Claudio

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Philippe Mathieu-Daudé]

On 3/18/21 10:56 AM, Claudio Fontana wrote:
> On 3/18/21 10:47 AM, Philippe Mathieu-Daudé wrote:
>> Hi Peter,
>>
>> On 3/11/21 11:43 AM, Claudio Fontana wrote:
>>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>>> KVM requires the target cpu to be at least ARMv8 architecture
>>>> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
>>>> "target/arm: Remove KVM support for 32-bit Arm hosts").
>>>>
>>>> A KVM-only build won't be able to run TCG cpus, move the
>>>> v7A CPU definitions to cpu_tcg.c.
>>>>
>>>> Reported-by: Peter Maydell <peter.maydell@linaro.org>
>>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>
>>>
>>> Here I think it's better to keep the "a15" cpu around,
>>> until we fix the board configuration situation.
>>>
>>> I added a patch that does that into my KVM-only build series, to avoid the resulting breakages.
>>
>> Actually I got a downstream report that this break migration from QEMU
>> 5.2 to QEMU 6.0.
>>
>> I first thought it was on an old kernel (with 32-bit KVM enabled),
>> but not, it is for Aarch64 VMs on recent KVM (without 32-bit support)
>> but the 'virt' machines were started with default Cortex-A15 CPU...
>>
>>     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
>>
>> I'm not sure upstream should care about this case, but I though
>> maybe you could give me hints about the best way to keep old VMs
>> working, as this likely affects any distribution. Obviously not
>> upgrading QEMU is not a solution :)
>>
>> The simplest seems to revert 82bf7ae84ce and this patch, but I
>> doubt this will be enough.
>>
>> Maybe there is some clever thing to do before reverting 82bf7ae84ce,
>> that could also benefit upstream, by doing something with versioned
>> machines? I have no idea (yet) how that work and if it could work.
> 
> Does just applying my series fix it?

But we are past soft-freeze so I'm looking for a surgical fix.

I'll send a partial revert for now.

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Philippe Mathieu-Daudé]

On 3/18/21 11:47 AM, Philippe Mathieu-Daudé wrote:
> On 3/18/21 10:56 AM, Claudio Fontana wrote:
>> On 3/18/21 10:47 AM, Philippe Mathieu-Daudé wrote:
>>> Hi Peter,
>>>
>>> On 3/11/21 11:43 AM, Claudio Fontana wrote:
>>>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>>>> KVM requires the target cpu to be at least ARMv8 architecture
>>>>> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
>>>>> "target/arm: Remove KVM support for 32-bit Arm hosts").
>>>>>
>>>>> A KVM-only build won't be able to run TCG cpus, move the
>>>>> v7A CPU definitions to cpu_tcg.c.
>>>>>
>>>>> Reported-by: Peter Maydell <peter.maydell@linaro.org>
>>>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>>
>>>>
>>>> Here I think it's better to keep the "a15" cpu around,
>>>> until we fix the board configuration situation.
>>>>
>>>> I added a patch that does that into my KVM-only build series, to avoid the resulting breakages.
>>>
>>> Actually I got a downstream report that this break migration from QEMU
>>> 5.2 to QEMU 6.0.
>>>
>>> I first thought it was on an old kernel (with 32-bit KVM enabled),
>>> but not, it is for Aarch64 VMs on recent KVM (without 32-bit support)
>>> but the 'virt' machines were started with default Cortex-A15 CPU...
>>>
>>>     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
>>>
>>> I'm not sure upstream should care about this case, but I though
>>> maybe you could give me hints about the best way to keep old VMs
>>> working, as this likely affects any distribution. Obviously not
>>> upgrading QEMU is not a solution :)
>>>
>>> The simplest seems to revert 82bf7ae84ce and this patch, but I
>>> doubt this will be enough.
>>>
>>> Maybe there is some clever thing to do before reverting 82bf7ae84ce,
>>> that could also benefit upstream, by doing something with versioned
>>> machines? I have no idea (yet) how that work and if it could work.
>>
>> Does just applying my series fix it?
> 
> But we are past soft-freeze so I'm looking for a surgical fix.
> 
> I'll send a partial revert for now.

Still, I'm not sure it makes sense. If you want to migrate a such
machine, KVM can not virtualize it, so you'll be forced to use TCG
right? In that case cpu_tcg is built in and you have the A15.

IOW the problem is not this patch, it is that since 82bf7ae84ce we
can not migrate A15.

So we need both 1/ revert 82bf7ae84ce and 2/ be sure the kernel
support 32-bit host... Am I missing something?

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Peter Maydell]

On Thu, 18 Mar 2021 at 11:09, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
> Still, I'm not sure it makes sense. If you want to migrate a such
> machine, KVM can not virtualize it, so you'll be forced to use TCG
> right? In that case cpu_tcg is built in and you have the A15.
>
> IOW the problem is not this patch, it is that since 82bf7ae84ce we
> can not migrate A15.

Do you mean "we can't migrate a TCG A15" ? That would be a problem.
Or do you mean "we can't migrate a KVM A15" ? That's entirely
expected when we drop support for KVM A15 :-)
Or do you mean "migration from KVM to TCG doesn't work?" That's
a pre-existing thing I don't expect to work (we don't put anything
in to stop it working, but I'm pretty sure there will be a bunch
of things that mean it doesn't in practice work.)

> So we need both 1/ revert 82bf7ae84ce and 2/ be sure the kernel
> support 32-bit host... Am I missing something?

We're definitely not reverting 82bf7ae84ce if we can avoid it...

thanks
-- PMM

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Philippe Mathieu-Daudé]

On 3/18/21 12:21 PM, Peter Maydell wrote:
> On Thu, 18 Mar 2021 at 11:09, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>> Still, I'm not sure it makes sense. If you want to migrate a such
>> machine, KVM can not virtualize it, so you'll be forced to use TCG
>> right? In that case cpu_tcg is built in and you have the A15.
>>
>> IOW the problem is not this patch, it is that since 82bf7ae84ce we
>> can not migrate A15.
> 
> Do you mean "we can't migrate a TCG A15" ? That would be a problem.

No problem here.

> Or do you mean "we can't migrate a KVM A15" ? That's entirely
> expected when we drop support for KVM A15 :-)

Yes, this is why I mentioned this is mostly a problem for downstream
distributions.

> Or do you mean "migration from KVM to TCG doesn't work?" That's
> a pre-existing thing I don't expect to work (we don't put anything
> in to stop it working, but I'm pretty sure there will be a bunch
> of things that mean it doesn't in practice work.)
> 
>> So we need both 1/ revert 82bf7ae84ce and 2/ be sure the kernel
>> support 32-bit host... Am I missing something?
> 
> We're definitely not reverting 82bf7ae84ce if we can avoid it...

I tend to agree. The problem is for the running VMs started before
82bf7ae84ce (so up to any fork based on v5.2). I don't know what
the forks are supposed to do with the running VMs if they want to
migrate them to newer QEMU (or upgrade the host QEMU).

I don't expect a guest being happy and reliable if we underneath
change its CPU by another one while migrating it...

KVM to TCG is not tested much indeed, and I don't think the performance
impact will be well accepted :)

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Peter Maydell]

On Thu, 18 Mar 2021 at 11:31, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
> I tend to agree. The problem is for the running VMs started before
> 82bf7ae84ce (so up to any fork based on v5.2). I don't know what
> the forks are supposed to do with the running VMs if they want to
> migrate them to newer QEMU (or upgrade the host QEMU).

Anybody with a Cortex-A15 KVM VM is just going to have to stay
with their pre-existing ancient hardware, their pre-existing
host kernel and their pre-existing QEMU binary. That's what
"we deprecated and then dropped support for this" means:
we no longer support running that kind of VM, so users who
were doing it need to either do something else instead, or
else just keep on going with the old versions they have.

thanks
-- PMM

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Andrew Jones]

On Thu, Mar 18, 2021 at 11:38:51AM +0000, Peter Maydell wrote:
> On Thu, 18 Mar 2021 at 11:31, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
> > I tend to agree. The problem is for the running VMs started before
> > 82bf7ae84ce (so up to any fork based on v5.2). I don't know what
> > the forks are supposed to do with the running VMs if they want to
> > migrate them to newer QEMU (or upgrade the host QEMU).
> 
> Anybody with a Cortex-A15 KVM VM is just going to have to stay
> with their pre-existing ancient hardware, their pre-existing
> host kernel and their pre-existing QEMU binary. That's what
> "we deprecated and then dropped support for this" means:
> we no longer support running that kind of VM, so users who
> were doing it need to either do something else instead, or
> else just keep on going with the old versions they have.
>

I strongly agree.

And, downstream-wise, I can't speak for anything but RHEL, but RHEL
cannot have this problem. There are no 32-bit ARM builds for RHEL.

Thanks,
drew

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Claudio Fontana]

On 3/18/21 1:37 PM, Andrew Jones wrote:
> On Thu, Mar 18, 2021 at 11:38:51AM +0000, Peter Maydell wrote:
>> On Thu, 18 Mar 2021 at 11:31, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>> I tend to agree. The problem is for the running VMs started before
>>> 82bf7ae84ce (so up to any fork based on v5.2). I don't know what
>>> the forks are supposed to do with the running VMs if they want to
>>> migrate them to newer QEMU (or upgrade the host QEMU).
>>
>> Anybody with a Cortex-A15 KVM VM is just going to have to stay
>> with their pre-existing ancient hardware, their pre-existing
>> host kernel and their pre-existing QEMU binary. That's what
>> "we deprecated and then dropped support for this" means:
>> we no longer support running that kind of VM, so users who
>> were doing it need to either do something else instead, or
>> else just keep on going with the old versions they have.
>>
> 
> I strongly agree.
> 
> And, downstream-wise, I can't speak for anything but RHEL, but RHEL
> cannot have this problem. There are no 32-bit ARM builds for RHEL.
> 
> Thanks,
> drew
> 

I don't see a strong issue with this either, there is no 32bit support for KVM ARM.

Thanks,

Claudio

Re: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Philippe Mathieu-Daudé]

On 3/18/21 1:50 PM, Claudio Fontana wrote:
> On 3/18/21 1:37 PM, Andrew Jones wrote:
>> On Thu, Mar 18, 2021 at 11:38:51AM +0000, Peter Maydell wrote:
>>> On Thu, 18 Mar 2021 at 11:31, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>>> I tend to agree. The problem is for the running VMs started before
>>>> 82bf7ae84ce (so up to any fork based on v5.2). I don't know what
>>>> the forks are supposed to do with the running VMs if they want to
>>>> migrate them to newer QEMU (or upgrade the host QEMU).
>>>
>>> Anybody with a Cortex-A15 KVM VM is just going to have to stay
>>> with their pre-existing ancient hardware, their pre-existing
>>> host kernel and their pre-existing QEMU binary. That's what
>>> "we deprecated and then dropped support for this" means:
>>> we no longer support running that kind of VM, so users who
>>> were doing it need to either do something else instead, or
>>> else just keep on going with the old versions they have.
>>>
>>
>> I strongly agree.
>>
>> And, downstream-wise, I can't speak for anything but RHEL, but RHEL
>> cannot have this problem. There are no 32-bit ARM builds for RHEL.

Great then. Sorry for the confusion.

> I don't see a strong issue with this either, there is no 32bit support for KVM ARM.

Re: [PATCH v2 0/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Peter Maydell]

On Sun, 21 Feb 2021 at 22:26, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> KVM requires the target cpu to be at least ARMv8 architecture.
>
> Restrict the last ARMv7 CPUs (A-profile) to TCG.
>
> Series almost fully reviewed (missing review is trivial code style).
>
> Since v1: Only include patches which don't depends on  previous series
>
> Philippe Mathieu-Daudé (3):
>   target/arm: Restrict v8M IDAU to TCG
>   target/arm/cpu: Update coding style to make checkpatch.pl happy
>   target/arm: Restrict v7A TCG cpus to TCG accel

I've applied patches 1 and 2 to target-arm.next, but patch 3 doesn't
apply (maybe a conflict with something else I've already queued in
target-arm.next). Could you rebase patch 3 once I've sent out/merged the
next arm pullreq and resend, please?

thanks
-- PMM

Re: [PATCH v2 0/3] target/arm: Restrict v7A TCG cpus to TCG accel

[Philippe Mathieu-Daudé]

On 3/5/21 3:38 PM, Peter Maydell wrote:
> On Sun, 21 Feb 2021 at 22:26, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> KVM requires the target cpu to be at least ARMv8 architecture.
>>
>> Restrict the last ARMv7 CPUs (A-profile) to TCG.
>>
>> Series almost fully reviewed (missing review is trivial code style).
>>
>> Since v1: Only include patches which don't depends on  previous series
>>
>> Philippe Mathieu-Daudé (3):
>>   target/arm: Restrict v8M IDAU to TCG
>>   target/arm/cpu: Update coding style to make checkpatch.pl happy
>>   target/arm: Restrict v7A TCG cpus to TCG accel
> 
> I've applied patches 1 and 2 to target-arm.next, but patch 3 doesn't
> apply (maybe a conflict with something else I've already queued in
> target-arm.next). Could you rebase patch 3 once I've sent out/merged the
> next arm pullreq and resend, please?

This is because of:

commit ed84a60ca80c403749c1fc1bab27c85d8edba39d
Author: Rebecca Cran <rebecca@nuviainc.com>
Date:   Tue Feb 16 15:45:43 2021 -0700

    target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

    Enable FEAT_SSBS for the "max" 32-bit CPU.

    Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20210216224543.16142-4-rebecca@nuviainc.com
    [PMM: fix typo causing compilation failure]
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..058672c9776 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2217,6 +2217,10 @@ static void arm_max_initfn(Object *obj)
         t = cpu->isar.id_pfr0;
         t = FIELD_DP32(t, ID_PFR0, DIT, 1);
         cpu->isar.id_pfr0 = t;
+
+        t = cpu->isar.id_pfr2;
+        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+        cpu->isar.id_pfr2 = t;
     }
 #endif
 }

Note this series' patch #3 was following #2. With #2 alone we get:

commit dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date:   Sun Feb 21 23:26:16 2021 +0100

    target/arm/cpu: Update coding style to make checkpatch.pl happy

    We will move this code in the next commit. Clean it up
    first to avoid checkpatch.pl errors.

With next commit:

commit 9aee50eefba8c39d17759c7def3ba5a899c86271
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Mon Feb 15 10:32:07 2021 +0000

    hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces

You might want to remove it, or take this series respin, or ignore
this discrepancy in description :)

Thanks,

Phil.