* [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 8:43 ` Carlo Caione
0 siblings, 0 replies; 16+ messages in thread
From: Carlo Caione @ 2022-12-19 8:43 UTC (permalink / raw)
To: David Airlie, Martin Blumenstingl, Jerome Brunet, Daniel Vetter,
Kevin Hilman, Neil Armstrong
Cc: linux-amlogic, dri-devel, linux-kernel, linux-arm-kernel, Carlo Caione
Having a bigger number of FIFO lines held after vsync is only useful to
SoCs using AFBC to give time to the AFBC decoder to be reset, configured
and enabled again.
For SoCs not using AFBC this, on the contrary, is causing on some
displays issues and a few pixels vertical offset in the displayed image.
Conditionally increase the number of lines held after vsync only for
SoCs using AFBC, leaving the default value for all the others.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
Fix display issues for amlogic SoCs not using AFBC
In 24e0d4058eff the number of lines held after VSYNC was incremented to give
time to the AFBC decoder to do its job. This is causing an issue (seen on
S905x) where the image (on some panels) is dislayed with a vertical offset.
With this patch we try to keep the fix only when AFBC is actually used
filtering on the SoC type.
To: Neil Armstrong <neil.armstrong@linaro.org>
To: David Airlie <airlied@gmail.com>
To: Daniel Vetter <daniel@ffwll.ch>
To: Kevin Hilman <khilman@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/gpu/drm/meson/meson_viu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index d4b907889a21..cd399b0b7181 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -436,15 +436,14 @@ void meson_viu_init(struct meson_drm *priv)
/* Initialize OSD1 fifo control register */
reg = VIU_OSD_DDR_PRIORITY_URGENT |
- VIU_OSD_HOLD_FIFO_LINES(31) |
VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
- reg |= VIU_OSD_BURST_LENGTH_32;
+ reg |= (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31));
else
- reg |= VIU_OSD_BURST_LENGTH_64;
+ reg |= (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
---
base-commit: 84e57d292203a45c96dbcb2e6be9dd80961d981a
change-id: 20221216-afbc_s905x-4baf5fdc9970
Best regards,
--
Carlo Caione
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 8:43 ` Carlo Caione
0 siblings, 0 replies; 16+ messages in thread
From: Carlo Caione @ 2022-12-19 8:43 UTC (permalink / raw)
To: David Airlie, Martin Blumenstingl, Jerome Brunet, Daniel Vetter,
Kevin Hilman, Neil Armstrong
Cc: linux-amlogic, dri-devel, linux-kernel, linux-arm-kernel, Carlo Caione
Having a bigger number of FIFO lines held after vsync is only useful to
SoCs using AFBC to give time to the AFBC decoder to be reset, configured
and enabled again.
For SoCs not using AFBC this, on the contrary, is causing on some
displays issues and a few pixels vertical offset in the displayed image.
Conditionally increase the number of lines held after vsync only for
SoCs using AFBC, leaving the default value for all the others.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
Fix display issues for amlogic SoCs not using AFBC
In 24e0d4058eff the number of lines held after VSYNC was incremented to give
time to the AFBC decoder to do its job. This is causing an issue (seen on
S905x) where the image (on some panels) is dislayed with a vertical offset.
With this patch we try to keep the fix only when AFBC is actually used
filtering on the SoC type.
To: Neil Armstrong <neil.armstrong@linaro.org>
To: David Airlie <airlied@gmail.com>
To: Daniel Vetter <daniel@ffwll.ch>
To: Kevin Hilman <khilman@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/gpu/drm/meson/meson_viu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index d4b907889a21..cd399b0b7181 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -436,15 +436,14 @@ void meson_viu_init(struct meson_drm *priv)
/* Initialize OSD1 fifo control register */
reg = VIU_OSD_DDR_PRIORITY_URGENT |
- VIU_OSD_HOLD_FIFO_LINES(31) |
VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
- reg |= VIU_OSD_BURST_LENGTH_32;
+ reg |= (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31));
else
- reg |= VIU_OSD_BURST_LENGTH_64;
+ reg |= (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
---
base-commit: 84e57d292203a45c96dbcb2e6be9dd80961d981a
change-id: 20221216-afbc_s905x-4baf5fdc9970
Best regards,
--
Carlo Caione
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 8:43 ` Carlo Caione
0 siblings, 0 replies; 16+ messages in thread
From: Carlo Caione @ 2022-12-19 8:43 UTC (permalink / raw)
To: David Airlie, Martin Blumenstingl, Jerome Brunet, Daniel Vetter,
Kevin Hilman, Neil Armstrong
Cc: linux-amlogic, dri-devel, linux-kernel, linux-arm-kernel, Carlo Caione
Having a bigger number of FIFO lines held after vsync is only useful to
SoCs using AFBC to give time to the AFBC decoder to be reset, configured
and enabled again.
For SoCs not using AFBC this, on the contrary, is causing on some
displays issues and a few pixels vertical offset in the displayed image.
Conditionally increase the number of lines held after vsync only for
SoCs using AFBC, leaving the default value for all the others.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
Fix display issues for amlogic SoCs not using AFBC
In 24e0d4058eff the number of lines held after VSYNC was incremented to give
time to the AFBC decoder to do its job. This is causing an issue (seen on
S905x) where the image (on some panels) is dislayed with a vertical offset.
With this patch we try to keep the fix only when AFBC is actually used
filtering on the SoC type.
To: Neil Armstrong <neil.armstrong@linaro.org>
To: David Airlie <airlied@gmail.com>
To: Daniel Vetter <daniel@ffwll.ch>
To: Kevin Hilman <khilman@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/gpu/drm/meson/meson_viu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index d4b907889a21..cd399b0b7181 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -436,15 +436,14 @@ void meson_viu_init(struct meson_drm *priv)
/* Initialize OSD1 fifo control register */
reg = VIU_OSD_DDR_PRIORITY_URGENT |
- VIU_OSD_HOLD_FIFO_LINES(31) |
VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
- reg |= VIU_OSD_BURST_LENGTH_32;
+ reg |= (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31));
else
- reg |= VIU_OSD_BURST_LENGTH_64;
+ reg |= (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
---
base-commit: 84e57d292203a45c96dbcb2e6be9dd80961d981a
change-id: 20221216-afbc_s905x-4baf5fdc9970
Best regards,
--
Carlo Caione
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 8:43 ` Carlo Caione
0 siblings, 0 replies; 16+ messages in thread
From: Carlo Caione @ 2022-12-19 8:43 UTC (permalink / raw)
To: David Airlie, Martin Blumenstingl, Jerome Brunet, Daniel Vetter,
Kevin Hilman, Neil Armstrong
Cc: linux-arm-kernel, linux-amlogic, linux-kernel, dri-devel, Carlo Caione
Having a bigger number of FIFO lines held after vsync is only useful to
SoCs using AFBC to give time to the AFBC decoder to be reset, configured
and enabled again.
For SoCs not using AFBC this, on the contrary, is causing on some
displays issues and a few pixels vertical offset in the displayed image.
Conditionally increase the number of lines held after vsync only for
SoCs using AFBC, leaving the default value for all the others.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
Fix display issues for amlogic SoCs not using AFBC
In 24e0d4058eff the number of lines held after VSYNC was incremented to give
time to the AFBC decoder to do its job. This is causing an issue (seen on
S905x) where the image (on some panels) is dislayed with a vertical offset.
With this patch we try to keep the fix only when AFBC is actually used
filtering on the SoC type.
To: Neil Armstrong <neil.armstrong@linaro.org>
To: David Airlie <airlied@gmail.com>
To: Daniel Vetter <daniel@ffwll.ch>
To: Kevin Hilman <khilman@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/gpu/drm/meson/meson_viu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index d4b907889a21..cd399b0b7181 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -436,15 +436,14 @@ void meson_viu_init(struct meson_drm *priv)
/* Initialize OSD1 fifo control register */
reg = VIU_OSD_DDR_PRIORITY_URGENT |
- VIU_OSD_HOLD_FIFO_LINES(31) |
VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
- reg |= VIU_OSD_BURST_LENGTH_32;
+ reg |= (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31));
else
- reg |= VIU_OSD_BURST_LENGTH_64;
+ reg |= (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
---
base-commit: 84e57d292203a45c96dbcb2e6be9dd80961d981a
change-id: 20221216-afbc_s905x-4baf5fdc9970
Best regards,
--
Carlo Caione
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
2022-12-19 8:43 ` Carlo Caione
(?)
(?)
@ 2022-12-19 11:00 ` Martin Blumenstingl
-1 siblings, 0 replies; 16+ messages in thread
From: Martin Blumenstingl @ 2022-12-19 11:00 UTC (permalink / raw)
To: Carlo Caione
Cc: David Airlie, Jerome Brunet, Daniel Vetter, Kevin Hilman,
Neil Armstrong, linux-amlogic, dri-devel, linux-kernel,
linux-arm-kernel
Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
On the 32-bit SoCs (for which VPU support is not upstream yet) it has
caused screen tearing instead of shifting the image.
> Conditionally increase the number of lines held after vsync only for
> SoCs using AFBC, leaving the default value for all the others.
That was also my approach (for a not-yet-upstream patch).
Since it's affecting already supported SoCs I suggest adding
"Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
is applying the patch).
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 11:00 ` Martin Blumenstingl
0 siblings, 0 replies; 16+ messages in thread
From: Martin Blumenstingl @ 2022-12-19 11:00 UTC (permalink / raw)
To: Carlo Caione
Cc: Neil Armstrong, Kevin Hilman, linux-kernel, dri-devel,
linux-amlogic, linux-arm-kernel, Jerome Brunet
Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
On the 32-bit SoCs (for which VPU support is not upstream yet) it has
caused screen tearing instead of shifting the image.
> Conditionally increase the number of lines held after vsync only for
> SoCs using AFBC, leaving the default value for all the others.
That was also my approach (for a not-yet-upstream patch).
Since it's affecting already supported SoCs I suggest adding
"Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
is applying the patch).
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 11:00 ` Martin Blumenstingl
0 siblings, 0 replies; 16+ messages in thread
From: Martin Blumenstingl @ 2022-12-19 11:00 UTC (permalink / raw)
To: Carlo Caione
Cc: David Airlie, Jerome Brunet, Daniel Vetter, Kevin Hilman,
Neil Armstrong, linux-amlogic, dri-devel, linux-kernel,
linux-arm-kernel
Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
On the 32-bit SoCs (for which VPU support is not upstream yet) it has
caused screen tearing instead of shifting the image.
> Conditionally increase the number of lines held after vsync only for
> SoCs using AFBC, leaving the default value for all the others.
That was also my approach (for a not-yet-upstream patch).
Since it's affecting already supported SoCs I suggest adding
"Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
is applying the patch).
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 11:00 ` Martin Blumenstingl
0 siblings, 0 replies; 16+ messages in thread
From: Martin Blumenstingl @ 2022-12-19 11:00 UTC (permalink / raw)
To: Carlo Caione
Cc: David Airlie, Jerome Brunet, Daniel Vetter, Kevin Hilman,
Neil Armstrong, linux-amlogic, dri-devel, linux-kernel,
linux-arm-kernel
Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
On the 32-bit SoCs (for which VPU support is not upstream yet) it has
caused screen tearing instead of shifting the image.
> Conditionally increase the number of lines held after vsync only for
> SoCs using AFBC, leaving the default value for all the others.
That was also my approach (for a not-yet-upstream patch).
Since it's affecting already supported SoCs I suggest adding
"Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
is applying the patch).
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
2022-12-19 11:00 ` Martin Blumenstingl
(?)
(?)
@ 2022-12-19 13:39 ` Neil Armstrong
-1 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2022-12-19 13:39 UTC (permalink / raw)
To: Martin Blumenstingl, Carlo Caione
Cc: David Airlie, Jerome Brunet, Daniel Vetter, Kevin Hilman,
linux-amlogic, dri-devel, linux-kernel, linux-arm-kernel
On 19/12/2022 12:00, Martin Blumenstingl wrote:
> Hi Carlo,
>
> On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>>
>> Having a bigger number of FIFO lines held after vsync is only useful to
>> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
>> and enabled again.
>>
>> For SoCs not using AFBC this, on the contrary, is causing on some
>> displays issues and a few pixels vertical offset in the displayed image.
> On the 32-bit SoCs (for which VPU support is not upstream yet) it has
> caused screen tearing instead of shifting the image.
>
>> Conditionally increase the number of lines held after vsync only for
>> SoCs using AFBC, leaving the default value for all the others.
> That was also my approach (for a not-yet-upstream patch).
> Since it's affecting already supported SoCs I suggest adding
> "Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
> is applying the patch).
>
> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Yep I'll add the Fixes tag when applying
Thank Carlo !
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 13:39 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2022-12-19 13:39 UTC (permalink / raw)
To: Martin Blumenstingl, Carlo Caione
Cc: Kevin Hilman, linux-kernel, dri-devel, linux-amlogic,
linux-arm-kernel, Jerome Brunet
On 19/12/2022 12:00, Martin Blumenstingl wrote:
> Hi Carlo,
>
> On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>>
>> Having a bigger number of FIFO lines held after vsync is only useful to
>> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
>> and enabled again.
>>
>> For SoCs not using AFBC this, on the contrary, is causing on some
>> displays issues and a few pixels vertical offset in the displayed image.
> On the 32-bit SoCs (for which VPU support is not upstream yet) it has
> caused screen tearing instead of shifting the image.
>
>> Conditionally increase the number of lines held after vsync only for
>> SoCs using AFBC, leaving the default value for all the others.
> That was also my approach (for a not-yet-upstream patch).
> Since it's affecting already supported SoCs I suggest adding
> "Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
> is applying the patch).
>
> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Yep I'll add the Fixes tag when applying
Thank Carlo !
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 13:39 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2022-12-19 13:39 UTC (permalink / raw)
To: Martin Blumenstingl, Carlo Caione
Cc: David Airlie, Jerome Brunet, Daniel Vetter, Kevin Hilman,
linux-amlogic, dri-devel, linux-kernel, linux-arm-kernel
On 19/12/2022 12:00, Martin Blumenstingl wrote:
> Hi Carlo,
>
> On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>>
>> Having a bigger number of FIFO lines held after vsync is only useful to
>> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
>> and enabled again.
>>
>> For SoCs not using AFBC this, on the contrary, is causing on some
>> displays issues and a few pixels vertical offset in the displayed image.
> On the 32-bit SoCs (for which VPU support is not upstream yet) it has
> caused screen tearing instead of shifting the image.
>
>> Conditionally increase the number of lines held after vsync only for
>> SoCs using AFBC, leaving the default value for all the others.
> That was also my approach (for a not-yet-upstream patch).
> Since it's affecting already supported SoCs I suggest adding
> "Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
> is applying the patch).
>
> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Yep I'll add the Fixes tag when applying
Thank Carlo !
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2022-12-19 13:39 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2022-12-19 13:39 UTC (permalink / raw)
To: Martin Blumenstingl, Carlo Caione
Cc: David Airlie, Jerome Brunet, Daniel Vetter, Kevin Hilman,
linux-amlogic, dri-devel, linux-kernel, linux-arm-kernel
On 19/12/2022 12:00, Martin Blumenstingl wrote:
> Hi Carlo,
>
> On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>>
>> Having a bigger number of FIFO lines held after vsync is only useful to
>> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
>> and enabled again.
>>
>> For SoCs not using AFBC this, on the contrary, is causing on some
>> displays issues and a few pixels vertical offset in the displayed image.
> On the 32-bit SoCs (for which VPU support is not upstream yet) it has
> caused screen tearing instead of shifting the image.
>
>> Conditionally increase the number of lines held after vsync only for
>> SoCs using AFBC, leaving the default value for all the others.
> That was also my approach (for a not-yet-upstream patch).
> Since it's affecting already supported SoCs I suggest adding
> "Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
> is applying the patch).
>
> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Yep I'll add the Fixes tag when applying
Thank Carlo !
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
2022-12-19 8:43 ` Carlo Caione
(?)
(?)
@ 2023-01-02 10:00 ` Neil Armstrong
-1 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2023-01-02 10:00 UTC (permalink / raw)
To: Jerome Brunet, David Airlie, Daniel Vetter, Martin Blumenstingl,
Kevin Hilman, Carlo Caione
Cc: dri-devel, linux-arm-kernel, linux-amlogic, linux-kernel
Hi,
On Mon, 19 Dec 2022 09:43:05 +0100, Carlo Caione wrote:
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
>
> [...]
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-fixes)
[1/1] drm/meson: Reduce the FIFO lines held when AFBC is not used
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=3b754ed6d1cd90017e66e5cc16f3923e4a952ffc
--
Neil
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2023-01-02 10:00 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2023-01-02 10:00 UTC (permalink / raw)
To: Jerome Brunet, David Airlie, Daniel Vetter, Martin Blumenstingl,
Kevin Hilman, Carlo Caione
Cc: linux-amlogic, linux-arm-kernel, dri-devel, linux-kernel
Hi,
On Mon, 19 Dec 2022 09:43:05 +0100, Carlo Caione wrote:
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
>
> [...]
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-fixes)
[1/1] drm/meson: Reduce the FIFO lines held when AFBC is not used
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=3b754ed6d1cd90017e66e5cc16f3923e4a952ffc
--
Neil
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2023-01-02 10:00 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2023-01-02 10:00 UTC (permalink / raw)
To: Jerome Brunet, David Airlie, Daniel Vetter, Martin Blumenstingl,
Kevin Hilman, Carlo Caione
Cc: dri-devel, linux-arm-kernel, linux-amlogic, linux-kernel
Hi,
On Mon, 19 Dec 2022 09:43:05 +0100, Carlo Caione wrote:
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
>
> [...]
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-fixes)
[1/1] drm/meson: Reduce the FIFO lines held when AFBC is not used
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=3b754ed6d1cd90017e66e5cc16f3923e4a952ffc
--
Neil
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
@ 2023-01-02 10:00 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2023-01-02 10:00 UTC (permalink / raw)
To: Jerome Brunet, David Airlie, Daniel Vetter, Martin Blumenstingl,
Kevin Hilman, Carlo Caione
Cc: dri-devel, linux-arm-kernel, linux-amlogic, linux-kernel
Hi,
On Mon, 19 Dec 2022 09:43:05 +0100, Carlo Caione wrote:
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
>
> [...]
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-fixes)
[1/1] drm/meson: Reduce the FIFO lines held when AFBC is not used
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=3b754ed6d1cd90017e66e5cc16f3923e4a952ffc
--
Neil
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-01-02 10:06 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-19 8:43 [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used Carlo Caione
2022-12-19 8:43 ` Carlo Caione
2022-12-19 8:43 ` Carlo Caione
2022-12-19 8:43 ` Carlo Caione
2022-12-19 11:00 ` Martin Blumenstingl
2022-12-19 11:00 ` Martin Blumenstingl
2022-12-19 11:00 ` Martin Blumenstingl
2022-12-19 11:00 ` Martin Blumenstingl
2022-12-19 13:39 ` Neil Armstrong
2022-12-19 13:39 ` Neil Armstrong
2022-12-19 13:39 ` Neil Armstrong
2022-12-19 13:39 ` Neil Armstrong
2023-01-02 10:00 ` Neil Armstrong
2023-01-02 10:00 ` Neil Armstrong
2023-01-02 10:00 ` Neil Armstrong
2023-01-02 10:00 ` Neil Armstrong
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