[PATCH v3 0/2] FPGA: TS-7300 FPGA manager

[PATCH v3 0/2] FPGA: TS-7300 FPGA manager

[Florian Fainelli]

Hi all,

This patch series adds support for loading bitstreams into the Altera Cyclone II
connected to an EP9302 on a TS-7300 board.

Changes in v3:

- fix write_init and write_complete signatures

Changes in v2:

- rebased against fpga/for-next
- added defines for configuration bits and delays
- added error mesage if ioremap() fails
- detailed how the configuration through CPLD is done

Florian Fainelli (2):
  ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
  FPGA: Add TS-7300 FPGA manager

 arch/arm/mach-ep93xx/ts72xx.c |  26 +++++++
 drivers/fpga/Kconfig          |   7 ++
 drivers/fpga/Makefile         |   1 +
 drivers/fpga/ts73xx-fpga.c    | 163 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 197 insertions(+)
 create mode 100644 drivers/fpga/ts73xx-fpga.c

-- 
2.9.3

[PATCH v3 0/2] FPGA: TS-7300 FPGA manager

[Florian Fainelli]

Hi all,

This patch series adds support for loading bitstreams into the Altera Cyclone II
connected to an EP9302 on a TS-7300 board.

Changes in v3:

- fix write_init and write_complete signatures

Changes in v2:

- rebased against fpga/for-next
- added defines for configuration bits and delays
- added error mesage if ioremap() fails
- detailed how the configuration through CPLD is done

Florian Fainelli (2):
  ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
  FPGA: Add TS-7300 FPGA manager

 arch/arm/mach-ep93xx/ts72xx.c |  26 +++++++
 drivers/fpga/Kconfig          |   7 ++
 drivers/fpga/Makefile         |   1 +
 drivers/fpga/ts73xx-fpga.c    | 163 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 197 insertions(+)
 create mode 100644 drivers/fpga/ts73xx-fpga.c

-- 
2.9.3

[PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300

[Florian Fainelli]

Register the TS-7300 FPGA manager device drivers which allows us to load
bitstreams into the on-board Altera Cyclone II FPGA.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 3b39ea353d30..acf72ea670ef 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
 	.phy_id		= 1,
 };
 
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+
+/* Relative to EP93XX_CS1_PHYS_BASE */
+#define TS73XX_FPGA_LOADER_BASE		0x03c00000
+
+static struct resource ts73xx_fpga_resources[] = {
+	{
+		.start	= EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
+		.end	= EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device ts73xx_fpga_device = {
+	.name	= "ts73xx-fpga-mgr",
+	.id	= -1,
+	.resource = ts73xx_fpga_resources,
+	.num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
+};
+
+#endif
+
 static void __init ts72xx_init_machine(void)
 {
 	ep93xx_init_devices();
@@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
 	platform_device_register(&ts72xx_wdt_device);
 
 	ep93xx_register_eth(&ts72xx_eth_data, 1);
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+	if (board_is_ts7300())
+		platform_device_register(&ts73xx_fpga_device);
+#endif
 }
 
 MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
-- 
2.9.3

[PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300

[Florian Fainelli]

Register the TS-7300 FPGA manager device drivers which allows us to load
bitstreams into the on-board Altera Cyclone II FPGA.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 3b39ea353d30..acf72ea670ef 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
 	.phy_id		= 1,
 };
 
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+
+/* Relative to EP93XX_CS1_PHYS_BASE */
+#define TS73XX_FPGA_LOADER_BASE		0x03c00000
+
+static struct resource ts73xx_fpga_resources[] = {
+	{
+		.start	= EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
+		.end	= EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device ts73xx_fpga_device = {
+	.name	= "ts73xx-fpga-mgr",
+	.id	= -1,
+	.resource = ts73xx_fpga_resources,
+	.num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
+};
+
+#endif
+
 static void __init ts72xx_init_machine(void)
 {
 	ep93xx_init_devices();
@@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
 	platform_device_register(&ts72xx_wdt_device);
 
 	ep93xx_register_eth(&ts72xx_eth_data, 1);
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+	if (board_is_ts7300())
+		platform_device_register(&ts73xx_fpga_device);
+#endif
 }
 
 MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
-- 
2.9.3

Re: [PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300

[Moritz Fischer]

Hi Florian,

On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Register the TS-7300 FPGA manager device drivers which allows us to load
> bitstreams into the on-board Altera Cyclone II FPGA.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
> index 3b39ea353d30..acf72ea670ef 100644
> --- a/arch/arm/mach-ep93xx/ts72xx.c
> +++ b/arch/arm/mach-ep93xx/ts72xx.c
> @@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
>         .phy_id         = 1,
>  };
>
> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
> +
> +/* Relative to EP93XX_CS1_PHYS_BASE */
> +#define TS73XX_FPGA_LOADER_BASE                0x03c00000
> +
> +static struct resource ts73xx_fpga_resources[] = {
> +       {
> +               .start  = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
> +               .end    = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
> +               .flags  = IORESOURCE_MEM,
> +       },
> +};
> +
> +static struct platform_device ts73xx_fpga_device = {
> +       .name   = "ts73xx-fpga-mgr",
> +       .id     = -1,
> +       .resource = ts73xx_fpga_resources,
> +       .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
> +};
> +
> +#endif
> +
>  static void __init ts72xx_init_machine(void)
>  {
>         ep93xx_init_devices();
> @@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
>         platform_device_register(&ts72xx_wdt_device);
>
>         ep93xx_register_eth(&ts72xx_eth_data, 1);
> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
> +       if (board_is_ts7300())
> +               platform_device_register(&ts73xx_fpga_device);
> +#endif
>  }
>
>  MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
> --
> 2.9.3
>

I think this is backwards, shouldn't this be your [PATCH 2/2]?
Otherwise you're using
the driver before you added it.

Thanks,

Moritz

[PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300

[Moritz Fischer]

Hi Florian,

On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Register the TS-7300 FPGA manager device drivers which allows us to load
> bitstreams into the on-board Altera Cyclone II FPGA.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
> index 3b39ea353d30..acf72ea670ef 100644
> --- a/arch/arm/mach-ep93xx/ts72xx.c
> +++ b/arch/arm/mach-ep93xx/ts72xx.c
> @@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
>         .phy_id         = 1,
>  };
>
> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
> +
> +/* Relative to EP93XX_CS1_PHYS_BASE */
> +#define TS73XX_FPGA_LOADER_BASE                0x03c00000
> +
> +static struct resource ts73xx_fpga_resources[] = {
> +       {
> +               .start  = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
> +               .end    = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
> +               .flags  = IORESOURCE_MEM,
> +       },
> +};
> +
> +static struct platform_device ts73xx_fpga_device = {
> +       .name   = "ts73xx-fpga-mgr",
> +       .id     = -1,
> +       .resource = ts73xx_fpga_resources,
> +       .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
> +};
> +
> +#endif
> +
>  static void __init ts72xx_init_machine(void)
>  {
>         ep93xx_init_devices();
> @@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
>         platform_device_register(&ts72xx_wdt_device);
>
>         ep93xx_register_eth(&ts72xx_eth_data, 1);
> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
> +       if (board_is_ts7300())
> +               platform_device_register(&ts73xx_fpga_device);
> +#endif
>  }
>
>  MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
> --
> 2.9.3
>

I think this is backwards, shouldn't this be your [PATCH 2/2]?
Otherwise you're using
the driver before you added it.

Thanks,

Moritz

Re: [PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300

[Florian Fainelli]

On 12/13/2016 10:14 PM, Moritz Fischer wrote:
> Hi Florian,
> 
> On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>> Register the TS-7300 FPGA manager device drivers which allows us to load
>> bitstreams into the on-board Altera Cyclone II FPGA.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>>  arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
>>  1 file changed, 26 insertions(+)
>>
>> diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
>> index 3b39ea353d30..acf72ea670ef 100644
>> --- a/arch/arm/mach-ep93xx/ts72xx.c
>> +++ b/arch/arm/mach-ep93xx/ts72xx.c
>> @@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
>>         .phy_id         = 1,
>>  };
>>
>> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
>> +
>> +/* Relative to EP93XX_CS1_PHYS_BASE */
>> +#define TS73XX_FPGA_LOADER_BASE                0x03c00000
>> +
>> +static struct resource ts73xx_fpga_resources[] = {
>> +       {
>> +               .start  = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
>> +               .end    = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
>> +               .flags  = IORESOURCE_MEM,
>> +       },
>> +};
>> +
>> +static struct platform_device ts73xx_fpga_device = {
>> +       .name   = "ts73xx-fpga-mgr",
>> +       .id     = -1,
>> +       .resource = ts73xx_fpga_resources,
>> +       .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
>> +};
>> +
>> +#endif
>> +
>>  static void __init ts72xx_init_machine(void)
>>  {
>>         ep93xx_init_devices();
>> @@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
>>         platform_device_register(&ts72xx_wdt_device);
>>
>>         ep93xx_register_eth(&ts72xx_eth_data, 1);
>> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
>> +       if (board_is_ts7300())
>> +               platform_device_register(&ts73xx_fpga_device);
>> +#endif
>>  }
>>
>>  MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
>> --
>> 2.9.3
>>
> 
> I think this is backwards, shouldn't this be your [PATCH 2/2]?
> Otherwise you're using
> the driver before you added it.

I can definitively re-order the patches, although I don't think this
really makes a difference, a driver without device does nothing, and
vice versa.
-- 
Florian

[PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300

[Florian Fainelli]

On 12/13/2016 10:14 PM, Moritz Fischer wrote:
> Hi Florian,
> 
> On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>> Register the TS-7300 FPGA manager device drivers which allows us to load
>> bitstreams into the on-board Altera Cyclone II FPGA.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>>  arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
>>  1 file changed, 26 insertions(+)
>>
>> diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
>> index 3b39ea353d30..acf72ea670ef 100644
>> --- a/arch/arm/mach-ep93xx/ts72xx.c
>> +++ b/arch/arm/mach-ep93xx/ts72xx.c
>> @@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
>>         .phy_id         = 1,
>>  };
>>
>> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
>> +
>> +/* Relative to EP93XX_CS1_PHYS_BASE */
>> +#define TS73XX_FPGA_LOADER_BASE                0x03c00000
>> +
>> +static struct resource ts73xx_fpga_resources[] = {
>> +       {
>> +               .start  = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
>> +               .end    = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
>> +               .flags  = IORESOURCE_MEM,
>> +       },
>> +};
>> +
>> +static struct platform_device ts73xx_fpga_device = {
>> +       .name   = "ts73xx-fpga-mgr",
>> +       .id     = -1,
>> +       .resource = ts73xx_fpga_resources,
>> +       .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
>> +};
>> +
>> +#endif
>> +
>>  static void __init ts72xx_init_machine(void)
>>  {
>>         ep93xx_init_devices();
>> @@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
>>         platform_device_register(&ts72xx_wdt_device);
>>
>>         ep93xx_register_eth(&ts72xx_eth_data, 1);
>> +#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
>> +       if (board_is_ts7300())
>> +               platform_device_register(&ts73xx_fpga_device);
>> +#endif
>>  }
>>
>>  MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
>> --
>> 2.9.3
>>
> 
> I think this is backwards, shouldn't this be your [PATCH 2/2]?
> Otherwise you're using
> the driver before you added it.

I can definitively re-order the patches, although I don't think this
really makes a difference, a driver without device does nothing, and
vice versa.
-- 
Florian

RE: [PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300

[Hartley Sweeten]

On Tuesday, December 13, 2016 7:36 PM, Florian Fainelli wrote:
>
> Register the TS-7300 FPGA manager device drivers which allows us to load
> bitstreams into the on-board Altera Cyclone II FPGA.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)

For the ep93xx core change:

Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>

[PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300

[Hartley Sweeten]

On Tuesday, December 13, 2016 7:36 PM, Florian Fainelli wrote:
>
> Register the TS-7300 FPGA manager device drivers which allows us to load
> bitstreams into the on-board Altera Cyclone II FPGA.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)

For the ep93xx core change:

Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>

[PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Florian Fainelli]

Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.

The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/fpga/Kconfig       |   7 ++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 171 insertions(+)
 create mode 100644 drivers/fpga/ts73xx-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2853a4..d9cbef60db80 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
 	help
 	  FPGA manager driver support for Altera Arria10 SoCFPGA.
 
+config FPGA_MGR_TS73XX
+	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+	depends on ARCH_EP93XX && MACH_TS72XX
+	help
+	  FPGA manager driver support for the Altera Cyclone II FPGA
+	  present on the TS-73xx SBC boards.
+
 config FPGA_MGR_ZYNQ_FPGA
 	tristate "Xilinx Zynq FPGA"
 	depends on ARCH_ZYNQ || COMPILE_TEST
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bcf42a6..a1160169e6d9 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 # FPGA Manager Drivers
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
+obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 
 # FPGA Bridge Drivers
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
new file mode 100644
index 000000000000..38d78d8c6b1e
--- /dev/null
+++ b/drivers/fpga/ts73xx-fpga.c
@@ -0,0 +1,163 @@
+/*
+ * Technologic Systems TS-73xx SBC FPGA loader
+ *
+ * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
+ * TS-7300, heavily based on load_fpga.c in their vendor tree.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/iopoll.h>
+#include <linux/fpga/fpga-mgr.h>
+
+#define TS73XX_FPGA_DATA_REG		0
+#define TS73XX_FPGA_CONFIG_REG		1
+
+#define TS73XX_FPGA_WRITE_DONE		0x1
+#define TS73XX_FPGA_WRITE_DONE_TIMEOUT	1000	/* us */
+#define TS73XX_FPGA_RESET		0x2
+#define TS73XX_FPGA_RESET_LOW_DELAY	30	/* us */
+#define TS73XX_FPGA_RESET_HIGH_DELAY	80	/* us */
+#define TS73XX_FPGA_LOAD_OK		0x4
+#define TS73XX_FPGA_CONFIG_LOAD		0x8
+
+struct ts73xx_fpga_priv {
+	void __iomem	*io_base;
+	struct device	*dev;
+};
+
+static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
+{
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
+				  struct fpga_image_info *info,
+				  const char *buf, size_t count)
+{
+	struct ts73xx_fpga_priv *priv = mgr->priv;
+
+	/* Reset the FPGA */
+	writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	udelay(TS73XX_FPGA_RESET_LOW_DELAY);
+	writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
+
+	return 0;
+}
+
+static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
+			     size_t count)
+{
+	struct ts73xx_fpga_priv *priv = mgr->priv;
+	size_t i = 0;
+	int ret;
+	u8 reg;
+
+	while (count--) {
+		ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
+					 reg, !(reg & TS73XX_FPGA_WRITE_DONE),
+					 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
+		if (ret < 0)
+			return ret;
+
+		writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
+		i++;
+	}
+
+	usleep_range(1000, 2000);
+	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	reg |= TS73XX_FPGA_CONFIG_LOAD;
+	writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	usleep_range(1000, 2000);
+
+	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	reg &= ~TS73XX_FPGA_CONFIG_LOAD;
+	writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+
+	return 0;
+}
+
+static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
+				      struct fpga_image_info *info)
+{
+	struct ts73xx_fpga_priv *priv = mgr->priv;
+	u8 reg;
+
+	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static const struct fpga_manager_ops ts73xx_fpga_ops = {
+	.state		= ts73xx_fpga_state,
+	.write_init	= ts73xx_fpga_write_init,
+	.write		= ts73xx_fpga_write,
+	.write_complete	= ts73xx_fpga_write_complete,
+};
+
+static int ts73xx_fpga_probe(struct platform_device *pdev)
+{
+	struct device *kdev = &pdev->dev;
+	struct ts73xx_fpga_priv *priv;
+	struct resource *res;
+	int err;
+
+	priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = kdev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->io_base = devm_ioremap_resource(kdev, res);
+	if (IS_ERR(priv->io_base)) {
+		dev_err(kdev, "unable to remap registers\n");
+		return PTR_ERR(priv->io_base);
+	}
+
+	err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
+				&ts73xx_fpga_ops, priv);
+	if (err) {
+		dev_err(kdev, "failed to register FPGA manager\n");
+		return err;
+	}
+
+	return err;
+}
+
+static int ts73xx_fpga_remove(struct platform_device *pdev)
+{
+	fpga_mgr_unregister(&pdev->dev);
+
+	return 0;
+}
+
+static struct platform_driver ts73xx_fpga_driver = {
+	.driver	= {
+		.name	= "ts73xx-fpga-mgr",
+	},
+	.probe	= ts73xx_fpga_probe,
+	.remove	= ts73xx_fpga_remove,
+};
+module_platform_driver(ts73xx_fpga_driver);
+
+MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
+MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
+MODULE_LICENSE("GPL v2");
-- 
2.9.3

[PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Florian Fainelli]

Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.

The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/fpga/Kconfig       |   7 ++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 171 insertions(+)
 create mode 100644 drivers/fpga/ts73xx-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2853a4..d9cbef60db80 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
 	help
 	  FPGA manager driver support for Altera Arria10 SoCFPGA.
 
+config FPGA_MGR_TS73XX
+	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+	depends on ARCH_EP93XX && MACH_TS72XX
+	help
+	  FPGA manager driver support for the Altera Cyclone II FPGA
+	  present on the TS-73xx SBC boards.
+
 config FPGA_MGR_ZYNQ_FPGA
 	tristate "Xilinx Zynq FPGA"
 	depends on ARCH_ZYNQ || COMPILE_TEST
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bcf42a6..a1160169e6d9 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 # FPGA Manager Drivers
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
+obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 
 # FPGA Bridge Drivers
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
new file mode 100644
index 000000000000..38d78d8c6b1e
--- /dev/null
+++ b/drivers/fpga/ts73xx-fpga.c
@@ -0,0 +1,163 @@
+/*
+ * Technologic Systems TS-73xx SBC FPGA loader
+ *
+ * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
+ * TS-7300, heavily based on load_fpga.c in their vendor tree.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/iopoll.h>
+#include <linux/fpga/fpga-mgr.h>
+
+#define TS73XX_FPGA_DATA_REG		0
+#define TS73XX_FPGA_CONFIG_REG		1
+
+#define TS73XX_FPGA_WRITE_DONE		0x1
+#define TS73XX_FPGA_WRITE_DONE_TIMEOUT	1000	/* us */
+#define TS73XX_FPGA_RESET		0x2
+#define TS73XX_FPGA_RESET_LOW_DELAY	30	/* us */
+#define TS73XX_FPGA_RESET_HIGH_DELAY	80	/* us */
+#define TS73XX_FPGA_LOAD_OK		0x4
+#define TS73XX_FPGA_CONFIG_LOAD		0x8
+
+struct ts73xx_fpga_priv {
+	void __iomem	*io_base;
+	struct device	*dev;
+};
+
+static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
+{
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
+				  struct fpga_image_info *info,
+				  const char *buf, size_t count)
+{
+	struct ts73xx_fpga_priv *priv = mgr->priv;
+
+	/* Reset the FPGA */
+	writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	udelay(TS73XX_FPGA_RESET_LOW_DELAY);
+	writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
+
+	return 0;
+}
+
+static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
+			     size_t count)
+{
+	struct ts73xx_fpga_priv *priv = mgr->priv;
+	size_t i = 0;
+	int ret;
+	u8 reg;
+
+	while (count--) {
+		ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
+					 reg, !(reg & TS73XX_FPGA_WRITE_DONE),
+					 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
+		if (ret < 0)
+			return ret;
+
+		writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
+		i++;
+	}
+
+	usleep_range(1000, 2000);
+	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	reg |= TS73XX_FPGA_CONFIG_LOAD;
+	writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	usleep_range(1000, 2000);
+
+	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	reg &= ~TS73XX_FPGA_CONFIG_LOAD;
+	writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+
+	return 0;
+}
+
+static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
+				      struct fpga_image_info *info)
+{
+	struct ts73xx_fpga_priv *priv = mgr->priv;
+	u8 reg;
+
+	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+	if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static const struct fpga_manager_ops ts73xx_fpga_ops = {
+	.state		= ts73xx_fpga_state,
+	.write_init	= ts73xx_fpga_write_init,
+	.write		= ts73xx_fpga_write,
+	.write_complete	= ts73xx_fpga_write_complete,
+};
+
+static int ts73xx_fpga_probe(struct platform_device *pdev)
+{
+	struct device *kdev = &pdev->dev;
+	struct ts73xx_fpga_priv *priv;
+	struct resource *res;
+	int err;
+
+	priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = kdev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->io_base = devm_ioremap_resource(kdev, res);
+	if (IS_ERR(priv->io_base)) {
+		dev_err(kdev, "unable to remap registers\n");
+		return PTR_ERR(priv->io_base);
+	}
+
+	err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
+				&ts73xx_fpga_ops, priv);
+	if (err) {
+		dev_err(kdev, "failed to register FPGA manager\n");
+		return err;
+	}
+
+	return err;
+}
+
+static int ts73xx_fpga_remove(struct platform_device *pdev)
+{
+	fpga_mgr_unregister(&pdev->dev);
+
+	return 0;
+}
+
+static struct platform_driver ts73xx_fpga_driver = {
+	.driver	= {
+		.name	= "ts73xx-fpga-mgr",
+	},
+	.probe	= ts73xx_fpga_probe,
+	.remove	= ts73xx_fpga_remove,
+};
+module_platform_driver(ts73xx_fpga_driver);
+
+MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
+MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
+MODULE_LICENSE("GPL v2");
-- 
2.9.3

Re: [PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Moritz Fischer]

Hi Florian,

On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Add support for loading bitstreams on the Altera Cyclone II FPGA
> populated on the TS-7300 board. This is done through the configuration
> and data registers offered through a memory interface between the EP93xx
> SoC and the FPGA via an intermediate CPLD device.
>
> The EP93xx SoC on the TS-7300 does not have direct means of configuring
> the on-board FPGA other than by using the special memory mapped
> interface to the CPLD. No other entity on the system can control the
> FPGA bitstream.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  drivers/fpga/Kconfig       |   7 ++
>  drivers/fpga/Makefile      |   1 +
>  drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 171 insertions(+)
>  create mode 100644 drivers/fpga/ts73xx-fpga.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ce861a2853a4..d9cbef60db80 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
>         help
>           FPGA manager driver support for Altera Arria10 SoCFPGA.
>
> +config FPGA_MGR_TS73XX
> +       tristate "Technologic Systems TS-73xx SBC FPGA Manager"
> +       depends on ARCH_EP93XX && MACH_TS72XX
> +       help
> +         FPGA manager driver support for the Altera Cyclone II FPGA
> +         present on the TS-73xx SBC boards.
> +
>  config FPGA_MGR_ZYNQ_FPGA
>         tristate "Xilinx Zynq FPGA"
>         depends on ARCH_ZYNQ || COMPILE_TEST
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 8df07bcf42a6..a1160169e6d9 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
>  # FPGA Manager Drivers
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
> +obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
>
>  # FPGA Bridge Drivers
> diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
> new file mode 100644
> index 000000000000..38d78d8c6b1e
> --- /dev/null
> +++ b/drivers/fpga/ts73xx-fpga.c
> @@ -0,0 +1,163 @@
> +/*
> + * Technologic Systems TS-73xx SBC FPGA loader
> + *
> + * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
> + *
> + * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
> + * TS-7300, heavily based on load_fpga.c in their vendor tree.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/string.h>
> +#include <linux/iopoll.h>
> +#include <linux/fpga/fpga-mgr.h>
> +
> +#define TS73XX_FPGA_DATA_REG           0
> +#define TS73XX_FPGA_CONFIG_REG         1
> +
> +#define TS73XX_FPGA_WRITE_DONE         0x1
> +#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000    /* us */
> +#define TS73XX_FPGA_RESET              0x2
> +#define TS73XX_FPGA_RESET_LOW_DELAY    30      /* us */
> +#define TS73XX_FPGA_RESET_HIGH_DELAY   80      /* us */
> +#define TS73XX_FPGA_LOAD_OK            0x4
> +#define TS73XX_FPGA_CONFIG_LOAD                0x8
> +
> +struct ts73xx_fpga_priv {
> +       void __iomem    *io_base;
> +       struct device   *dev;
> +};
> +
> +static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
> +{
> +       return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
> +                                 struct fpga_image_info *info,
> +                                 const char *buf, size_t count)
> +{
> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> +
> +       /* Reset the FPGA */
> +       writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       udelay(TS73XX_FPGA_RESET_LOW_DELAY);
> +       writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
> +
> +       return 0;
> +}
> +
> +static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
> +                            size_t count)
> +{
> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> +       size_t i = 0;
> +       int ret;
> +       u8 reg;
> +
> +       while (count--) {
> +               ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
> +                                        reg, !(reg & TS73XX_FPGA_WRITE_DONE),
> +                                        1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
> +               if (ret < 0)
> +                       return ret;
> +
> +               writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
> +               i++;
> +       }
> +

<snip>
> +       usleep_range(1000, 2000);
> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       reg |= TS73XX_FPGA_CONFIG_LOAD;
> +       writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       usleep_range(1000, 2000);

</snip>

Just to clarify is this block what triggers the actual write? I'm asking because
I'm wondering if in the current implementation the ts73xx_fpga_write() function
can be called multiple times in your implementation before you finally get to
the write complete callback.

> +
> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       reg &= ~TS73XX_FPGA_CONFIG_LOAD;
> +       writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +
> +       return 0;
> +}
> +
> +static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
> +                                     struct fpga_image_info *info)
> +{
> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> +       u8 reg;
> +
> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
> +               return -ETIMEDOUT;
> +
> +       return 0;
> +}
> +
> +static const struct fpga_manager_ops ts73xx_fpga_ops = {
> +       .state          = ts73xx_fpga_state,
> +       .write_init     = ts73xx_fpga_write_init,
> +       .write          = ts73xx_fpga_write,
> +       .write_complete = ts73xx_fpga_write_complete,
> +};
> +
> +static int ts73xx_fpga_probe(struct platform_device *pdev)
> +{
> +       struct device *kdev = &pdev->dev;
> +       struct ts73xx_fpga_priv *priv;
> +       struct resource *res;
> +       int err;
> +
> +       priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = kdev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->io_base = devm_ioremap_resource(kdev, res);
> +       if (IS_ERR(priv->io_base)) {
> +               dev_err(kdev, "unable to remap registers\n");
> +               return PTR_ERR(priv->io_base);
> +       }
> +
> +       err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
> +                               &ts73xx_fpga_ops, priv);
> +       if (err) {
> +               dev_err(kdev, "failed to register FPGA manager\n");
> +               return err;
> +       }
> +
> +       return err;
> +}
> +
> +static int ts73xx_fpga_remove(struct platform_device *pdev)
> +{
> +       fpga_mgr_unregister(&pdev->dev);
> +
> +       return 0;
> +}
> +
> +static struct platform_driver ts73xx_fpga_driver = {
> +       .driver = {
> +               .name   = "ts73xx-fpga-mgr",
> +       },
> +       .probe  = ts73xx_fpga_probe,
> +       .remove = ts73xx_fpga_remove,
> +};
> +module_platform_driver(ts73xx_fpga_driver);
> +
> +MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
> +MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.9.3
>

Thanks,
Moritz

[PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Moritz Fischer]

Hi Florian,

On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Add support for loading bitstreams on the Altera Cyclone II FPGA
> populated on the TS-7300 board. This is done through the configuration
> and data registers offered through a memory interface between the EP93xx
> SoC and the FPGA via an intermediate CPLD device.
>
> The EP93xx SoC on the TS-7300 does not have direct means of configuring
> the on-board FPGA other than by using the special memory mapped
> interface to the CPLD. No other entity on the system can control the
> FPGA bitstream.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  drivers/fpga/Kconfig       |   7 ++
>  drivers/fpga/Makefile      |   1 +
>  drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 171 insertions(+)
>  create mode 100644 drivers/fpga/ts73xx-fpga.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ce861a2853a4..d9cbef60db80 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
>         help
>           FPGA manager driver support for Altera Arria10 SoCFPGA.
>
> +config FPGA_MGR_TS73XX
> +       tristate "Technologic Systems TS-73xx SBC FPGA Manager"
> +       depends on ARCH_EP93XX && MACH_TS72XX
> +       help
> +         FPGA manager driver support for the Altera Cyclone II FPGA
> +         present on the TS-73xx SBC boards.
> +
>  config FPGA_MGR_ZYNQ_FPGA
>         tristate "Xilinx Zynq FPGA"
>         depends on ARCH_ZYNQ || COMPILE_TEST
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 8df07bcf42a6..a1160169e6d9 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
>  # FPGA Manager Drivers
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
> +obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
>
>  # FPGA Bridge Drivers
> diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
> new file mode 100644
> index 000000000000..38d78d8c6b1e
> --- /dev/null
> +++ b/drivers/fpga/ts73xx-fpga.c
> @@ -0,0 +1,163 @@
> +/*
> + * Technologic Systems TS-73xx SBC FPGA loader
> + *
> + * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
> + *
> + * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
> + * TS-7300, heavily based on load_fpga.c in their vendor tree.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/string.h>
> +#include <linux/iopoll.h>
> +#include <linux/fpga/fpga-mgr.h>
> +
> +#define TS73XX_FPGA_DATA_REG           0
> +#define TS73XX_FPGA_CONFIG_REG         1
> +
> +#define TS73XX_FPGA_WRITE_DONE         0x1
> +#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000    /* us */
> +#define TS73XX_FPGA_RESET              0x2
> +#define TS73XX_FPGA_RESET_LOW_DELAY    30      /* us */
> +#define TS73XX_FPGA_RESET_HIGH_DELAY   80      /* us */
> +#define TS73XX_FPGA_LOAD_OK            0x4
> +#define TS73XX_FPGA_CONFIG_LOAD                0x8
> +
> +struct ts73xx_fpga_priv {
> +       void __iomem    *io_base;
> +       struct device   *dev;
> +};
> +
> +static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
> +{
> +       return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
> +                                 struct fpga_image_info *info,
> +                                 const char *buf, size_t count)
> +{
> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> +
> +       /* Reset the FPGA */
> +       writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       udelay(TS73XX_FPGA_RESET_LOW_DELAY);
> +       writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
> +
> +       return 0;
> +}
> +
> +static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
> +                            size_t count)
> +{
> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> +       size_t i = 0;
> +       int ret;
> +       u8 reg;
> +
> +       while (count--) {
> +               ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
> +                                        reg, !(reg & TS73XX_FPGA_WRITE_DONE),
> +                                        1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
> +               if (ret < 0)
> +                       return ret;
> +
> +               writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
> +               i++;
> +       }
> +

<snip>
> +       usleep_range(1000, 2000);
> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       reg |= TS73XX_FPGA_CONFIG_LOAD;
> +       writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       usleep_range(1000, 2000);

</snip>

Just to clarify is this block what triggers the actual write? I'm asking because
I'm wondering if in the current implementation the ts73xx_fpga_write() function
can be called multiple times in your implementation before you finally get to
the write complete callback.

> +
> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       reg &= ~TS73XX_FPGA_CONFIG_LOAD;
> +       writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +
> +       return 0;
> +}
> +
> +static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
> +                                     struct fpga_image_info *info)
> +{
> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> +       u8 reg;
> +
> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> +       if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
> +               return -ETIMEDOUT;
> +
> +       return 0;
> +}
> +
> +static const struct fpga_manager_ops ts73xx_fpga_ops = {
> +       .state          = ts73xx_fpga_state,
> +       .write_init     = ts73xx_fpga_write_init,
> +       .write          = ts73xx_fpga_write,
> +       .write_complete = ts73xx_fpga_write_complete,
> +};
> +
> +static int ts73xx_fpga_probe(struct platform_device *pdev)
> +{
> +       struct device *kdev = &pdev->dev;
> +       struct ts73xx_fpga_priv *priv;
> +       struct resource *res;
> +       int err;
> +
> +       priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = kdev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->io_base = devm_ioremap_resource(kdev, res);
> +       if (IS_ERR(priv->io_base)) {
> +               dev_err(kdev, "unable to remap registers\n");
> +               return PTR_ERR(priv->io_base);
> +       }
> +
> +       err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
> +                               &ts73xx_fpga_ops, priv);
> +       if (err) {
> +               dev_err(kdev, "failed to register FPGA manager\n");
> +               return err;
> +       }
> +
> +       return err;
> +}
> +
> +static int ts73xx_fpga_remove(struct platform_device *pdev)
> +{
> +       fpga_mgr_unregister(&pdev->dev);
> +
> +       return 0;
> +}
> +
> +static struct platform_driver ts73xx_fpga_driver = {
> +       .driver = {
> +               .name   = "ts73xx-fpga-mgr",
> +       },
> +       .probe  = ts73xx_fpga_probe,
> +       .remove = ts73xx_fpga_remove,
> +};
> +module_platform_driver(ts73xx_fpga_driver);
> +
> +MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
> +MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.9.3
>

Thanks,
Moritz

Re: [PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Florian Fainelli]

On 12/13/2016 10:07 PM, Moritz Fischer wrote:
> Hi Florian,
> 
> On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>> Add support for loading bitstreams on the Altera Cyclone II FPGA
>> populated on the TS-7300 board. This is done through the configuration
>> and data registers offered through a memory interface between the EP93xx
>> SoC and the FPGA via an intermediate CPLD device.
>>
>> The EP93xx SoC on the TS-7300 does not have direct means of configuring
>> the on-board FPGA other than by using the special memory mapped
>> interface to the CPLD. No other entity on the system can control the
>> FPGA bitstream.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>>  drivers/fpga/Kconfig       |   7 ++
>>  drivers/fpga/Makefile      |   1 +
>>  drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 171 insertions(+)
>>  create mode 100644 drivers/fpga/ts73xx-fpga.c
>>
>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
>> index ce861a2853a4..d9cbef60db80 100644
>> --- a/drivers/fpga/Kconfig
>> +++ b/drivers/fpga/Kconfig
>> @@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
>>         help
>>           FPGA manager driver support for Altera Arria10 SoCFPGA.
>>
>> +config FPGA_MGR_TS73XX
>> +       tristate "Technologic Systems TS-73xx SBC FPGA Manager"
>> +       depends on ARCH_EP93XX && MACH_TS72XX
>> +       help
>> +         FPGA manager driver support for the Altera Cyclone II FPGA
>> +         present on the TS-73xx SBC boards.
>> +
>>  config FPGA_MGR_ZYNQ_FPGA
>>         tristate "Xilinx Zynq FPGA"
>>         depends on ARCH_ZYNQ || COMPILE_TEST
>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
>> index 8df07bcf42a6..a1160169e6d9 100644
>> --- a/drivers/fpga/Makefile
>> +++ b/drivers/fpga/Makefile
>> @@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
>>  # FPGA Manager Drivers
>>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
>>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
>> +obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
>>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
>>
>>  # FPGA Bridge Drivers
>> diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
>> new file mode 100644
>> index 000000000000..38d78d8c6b1e
>> --- /dev/null
>> +++ b/drivers/fpga/ts73xx-fpga.c
>> @@ -0,0 +1,163 @@
>> +/*
>> + * Technologic Systems TS-73xx SBC FPGA loader
>> + *
>> + * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
>> + *
>> + * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
>> + * TS-7300, heavily based on load_fpga.c in their vendor tree.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; version 2 of the License.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/string.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/fpga/fpga-mgr.h>
>> +
>> +#define TS73XX_FPGA_DATA_REG           0
>> +#define TS73XX_FPGA_CONFIG_REG         1
>> +
>> +#define TS73XX_FPGA_WRITE_DONE         0x1
>> +#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000    /* us */
>> +#define TS73XX_FPGA_RESET              0x2
>> +#define TS73XX_FPGA_RESET_LOW_DELAY    30      /* us */
>> +#define TS73XX_FPGA_RESET_HIGH_DELAY   80      /* us */
>> +#define TS73XX_FPGA_LOAD_OK            0x4
>> +#define TS73XX_FPGA_CONFIG_LOAD                0x8
>> +
>> +struct ts73xx_fpga_priv {
>> +       void __iomem    *io_base;
>> +       struct device   *dev;
>> +};
>> +
>> +static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
>> +{
>> +       return FPGA_MGR_STATE_UNKNOWN;
>> +}
>> +
>> +static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
>> +                                 struct fpga_image_info *info,
>> +                                 const char *buf, size_t count)
>> +{
>> +       struct ts73xx_fpga_priv *priv = mgr->priv;
>> +
>> +       /* Reset the FPGA */
>> +       writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
>> +       udelay(TS73XX_FPGA_RESET_LOW_DELAY);
>> +       writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
>> +       udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
>> +
>> +       return 0;
>> +}
>> +
>> +static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
>> +                            size_t count)
>> +{
>> +       struct ts73xx_fpga_priv *priv = mgr->priv;
>> +       size_t i = 0;
>> +       int ret;
>> +       u8 reg;
>> +
>> +       while (count--) {
>> +               ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
>> +                                        reg, !(reg & TS73XX_FPGA_WRITE_DONE),
>> +                                        1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
>> +               if (ret < 0)
>> +                       return ret;
>> +
>> +               writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
>> +               i++;
>> +       }
>> +
> 
> <snip>
>> +       usleep_range(1000, 2000);
>> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
>> +       reg |= TS73XX_FPGA_CONFIG_LOAD;
>> +       writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
>> +       usleep_range(1000, 2000);
> 
> </snip>
> 
> Just to clarify is this block what triggers the actual write? I'm asking because
> I'm wondering if in the current implementation the ts73xx_fpga_write() function
> can be called multiple times in your implementation before you finally get to
> the write complete callback.

My understanding is that, yes, this triggers the final write. You are
right that ts73xx_fpga_write() can be called multiple times. It sounds
like what my write_complete function does right now is just return that
we successfully completed the bistream write, but this snippet that you
are quoting should actually be moved into write_complete.

Does that sound reasonable?
-- 
Florian

[PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Florian Fainelli]

On 12/13/2016 10:07 PM, Moritz Fischer wrote:
> Hi Florian,
> 
> On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>> Add support for loading bitstreams on the Altera Cyclone II FPGA
>> populated on the TS-7300 board. This is done through the configuration
>> and data registers offered through a memory interface between the EP93xx
>> SoC and the FPGA via an intermediate CPLD device.
>>
>> The EP93xx SoC on the TS-7300 does not have direct means of configuring
>> the on-board FPGA other than by using the special memory mapped
>> interface to the CPLD. No other entity on the system can control the
>> FPGA bitstream.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>>  drivers/fpga/Kconfig       |   7 ++
>>  drivers/fpga/Makefile      |   1 +
>>  drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 171 insertions(+)
>>  create mode 100644 drivers/fpga/ts73xx-fpga.c
>>
>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
>> index ce861a2853a4..d9cbef60db80 100644
>> --- a/drivers/fpga/Kconfig
>> +++ b/drivers/fpga/Kconfig
>> @@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
>>         help
>>           FPGA manager driver support for Altera Arria10 SoCFPGA.
>>
>> +config FPGA_MGR_TS73XX
>> +       tristate "Technologic Systems TS-73xx SBC FPGA Manager"
>> +       depends on ARCH_EP93XX && MACH_TS72XX
>> +       help
>> +         FPGA manager driver support for the Altera Cyclone II FPGA
>> +         present on the TS-73xx SBC boards.
>> +
>>  config FPGA_MGR_ZYNQ_FPGA
>>         tristate "Xilinx Zynq FPGA"
>>         depends on ARCH_ZYNQ || COMPILE_TEST
>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
>> index 8df07bcf42a6..a1160169e6d9 100644
>> --- a/drivers/fpga/Makefile
>> +++ b/drivers/fpga/Makefile
>> @@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
>>  # FPGA Manager Drivers
>>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
>>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
>> +obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
>>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
>>
>>  # FPGA Bridge Drivers
>> diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
>> new file mode 100644
>> index 000000000000..38d78d8c6b1e
>> --- /dev/null
>> +++ b/drivers/fpga/ts73xx-fpga.c
>> @@ -0,0 +1,163 @@
>> +/*
>> + * Technologic Systems TS-73xx SBC FPGA loader
>> + *
>> + * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
>> + *
>> + * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
>> + * TS-7300, heavily based on load_fpga.c in their vendor tree.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; version 2 of the License.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/string.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/fpga/fpga-mgr.h>
>> +
>> +#define TS73XX_FPGA_DATA_REG           0
>> +#define TS73XX_FPGA_CONFIG_REG         1
>> +
>> +#define TS73XX_FPGA_WRITE_DONE         0x1
>> +#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000    /* us */
>> +#define TS73XX_FPGA_RESET              0x2
>> +#define TS73XX_FPGA_RESET_LOW_DELAY    30      /* us */
>> +#define TS73XX_FPGA_RESET_HIGH_DELAY   80      /* us */
>> +#define TS73XX_FPGA_LOAD_OK            0x4
>> +#define TS73XX_FPGA_CONFIG_LOAD                0x8
>> +
>> +struct ts73xx_fpga_priv {
>> +       void __iomem    *io_base;
>> +       struct device   *dev;
>> +};
>> +
>> +static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
>> +{
>> +       return FPGA_MGR_STATE_UNKNOWN;
>> +}
>> +
>> +static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
>> +                                 struct fpga_image_info *info,
>> +                                 const char *buf, size_t count)
>> +{
>> +       struct ts73xx_fpga_priv *priv = mgr->priv;
>> +
>> +       /* Reset the FPGA */
>> +       writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
>> +       udelay(TS73XX_FPGA_RESET_LOW_DELAY);
>> +       writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
>> +       udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
>> +
>> +       return 0;
>> +}
>> +
>> +static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
>> +                            size_t count)
>> +{
>> +       struct ts73xx_fpga_priv *priv = mgr->priv;
>> +       size_t i = 0;
>> +       int ret;
>> +       u8 reg;
>> +
>> +       while (count--) {
>> +               ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
>> +                                        reg, !(reg & TS73XX_FPGA_WRITE_DONE),
>> +                                        1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
>> +               if (ret < 0)
>> +                       return ret;
>> +
>> +               writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
>> +               i++;
>> +       }
>> +
> 
> <snip>
>> +       usleep_range(1000, 2000);
>> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
>> +       reg |= TS73XX_FPGA_CONFIG_LOAD;
>> +       writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
>> +       usleep_range(1000, 2000);
> 
> </snip>
> 
> Just to clarify is this block what triggers the actual write? I'm asking because
> I'm wondering if in the current implementation the ts73xx_fpga_write() function
> can be called multiple times in your implementation before you finally get to
> the write complete callback.

My understanding is that, yes, this triggers the final write. You are
right that ts73xx_fpga_write() can be called multiple times. It sounds
like what my write_complete function does right now is just return that
we successfully completed the bistream write, but this snippet that you
are quoting should actually be moved into write_complete.

Does that sound reasonable?
-- 
Florian

RE: [PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Hartley Sweeten]

On Wednesday, December 14, 2016 11:55 AM, Florian Fainelli wrote:
> My understanding is that, yes, this triggers the final write. You are
> right that ts73xx_fpga_write() can be called multiple times. It sounds
> like what my write_complete function does right now is just return that
> we successfully completed the bistream write, but this snippet that you
> are quoting should actually be moved into write_complete.

Florian,

I'm in the process of getting a TS-7300 board so I can help test this. Hopefully
I will have it by next week.

Hartley

[PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Hartley Sweeten]

On Wednesday, December 14, 2016 11:55 AM, Florian Fainelli wrote:
> My understanding is that, yes, this triggers the final write. You are
> right that ts73xx_fpga_write() can be called multiple times. It sounds
> like what my write_complete function does right now is just return that
> we successfully completed the bistream write, but this snippet that you
> are quoting should actually be moved into write_complete.

Florian,

I'm in the process of getting a TS-7300 board so I can help test this. Hopefully
I will have it by next week.

Hartley

Re: [PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Florian Fainelli]

On 12/14/2016 10:58 AM, Hartley Sweeten wrote:
> On Wednesday, December 14, 2016 11:55 AM, Florian Fainelli wrote:
>> My understanding is that, yes, this triggers the final write. You are
>> right that ts73xx_fpga_write() can be called multiple times. It sounds
>> like what my write_complete function does right now is just return that
>> we successfully completed the bistream write, but this snippet that you
>> are quoting should actually be moved into write_complete.
> 
> Florian,
> 
> I'm in the process of getting a TS-7300 board so I can help test this. Hopefully
> I will have it by next week.

Great! I got a few things on my list that have not been submitted yet:

- tmp124 support through drivers/hwmon/lm70.c
- specific memcpy_{from,to}io accessors for ethoc from the FPGA
- serial port support for the UARTs from the FPGA

And some other things that are giving me issues at the moment, like
SPI_3WIRE support for spi-ep93xx so I can configure the tmp124 to send
alarms/have temperature thresholds.

My branch is here:

https://github.com/ffainelli/linux/tree/ts72xx

Cheers
-- 
Florian

[PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Florian Fainelli]

On 12/14/2016 10:58 AM, Hartley Sweeten wrote:
> On Wednesday, December 14, 2016 11:55 AM, Florian Fainelli wrote:
>> My understanding is that, yes, this triggers the final write. You are
>> right that ts73xx_fpga_write() can be called multiple times. It sounds
>> like what my write_complete function does right now is just return that
>> we successfully completed the bistream write, but this snippet that you
>> are quoting should actually be moved into write_complete.
> 
> Florian,
> 
> I'm in the process of getting a TS-7300 board so I can help test this. Hopefully
> I will have it by next week.

Great! I got a few things on my list that have not been submitted yet:

- tmp124 support through drivers/hwmon/lm70.c
- specific memcpy_{from,to}io accessors for ethoc from the FPGA
- serial port support for the UARTs from the FPGA

And some other things that are giving me issues at the moment, like
SPI_3WIRE support for spi-ep93xx so I can configure the tmp124 to send
alarms/have temperature thresholds.

My branch is here:

https://github.com/ffainelli/linux/tree/ts72xx

Cheers
-- 
Florian

Re: [PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Alan Tull]

On Wed, 14 Dec 2016, Florian Fainelli wrote:

> On 12/13/2016 10:07 PM, Moritz Fischer wrote:
> > Hi Florian,
> > 
> > On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> >> Add support for loading bitstreams on the Altera Cyclone II FPGA
> >> populated on the TS-7300 board. This is done through the configuration
> >> and data registers offered through a memory interface between the EP93xx
> >> SoC and the FPGA via an intermediate CPLD device.
> >>
> >> The EP93xx SoC on the TS-7300 does not have direct means of configuring
> >> the on-board FPGA other than by using the special memory mapped
> >> interface to the CPLD. No other entity on the system can control the
> >> FPGA bitstream.
> >>
> >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> >> ---
> >>  drivers/fpga/Kconfig       |   7 ++
> >>  drivers/fpga/Makefile      |   1 +
> >>  drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
> >>  3 files changed, 171 insertions(+)
> >>  create mode 100644 drivers/fpga/ts73xx-fpga.c
> >>
> >> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> >> index ce861a2853a4..d9cbef60db80 100644
> >> --- a/drivers/fpga/Kconfig
> >> +++ b/drivers/fpga/Kconfig
> >> @@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
> >>         help
> >>           FPGA manager driver support for Altera Arria10 SoCFPGA.
> >>
> >> +config FPGA_MGR_TS73XX
> >> +       tristate "Technologic Systems TS-73xx SBC FPGA Manager"
> >> +       depends on ARCH_EP93XX && MACH_TS72XX
> >> +       help
> >> +         FPGA manager driver support for the Altera Cyclone II FPGA
> >> +         present on the TS-73xx SBC boards.
> >> +
> >>  config FPGA_MGR_ZYNQ_FPGA
> >>         tristate "Xilinx Zynq FPGA"
> >>         depends on ARCH_ZYNQ || COMPILE_TEST
> >> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> >> index 8df07bcf42a6..a1160169e6d9 100644
> >> --- a/drivers/fpga/Makefile
> >> +++ b/drivers/fpga/Makefile
> >> @@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
> >>  # FPGA Manager Drivers
> >>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
> >>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
> >> +obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> >>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> >>
> >>  # FPGA Bridge Drivers
> >> diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
> >> new file mode 100644
> >> index 000000000000..38d78d8c6b1e
> >> --- /dev/null
> >> +++ b/drivers/fpga/ts73xx-fpga.c
> >> @@ -0,0 +1,163 @@
> >> +/*
> >> + * Technologic Systems TS-73xx SBC FPGA loader
> >> + *
> >> + * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
> >> + *
> >> + * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
> >> + * TS-7300, heavily based on load_fpga.c in their vendor tree.
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; version 2 of the License.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> + * GNU General Public License for more details.
> >> + */
> >> +
> >> +#include <linux/delay.h>
> >> +#include <linux/io.h>
> >> +#include <linux/module.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/string.h>
> >> +#include <linux/iopoll.h>
> >> +#include <linux/fpga/fpga-mgr.h>
> >> +
> >> +#define TS73XX_FPGA_DATA_REG           0
> >> +#define TS73XX_FPGA_CONFIG_REG         1
> >> +
> >> +#define TS73XX_FPGA_WRITE_DONE         0x1
> >> +#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000    /* us */
> >> +#define TS73XX_FPGA_RESET              0x2
> >> +#define TS73XX_FPGA_RESET_LOW_DELAY    30      /* us */
> >> +#define TS73XX_FPGA_RESET_HIGH_DELAY   80      /* us */
> >> +#define TS73XX_FPGA_LOAD_OK            0x4
> >> +#define TS73XX_FPGA_CONFIG_LOAD                0x8
> >> +
> >> +struct ts73xx_fpga_priv {
> >> +       void __iomem    *io_base;
> >> +       struct device   *dev;
> >> +};
> >> +
> >> +static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
> >> +{
> >> +       return FPGA_MGR_STATE_UNKNOWN;
> >> +}
> >> +
> >> +static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
> >> +                                 struct fpga_image_info *info,
> >> +                                 const char *buf, size_t count)
> >> +{
> >> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> >> +
> >> +       /* Reset the FPGA */
> >> +       writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> >> +       udelay(TS73XX_FPGA_RESET_LOW_DELAY);
> >> +       writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> >> +       udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
> >> +
> >> +       return 0;
> >> +}
> >> +
> >> +static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
> >> +                            size_t count)
> >> +{
> >> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> >> +       size_t i = 0;
> >> +       int ret;
> >> +       u8 reg;
> >> +
> >> +       while (count--) {
> >> +               ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
> >> +                                        reg, !(reg & TS73XX_FPGA_WRITE_DONE),
> >> +                                        1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
> >> +               if (ret < 0)
> >> +                       return ret;
> >> +
> >> +               writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
> >> +               i++;
> >> +       }
> >> +
> > 
> > <snip>
> >> +       usleep_range(1000, 2000);
> >> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> >> +       reg |= TS73XX_FPGA_CONFIG_LOAD;
> >> +       writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> >> +       usleep_range(1000, 2000);
> > 
> > </snip>
> > 
> > Just to clarify is this block what triggers the actual write? I'm asking because
> > I'm wondering if in the current implementation the ts73xx_fpga_write() function
> > can be called multiple times in your implementation before you finally get to
> > the write complete callback.
> 
> My understanding is that, yes, this triggers the final write. You are
> right that ts73xx_fpga_write() can be called multiple times. It sounds
> like what my write_complete function does right now is just return that
> we successfully completed the bistream write, but this snippet that you
> are quoting should actually be moved into write_complete.


Just to be clear, write_init is called, then write may be called
multiple times with chunks of the image buffer, then write_complete is
called.  Yes please move that to write_complete.

Alan

> 
> Does that sound reasonable?
> -- 
> Florian
> 

[PATCH v3 2/2] FPGA: Add TS-7300 FPGA manager

[Alan Tull]

On Wed, 14 Dec 2016, Florian Fainelli wrote:

> On 12/13/2016 10:07 PM, Moritz Fischer wrote:
> > Hi Florian,
> > 
> > On Tue, Dec 13, 2016 at 6:35 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> >> Add support for loading bitstreams on the Altera Cyclone II FPGA
> >> populated on the TS-7300 board. This is done through the configuration
> >> and data registers offered through a memory interface between the EP93xx
> >> SoC and the FPGA via an intermediate CPLD device.
> >>
> >> The EP93xx SoC on the TS-7300 does not have direct means of configuring
> >> the on-board FPGA other than by using the special memory mapped
> >> interface to the CPLD. No other entity on the system can control the
> >> FPGA bitstream.
> >>
> >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> >> ---
> >>  drivers/fpga/Kconfig       |   7 ++
> >>  drivers/fpga/Makefile      |   1 +
> >>  drivers/fpga/ts73xx-fpga.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
> >>  3 files changed, 171 insertions(+)
> >>  create mode 100644 drivers/fpga/ts73xx-fpga.c
> >>
> >> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> >> index ce861a2853a4..d9cbef60db80 100644
> >> --- a/drivers/fpga/Kconfig
> >> +++ b/drivers/fpga/Kconfig
> >> @@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
> >>         help
> >>           FPGA manager driver support for Altera Arria10 SoCFPGA.
> >>
> >> +config FPGA_MGR_TS73XX
> >> +       tristate "Technologic Systems TS-73xx SBC FPGA Manager"
> >> +       depends on ARCH_EP93XX && MACH_TS72XX
> >> +       help
> >> +         FPGA manager driver support for the Altera Cyclone II FPGA
> >> +         present on the TS-73xx SBC boards.
> >> +
> >>  config FPGA_MGR_ZYNQ_FPGA
> >>         tristate "Xilinx Zynq FPGA"
> >>         depends on ARCH_ZYNQ || COMPILE_TEST
> >> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> >> index 8df07bcf42a6..a1160169e6d9 100644
> >> --- a/drivers/fpga/Makefile
> >> +++ b/drivers/fpga/Makefile
> >> @@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
> >>  # FPGA Manager Drivers
> >>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
> >>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
> >> +obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> >>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> >>
> >>  # FPGA Bridge Drivers
> >> diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
> >> new file mode 100644
> >> index 000000000000..38d78d8c6b1e
> >> --- /dev/null
> >> +++ b/drivers/fpga/ts73xx-fpga.c
> >> @@ -0,0 +1,163 @@
> >> +/*
> >> + * Technologic Systems TS-73xx SBC FPGA loader
> >> + *
> >> + * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
> >> + *
> >> + * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
> >> + * TS-7300, heavily based on load_fpga.c in their vendor tree.
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; version 2 of the License.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> + * GNU General Public License for more details.
> >> + */
> >> +
> >> +#include <linux/delay.h>
> >> +#include <linux/io.h>
> >> +#include <linux/module.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/string.h>
> >> +#include <linux/iopoll.h>
> >> +#include <linux/fpga/fpga-mgr.h>
> >> +
> >> +#define TS73XX_FPGA_DATA_REG           0
> >> +#define TS73XX_FPGA_CONFIG_REG         1
> >> +
> >> +#define TS73XX_FPGA_WRITE_DONE         0x1
> >> +#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000    /* us */
> >> +#define TS73XX_FPGA_RESET              0x2
> >> +#define TS73XX_FPGA_RESET_LOW_DELAY    30      /* us */
> >> +#define TS73XX_FPGA_RESET_HIGH_DELAY   80      /* us */
> >> +#define TS73XX_FPGA_LOAD_OK            0x4
> >> +#define TS73XX_FPGA_CONFIG_LOAD                0x8
> >> +
> >> +struct ts73xx_fpga_priv {
> >> +       void __iomem    *io_base;
> >> +       struct device   *dev;
> >> +};
> >> +
> >> +static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
> >> +{
> >> +       return FPGA_MGR_STATE_UNKNOWN;
> >> +}
> >> +
> >> +static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
> >> +                                 struct fpga_image_info *info,
> >> +                                 const char *buf, size_t count)
> >> +{
> >> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> >> +
> >> +       /* Reset the FPGA */
> >> +       writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> >> +       udelay(TS73XX_FPGA_RESET_LOW_DELAY);
> >> +       writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> >> +       udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
> >> +
> >> +       return 0;
> >> +}
> >> +
> >> +static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
> >> +                            size_t count)
> >> +{
> >> +       struct ts73xx_fpga_priv *priv = mgr->priv;
> >> +       size_t i = 0;
> >> +       int ret;
> >> +       u8 reg;
> >> +
> >> +       while (count--) {
> >> +               ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
> >> +                                        reg, !(reg & TS73XX_FPGA_WRITE_DONE),
> >> +                                        1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
> >> +               if (ret < 0)
> >> +                       return ret;
> >> +
> >> +               writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
> >> +               i++;
> >> +       }
> >> +
> > 
> > <snip>
> >> +       usleep_range(1000, 2000);
> >> +       reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
> >> +       reg |= TS73XX_FPGA_CONFIG_LOAD;
> >> +       writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
> >> +       usleep_range(1000, 2000);
> > 
> > </snip>
> > 
> > Just to clarify is this block what triggers the actual write? I'm asking because
> > I'm wondering if in the current implementation the ts73xx_fpga_write() function
> > can be called multiple times in your implementation before you finally get to
> > the write complete callback.
> 
> My understanding is that, yes, this triggers the final write. You are
> right that ts73xx_fpga_write() can be called multiple times. It sounds
> like what my write_complete function does right now is just return that
> we successfully completed the bistream write, but this snippet that you
> are quoting should actually be moved into write_complete.


Just to be clear, write_init is called, then write may be called
multiple times with chunks of the image buffer, then write_complete is
called.  Yes please move that to write_complete.

Alan

> 
> Does that sound reasonable?
> -- 
> Florian
>