From: Leonard Crestez <leonard.crestez@nxp.com> To: Stephen Boyd <sboyd@kernel.org>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Rob Herring <robh+dt@kernel.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Shawn Guo" <shawnguo@kernel.org>, "Chanwoo Choi" <cw00.choi@samsung.com>, "Mark Rutland" <mark.rutland@arm.com>, "Michael Turquette" <mturquette@baylibre.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Saravana Kannan" <saravanak@google.com>, "Angus Ainslie" <angus@akkea.ca>, "Martin Kepplinger" <martink@posteo.de>, "Matthias Kaehlcke" <mka@chromium.org>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Alexandre Bailon" <abailon@baylibre.com>, "Georgi Djakov" <georgi.djakov@linaro.org>, "Dong Aisheng" <aisheng.dong@nxp.com>, "Abel Vesa" <abel.vesa@nxp.com>, "Jacky Bai" <ping.bai@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Fabio Estevam" <fabio.estevam@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 6/6] arm64: dts: imx8m: Add ddr controller nodes Date: Sat, 9 Nov 2019 00:39:56 +0200 [thread overview] Message-ID: <cfaee2ac845b07497a25f688915b60c9bb7c7ac1.1573252696.git.leonard.crestez@nxp.com> (raw) In-Reply-To: <cover.1573252696.git.leonard.crestez@nxp.com> In-Reply-To: <cover.1573252696.git.leonard.crestez@nxp.com> This is used by the imx-ddrc devfreq driver to implement dynamic frequency scaling of DRAM. Add a devfreq-event link to the dram PMU in order to support on-demand scaling of ddrc based on measured dram bandwidth usage. Support for proactive scaling via interconnect will come later. The high-performance bus masters which need that (display, vpu, gpu) are not yet enabled in upstream anyway. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 ++++++++++++++ arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++- .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 ++++++++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 13 +++++++++- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 +++++++++- 6 files changed, 96 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 28ab17a277bb..ecf0d385c164 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -75,10 +75,28 @@ &A53_0 { cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6edbdfe2d0d7..0fffc6362c43 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -856,11 +856,22 @@ #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; - ddr-pmu@3d800000 { + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + devfreq-events = <&ddr_pmu>; + }; + + ddr_pmu: ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 071949412caf..b051c927c11e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -15,10 +15,28 @@ &A53_0 { cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + opp-600M { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + &i2c1 { pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index e91625063f8e..c952bfb906a7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -757,11 +757,22 @@ #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; - ddr-pmu@3d800000 { + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MN_CLK_DRAM_CORE>, + <&clk IMX8MN_DRAM_PLL>, + <&clk IMX8MN_CLK_DRAM_ALT>, + <&clk IMX8MN_CLK_DRAM_APB>; + devfreq-events = <&ddr_pmu>; + }; + + ddr_pmu: ddr-pmu@3d800000 { compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index c36685916683..ee6dc5f07622 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -103,10 +103,34 @@ &A53_3 { cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + /* + * On imx8mq B0 PLL can't be bypassed so low bus is 166M + */ + opp-166M { + opp-hz = /bits/ 64 <166935483>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 7f9319452b58..d2270e99098e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1111,11 +1111,22 @@ interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; }; - ddr-pmu@3d800000 { + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, + <&clk IMX8MQ_DRAM_PLL_OUT>, + <&clk IMX8MQ_CLK_DRAM_ALT>, + <&clk IMX8MQ_CLK_DRAM_APB>; + devfreq-events = <&ddr_pmu>; + }; + + ddr_pmu: ddr-pmu@3d800000 { compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Leonard Crestez <leonard.crestez@nxp.com> To: Stephen Boyd <sboyd@kernel.org>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Rob Herring <robh+dt@kernel.org> Cc: "Mark Rutland" <mark.rutland@arm.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Jacky Bai" <ping.bai@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, "Michael Turquette" <mturquette@baylibre.com>, "Angus Ainslie" <angus@akkea.ca>, "Alexandre Bailon" <abailon@baylibre.com>, linux-clk@vger.kernel.org, "Abel Vesa" <abel.vesa@nxp.com>, "Saravana Kannan" <saravanak@google.com>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Chanwoo Choi" <cw00.choi@samsung.com>, "Matthias Kaehlcke" <mka@chromium.org>, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, "Martin Kepplinger" <martink@posteo.de>, linux-arm-kernel@lists.infradead.org, "Dong Aisheng" <aisheng.dong@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, kernel@pengutronix.de, "Fabio Estevam" <fabio.estevam@nxp.com>, "Shawn Guo" <shawnguo@kernel.org>, "Georgi Djakov" <georgi.djakov@linaro.org> Subject: [PATCH v4 6/6] arm64: dts: imx8m: Add ddr controller nodes Date: Sat, 9 Nov 2019 00:39:56 +0200 [thread overview] Message-ID: <cfaee2ac845b07497a25f688915b60c9bb7c7ac1.1573252696.git.leonard.crestez@nxp.com> (raw) In-Reply-To: <cover.1573252696.git.leonard.crestez@nxp.com> In-Reply-To: <cover.1573252696.git.leonard.crestez@nxp.com> This is used by the imx-ddrc devfreq driver to implement dynamic frequency scaling of DRAM. Add a devfreq-event link to the dram PMU in order to support on-demand scaling of ddrc based on measured dram bandwidth usage. Support for proactive scaling via interconnect will come later. The high-performance bus masters which need that (display, vpu, gpu) are not yet enabled in upstream anyway. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 ++++++++++++++ arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++- .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 ++++++++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 13 +++++++++- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 +++++++++- 6 files changed, 96 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 28ab17a277bb..ecf0d385c164 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -75,10 +75,28 @@ &A53_0 { cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6edbdfe2d0d7..0fffc6362c43 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -856,11 +856,22 @@ #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; - ddr-pmu@3d800000 { + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + devfreq-events = <&ddr_pmu>; + }; + + ddr_pmu: ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 071949412caf..b051c927c11e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -15,10 +15,28 @@ &A53_0 { cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + opp-600M { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + &i2c1 { pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index e91625063f8e..c952bfb906a7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -757,11 +757,22 @@ #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; - ddr-pmu@3d800000 { + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MN_CLK_DRAM_CORE>, + <&clk IMX8MN_DRAM_PLL>, + <&clk IMX8MN_CLK_DRAM_ALT>, + <&clk IMX8MN_CLK_DRAM_APB>; + devfreq-events = <&ddr_pmu>; + }; + + ddr_pmu: ddr-pmu@3d800000 { compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index c36685916683..ee6dc5f07622 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -103,10 +103,34 @@ &A53_3 { cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + /* + * On imx8mq B0 PLL can't be bypassed so low bus is 166M + */ + opp-166M { + opp-hz = /bits/ 64 <166935483>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 7f9319452b58..d2270e99098e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1111,11 +1111,22 @@ interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; }; - ddr-pmu@3d800000 { + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, + <&clk IMX8MQ_DRAM_PLL_OUT>, + <&clk IMX8MQ_CLK_DRAM_ALT>, + <&clk IMX8MQ_CLK_DRAM_APB>; + devfreq-events = <&ddr_pmu>; + }; + + ddr_pmu: ddr-pmu@3d800000 { compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-08 22:40 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-08 22:39 [PATCH v4 0/6] PM / devfreq: Add dynamic scaling for imx8m ddr controller Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 1/6] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-12 11:18 ` Abel Vesa 2019-11-12 11:18 ` Abel Vesa 2019-11-12 13:43 ` Leonard Crestez 2019-11-12 13:43 ` Leonard Crestez 2019-11-12 15:10 ` Abel Vesa 2019-11-12 15:10 ` Abel Vesa 2019-11-08 22:39 ` [PATCH v4 2/6] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-12 11:18 ` Abel Vesa 2019-11-12 11:18 ` Abel Vesa 2019-11-08 22:39 ` [PATCH v4 3/6] dt-bindings: memory: Add bindings for imx8m ddr controller Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 4/6] PM / devfreq: Add dynamic scaling " Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-11 3:23 ` Chanwoo Choi 2019-11-11 3:23 ` Chanwoo Choi 2019-11-11 17:23 ` Leonard Crestez 2019-11-11 17:23 ` Leonard Crestez 2019-11-12 1:00 ` Chanwoo Choi 2019-11-12 1:00 ` Chanwoo Choi 2019-11-12 14:47 ` Leonard Crestez 2019-11-12 14:47 ` Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 5/6] PM / devfreq: imx8m-ddrc: Measure bandwidth with perf Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-11 5:18 ` Chanwoo Choi 2019-11-11 5:18 ` Chanwoo Choi 2019-11-12 13:17 ` Leonard Crestez 2019-11-12 13:17 ` Leonard Crestez 2019-11-13 1:43 ` Chanwoo Choi 2019-11-13 1:43 ` Chanwoo Choi 2019-11-08 22:39 ` Leonard Crestez [this message] 2019-11-08 22:39 ` [PATCH v4 6/6] arm64: dts: imx8m: Add ddr controller nodes Leonard Crestez 2020-06-22 13:58 ` [PATCH v4 0/6] PM / devfreq: Add dynamic scaling for imx8m ddr controller Martin Kepplinger 2020-06-24 6:08 ` Leonard Crestez 2020-06-24 6:08 ` Leonard Crestez 2020-06-25 6:57 ` Martin Kepplinger 2020-06-25 6:57 ` Martin Kepplinger 2020-06-25 14:47 ` Abel Vesa 2020-06-25 14:47 ` Abel Vesa 2020-06-29 6:32 ` Martin Kepplinger 2020-06-29 6:32 ` Martin Kepplinger
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=cfaee2ac845b07497a25f688915b60c9bb7c7ac1.1573252696.git.leonard.crestez@nxp.com \ --to=leonard.crestez@nxp.com \ --cc=Anson.Huang@nxp.com \ --cc=a.swigon@partner.samsung.com \ --cc=abailon@baylibre.com \ --cc=abel.vesa@nxp.com \ --cc=aisheng.dong@nxp.com \ --cc=angus@akkea.ca \ --cc=cw00.choi@samsung.com \ --cc=devicetree@vger.kernel.org \ --cc=fabio.estevam@nxp.com \ --cc=georgi.djakov@linaro.org \ --cc=kernel@pengutronix.de \ --cc=krzk@kernel.org \ --cc=kyungmin.park@samsung.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-imx@nxp.com \ --cc=linux-pm@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=martink@posteo.de \ --cc=mka@chromium.org \ --cc=mturquette@baylibre.com \ --cc=myungjoo.ham@samsung.com \ --cc=ping.bai@nxp.com \ --cc=rjw@rjwysocki.net \ --cc=robh+dt@kernel.org \ --cc=saravanak@google.com \ --cc=sboyd@kernel.org \ --cc=shawnguo@kernel.org \ --cc=viresh.kumar@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.