[Qemu-devel] [PATCH v2 0/9] Extend Microblaze Properties

[Qemu-devel] [PATCH v2 0/9] Extend Microblaze Properties

[Alistair Francis]

This patch series extends the MicroBlaze properties
that I have been working on. It applies on top of my
original work:
'Add Microblaze configuration options'.

This patch series converts various MicroBlaze PVR registers
to properties. This then allows the individual Microblaze
machine reset functions to be removed as well as some other
dead code.

V2:
 - Rename the usefpu variable
 - Rename the usemmu variable
 - Convert version_mask to a string

Alistair Francis (9):
  target-microblaze: Rename the usefpu variable
  target-microblaze: Convert use-mmu to a CPU property
  target-microblaze: Convert dcache-writeback to a CPU property
  target-microblaze: Convert endi to a CPU property
  target-microblaze: Convert version_mask to a CPU property
  target-microblaze: Convert pvr-full to a CPU property
  ml605_mmu: Move the hardcoded values to the init function
  s3adsp1800: Remove the hardcoded values from the reset
  target-microblaze: Remove dead code

 hw/microblaze/petalogix_ml605_mmu.c      |   23 ++++-----
 hw/microblaze/petalogix_s3adsp1800_mmu.c |    9 +---
 target-microblaze/cpu-qom.h              |    7 ++-
 target-microblaze/cpu.c                  |   78 +++++++++++++++++++++++++----
 target-microblaze/cpu.h                  |    4 +-
 target-microblaze/helper.c               |    6 +-
 target-microblaze/translate.c            |    6 +-
 7 files changed, 91 insertions(+), 42 deletions(-)

[Qemu-devel] [PATCH v2 1/9] target-microblaze: Rename the usefpu variable

[Alistair Francis]

Rename the usefpu variable to use_fpu.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
 target-microblaze/cpu-qom.h   |    2 +-
 target-microblaze/cpu.c       |    8 ++++----
 target-microblaze/translate.c |    6 +++---
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index a6474f9..aa9c032 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -63,7 +63,7 @@ typedef struct MicroBlazeCPU {
     struct {
         bool stackprot;
         uint32_t base_vectors;
-        uint8_t usefpu;
+        uint8_t use_fpu;
     } cfg;
 
     CPUMBState env;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 13ae49a..a6b6fd7 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -114,10 +114,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         | 0;
 
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
-                        (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0);
+                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0);
 
-    env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
-                        (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
+    env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
+                        (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
 
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
@@ -167,7 +167,7 @@ static Property mb_properties[] = {
      * If use-fpu = 2 - Floating point conversion and square root instructions
      *                  are enabled
      */
-    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2),
+    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 8187700..1f5fe9a 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1411,11 +1411,11 @@ static void dec_rts(DisasContext *dc)
 
 static int dec_check_fpuv2(DisasContext *dc)
 {
-    if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
+    if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
     }
-    return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
+    return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
 }
 
 static void dec_fpu(DisasContext *dc)
@@ -1424,7 +1424,7 @@ static void dec_fpu(DisasContext *dc)
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
-          && (dc->cpu->cfg.usefpu != 1)) {
+          && (dc->cpu->cfg.use_fpu != 1)) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
         return;
-- 
1.7.1

[Qemu-devel] [PATCH v2 4/9] target-microblaze: Convert endi to a CPU property

[Alistair Francis]

Originally the endi PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/microblaze/petalogix_ml605_mmu.c |    2 +-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    2 ++
 target-microblaze/cpu.h             |    2 +-
 4 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 995a579..e9adc2f 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
@@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index 3b6165d..d1d814b 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
         uint8_t use_fpu;
         bool use_mmu;
         bool dcache_writeback;
+        bool endi;
     } cfg;
 
     CPUMBState env;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 92c51a0..e6167d5 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -115,6 +115,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@@ -174,6 +175,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
+    DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 54e41e8..0f82abd 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
 #define PVR0_USE_DCACHE_MASK            0x01000000
 #define PVR0_USE_MMU_MASK               0x00800000
 #define PVR0_USE_BTC			0x00400000
-#define PVR0_ENDI			0x00200000
+#define PVR0_ENDI_MASK                  0x00200000
 #define PVR0_FAULT			0x00100000
 #define PVR0_VERSION_MASK               0x0000FF00
 #define PVR0_USER1_MASK                 0x000000FF
-- 
1.7.1

[Qemu-devel] [PATCH v2 5/9] target-microblaze: Convert version_mask to a CPU property

[Alistair Francis]

Originally the version_mask PVR bits were manually set for each
machine. This is a hassle and difficult to read, instead set them
based on the CPU properties.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
 - Convert version_mask to a string instead of a bool

 hw/microblaze/petalogix_ml605_mmu.c |    2 +-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |   53 ++++++++++++++++++++++++++++++++++-
 3 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index e9adc2f..609c90b 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
+    env->pvr.regs[0] |= (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
 }
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index d1d814b..7da25fa 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
         bool use_mmu;
         bool dcache_writeback;
         bool endi;
+        char *version;
     } cfg;
 
     CPUMBState env;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index e6167d5..a6e1872 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -26,6 +26,42 @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 
+static const struct {
+    const char *name;
+    uint8_t version_id;
+} mb_cpu_lookup[] = {
+    /* These key value are as per MBV field in PVR0 */
+    {"5.00.a", 0x01},
+    {"5.00.b", 0x02},
+    {"5.00.c", 0x03},
+    {"6.00.a", 0x04},
+    {"6.00.b", 0x06},
+    {"7.00.a", 0x05},
+    {"7.00.b", 0x07},
+    {"7.10.a", 0x08},
+    {"7.10.b", 0x09},
+    {"7.10.c", 0x0a},
+    {"7.10.d", 0x0b},
+    {"7.20.a", 0x0c},
+    {"7.20.b", 0x0d},
+    {"7.20.c", 0x0e},
+    {"7.20.d", 0x0f},
+    {"7.30.a", 0x10},
+    {"7.30.b", 0x11},
+    {"8.00.a", 0x12},
+    {"8.00.b", 0x13},
+    {"8.10.a", 0x14},
+    {"8.20.a", 0x15},
+    {"8.20.b", 0x16},
+    {"8.30.a", 0x17},
+    {"8.40.a", 0x18},
+    {"8.40.b", 0x19},
+    {"9.0", 0x1B},
+    {"9.1", 0x1D},
+    {"9.2", 0x1F},
+    {"9.3", 0x20},
+    {NULL, 0},
+};
 
 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
 {
@@ -88,6 +124,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
     CPUMBState *env = &cpu->env;
+    uint8_t version_code = 0;
+    int i = 0;
 
     qemu_init_vcpu(cs);
 
@@ -112,10 +150,22 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         | PVR2_FPU_EXC_MASK \
                         | 0;
 
+    for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
+        if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
+            version_code = mb_cpu_lookup[i].version_id;
+            break;
+        }
+    }
+
+    if (!version_code) {
+        qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
+    }
+
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
-                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+                        (version_code << 16);
 
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@@ -176,6 +226,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
+    DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
1.7.1

[Qemu-devel] [PATCH v2 6/9] target-microblaze: Convert pvr-full to a CPU property

[Alistair Francis]

Originally the pvr-full PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
 - Rename DTS mapping

 target-microblaze/cpu-qom.h |    1 +
 target-microblaze/cpu.c     |    5 +++--
 target-microblaze/helper.c  |    4 ++--
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index 7da25fa..74d70de 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
         bool dcache_writeback;
         bool endi;
         char *version;
+        bool pvr_full;
     } cfg;
 
     CPUMBState env;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index a6e1872..8a86aa5 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -129,8 +129,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     qemu_init_vcpu(cs);
 
-    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
-                       | PVR0_USE_BARREL_MASK \
+    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
                        | PVR0_USE_DIV_MASK \
                        | PVR0_USE_HW_MUL_MASK \
                        | PVR0_USE_EXC_MASK \
@@ -166,6 +165,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
                         (version_code << 16);
+                        (cpu->cfg.pvr_full ? PVR0_PVR_FULL_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@@ -227,6 +227,7 @@ static Property mb_properties[] = {
                      false),
     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
+    DEFINE_PROP_BOOL("pvr", MicroBlazeCPU, cfg.pvr_full, true),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 5156c12..c3e1d79 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
     mmu_available = 0;
     if (cpu->cfg.use_mmu) {
         mmu_available = 1;
-        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
-            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
+        if (cpu->cfg.pvr_full &&
+            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
             mmu_available = 0;
         }
     }
-- 
1.7.1

[Qemu-devel] [PATCH v2 7/9] ml605_mmu: Move the hardcoded values to the init function

[Alistair Francis]

Move the hard coded register values to the init function.
This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.

The hardcoded PVR0 values can be removed as they are setting
the endianness and stack protection, which is already done
or invalid.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
 - Don't set PVR0

 hw/microblaze/petalogix_ml605_mmu.c |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 609c90b..ed84a37 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -64,17 +64,6 @@
 #define SPI_IRQ             4
 #define UART16550_IRQ       5
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
-    /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= (0x14 << 8);
-    env->pvr.regs[4] = 0xc56b8000;
-    env->pvr.regs[5] = 0xc56be000;
-}
-
 static void
 petalogix_ml605_init(MachineState *machine)
 {
@@ -205,10 +194,15 @@ petalogix_ml605_init(MachineState *machine)
         }
     }
 
+    /* setup PVR to match kernel settings */
+    cpu->env.pvr.regs[4] = 0xc56b8000;
+    cpu->env.pvr.regs[5] = 0xc56be000;
+    cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
+
     microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 
 }
 
-- 
1.7.1

[Qemu-devel] [PATCH v2 8/9] s3adsp1800: Remove the hardcoded values from the reset

[Alistair Francis]

Remove the hardcoded values from the machine specific reset
function, as the same values are already set in the standard
MicroBlaze reset.

This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/microblaze/petalogix_s3adsp1800_mmu.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index 84f6e74..7109e63 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -51,13 +51,6 @@
 #define ETHLITE_IRQ         1
 #define UARTLITE_IRQ        3
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family.  */
-}
-
 static void
 petalogix_s3adsp1800_init(MachineState *machine)
 {
@@ -132,7 +125,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
     microblaze_load_kernel(cpu, ddr_base, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 }
 
 static QEMUMachine petalogix_s3adsp1800_machine = {
-- 
1.7.1

[Qemu-devel] [PATCH v2 9/9] target-microblaze: Remove dead code

[Alistair Francis]

This code is already being run in the mb_cpu_realizefn()
function. As PVR registers are preserved on reset this
code is not required.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-microblaze/cpu.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 8a86aa5..1380f91 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -178,10 +178,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->sregs[SR_PC] = cpu->cfg.base_vectors;
 
-#if defined(CONFIG_USER_ONLY)
-    env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp.  */
-#endif
-
     mcc->parent_realize(dev, errp);
 }
 
-- 
1.7.1

Re: [Qemu-devel] [PATCH v2 1/9] target-microblaze: Rename the usefpu variable

[Peter Crosthwaite]

On Thu, Jun 4, 2015 at 11:39 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Rename the usefpu variable to use_fpu.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  target-microblaze/cpu-qom.h   |    2 +-
>  target-microblaze/cpu.c       |    8 ++++----
>  target-microblaze/translate.c |    6 +++---
>  3 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index a6474f9..aa9c032 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -63,7 +63,7 @@ typedef struct MicroBlazeCPU {
>      struct {
>          bool stackprot;
>          uint32_t base_vectors;
> -        uint8_t usefpu;
> +        uint8_t use_fpu;
>      } cfg;
>
>      CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 13ae49a..a6b6fd7 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -114,10 +114,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                          | 0;
>
>      env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
> -                        (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0);
> +                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0);
>
> -    env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
> -                        (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
> +    env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> +                        (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>
>      env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
>      env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
> @@ -167,7 +167,7 @@ static Property mb_properties[] = {
>       * If use-fpu = 2 - Floating point conversion and square root instructions
>       *                  are enabled
>       */
> -    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2),
> +    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 8187700..1f5fe9a 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -1411,11 +1411,11 @@ static void dec_rts(DisasContext *dc)
>
>  static int dec_check_fpuv2(DisasContext *dc)
>  {
> -    if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
> +    if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
>          tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
>          t_gen_raise_exception(dc, EXCP_HW_EXCP);
>      }
> -    return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
> +    return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
>  }
>
>  static void dec_fpu(DisasContext *dc)
> @@ -1424,7 +1424,7 @@ static void dec_fpu(DisasContext *dc)
>
>      if ((dc->tb_flags & MSR_EE_FLAG)
>            && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
> -          && (dc->cpu->cfg.usefpu != 1)) {
> +          && (dc->cpu->cfg.use_fpu != 1)) {
>          tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
>          t_gen_raise_exception(dc, EXCP_HW_EXCP);
>          return;
> --
> 1.7.1
>
>

[Qemu-devel] [PATCH v2 2/9] target-microblaze: Convert use-mmu to a CPU property

[Peter Crosthwaite]

From: Alistair Francis <alistair.francis@xilinx.com>

Originally the use-mmu PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
 - Fix up variable name

 target-microblaze/cpu-qom.h |    1 +
 target-microblaze/cpu.c     |    5 +++--
 target-microblaze/cpu.h     |    2 +-
 target-microblaze/helper.c  |    2 +-
 4 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index aa9c032..6bde2e9 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -64,6 +64,7 @@ typedef struct MicroBlazeCPU {
         bool stackprot;
         uint32_t base_vectors;
         uint8_t use_fpu;
+        bool use_mmu;
     } cfg;
 
     CPUMBState env;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index a6b6fd7..c4cd68a 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -98,7 +98,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                        | PVR0_USE_EXC_MASK \
                        | PVR0_USE_ICACHE_MASK \
                        | PVR0_USE_DCACHE_MASK \
-                       | PVR0_USE_MMU \
                        | (0xb << 8);
     env->pvr.regs[2] = PVR2_D_OPB_MASK \
                         | PVR2_D_LMB_MASK \
@@ -114,7 +113,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         | 0;
 
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
-                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0);
+                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
+                        (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@@ -168,6 +168,7 @@ static Property mb_properties[] = {
      *                  are enabled
      */
     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
+    DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 60a7500..54e41e8 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -122,7 +122,7 @@ typedef struct CPUMBState CPUMBState;
 #define PVR0_USE_EXC_MASK               0x04000000
 #define PVR0_USE_ICACHE_MASK            0x02000000
 #define PVR0_USE_DCACHE_MASK            0x01000000
-#define PVR0_USE_MMU                    0x00800000      /* new */
+#define PVR0_USE_MMU_MASK               0x00800000
 #define PVR0_USE_BTC			0x00400000
 #define PVR0_ENDI			0x00200000
 #define PVR0_FAULT			0x00100000
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 69c3252..5156c12 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -56,7 +56,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
     int prot;
 
     mmu_available = 0;
-    if (env->pvr.regs[0] & PVR0_USE_MMU) {
+    if (cpu->cfg.use_mmu) {
         mmu_available = 1;
         if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
             && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
-- 
1.7.1

[Qemu-devel] [PATCH v2 3/9] target-microblaze: Convert dcache-writeback to a CPU property

[Peter Crosthwaite]

From: Alistair Francis <alistair.francis@xilinx.com>

Originally  the dcache-writeback PVR bits were manually set for each machine.
This is a hassle and difficult to read, instead set them based on the CPU
properties.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    5 +++++
 3 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 05c120a..995a579 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
     env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
@@ -98,6 +97,8 @@ petalogix_ml605_init(MachineState *machine)
      * root instructions
      */
     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
+                             &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index 6bde2e9..3b6165d 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -65,6 +65,7 @@ typedef struct MicroBlazeCPU {
         uint32_t base_vectors;
         uint8_t use_fpu;
         bool use_mmu;
+        bool dcache_writeback;
     } cfg;
 
     CPUMBState env;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index c4cd68a..92c51a0 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -119,6 +119,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
 
+    env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
+                                        PVR5_DCACHE_WRITEBACK_MASK : 0;
+
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
 
@@ -169,6 +172,8 @@ static Property mb_properties[] = {
      */
     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
+    DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
+                     false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
1.7.1

Re: [Qemu-devel] [PATCH v2 1/9] target-microblaze: Rename the usefpu variable

[Alistair Francis]

On Fri, Jun 5, 2015 at 6:04 PM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Thu, Jun 4, 2015 at 11:39 PM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> Rename the usefpu variable to use_fpu.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>
> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Thanks Peter

Alistair

>
>> ---
>>  target-microblaze/cpu-qom.h   |    2 +-
>>  target-microblaze/cpu.c       |    8 ++++----
>>  target-microblaze/translate.c |    6 +++---
>>  3 files changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
>> index a6474f9..aa9c032 100644
>> --- a/target-microblaze/cpu-qom.h
>> +++ b/target-microblaze/cpu-qom.h
>> @@ -63,7 +63,7 @@ typedef struct MicroBlazeCPU {
>>      struct {
>>          bool stackprot;
>>          uint32_t base_vectors;
>> -        uint8_t usefpu;
>> +        uint8_t use_fpu;
>>      } cfg;
>>
>>      CPUMBState env;
>> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
>> index 13ae49a..a6b6fd7 100644
>> --- a/target-microblaze/cpu.c
>> +++ b/target-microblaze/cpu.c
>> @@ -114,10 +114,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>>                          | 0;
>>
>>      env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
>> -                        (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0);
>> +                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0);
>>
>> -    env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
>> -                        (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>> +    env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>> +                        (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>>
>>      env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
>>      env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
>> @@ -167,7 +167,7 @@ static Property mb_properties[] = {
>>       * If use-fpu = 2 - Floating point conversion and square root instructions
>>       *                  are enabled
>>       */
>> -    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2),
>> +    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
>>      DEFINE_PROP_END_OF_LIST(),
>>  };
>>
>> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
>> index 8187700..1f5fe9a 100644
>> --- a/target-microblaze/translate.c
>> +++ b/target-microblaze/translate.c
>> @@ -1411,11 +1411,11 @@ static void dec_rts(DisasContext *dc)
>>
>>  static int dec_check_fpuv2(DisasContext *dc)
>>  {
>> -    if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
>> +    if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
>>          tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
>>          t_gen_raise_exception(dc, EXCP_HW_EXCP);
>>      }
>> -    return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
>> +    return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
>>  }
>>
>>  static void dec_fpu(DisasContext *dc)
>> @@ -1424,7 +1424,7 @@ static void dec_fpu(DisasContext *dc)
>>
>>      if ((dc->tb_flags & MSR_EE_FLAG)
>>            && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
>> -          && (dc->cpu->cfg.usefpu != 1)) {
>> +          && (dc->cpu->cfg.use_fpu != 1)) {
>>          tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
>>          t_gen_raise_exception(dc, EXCP_HW_EXCP);
>>          return;
>> --
>> 1.7.1
>>
>>
>

Re: [Qemu-devel] [PATCH v2 2/9] target-microblaze: Convert use-mmu to a CPU property

[Peter Crosthwaite]

On Mon, Jun 8, 2015 at 4:31 PM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> From: Alistair Francis <alistair.francis@xilinx.com>
>
> Originally the use-mmu PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
> V2:
>  - Fix up variable name
>
>  target-microblaze/cpu-qom.h |    1 +
>  target-microblaze/cpu.c     |    5 +++--
>  target-microblaze/cpu.h     |    2 +-
>  target-microblaze/helper.c  |    2 +-
>  4 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index aa9c032..6bde2e9 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -64,6 +64,7 @@ typedef struct MicroBlazeCPU {
>          bool stackprot;
>          uint32_t base_vectors;
>          uint8_t use_fpu;
> +        bool use_mmu;
>      } cfg;
>
>      CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index a6b6fd7..c4cd68a 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -98,7 +98,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                         | PVR0_USE_EXC_MASK \
>                         | PVR0_USE_ICACHE_MASK \
>                         | PVR0_USE_DCACHE_MASK \
> -                       | PVR0_USE_MMU \
>                         | (0xb << 8);
>      env->pvr.regs[2] = PVR2_D_OPB_MASK \
>                          | PVR2_D_LMB_MASK \
> @@ -114,7 +113,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                          | 0;
>
>      env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
> -                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0);
> +                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
> +                        (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
>
>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
> @@ -168,6 +168,7 @@ static Property mb_properties[] = {
>       *                  are enabled
>       */
>      DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
> +    DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
> index 60a7500..54e41e8 100644
> --- a/target-microblaze/cpu.h
> +++ b/target-microblaze/cpu.h
> @@ -122,7 +122,7 @@ typedef struct CPUMBState CPUMBState;
>  #define PVR0_USE_EXC_MASK               0x04000000
>  #define PVR0_USE_ICACHE_MASK            0x02000000
>  #define PVR0_USE_DCACHE_MASK            0x01000000
> -#define PVR0_USE_MMU                    0x00800000      /* new */
> +#define PVR0_USE_MMU_MASK               0x00800000
>  #define PVR0_USE_BTC                   0x00400000
>  #define PVR0_ENDI                      0x00200000
>  #define PVR0_FAULT                     0x00100000
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index 69c3252..5156c12 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -56,7 +56,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
>      int prot;
>
>      mmu_available = 0;
> -    if (env->pvr.regs[0] & PVR0_USE_MMU) {
> +    if (cpu->cfg.use_mmu) {
>          mmu_available = 1;
>          if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
>              && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
> --
> 1.7.1
>

Re: [Qemu-devel] [PATCH v2 3/9] target-microblaze: Convert dcache-writeback to a CPU property

[Peter Crosthwaite]

On Mon, Jun 8, 2015 at 4:31 PM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> From: Alistair Francis <alistair.francis@xilinx.com>
>
> Originally  the dcache-writeback PVR bits were manually set for each machine.
> This is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
>  target-microblaze/cpu-qom.h         |    1 +
>  target-microblaze/cpu.c             |    5 +++++
>  3 files changed, 8 insertions(+), 1 deletions(-)
>
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
> index 05c120a..995a579 100644
> --- a/hw/microblaze/petalogix_ml605_mmu.c
> +++ b/hw/microblaze/petalogix_ml605_mmu.c
> @@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
>
>      env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
>      /* setup pvr to match kernel setting */
> -    env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
>      env->pvr.regs[0] |= PVR0_ENDI;
>      env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
>      env->pvr.regs[4] = 0xc56b8000;
> @@ -98,6 +97,8 @@ petalogix_ml605_init(MachineState *machine)
>       * root instructions
>       */
>      object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
> +    object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
> +                             &error_abort);
>      object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
>
>      /* Attach emulated BRAM through the LMB.  */
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index 6bde2e9..3b6165d 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -65,6 +65,7 @@ typedef struct MicroBlazeCPU {
>          uint32_t base_vectors;
>          uint8_t use_fpu;
>          bool use_mmu;
> +        bool dcache_writeback;
>      } cfg;
>
>      CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index c4cd68a..92c51a0 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -119,6 +119,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>
> +    env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
> +                                        PVR5_DCACHE_WRITEBACK_MASK : 0;
> +
>      env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
>      env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
>
> @@ -169,6 +172,8 @@ static Property mb_properties[] = {
>       */
>      DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
>      DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
> +    DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
> +                     false),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> --
> 1.7.1
>

Re: [Qemu-devel] [PATCH v2 4/9] target-microblaze: Convert endi to a CPU property

[Peter Crosthwaite]

On Thu, Jun 4, 2015 at 11:41 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Originally the endi PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  hw/microblaze/petalogix_ml605_mmu.c |    2 +-
>  target-microblaze/cpu-qom.h         |    1 +
>  target-microblaze/cpu.c             |    2 ++
>  target-microblaze/cpu.h             |    2 +-
>  4 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
> index 995a579..e9adc2f 100644
> --- a/hw/microblaze/petalogix_ml605_mmu.c
> +++ b/hw/microblaze/petalogix_ml605_mmu.c
> @@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
>
>      env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
>      /* setup pvr to match kernel setting */
> -    env->pvr.regs[0] |= PVR0_ENDI;
>      env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
>      env->pvr.regs[4] = 0xc56b8000;
>      env->pvr.regs[5] = 0xc56be000;
> @@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
>      object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
>      object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
>                               &error_abort);
> +    object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
>      object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
>
>      /* Attach emulated BRAM through the LMB.  */
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index 3b6165d..d1d814b 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
>          uint8_t use_fpu;
>          bool use_mmu;
>          bool dcache_writeback;
> +        bool endi;
>      } cfg;
>
>      CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 92c51a0..e6167d5 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -115,6 +115,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>      env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
>                          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
> +                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
>
>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
> @@ -174,6 +175,7 @@ static Property mb_properties[] = {
>      DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
>      DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
>                       false),
> +    DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
> index 54e41e8..0f82abd 100644
> --- a/target-microblaze/cpu.h
> +++ b/target-microblaze/cpu.h
> @@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
>  #define PVR0_USE_DCACHE_MASK            0x01000000
>  #define PVR0_USE_MMU_MASK               0x00800000
>  #define PVR0_USE_BTC                   0x00400000
> -#define PVR0_ENDI                      0x00200000
> +#define PVR0_ENDI_MASK                  0x00200000
>  #define PVR0_FAULT                     0x00100000
>  #define PVR0_VERSION_MASK               0x0000FF00
>  #define PVR0_USER1_MASK                 0x000000FF
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v2 5/9] target-microblaze: Convert version_mask to a CPU property

[Peter Crosthwaite]

On Thu, Jun 4, 2015 at 11:42 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Originally the version_mask PVR bits were manually set for each
> machine. This is a hassle and difficult to read, instead set them
> based on the CPU properties.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V2:
>  - Convert version_mask to a string instead of a bool
>
>  hw/microblaze/petalogix_ml605_mmu.c |    2 +-
>  target-microblaze/cpu-qom.h         |    1 +
>  target-microblaze/cpu.c             |   53 ++++++++++++++++++++++++++++++++++-
>  3 files changed, 54 insertions(+), 2 deletions(-)
>
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
> index e9adc2f..609c90b 100644
> --- a/hw/microblaze/petalogix_ml605_mmu.c
> +++ b/hw/microblaze/petalogix_ml605_mmu.c
> @@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
>
>      env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
>      /* setup pvr to match kernel setting */
> -    env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
> +    env->pvr.regs[0] |= (0x14 << 8);
>      env->pvr.regs[4] = 0xc56b8000;
>      env->pvr.regs[5] = 0xc56be000;
>  }
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index d1d814b..7da25fa 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
>          bool use_mmu;
>          bool dcache_writeback;
>          bool endi;
> +        char *version;
>      } cfg;
>
>      CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index e6167d5..a6e1872 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -26,6 +26,42 @@
>  #include "hw/qdev-properties.h"
>  #include "migration/vmstate.h"
>
> +static const struct {
> +    const char *name;
> +    uint8_t version_id;
> +} mb_cpu_lookup[] = {
> +    /* These key value are as per MBV field in PVR0 */
> +    {"5.00.a", 0x01},
> +    {"5.00.b", 0x02},
> +    {"5.00.c", 0x03},
> +    {"6.00.a", 0x04},
> +    {"6.00.b", 0x06},
> +    {"7.00.a", 0x05},
> +    {"7.00.b", 0x07},
> +    {"7.10.a", 0x08},
> +    {"7.10.b", 0x09},
> +    {"7.10.c", 0x0a},
> +    {"7.10.d", 0x0b},
> +    {"7.20.a", 0x0c},
> +    {"7.20.b", 0x0d},
> +    {"7.20.c", 0x0e},
> +    {"7.20.d", 0x0f},
> +    {"7.30.a", 0x10},
> +    {"7.30.b", 0x11},
> +    {"8.00.a", 0x12},
> +    {"8.00.b", 0x13},
> +    {"8.10.a", 0x14},
> +    {"8.20.a", 0x15},
> +    {"8.20.b", 0x16},
> +    {"8.30.a", 0x17},
> +    {"8.40.a", 0x18},
> +    {"8.40.b", 0x19},

missing 8.50.a (0x1a)

Otherwise,

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Regards,
Peter

> +    {"9.0", 0x1B},
> +    {"9.1", 0x1D},
> +    {"9.2", 0x1F},
> +    {"9.3", 0x20},
> +    {NULL, 0},
> +};
>
>  static void mb_cpu_set_pc(CPUState *cs, vaddr value)
>  {
> @@ -88,6 +124,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>      MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
>      MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
>      CPUMBState *env = &cpu->env;
> +    uint8_t version_code = 0;
> +    int i = 0;
>
>      qemu_init_vcpu(cs);
>
> @@ -112,10 +150,22 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                          | PVR2_FPU_EXC_MASK \
>                          | 0;
>
> +    for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
> +        if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
> +            version_code = mb_cpu_lookup[i].version_id;
> +            break;
> +        }
> +    }
> +
> +    if (!version_code) {
> +        qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
> +    }
> +
>      env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
>                          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
> -                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
> +                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
> +                        (version_code << 16);
>
>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
> @@ -176,6 +226,7 @@ static Property mb_properties[] = {
>      DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
>                       false),
>      DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
> +    DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v2 6/9] target-microblaze: Convert pvr-full to a CPU property

[Peter Crosthwaite]

On Thu, Jun 4, 2015 at 11:42 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Originally the pvr-full PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V2:
>  - Rename DTS mapping
>
>  target-microblaze/cpu-qom.h |    1 +
>  target-microblaze/cpu.c     |    5 +++--
>  target-microblaze/helper.c  |    4 ++--
>  3 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index 7da25fa..74d70de 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
>          bool dcache_writeback;
>          bool endi;
>          char *version;
> +        bool pvr_full;
>      } cfg;
>
>      CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index a6e1872..8a86aa5 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -129,8 +129,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>
>      qemu_init_vcpu(cs);
>
> -    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
> -                       | PVR0_USE_BARREL_MASK \
> +    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
>                         | PVR0_USE_DIV_MASK \
>                         | PVR0_USE_HW_MUL_MASK \
>                         | PVR0_USE_EXC_MASK \
> @@ -166,6 +165,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
>                          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
>                          (version_code << 16);
> +                        (cpu->cfg.pvr_full ? PVR0_PVR_FULL_MASK : 0);
>
>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
> @@ -227,6 +227,7 @@ static Property mb_properties[] = {
>                       false),
>      DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
>      DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> +    DEFINE_PROP_BOOL("pvr", MicroBlazeCPU, cfg.pvr_full, true),


>From UG984, C_PVR config option has 3 encodings (0-2). Even if we do
not support the functional difference for basic vs none (0 v 1) on
this setting, the prop should match the encoding scheme. This should
be uint8_t where 2 means full version PVR.

Regards,
Peter

>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index 5156c12..c3e1d79 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
>      mmu_available = 0;
>      if (cpu->cfg.use_mmu) {
>          mmu_available = 1;
> -        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
> -            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
> +        if (cpu->cfg.pvr_full &&
> +            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
>              mmu_available = 0;
>          }
>      }
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v2 7/9] ml605_mmu: Move the hardcoded values to the init function

[Peter Crosthwaite]

On Thu, Jun 4, 2015 at 11:43 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Move the hard coded register values to the init function.
> This also allows the entire reset function to be deleted, as
> PVR registers are now preserved on reset.
>
> The hardcoded PVR0 values can be removed as they are setting
> the endianness and stack protection, which is already done
> or invalid.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
> V2:
>  - Don't set PVR0
>
>  hw/microblaze/petalogix_ml605_mmu.c |   18 ++++++------------
>  1 files changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
> index 609c90b..ed84a37 100644
> --- a/hw/microblaze/petalogix_ml605_mmu.c
> +++ b/hw/microblaze/petalogix_ml605_mmu.c
> @@ -64,17 +64,6 @@
>  #define SPI_IRQ             4
>  #define UART16550_IRQ       5
>
> -static void machine_cpu_reset(MicroBlazeCPU *cpu)
> -{
> -    CPUMBState *env = &cpu->env;
> -
> -    env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
> -    /* setup pvr to match kernel setting */
> -    env->pvr.regs[0] |= (0x14 << 8);
> -    env->pvr.regs[4] = 0xc56b8000;
> -    env->pvr.regs[5] = 0xc56be000;
> -}
> -
>  static void
>  petalogix_ml605_init(MachineState *machine)
>  {
> @@ -205,10 +194,15 @@ petalogix_ml605_init(MachineState *machine)
>          }
>      }
>
> +    /* setup PVR to match kernel settings */
> +    cpu->env.pvr.regs[4] = 0xc56b8000;
> +    cpu->env.pvr.regs[5] = 0xc56be000;
> +    cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
> +
>      microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
>                             machine->initrd_filename,
>                             BINARY_DEVICE_TREE_FILE,
> -                           machine_cpu_reset);
> +                           NULL);
>
>  }
>
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v2 8/9] s3adsp1800: Remove the hardcoded values from the reset

[Peter Crosthwaite]

On Thu, Jun 4, 2015 at 11:43 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Remove the hardcoded values from the machine specific reset
> function, as the same values are already set in the standard
> MicroBlaze reset.
>
> This also allows the entire reset function to be deleted, as
> PVR registers are now preserved on reset.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  hw/microblaze/petalogix_s3adsp1800_mmu.c |    9 +--------
>  1 files changed, 1 insertions(+), 8 deletions(-)
>
> diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
> index 84f6e74..7109e63 100644
> --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
> +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
> @@ -51,13 +51,6 @@
>  #define ETHLITE_IRQ         1
>  #define UARTLITE_IRQ        3
>
> -static void machine_cpu_reset(MicroBlazeCPU *cpu)
> -{
> -    CPUMBState *env = &cpu->env;
> -
> -    env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family.  */
> -}
> -
>  static void
>  petalogix_s3adsp1800_init(MachineState *machine)
>  {
> @@ -132,7 +125,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
>      microblaze_load_kernel(cpu, ddr_base, ram_size,
>                             machine->initrd_filename,
>                             BINARY_DEVICE_TREE_FILE,
> -                           machine_cpu_reset);
> +                           NULL);
>  }
>
>  static QEMUMachine petalogix_s3adsp1800_machine = {
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v2 9/9] target-microblaze: Remove dead code

[Peter Crosthwaite]

On Thu, Jun 4, 2015 at 11:44 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> This code is already being run in the mb_cpu_realizefn()
> function. As PVR registers are preserved on reset this
> code is not required.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  target-microblaze/cpu.c |    4 ----
>  1 files changed, 0 insertions(+), 4 deletions(-)
>
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 8a86aa5..1380f91 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -178,10 +178,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>
>      env->sregs[SR_PC] = cpu->cfg.base_vectors;
>
> -#if defined(CONFIG_USER_ONLY)
> -    env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp.  */
> -#endif
> -
>      mcc->parent_realize(dev, errp);
>  }
>
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v2 6/9] target-microblaze: Convert pvr-full to a CPU property

[Alistair Francis]

On Mon, Jun 15, 2015 at 12:41 PM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Thu, Jun 4, 2015 at 11:42 PM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> Originally the pvr-full PVR bits were manually set for each machine. This
>> is a hassle and difficult to read, instead set them based on the CPU
>> properties.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> V2:
>>  - Rename DTS mapping
>>
>>  target-microblaze/cpu-qom.h |    1 +
>>  target-microblaze/cpu.c     |    5 +++--
>>  target-microblaze/helper.c  |    4 ++--
>>  3 files changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
>> index 7da25fa..74d70de 100644
>> --- a/target-microblaze/cpu-qom.h
>> +++ b/target-microblaze/cpu-qom.h
>> @@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
>>          bool dcache_writeback;
>>          bool endi;
>>          char *version;
>> +        bool pvr_full;
>>      } cfg;
>>
>>      CPUMBState env;
>> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
>> index a6e1872..8a86aa5 100644
>> --- a/target-microblaze/cpu.c
>> +++ b/target-microblaze/cpu.c
>> @@ -129,8 +129,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>>
>>      qemu_init_vcpu(cs);
>>
>> -    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
>> -                       | PVR0_USE_BARREL_MASK \
>> +    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
>>                         | PVR0_USE_DIV_MASK \
>>                         | PVR0_USE_HW_MUL_MASK \
>>                         | PVR0_USE_EXC_MASK \
>> @@ -166,6 +165,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>>                          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
>>                          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
>>                          (version_code << 16);
>> +                        (cpu->cfg.pvr_full ? PVR0_PVR_FULL_MASK : 0);
>>
>>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>> @@ -227,6 +227,7 @@ static Property mb_properties[] = {
>>                       false),
>>      DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
>>      DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
>> +    DEFINE_PROP_BOOL("pvr", MicroBlazeCPU, cfg.pvr_full, true),
>
>
> From UG984, C_PVR config option has 3 encodings (0-2). Even if we do
> not support the functional difference for basic vs none (0 v 1) on
> this setting, the prop should match the encoding scheme. This should
> be uint8_t where 2 means full version PVR.

Thanks Peter, you are correct. I just assumed it was a bool, thanks for
double checking. Fixed in version 3.

Thanks,

Alistair

>
> Regards,
> Peter
>
>>      DEFINE_PROP_END_OF_LIST(),
>>  };
>>
>> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
>> index 5156c12..c3e1d79 100644
>> --- a/target-microblaze/helper.c
>> +++ b/target-microblaze/helper.c
>> @@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
>>      mmu_available = 0;
>>      if (cpu->cfg.use_mmu) {
>>          mmu_available = 1;
>> -        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
>> -            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
>> +        if (cpu->cfg.pvr_full &&
>> +            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
>>              mmu_available = 0;
>>          }
>>      }
>> --
>> 1.7.1
>>
>>
>

Re: [Qemu-devel] [PATCH v2 4/9] target-microblaze: Convert endi to a CPU property

[Alistair Francis]

On Mon, Jun 15, 2015 at 12:31 PM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Thu, Jun 4, 2015 at 11:41 PM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> Originally the endi PVR bits were manually set for each machine. This
>> is a hassle and difficult to read, instead set them based on the CPU
>> properties.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Thanks Peter. Also thanks for all of the other reviewed-by

>
>> ---
>>  hw/microblaze/petalogix_ml605_mmu.c |    2 +-
>>  target-microblaze/cpu-qom.h         |    1 +
>>  target-microblaze/cpu.c             |    2 ++
>>  target-microblaze/cpu.h             |    2 +-
>>  4 files changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
>> index 995a579..e9adc2f 100644
>> --- a/hw/microblaze/petalogix_ml605_mmu.c
>> +++ b/hw/microblaze/petalogix_ml605_mmu.c
>> @@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
>>
>>      env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
>>      /* setup pvr to match kernel setting */
>> -    env->pvr.regs[0] |= PVR0_ENDI;
>>      env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
>>      env->pvr.regs[4] = 0xc56b8000;
>>      env->pvr.regs[5] = 0xc56be000;
>> @@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
>>      object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
>>      object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
>>                               &error_abort);
>> +    object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
>>      object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
>>
>>      /* Attach emulated BRAM through the LMB.  */
>> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
>> index 3b6165d..d1d814b 100644
>> --- a/target-microblaze/cpu-qom.h
>> +++ b/target-microblaze/cpu-qom.h
>> @@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
>>          uint8_t use_fpu;
>>          bool use_mmu;
>>          bool dcache_writeback;
>> +        bool endi;
>>      } cfg;
>>
>>      CPUMBState env;
>> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
>> index 92c51a0..e6167d5 100644
>> --- a/target-microblaze/cpu.c
>> +++ b/target-microblaze/cpu.c
>> @@ -115,6 +115,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>>      env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
>>                          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
>>                          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
>> +                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);

I just realised that we all missed this. GCC found it, but only as a warning, so
I didn't notice it during testing. All fixed now.

Thanks,

Alistair

>>
>>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>> @@ -174,6 +175,7 @@ static Property mb_properties[] = {
>>      DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
>>      DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
>>                       false),
>> +    DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
>>      DEFINE_PROP_END_OF_LIST(),
>>  };
>>
>> diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
>> index 54e41e8..0f82abd 100644
>> --- a/target-microblaze/cpu.h
>> +++ b/target-microblaze/cpu.h
>> @@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
>>  #define PVR0_USE_DCACHE_MASK            0x01000000
>>  #define PVR0_USE_MMU_MASK               0x00800000
>>  #define PVR0_USE_BTC                   0x00400000
>> -#define PVR0_ENDI                      0x00200000
>> +#define PVR0_ENDI_MASK                  0x00200000
>>  #define PVR0_FAULT                     0x00100000
>>  #define PVR0_VERSION_MASK               0x0000FF00
>>  #define PVR0_USER1_MASK                 0x000000FF
>> --
>> 1.7.1
>>
>>
>