[Qemu-devel] [PATCH v1 0/3] xlnx-zynqmp: Connect the AHCI SATA device

[Qemu-devel] [PATCH v1 0/3] xlnx-zynqmp: Connect the AHCI SATA device

[Alistair Francis]

This series connects the AHCI SATA device to the ZynqMP
machine. It requires a restructure of the AHCI file to
make the AHCI state struct visible. It also requires a
small change to object_class_dynamic_cast() to return
NULL if the class doesn't have a type.

Alistair Francis (3):
  ahci: Seperate the AHCI state structure into the header
  object.c: object_class_dynamic_cast return NULL if the class has no
    type
  xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP

 hw/arm/xlnx-zynqmp.c         |   20 ++++++++++++++++++++
 hw/ide/ahci.c                |   13 -------------
 hw/ide/ahci.h                |   14 ++++++++++++++
 include/hw/arm/xlnx-zynqmp.h |    3 +++
 qom/object.c                 |    2 +-
 5 files changed, 38 insertions(+), 14 deletions(-)

[Qemu-devel] [PATCH v1 1/3] ahci: Separate the AHCI state structure into the header

[Alistair Francis]

Pull the AHCI state structure out into the header. This allows
other containers to access the struct. This is required to add
the device to modern SoC containers.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
---
 hw/ide/ahci.c |   13 -------------
 hw/ide/ahci.h |   14 ++++++++++++++
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 48749c1..02d85fa 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -25,7 +25,6 @@
 #include <hw/pci/msi.h>
 #include <hw/i386/pc.h>
 #include <hw/pci/pci.h>
-#include <hw/sysbus.h>
 
 #include "qemu/error-report.h"
 #include "sysemu/block-backend.h"
@@ -1625,18 +1624,6 @@ const VMStateDescription vmstate_ahci = {
     },
 };
 
-#define TYPE_SYSBUS_AHCI "sysbus-ahci"
-#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
-
-typedef struct SysbusAHCIState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-    /*< public >*/
-
-    AHCIState ahci;
-    uint32_t num_ports;
-} SysbusAHCIState;
-
 static const VMStateDescription vmstate_sysbus_ahci = {
     .name = "sysbus-ahci",
     .fields = (VMStateField[]) {
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 68d5074..5ab8ea4 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -24,6 +24,8 @@
 #ifndef HW_IDE_AHCI_H
 #define HW_IDE_AHCI_H
 
+#include <hw/sysbus.h>
+
 #define AHCI_MEM_BAR_SIZE         0x1000
 #define AHCI_MAX_PORTS            32
 #define AHCI_MAX_SG               168 /* hardware max is 64K */
@@ -369,4 +371,16 @@ void ahci_reset(AHCIState *s);
 
 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
 
+#define TYPE_SYSBUS_AHCI "sysbus-ahci"
+#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
+
+typedef struct SysbusAHCIState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+
+    AHCIState ahci;
+    uint32_t num_ports;
+} SysbusAHCIState;
+
 #endif /* HW_IDE_AHCI_H */
-- 
1.7.1

[Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Alistair Francis]

If the ObjectClass has no type return NULL instead of trying to compare
the type name.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
---
 qom/object.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/qom/object.c b/qom/object.c
index eea8edf..2d6d715 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -603,7 +603,7 @@ ObjectClass *object_class_dynamic_cast(ObjectClass *class,
     TypeImpl *target_type;
     TypeImpl *type;
 
-    if (!class) {
+    if (!class || !class->type) {
         return NULL;
     }
 
-- 
1.7.1

[Qemu-devel] [PATCH v1 3/3] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP

[Alistair Francis]

Connect the Sysbus AHCI device to ZynqMP.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
---
 hw/arm/xlnx-zynqmp.c         |   20 ++++++++++++++++++++
 include/hw/arm/xlnx-zynqmp.h |    3 +++
 2 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 62ef4ce..7adcce9 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -28,6 +28,9 @@
 #define GIC_DIST_ADDR       0xf9010000
 #define GIC_CPU_ADDR        0xf9020000
 
+#define SYSBUS_AHCI_ADDR    0xFD0C0000
+#define SYSBUS_AHCI_INTR    133
+
 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
 };
@@ -90,6 +93,9 @@ static void xlnx_zynqmp_init(Object *obj)
         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
     }
+
+    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
+    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 }
 
 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -235,6 +241,20 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                            gic_spi[uart_intr[i]]);
     }
+
+    object_property_set_int(OBJECT(&s->sata), 2, "num-ports", &err);
+    if (err) {
+        error_propagate((errp), (err));
+        return;
+    }
+    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
+    if (err) {
+        error_propagate((errp), (err));
+        return;
+    }
+
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SYSBUS_AHCI_ADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SYSBUS_AHCI_INTR]);
 }
 
 static Property xlnx_zynqmp_props[] = {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index c379632..024e316 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,8 @@
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
+#include "hw/ide/pci.h"
+#include "hw/ide/ahci.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -54,6 +56,7 @@ typedef struct XlnxZynqMPState {
     MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+    SysbusAHCIState sata;
 
     char *boot_cpu;
     ARMCPU *boot_cpu_ptr;
-- 
1.7.1

Re: [Qemu-devel] [PATCH v1 1/3] ahci: Separate the AHCI state structure into the header

[John Snow]

On 07/27/2015 02:37 PM, Alistair Francis wrote:
> Pull the AHCI state structure out into the header. This allows
> other containers to access the struct. This is required to add
> the device to modern SoC containers.
> 

Is there a reason this structure needs to be directly inlined into
XlnxZynqMPState, instead of using e.g.
qdev_create/object_property_add_child and letting SysbusAHCIState be the
business of ahci.c?

Asking as a bit of a qdev outsider.

--js

> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
> ---
>  hw/ide/ahci.c |   13 -------------
>  hw/ide/ahci.h |   14 ++++++++++++++
>  2 files changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 48749c1..02d85fa 100644
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -25,7 +25,6 @@
>  #include <hw/pci/msi.h>
>  #include <hw/i386/pc.h>
>  #include <hw/pci/pci.h>
> -#include <hw/sysbus.h>
>  
>  #include "qemu/error-report.h"
>  #include "sysemu/block-backend.h"
> @@ -1625,18 +1624,6 @@ const VMStateDescription vmstate_ahci = {
>      },
>  };
>  
> -#define TYPE_SYSBUS_AHCI "sysbus-ahci"
> -#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
> -
> -typedef struct SysbusAHCIState {
> -    /*< private >*/
> -    SysBusDevice parent_obj;
> -    /*< public >*/
> -
> -    AHCIState ahci;
> -    uint32_t num_ports;
> -} SysbusAHCIState;
> -
>  static const VMStateDescription vmstate_sysbus_ahci = {
>      .name = "sysbus-ahci",
>      .fields = (VMStateField[]) {
> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
> index 68d5074..5ab8ea4 100644
> --- a/hw/ide/ahci.h
> +++ b/hw/ide/ahci.h
> @@ -24,6 +24,8 @@
>  #ifndef HW_IDE_AHCI_H
>  #define HW_IDE_AHCI_H
>  
> +#include <hw/sysbus.h>
> +
>  #define AHCI_MEM_BAR_SIZE         0x1000
>  #define AHCI_MAX_PORTS            32
>  #define AHCI_MAX_SG               168 /* hardware max is 64K */
> @@ -369,4 +371,16 @@ void ahci_reset(AHCIState *s);
>  
>  void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
>  
> +#define TYPE_SYSBUS_AHCI "sysbus-ahci"
> +#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
> +
> +typedef struct SysbusAHCIState {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +    /*< public >*/
> +
> +    AHCIState ahci;
> +    uint32_t num_ports;
> +} SysbusAHCIState;
> +
>  #endif /* HW_IDE_AHCI_H */
> 

Re: [Qemu-devel] [PATCH v1 1/3] ahci: Separate the AHCI state structure into the header

[Alistair Francis]

On Wed, Jul 29, 2015 at 3:21 PM, John Snow <jsnow@redhat.com> wrote:
>
>
> On 07/27/2015 02:37 PM, Alistair Francis wrote:
>> Pull the AHCI state structure out into the header. This allows
>> other containers to access the struct. This is required to add
>> the device to modern SoC containers.
>>
>
> Is there a reason this structure needs to be directly inlined into
> XlnxZynqMPState, instead of using e.g.
> qdev_create/object_property_add_child and letting SysbusAHCIState be the
> business of ahci.c?

AFAIK there isn't a huge advantage, it ends up achieving basically the
same thing. It just means that we don't need to use
the old qdev_* functions (as much). It also follows with QOMificatiom and
the device creation can be split up over the init and realise functions.

This is also the way I did machine creation for the Netduino 2 and how
it is done for the rest of the ZynqMP device.

Thanks,

Alistair

>
> Asking as a bit of a qdev outsider.
>
> --js
>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
>> ---
>>  hw/ide/ahci.c |   13 -------------
>>  hw/ide/ahci.h |   14 ++++++++++++++
>>  2 files changed, 14 insertions(+), 13 deletions(-)
>>
>> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>> index 48749c1..02d85fa 100644
>> --- a/hw/ide/ahci.c
>> +++ b/hw/ide/ahci.c
>> @@ -25,7 +25,6 @@
>>  #include <hw/pci/msi.h>
>>  #include <hw/i386/pc.h>
>>  #include <hw/pci/pci.h>
>> -#include <hw/sysbus.h>
>>
>>  #include "qemu/error-report.h"
>>  #include "sysemu/block-backend.h"
>> @@ -1625,18 +1624,6 @@ const VMStateDescription vmstate_ahci = {
>>      },
>>  };
>>
>> -#define TYPE_SYSBUS_AHCI "sysbus-ahci"
>> -#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
>> -
>> -typedef struct SysbusAHCIState {
>> -    /*< private >*/
>> -    SysBusDevice parent_obj;
>> -    /*< public >*/
>> -
>> -    AHCIState ahci;
>> -    uint32_t num_ports;
>> -} SysbusAHCIState;
>> -
>>  static const VMStateDescription vmstate_sysbus_ahci = {
>>      .name = "sysbus-ahci",
>>      .fields = (VMStateField[]) {
>> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
>> index 68d5074..5ab8ea4 100644
>> --- a/hw/ide/ahci.h
>> +++ b/hw/ide/ahci.h
>> @@ -24,6 +24,8 @@
>>  #ifndef HW_IDE_AHCI_H
>>  #define HW_IDE_AHCI_H
>>
>> +#include <hw/sysbus.h>
>> +
>>  #define AHCI_MEM_BAR_SIZE         0x1000
>>  #define AHCI_MAX_PORTS            32
>>  #define AHCI_MAX_SG               168 /* hardware max is 64K */
>> @@ -369,4 +371,16 @@ void ahci_reset(AHCIState *s);
>>
>>  void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
>>
>> +#define TYPE_SYSBUS_AHCI "sysbus-ahci"
>> +#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
>> +
>> +typedef struct SysbusAHCIState {
>> +    /*< private >*/
>> +    SysBusDevice parent_obj;
>> +    /*< public >*/
>> +
>> +    AHCIState ahci;
>> +    uint32_t num_ports;
>> +} SysbusAHCIState;
>> +
>>  #endif /* HW_IDE_AHCI_H */
>>
>

Re: [Qemu-devel] [PATCH v1 0/3] xlnx-zynqmp: Connect the AHCI SATA device

[Alistair Francis]

On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> This series connects the AHCI SATA device to the ZynqMP
> machine. It requires a restructure of the AHCI file to
> make the AHCI state struct visible. It also requires a
> small change to object_class_dynamic_cast() to return
> NULL if the class doesn't have a type.

Ping!

Not a huge rush, this was probably lost as I sent it during
the freeze.

Thanks,

Alistair

>
> Alistair Francis (3):
>   ahci: Seperate the AHCI state structure into the header
>   object.c: object_class_dynamic_cast return NULL if the class has no
>     type
>   xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP
>
>  hw/arm/xlnx-zynqmp.c         |   20 ++++++++++++++++++++
>  hw/ide/ahci.c                |   13 -------------
>  hw/ide/ahci.h                |   14 ++++++++++++++
>  include/hw/arm/xlnx-zynqmp.h |    3 +++
>  qom/object.c                 |    2 +-
>  5 files changed, 38 insertions(+), 14 deletions(-)
>
>

Re: [Qemu-devel] [PATCH v1 1/3] ahci: Separate the AHCI state structure into the header

[Peter Crosthwaite]

On Wed, Jul 29, 2015 at 5:12 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Wed, Jul 29, 2015 at 3:21 PM, John Snow <jsnow@redhat.com> wrote:
>>
>>
>> On 07/27/2015 02:37 PM, Alistair Francis wrote:
>>> Pull the AHCI state structure out into the header. This allows
>>> other containers to access the struct. This is required to add
>>> the device to modern SoC containers.
>>>
>>
>> Is there a reason this structure needs to be directly inlined into
>> XlnxZynqMPState, instead of using e.g.
>> qdev_create/object_property_add_child and letting SysbusAHCIState be the
>> business of ahci.c?
>

This has come up a few times, and the conclusion was to do the
inlining by preference. I vaguely remember PMM started an effort to
build infrastructure to hide the internals from use by outsiders, but
the struct def is desirable for the inlining even if the internals are
private a different module. It has been the policy on ARM SoC for
quite some time. We have made a quite a few of these conversions for
an example of a big one, see:

[PATCH v4 00/24] arm: ARM11MPCore+A9MPCore+A15MPCore QOM'ification

> AFAIK there isn't a huge advantage, it ends up achieving basically the
> same thing. It just means that we don't need to use
> the old qdev_* functions (as much). It also follows with QOMificatiom and
> the device creation can be split up over the init and realise functions.
>

You can use object_new in place of object_initialize to achieve the
split without inlining as well.

Regards,
Peter

> This is also the way I did machine creation for the Netduino 2 and how
> it is done for the rest of the ZynqMP device.
>
> Thanks,
>
> Alistair
>
>>
>> Asking as a bit of a qdev outsider.
>>
>> --js
>>
>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
>>> ---
>>>  hw/ide/ahci.c |   13 -------------
>>>  hw/ide/ahci.h |   14 ++++++++++++++
>>>  2 files changed, 14 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>>> index 48749c1..02d85fa 100644
>>> --- a/hw/ide/ahci.c
>>> +++ b/hw/ide/ahci.c
>>> @@ -25,7 +25,6 @@
>>>  #include <hw/pci/msi.h>
>>>  #include <hw/i386/pc.h>
>>>  #include <hw/pci/pci.h>
>>> -#include <hw/sysbus.h>
>>>
>>>  #include "qemu/error-report.h"
>>>  #include "sysemu/block-backend.h"
>>> @@ -1625,18 +1624,6 @@ const VMStateDescription vmstate_ahci = {
>>>      },
>>>  };
>>>
>>> -#define TYPE_SYSBUS_AHCI "sysbus-ahci"
>>> -#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
>>> -
>>> -typedef struct SysbusAHCIState {
>>> -    /*< private >*/
>>> -    SysBusDevice parent_obj;
>>> -    /*< public >*/
>>> -
>>> -    AHCIState ahci;
>>> -    uint32_t num_ports;
>>> -} SysbusAHCIState;
>>> -
>>>  static const VMStateDescription vmstate_sysbus_ahci = {
>>>      .name = "sysbus-ahci",
>>>      .fields = (VMStateField[]) {
>>> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
>>> index 68d5074..5ab8ea4 100644
>>> --- a/hw/ide/ahci.h
>>> +++ b/hw/ide/ahci.h
>>> @@ -24,6 +24,8 @@
>>>  #ifndef HW_IDE_AHCI_H
>>>  #define HW_IDE_AHCI_H
>>>
>>> +#include <hw/sysbus.h>
>>> +
>>>  #define AHCI_MEM_BAR_SIZE         0x1000
>>>  #define AHCI_MAX_PORTS            32
>>>  #define AHCI_MAX_SG               168 /* hardware max is 64K */
>>> @@ -369,4 +371,16 @@ void ahci_reset(AHCIState *s);
>>>
>>>  void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
>>>
>>> +#define TYPE_SYSBUS_AHCI "sysbus-ahci"
>>> +#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
>>> +
>>> +typedef struct SysbusAHCIState {
>>> +    /*< private >*/
>>> +    SysBusDevice parent_obj;
>>> +    /*< public >*/
>>> +
>>> +    AHCIState ahci;
>>> +    uint32_t num_ports;
>>> +} SysbusAHCIState;
>>> +
>>>  #endif /* HW_IDE_AHCI_H */
>>>
>>
>

Re: [Qemu-devel] [PATCH v1 1/3] ahci: Separate the AHCI state structure into the header

[Peter Crosthwaite]

On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Pull the AHCI state structure out into the header. This allows
> other containers to access the struct. This is required to add
> the device to modern SoC containers.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
> ---
>  hw/ide/ahci.c |   13 -------------
>  hw/ide/ahci.h |   14 ++++++++++++++
>  2 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 48749c1..02d85fa 100644
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -25,7 +25,6 @@
>  #include <hw/pci/msi.h>
>  #include <hw/i386/pc.h>
>  #include <hw/pci/pci.h>
> -#include <hw/sysbus.h>
>
>  #include "qemu/error-report.h"
>  #include "sysemu/block-backend.h"
> @@ -1625,18 +1624,6 @@ const VMStateDescription vmstate_ahci = {
>      },
>  };
>
> -#define TYPE_SYSBUS_AHCI "sysbus-ahci"
> -#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
> -
> -typedef struct SysbusAHCIState {
> -    /*< private >*/
> -    SysBusDevice parent_obj;
> -    /*< public >*/
> -
> -    AHCIState ahci;
> -    uint32_t num_ports;
> -} SysbusAHCIState;
> -
>  static const VMStateDescription vmstate_sysbus_ahci = {
>      .name = "sysbus-ahci",
>      .fields = (VMStateField[]) {
> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
> index 68d5074..5ab8ea4 100644
> --- a/hw/ide/ahci.h
> +++ b/hw/ide/ahci.h
> @@ -24,6 +24,8 @@
>  #ifndef HW_IDE_AHCI_H
>  #define HW_IDE_AHCI_H
>
> +#include <hw/sysbus.h>
> +

Odd that this is the only header. Out-of scope, but should this header
be including the same for PCI? It uses PCIDevice * defs, so I am
guessing it is relying on clients to pre-include the deps.

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Regards,
Peter

>  #define AHCI_MEM_BAR_SIZE         0x1000
>  #define AHCI_MAX_PORTS            32
>  #define AHCI_MAX_SG               168 /* hardware max is 64K */
> @@ -369,4 +371,16 @@ void ahci_reset(AHCIState *s);
>
>  void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
>
> +#define TYPE_SYSBUS_AHCI "sysbus-ahci"
> +#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
> +
> +typedef struct SysbusAHCIState {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +    /*< public >*/
> +
> +    AHCIState ahci;
> +    uint32_t num_ports;
> +} SysbusAHCIState;
> +
>  #endif /* HW_IDE_AHCI_H */
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Peter Crosthwaite]

On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> If the ObjectClass has no type return NULL instead of trying to compare
> the type name.
>

What was the issue?

Regards,
Peter

> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
> ---
>  qom/object.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/qom/object.c b/qom/object.c
> index eea8edf..2d6d715 100644
> --- a/qom/object.c
> +++ b/qom/object.c
> @@ -603,7 +603,7 @@ ObjectClass *object_class_dynamic_cast(ObjectClass *class,
>      TypeImpl *target_type;
>      TypeImpl *type;
>
> -    if (!class) {
> +    if (!class || !class->type) {
>          return NULL;
>      }
>
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v1 1/3] ahci: Separate the AHCI state structure into the header

[Peter Crosthwaite]

On Sat, Aug 15, 2015 at 2:21 PM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> Pull the AHCI state structure out into the header. This allows
>> other containers to access the struct. This is required to add
>> the device to modern SoC containers.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
>> ---
>>  hw/ide/ahci.c |   13 -------------
>>  hw/ide/ahci.h |   14 ++++++++++++++
>>  2 files changed, 14 insertions(+), 13 deletions(-)
>>
>> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>> index 48749c1..02d85fa 100644
>> --- a/hw/ide/ahci.c
>> +++ b/hw/ide/ahci.c
>> @@ -25,7 +25,6 @@
>>  #include <hw/pci/msi.h>
>>  #include <hw/i386/pc.h>
>>  #include <hw/pci/pci.h>
>> -#include <hw/sysbus.h>
>>
>>  #include "qemu/error-report.h"
>>  #include "sysemu/block-backend.h"
>> @@ -1625,18 +1624,6 @@ const VMStateDescription vmstate_ahci = {
>>      },
>>  };
>>
>> -#define TYPE_SYSBUS_AHCI "sysbus-ahci"
>> -#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
>> -
>> -typedef struct SysbusAHCIState {
>> -    /*< private >*/
>> -    SysBusDevice parent_obj;
>> -    /*< public >*/
>> -
>> -    AHCIState ahci;
>> -    uint32_t num_ports;
>> -} SysbusAHCIState;
>> -
>>  static const VMStateDescription vmstate_sysbus_ahci = {
>>      .name = "sysbus-ahci",
>>      .fields = (VMStateField[]) {
>> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
>> index 68d5074..5ab8ea4 100644
>> --- a/hw/ide/ahci.h
>> +++ b/hw/ide/ahci.h
>> @@ -24,6 +24,8 @@
>>  #ifndef HW_IDE_AHCI_H
>>  #define HW_IDE_AHCI_H
>>
>> +#include <hw/sysbus.h>
>> +
>
> Odd that this is the only header. Out-of scope, but should this header
> be including the same for PCI? It uses PCIDevice * defs, so I am
> guessing it is relying on clients to pre-include the deps.
>
> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>

Sorry old habit, try:

Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>

> Regards,
> Peter
>
>>  #define AHCI_MEM_BAR_SIZE         0x1000
>>  #define AHCI_MAX_PORTS            32
>>  #define AHCI_MAX_SG               168 /* hardware max is 64K */
>> @@ -369,4 +371,16 @@ void ahci_reset(AHCIState *s);
>>
>>  void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
>>
>> +#define TYPE_SYSBUS_AHCI "sysbus-ahci"
>> +#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
>> +
>> +typedef struct SysbusAHCIState {
>> +    /*< private >*/
>> +    SysBusDevice parent_obj;
>> +    /*< public >*/
>> +
>> +    AHCIState ahci;
>> +    uint32_t num_ports;
>> +} SysbusAHCIState;
>> +
>>  #endif /* HW_IDE_AHCI_H */
>> --
>> 1.7.1
>>
>>

Re: [Qemu-devel] [PATCH v1 3/3] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP

[Peter Crosthwaite]

On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Connect the Sysbus AHCI device to ZynqMP.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
> ---
>  hw/arm/xlnx-zynqmp.c         |   20 ++++++++++++++++++++
>  include/hw/arm/xlnx-zynqmp.h |    3 +++
>  2 files changed, 23 insertions(+), 0 deletions(-)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 62ef4ce..7adcce9 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -28,6 +28,9 @@
>  #define GIC_DIST_ADDR       0xf9010000
>  #define GIC_CPU_ADDR        0xf9020000
>
> +#define SYSBUS_AHCI_ADDR    0xFD0C0000
> +#define SYSBUS_AHCI_INTR    133
> +
>  static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
>      0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
>  };
> @@ -90,6 +93,9 @@ static void xlnx_zynqmp_init(Object *obj)
>          object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
>          qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
>      }
> +
> +    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
> +    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
>  }
>
>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> @@ -235,6 +241,20 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>          sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
>                             gic_spi[uart_intr[i]]);
>      }
> +
> +    object_property_set_int(OBJECT(&s->sata), 2, "num-ports", &err);

2 Should get a macro up top.

> +    if (err) {
> +        error_propagate((errp), (err));
> +        return;
> +    }

What is the user visible failure case here? I think this can be
error_abort'ed. I think some of the others in the file (mainly the
reset-cbar one) could be error_aborted as well.

Regards,
Peter

> +    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
> +    if (err) {
> +        error_propagate((errp), (err));
> +        return;
> +    }
> +
> +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SYSBUS_AHCI_ADDR);
> +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SYSBUS_AHCI_INTR]);
>  }
>
>  static Property xlnx_zynqmp_props[] = {
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index c379632..024e316 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -22,6 +22,8 @@
>  #include "hw/intc/arm_gic.h"
>  #include "hw/net/cadence_gem.h"
>  #include "hw/char/cadence_uart.h"
> +#include "hw/ide/pci.h"
> +#include "hw/ide/ahci.h"
>
>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
> @@ -54,6 +56,7 @@ typedef struct XlnxZynqMPState {
>      MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
> +    SysbusAHCIState sata;
>
>      char *boot_cpu;
>      ARMCPU *boot_cpu_ptr;
> --
> 1.7.1
>
>

Re: [Qemu-devel] [PATCH v1 1/3] ahci: Separate the AHCI state structure into the header

[Peter Maydell]

On 15 August 2015 at 22:18, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> This has come up a few times, and the conclusion was to do the
> inlining by preference. I vaguely remember PMM started an effort to
> build infrastructure to hide the internals from use by outsiders, but
> the struct def is desirable for the inlining even if the internals are
> private a different module.

The idea was just to mark up the fields which are supposed
to be private to the implementation, so everybody can use
the same header, but outsiders get a warning/error if they
try to touch things they shouldn't.

https://lists.gnu.org/archive/html/qemu-devel/2014-05/msg01846.html

I should probably get back to that at some point -- Paolo
had an interesting suggestion involving some cpp macros
which I never got round to investigating.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Alistair Francis]

On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> If the ObjectClass has no type return NULL instead of trying to compare
>> the type name.
>>
>
> What was the issue?

There is a seg fault in object_class_dynamic_cast() because there is
no type in the ObjectClass struct.

It happens when it is trying to cast the "pci-device", which is called
from the ahci_irq_lower() function. The function is testing if the
device is a pci device, so it should return NULL if it isn't valid.

Thanks,

Alistair

>
> Regards,
> Peter
>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
>> ---
>>  qom/object.c |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/qom/object.c b/qom/object.c
>> index eea8edf..2d6d715 100644
>> --- a/qom/object.c
>> +++ b/qom/object.c
>> @@ -603,7 +603,7 @@ ObjectClass *object_class_dynamic_cast(ObjectClass *class,
>>      TypeImpl *target_type;
>>      TypeImpl *type;
>>
>> -    if (!class) {
>> +    if (!class || !class->type) {
>>          return NULL;
>>      }
>>
>> --
>> 1.7.1
>>
>>
>

Re: [Qemu-devel] [PATCH v1 1/3] ahci: Separate the AHCI state structure into the header

[Alistair Francis]

On Sat, Aug 15, 2015 at 2:25 PM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Sat, Aug 15, 2015 at 2:21 PM, Peter Crosthwaite
> <crosthwaitepeter@gmail.com> wrote:
>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>> <alistair.francis@xilinx.com> wrote:
>>> Pull the AHCI state structure out into the header. This allows
>>> other containers to access the struct. This is required to add
>>> the device to modern SoC containers.
>>>
>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
>>> ---
>>>  hw/ide/ahci.c |   13 -------------
>>>  hw/ide/ahci.h |   14 ++++++++++++++
>>>  2 files changed, 14 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>>> index 48749c1..02d85fa 100644
>>> --- a/hw/ide/ahci.c
>>> +++ b/hw/ide/ahci.c
>>> @@ -25,7 +25,6 @@
>>>  #include <hw/pci/msi.h>
>>>  #include <hw/i386/pc.h>
>>>  #include <hw/pci/pci.h>
>>> -#include <hw/sysbus.h>
>>>
>>>  #include "qemu/error-report.h"
>>>  #include "sysemu/block-backend.h"
>>> @@ -1625,18 +1624,6 @@ const VMStateDescription vmstate_ahci = {
>>>      },
>>>  };
>>>
>>> -#define TYPE_SYSBUS_AHCI "sysbus-ahci"
>>> -#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
>>> -
>>> -typedef struct SysbusAHCIState {
>>> -    /*< private >*/
>>> -    SysBusDevice parent_obj;
>>> -    /*< public >*/
>>> -
>>> -    AHCIState ahci;
>>> -    uint32_t num_ports;
>>> -} SysbusAHCIState;
>>> -
>>>  static const VMStateDescription vmstate_sysbus_ahci = {
>>>      .name = "sysbus-ahci",
>>>      .fields = (VMStateField[]) {
>>> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
>>> index 68d5074..5ab8ea4 100644
>>> --- a/hw/ide/ahci.h
>>> +++ b/hw/ide/ahci.h
>>> @@ -24,6 +24,8 @@
>>>  #ifndef HW_IDE_AHCI_H
>>>  #define HW_IDE_AHCI_H
>>>
>>> +#include <hw/sysbus.h>
>>> +
>>
>> Odd that this is the only header. Out-of scope, but should this header
>> be including the same for PCI? It uses PCIDevice * defs, so I am
>> guessing it is relying on clients to pre-include the deps.
>>
>> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>
> Sorry old habit, try:
>
> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>

Thanks Peter,

Alistair

>
>> Regards,
>> Peter
>>
>>>  #define AHCI_MEM_BAR_SIZE         0x1000
>>>  #define AHCI_MAX_PORTS            32
>>>  #define AHCI_MAX_SG               168 /* hardware max is 64K */
>>> @@ -369,4 +371,16 @@ void ahci_reset(AHCIState *s);
>>>
>>>  void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
>>>
>>> +#define TYPE_SYSBUS_AHCI "sysbus-ahci"
>>> +#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
>>> +
>>> +typedef struct SysbusAHCIState {
>>> +    /*< private >*/
>>> +    SysBusDevice parent_obj;
>>> +    /*< public >*/
>>> +
>>> +    AHCIState ahci;
>>> +    uint32_t num_ports;
>>> +} SysbusAHCIState;
>>> +
>>>  #endif /* HW_IDE_AHCI_H */
>>> --
>>> 1.7.1
>>>
>>>
>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Andreas Färber]

Am 18.08.2015 um 00:24 schrieb Alistair Francis:
> On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
> <crosthwaitepeter@gmail.com> wrote:
>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>> <alistair.francis@xilinx.com> wrote:
>>> If the ObjectClass has no type return NULL instead of trying to compare
>>> the type name.
>>>
>>
>> What was the issue?
> 
> There is a seg fault in object_class_dynamic_cast() because there is
> no type in the ObjectClass struct.

That should never happen, ever since TYPE_OBJECT is no longer NULL.

> It happens when it is trying to cast the "pci-device", which is called
> from the ahci_irq_lower() function. The function is testing if the
> device is a pci device, so it should return NULL if it isn't valid.

It rather sounds as if some build-time dependency is wrong, which we
used to run into for the Container type before Paolo macrofied this.

Please try again with a clean build - if it still occurs, we'll need a
reproducible test case to investigate what is going on rather than
papering over a latent bug.

Thanks,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)

Re: [Qemu-devel] [PATCH v1 3/3] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP

[Alistair Francis]

On Sat, Aug 15, 2015 at 2:29 PM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> Connect the Sysbus AHCI device to ZynqMP.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com>
>> ---
>>  hw/arm/xlnx-zynqmp.c         |   20 ++++++++++++++++++++
>>  include/hw/arm/xlnx-zynqmp.h |    3 +++
>>  2 files changed, 23 insertions(+), 0 deletions(-)
>>
>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>> index 62ef4ce..7adcce9 100644
>> --- a/hw/arm/xlnx-zynqmp.c
>> +++ b/hw/arm/xlnx-zynqmp.c
>> @@ -28,6 +28,9 @@
>>  #define GIC_DIST_ADDR       0xf9010000
>>  #define GIC_CPU_ADDR        0xf9020000
>>
>> +#define SYSBUS_AHCI_ADDR    0xFD0C0000
>> +#define SYSBUS_AHCI_INTR    133
>> +
>>  static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
>>      0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
>>  };
>> @@ -90,6 +93,9 @@ static void xlnx_zynqmp_init(Object *obj)
>>          object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
>>          qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
>>      }
>> +
>> +    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
>> +    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
>>  }
>>
>>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>> @@ -235,6 +241,20 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>>          sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
>>                             gic_spi[uart_intr[i]]);
>>      }
>> +
>> +    object_property_set_int(OBJECT(&s->sata), 2, "num-ports", &err);
>
> 2 Should get a macro up top.

Ok, will fix

>
>> +    if (err) {
>> +        error_propagate((errp), (err));
>> +        return;
>> +    }
>
> What is the user visible failure case here? I think this can be
> error_abort'ed. I think some of the others in the file (mainly the
> reset-cbar one) could be error_aborted as well.

Fair point. I was just following what most of the others do. Thinking
about it I agree that pretty much all of the non-realise calls should
just abort. I'll fix this and the others in the next version.

Thanks,

Alistair

>
> Regards,
> Peter
>
>> +    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
>> +    if (err) {
>> +        error_propagate((errp), (err));
>> +        return;
>> +    }
>> +
>> +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SYSBUS_AHCI_ADDR);
>> +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SYSBUS_AHCI_INTR]);
>>  }
>>
>>  static Property xlnx_zynqmp_props[] = {
>> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
>> index c379632..024e316 100644
>> --- a/include/hw/arm/xlnx-zynqmp.h
>> +++ b/include/hw/arm/xlnx-zynqmp.h
>> @@ -22,6 +22,8 @@
>>  #include "hw/intc/arm_gic.h"
>>  #include "hw/net/cadence_gem.h"
>>  #include "hw/char/cadence_uart.h"
>> +#include "hw/ide/pci.h"
>> +#include "hw/ide/ahci.h"
>>
>>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
>> @@ -54,6 +56,7 @@ typedef struct XlnxZynqMPState {
>>      MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
>>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>> +    SysbusAHCIState sata;
>>
>>      char *boot_cpu;
>>      ARMCPU *boot_cpu_ptr;
>> --
>> 1.7.1
>>
>>
>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Peter Crosthwaite]

On Mon, Aug 17, 2015 at 3:33 PM, Andreas Färber <afaerber@suse.de> wrote:
> Am 18.08.2015 um 00:24 schrieb Alistair Francis:
>> On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
>> <crosthwaitepeter@gmail.com> wrote:
>>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>>> <alistair.francis@xilinx.com> wrote:
>>>> If the ObjectClass has no type return NULL instead of trying to compare
>>>> the type name.
>>>>
>>>
>>> What was the issue?
>>
>> There is a seg fault in object_class_dynamic_cast() because there is
>> no type in the ObjectClass struct.
>
> That should never happen, ever since TYPE_OBJECT is no longer NULL.
>
>> It happens when it is trying to cast the "pci-device", which is called
>> from the ahci_irq_lower() function. The function is testing if the
>> device is a pci device, so it should return NULL if it isn't valid.

Yes so I vaguely remember this now. It is about MSI interrupts which
have nothing to do with sysbus implementation. My solution was to rip
that PCI specific stuff out of AHCI completely in my branch. Should
sysbus and PCI AHCI classes install their own separate logic for this
part via a virtualised hook?

On the topic though, I notice many PCI devices have this MSI specific
logic in them. Is it possible for devs to just treat interrupts as
pins and the PCI layers do the MSI vs non-MSI logic switch in core
layers?

If Andreas' idea don't work this is still a core QOM bug though. I
think object_dynamic_cast should not have this segfault when passed a
non implementing object.

Regards,
Peter

>
> It rather sounds as if some build-time dependency is wrong, which we
> used to run into for the Container type before Paolo macrofied this.
>
> Please try again with a clean build - if it still occurs, we'll need a
> reproducible test case to investigate what is going on rather than
> papering over a latent bug.
>
> Thanks,
> Andreas
>
> --
> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Alistair Francis]

On Mon, Aug 17, 2015 at 4:37 PM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Mon, Aug 17, 2015 at 3:33 PM, Andreas Färber <afaerber@suse.de> wrote:
>> Am 18.08.2015 um 00:24 schrieb Alistair Francis:
>>> On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
>>> <crosthwaitepeter@gmail.com> wrote:
>>>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>>>> <alistair.francis@xilinx.com> wrote:
>>>>> If the ObjectClass has no type return NULL instead of trying to compare
>>>>> the type name.
>>>>>
>>>>
>>>> What was the issue?
>>>
>>> There is a seg fault in object_class_dynamic_cast() because there is
>>> no type in the ObjectClass struct.
>>
>> That should never happen, ever since TYPE_OBJECT is no longer NULL.
>>
>>> It happens when it is trying to cast the "pci-device", which is called
>>> from the ahci_irq_lower() function. The function is testing if the
>>> device is a pci device, so it should return NULL if it isn't valid.
>
> Yes so I vaguely remember this now. It is about MSI interrupts which
> have nothing to do with sysbus implementation. My solution was to rip
> that PCI specific stuff out of AHCI completely in my branch. Should
> sysbus and PCI AHCI classes install their own separate logic for this
> part via a virtualised hook?
>
> On the topic though, I notice many PCI devices have this MSI specific
> logic in them. Is it possible for devs to just treat interrupts as
> pins and the PCI layers do the MSI vs non-MSI logic switch in core
> layers?
>
> If Andreas' idea don't work this is still a core QOM bug though. I
> think object_dynamic_cast should not have this segfault when passed a
> non implementing object.
>
> Regards,
> Peter
>
>>
>> It rather sounds as if some build-time dependency is wrong, which we
>> used to run into for the Container type before Paolo macrofied this.
>>
>> Please try again with a clean build - if it still occurs, we'll need a
>> reproducible test case to investigate what is going on rather than
>> papering over a latent bug.

Hey,

Sorry abut the delay, but I didn't get a chance to look at this last
week. I tried with a clean setup and still see the seg fault.

I will try to look into it more this week, but if anyone is interested
here are the steps to reproduce:

On the latest mainline QEMU, with my 2nd and 3rd patches applied
$ ./configure --target-list="aarch64-softmmu,microblazeel-softmmu"
--disable-pie --disable-sdl --disable-werror # This is what is
required at work
$ ./aarch64-softmmu/qemu-system-aarch64 -M xlnx-ep108 -display none
-kernel ./u-boot.elf -m 8000000 -nographic -serial mon:stdio # Boot
u-boot on QEMU

The image I'm using is available at: http://1drv.ms/1NxDXLo

Thanks,

Alistair

>>
>> Thanks,
>> Andreas
>>
>> --
>> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
>> GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)
>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Peter Crosthwaite]

On Mon, Aug 24, 2015 at 4:36 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Mon, Aug 17, 2015 at 4:37 PM, Peter Crosthwaite
> <crosthwaitepeter@gmail.com> wrote:
>> On Mon, Aug 17, 2015 at 3:33 PM, Andreas Färber <afaerber@suse.de> wrote:
>>> Am 18.08.2015 um 00:24 schrieb Alistair Francis:
>>>> On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
>>>> <crosthwaitepeter@gmail.com> wrote:
>>>>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>>>>> <alistair.francis@xilinx.com> wrote:
>>>>>> If the ObjectClass has no type return NULL instead of trying to compare
>>>>>> the type name.
>>>>>>
>>>>>
>>>>> What was the issue?
>>>>
>>>> There is a seg fault in object_class_dynamic_cast() because there is
>>>> no type in the ObjectClass struct.
>>>
>>> That should never happen, ever since TYPE_OBJECT is no longer NULL.
>>>
>>>> It happens when it is trying to cast the "pci-device", which is called
>>>> from the ahci_irq_lower() function. The function is testing if the
>>>> device is a pci device, so it should return NULL if it isn't valid.
>>
>> Yes so I vaguely remember this now. It is about MSI interrupts which
>> have nothing to do with sysbus implementation. My solution was to rip
>> that PCI specific stuff out of AHCI completely in my branch. Should
>> sysbus and PCI AHCI classes install their own separate logic for this
>> part via a virtualised hook?
>>
>> On the topic though, I notice many PCI devices have this MSI specific
>> logic in them. Is it possible for devs to just treat interrupts as
>> pins and the PCI layers do the MSI vs non-MSI logic switch in core
>> layers?
>>
>> If Andreas' idea don't work this is still a core QOM bug though. I
>> think object_dynamic_cast should not have this segfault when passed a
>> non implementing object.
>>
>> Regards,
>> Peter
>>
>>>
>>> It rather sounds as if some build-time dependency is wrong, which we
>>> used to run into for the Container type before Paolo macrofied this.
>>>
>>> Please try again with a clean build - if it still occurs, we'll need a
>>> reproducible test case to investigate what is going on rather than
>>> papering over a latent bug.
>
> Hey,
>
> Sorry abut the delay, but I didn't get a chance to look at this last
> week. I tried with a clean setup and still see the seg fault.
>
> I will try to look into it more this week, but if anyone is interested
> here are the steps to reproduce:
>
> On the latest mainline QEMU, with my 2nd and 3rd patches applied
> $ ./configure --target-list="aarch64-softmmu,microblazeel-softmmu"
> --disable-pie --disable-sdl --disable-werror # This is what is
> required at work
> $ ./aarch64-softmmu/qemu-system-aarch64 -M xlnx-ep108 -display none
> -kernel ./u-boot.elf -m 8000000 -nographic -serial mon:stdio # Boot
> u-boot on QEMU
>
> The image I'm using is available at: http://1drv.ms/1NxDXLo
>

So it's not a core bug. That container_of in ahci_lower_irq is
incorrectly assuming that the passed AHCIState * is always for a PCI,
which it is not in the sysbus case. So it's incorrectly getting the
offset of QOM the object and the QOM cast is treating some invalid
offset into the (or past) object as a QOM object base address.

The simplest solution is a back pointer in AHCIState to the
encapsulating device (would be a DeviceState *). The container_of is
replaced with a nav of this pointer and then the conditional PCI cast
can work.

Regards,
Peter

> Thanks,
>
> Alistair
>
>>>
>>> Thanks,
>>> Andreas
>>>
>>> --
>>> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
>>> GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)
>>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Alistair Francis]

On Tue, Aug 25, 2015 at 12:43 AM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Mon, Aug 24, 2015 at 4:36 PM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> On Mon, Aug 17, 2015 at 4:37 PM, Peter Crosthwaite
>> <crosthwaitepeter@gmail.com> wrote:
>>> On Mon, Aug 17, 2015 at 3:33 PM, Andreas Färber <afaerber@suse.de> wrote:
>>>> Am 18.08.2015 um 00:24 schrieb Alistair Francis:
>>>>> On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
>>>>> <crosthwaitepeter@gmail.com> wrote:
>>>>>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>>>>>> <alistair.francis@xilinx.com> wrote:
>>>>>>> If the ObjectClass has no type return NULL instead of trying to compare
>>>>>>> the type name.
>>>>>>>
>>>>>>
>>>>>> What was the issue?
>>>>>
>>>>> There is a seg fault in object_class_dynamic_cast() because there is
>>>>> no type in the ObjectClass struct.
>>>>
>>>> That should never happen, ever since TYPE_OBJECT is no longer NULL.
>>>>
>>>>> It happens when it is trying to cast the "pci-device", which is called
>>>>> from the ahci_irq_lower() function. The function is testing if the
>>>>> device is a pci device, so it should return NULL if it isn't valid.
>>>
>>> Yes so I vaguely remember this now. It is about MSI interrupts which
>>> have nothing to do with sysbus implementation. My solution was to rip
>>> that PCI specific stuff out of AHCI completely in my branch. Should
>>> sysbus and PCI AHCI classes install their own separate logic for this
>>> part via a virtualised hook?
>>>
>>> On the topic though, I notice many PCI devices have this MSI specific
>>> logic in them. Is it possible for devs to just treat interrupts as
>>> pins and the PCI layers do the MSI vs non-MSI logic switch in core
>>> layers?
>>>
>>> If Andreas' idea don't work this is still a core QOM bug though. I
>>> think object_dynamic_cast should not have this segfault when passed a
>>> non implementing object.
>>>
>>> Regards,
>>> Peter
>>>
>>>>
>>>> It rather sounds as if some build-time dependency is wrong, which we
>>>> used to run into for the Container type before Paolo macrofied this.
>>>>
>>>> Please try again with a clean build - if it still occurs, we'll need a
>>>> reproducible test case to investigate what is going on rather than
>>>> papering over a latent bug.
>>
>> Hey,
>>
>> Sorry abut the delay, but I didn't get a chance to look at this last
>> week. I tried with a clean setup and still see the seg fault.
>>
>> I will try to look into it more this week, but if anyone is interested
>> here are the steps to reproduce:
>>
>> On the latest mainline QEMU, with my 2nd and 3rd patches applied
>> $ ./configure --target-list="aarch64-softmmu,microblazeel-softmmu"
>> --disable-pie --disable-sdl --disable-werror # This is what is
>> required at work
>> $ ./aarch64-softmmu/qemu-system-aarch64 -M xlnx-ep108 -display none
>> -kernel ./u-boot.elf -m 8000000 -nographic -serial mon:stdio # Boot
>> u-boot on QEMU
>>
>> The image I'm using is available at: http://1drv.ms/1NxDXLo
>>
>
> So it's not a core bug. That container_of in ahci_lower_irq is
> incorrectly assuming that the passed AHCIState * is always for a PCI,
> which it is not in the sysbus case. So it's incorrectly getting the
> offset of QOM the object and the QOM cast is treating some invalid
> offset into the (or past) object as a QOM object base address.
>
> The simplest solution is a back pointer in AHCIState to the
> encapsulating device (would be a DeviceState *). The container_of is
> replaced with a nav of this pointer and then the conditional PCI cast
> can work.

This seems to fix the problem. It seems hacky though, I can't find a
better way to check the validity of the PCIDevice. Any ideas?

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 02d85fa..77e58a9 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -137,8 +137,11 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
 {
     AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
-    PCIDevice *pci_dev =
-        (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE);
+    PCIDevice *pci_dev = NULL;
+
+    if (s->parent_obj) {
+        pci_dev = PCI_DEVICE(d);
+    }

     DPRINTF(0, "lower irq\n");

diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index c055d6b..ac7d2de 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -287,6 +287,8 @@ struct AHCIDevice {
 };

 typedef struct AHCIState {
+    DeviceState *parent_obj;
+
     AHCIDevice *dev;
     AHCIControlRegs control_regs;
     MemoryRegion mem;

Thanks,

Alistair

>
> Regards,
> Peter
>
>> Thanks,
>>
>> Alistair
>>
>>>>
>>>> Thanks,
>>>> Andreas
>>>>
>>>> --
>>>> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
>>>> GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)
>>>
>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Peter Crosthwaite]

On Wed, Aug 26, 2015 at 1:36 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Tue, Aug 25, 2015 at 12:43 AM, Peter Crosthwaite
> <crosthwaitepeter@gmail.com> wrote:
>> On Mon, Aug 24, 2015 at 4:36 PM, Alistair Francis
>> <alistair.francis@xilinx.com> wrote:
>>> On Mon, Aug 17, 2015 at 4:37 PM, Peter Crosthwaite
>>> <crosthwaitepeter@gmail.com> wrote:
>>>> On Mon, Aug 17, 2015 at 3:33 PM, Andreas Färber <afaerber@suse.de> wrote:
>>>>> Am 18.08.2015 um 00:24 schrieb Alistair Francis:
>>>>>> On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
>>>>>> <crosthwaitepeter@gmail.com> wrote:
>>>>>>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>>>>>>> <alistair.francis@xilinx.com> wrote:
>>>>>>>> If the ObjectClass has no type return NULL instead of trying to compare
>>>>>>>> the type name.
>>>>>>>>
>>>>>>>
>>>>>>> What was the issue?
>>>>>>
>>>>>> There is a seg fault in object_class_dynamic_cast() because there is
>>>>>> no type in the ObjectClass struct.
>>>>>
>>>>> That should never happen, ever since TYPE_OBJECT is no longer NULL.
>>>>>
>>>>>> It happens when it is trying to cast the "pci-device", which is called
>>>>>> from the ahci_irq_lower() function. The function is testing if the
>>>>>> device is a pci device, so it should return NULL if it isn't valid.
>>>>
>>>> Yes so I vaguely remember this now. It is about MSI interrupts which
>>>> have nothing to do with sysbus implementation. My solution was to rip
>>>> that PCI specific stuff out of AHCI completely in my branch. Should
>>>> sysbus and PCI AHCI classes install their own separate logic for this
>>>> part via a virtualised hook?
>>>>
>>>> On the topic though, I notice many PCI devices have this MSI specific
>>>> logic in them. Is it possible for devs to just treat interrupts as
>>>> pins and the PCI layers do the MSI vs non-MSI logic switch in core
>>>> layers?
>>>>
>>>> If Andreas' idea don't work this is still a core QOM bug though. I
>>>> think object_dynamic_cast should not have this segfault when passed a
>>>> non implementing object.
>>>>
>>>> Regards,
>>>> Peter
>>>>
>>>>>
>>>>> It rather sounds as if some build-time dependency is wrong, which we
>>>>> used to run into for the Container type before Paolo macrofied this.
>>>>>
>>>>> Please try again with a clean build - if it still occurs, we'll need a
>>>>> reproducible test case to investigate what is going on rather than
>>>>> papering over a latent bug.
>>>
>>> Hey,
>>>
>>> Sorry abut the delay, but I didn't get a chance to look at this last
>>> week. I tried with a clean setup and still see the seg fault.
>>>
>>> I will try to look into it more this week, but if anyone is interested
>>> here are the steps to reproduce:
>>>
>>> On the latest mainline QEMU, with my 2nd and 3rd patches applied
>>> $ ./configure --target-list="aarch64-softmmu,microblazeel-softmmu"
>>> --disable-pie --disable-sdl --disable-werror # This is what is
>>> required at work
>>> $ ./aarch64-softmmu/qemu-system-aarch64 -M xlnx-ep108 -display none
>>> -kernel ./u-boot.elf -m 8000000 -nographic -serial mon:stdio # Boot
>>> u-boot on QEMU
>>>
>>> The image I'm using is available at: http://1drv.ms/1NxDXLo
>>>
>>
>> So it's not a core bug. That container_of in ahci_lower_irq is
>> incorrectly assuming that the passed AHCIState * is always for a PCI,
>> which it is not in the sysbus case. So it's incorrectly getting the
>> offset of QOM the object and the QOM cast is treating some invalid
>> offset into the (or past) object as a QOM object base address.
>>
>> The simplest solution is a back pointer in AHCIState to the
>> encapsulating device (would be a DeviceState *). The container_of is
>> replaced with a nav of this pointer and then the conditional PCI cast
>> can work.
>
> This seems to fix the problem.

I assume you have the appropriate setters for the new variable
elsewhere in the code as well?

>It seems hacky though, I can't find a
> better way to check the validity of the PCIDevice. Any ideas?
>

So there a few problems in the way of a correct solution. The caller
for ahci_lower_irq does not have access to the QOM object pointer,
it's been abstracted away by AHCIState (which is not a QOM object). So
you would need to replumb the call path to ahci_lower_irq to pass the
QOM object. This would let you drop the container_of completely.

The next step would be to virtualise ahci_lower_irq, as this is
implementation dependent (assume specific devices really do need to
control the use of PCI MSI?), one implementation for sysbus, one for
PCI. This is blocked by the re-plumbing described above as the
virtualised called itself will need a ptr to the QOM object.

But I think the back ptr is an acceptable solution for the meantime,
this is a clear bug in Sysbus AHCI and should probably even go to
qemu-stable.

> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 02d85fa..77e58a9 100644
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -137,8 +137,11 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
>  static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
>  {
>      AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
> -    PCIDevice *pci_dev =
> -        (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE);
> +    PCIDevice *pci_dev = NULL;
> +
> +    if (s->parent_obj) {

I would make the parent obj compulsory for all AHCIState
implementations and drop the NULL guard.

> +        pci_dev = PCI_DEVICE(d);
> +    }
>
>      DPRINTF(0, "lower irq\n");
>
> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
> index c055d6b..ac7d2de 100644
> --- a/hw/ide/ahci.h
> +++ b/hw/ide/ahci.h
> @@ -287,6 +287,8 @@ struct AHCIDevice {
>  };
>
>  typedef struct AHCIState {
> +    DeviceState *parent_obj;

This name is really for QOM inline parents. We decided a while back to
use "parent" for the QOM parents and "container" for non-parental
containers. Memory regions use the .container field for a similar
purpose.

Regards,
Peter

> +
>      AHCIDevice *dev;
>      AHCIControlRegs control_regs;
>      MemoryRegion mem;
>
> Thanks,
>
> Alistair
>
>>
>> Regards,
>> Peter
>>
>>> Thanks,
>>>
>>> Alistair
>>>
>>>>>
>>>>> Thanks,
>>>>> Andreas
>>>>>
>>>>> --
>>>>> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
>>>>> GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)
>>>>
>>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[John Snow]

On 08/26/2015 05:02 PM, Peter Crosthwaite wrote:
> On Wed, Aug 26, 2015 at 1:36 PM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> On Tue, Aug 25, 2015 at 12:43 AM, Peter Crosthwaite
>> <crosthwaitepeter@gmail.com> wrote:
>>> On Mon, Aug 24, 2015 at 4:36 PM, Alistair Francis
>>> <alistair.francis@xilinx.com> wrote:
>>>> On Mon, Aug 17, 2015 at 4:37 PM, Peter Crosthwaite
>>>> <crosthwaitepeter@gmail.com> wrote:
>>>>> On Mon, Aug 17, 2015 at 3:33 PM, Andreas Färber <afaerber@suse.de> wrote:
>>>>>> Am 18.08.2015 um 00:24 schrieb Alistair Francis:
>>>>>>> On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
>>>>>>> <crosthwaitepeter@gmail.com> wrote:
>>>>>>>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>>>>>>>> <alistair.francis@xilinx.com> wrote:
>>>>>>>>> If the ObjectClass has no type return NULL instead of trying to compare
>>>>>>>>> the type name.
>>>>>>>>>
>>>>>>>>
>>>>>>>> What was the issue?
>>>>>>>
>>>>>>> There is a seg fault in object_class_dynamic_cast() because there is
>>>>>>> no type in the ObjectClass struct.
>>>>>>
>>>>>> That should never happen, ever since TYPE_OBJECT is no longer NULL.
>>>>>>
>>>>>>> It happens when it is trying to cast the "pci-device", which is called
>>>>>>> from the ahci_irq_lower() function. The function is testing if the
>>>>>>> device is a pci device, so it should return NULL if it isn't valid.
>>>>>
>>>>> Yes so I vaguely remember this now. It is about MSI interrupts which
>>>>> have nothing to do with sysbus implementation. My solution was to rip
>>>>> that PCI specific stuff out of AHCI completely in my branch. Should
>>>>> sysbus and PCI AHCI classes install their own separate logic for this
>>>>> part via a virtualised hook?
>>>>>
>>>>> On the topic though, I notice many PCI devices have this MSI specific
>>>>> logic in them. Is it possible for devs to just treat interrupts as
>>>>> pins and the PCI layers do the MSI vs non-MSI logic switch in core
>>>>> layers?
>>>>>
>>>>> If Andreas' idea don't work this is still a core QOM bug though. I
>>>>> think object_dynamic_cast should not have this segfault when passed a
>>>>> non implementing object.
>>>>>
>>>>> Regards,
>>>>> Peter
>>>>>
>>>>>>
>>>>>> It rather sounds as if some build-time dependency is wrong, which we
>>>>>> used to run into for the Container type before Paolo macrofied this.
>>>>>>
>>>>>> Please try again with a clean build - if it still occurs, we'll need a
>>>>>> reproducible test case to investigate what is going on rather than
>>>>>> papering over a latent bug.
>>>>
>>>> Hey,
>>>>
>>>> Sorry abut the delay, but I didn't get a chance to look at this last
>>>> week. I tried with a clean setup and still see the seg fault.
>>>>
>>>> I will try to look into it more this week, but if anyone is interested
>>>> here are the steps to reproduce:
>>>>
>>>> On the latest mainline QEMU, with my 2nd and 3rd patches applied
>>>> $ ./configure --target-list="aarch64-softmmu,microblazeel-softmmu"
>>>> --disable-pie --disable-sdl --disable-werror # This is what is
>>>> required at work
>>>> $ ./aarch64-softmmu/qemu-system-aarch64 -M xlnx-ep108 -display none
>>>> -kernel ./u-boot.elf -m 8000000 -nographic -serial mon:stdio # Boot
>>>> u-boot on QEMU
>>>>
>>>> The image I'm using is available at: http://1drv.ms/1NxDXLo
>>>>
>>>
>>> So it's not a core bug. That container_of in ahci_lower_irq is
>>> incorrectly assuming that the passed AHCIState * is always for a PCI,
>>> which it is not in the sysbus case. So it's incorrectly getting the
>>> offset of QOM the object and the QOM cast is treating some invalid
>>> offset into the (or past) object as a QOM object base address.
>>>
>>> The simplest solution is a back pointer in AHCIState to the
>>> encapsulating device (would be a DeviceState *). The container_of is
>>> replaced with a nav of this pointer and then the conditional PCI cast
>>> can work.
>>
>> This seems to fix the problem.
> 
> I assume you have the appropriate setters for the new variable
> elsewhere in the code as well?
> 
>> It seems hacky though, I can't find a
>> better way to check the validity of the PCIDevice. Any ideas?
>>
> 
> So there a few problems in the way of a correct solution. The caller
> for ahci_lower_irq does not have access to the QOM object pointer,
> it's been abstracted away by AHCIState (which is not a QOM object). So
> you would need to replumb the call path to ahci_lower_irq to pass the
> QOM object. This would let you drop the container_of completely.
> 
> The next step would be to virtualise ahci_lower_irq, as this is
> implementation dependent (assume specific devices really do need to
> control the use of PCI MSI?), one implementation for sysbus, one for
> PCI. This is blocked by the re-plumbing described above as the
> virtualised called itself will need a ptr to the QOM object.
> 
> But I think the back ptr is an acceptable solution for the meantime,
> this is a clear bug in Sysbus AHCI and should probably even go to
> qemu-stable.
> 

I'm not intricately familiar with how the QOM plumbing works, but I can
definitely see how assuming all AHCIState pointers come from
AHCIPCIState is a problem...

For the uninitiated, how does MSI work with Sysbus? What does a Sysbus
AHCI device look like to a guest, and what happens if it tries to
utilize the functionality?

(Well, segfault, I guess.)

If someone wants to clue in the device model newbie and send a patch my
way, I'll take it.

--js

>> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>> index 02d85fa..77e58a9 100644
>> --- a/hw/ide/ahci.c
>> +++ b/hw/ide/ahci.c
>> @@ -137,8 +137,11 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
>>  static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
>>  {
>>      AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
>> -    PCIDevice *pci_dev =
>> -        (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE);
>> +    PCIDevice *pci_dev = NULL;
>> +
>> +    if (s->parent_obj) {
> 
> I would make the parent obj compulsory for all AHCIState
> implementations and drop the NULL guard.
> 
>> +        pci_dev = PCI_DEVICE(d);
>> +    }
>>
>>      DPRINTF(0, "lower irq\n");
>>
>> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
>> index c055d6b..ac7d2de 100644
>> --- a/hw/ide/ahci.h
>> +++ b/hw/ide/ahci.h
>> @@ -287,6 +287,8 @@ struct AHCIDevice {
>>  };
>>
>>  typedef struct AHCIState {
>> +    DeviceState *parent_obj;
> 
> This name is really for QOM inline parents. We decided a while back to
> use "parent" for the QOM parents and "container" for non-parental
> containers. Memory regions use the .container field for a similar
> purpose.
> 
> Regards,
> Peter
> 
>> +
>>      AHCIDevice *dev;
>>      AHCIControlRegs control_regs;
>>      MemoryRegion mem;
>>
>> Thanks,
>>
>> Alistair
>>
>>>
>>> Regards,
>>> Peter
>>>
>>>> Thanks,
>>>>
>>>> Alistair
>>>>
>>>>>>
>>>>>> Thanks,
>>>>>> Andreas
>>>>>>
>>>>>> --
>>>>>> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
>>>>>> GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)
>>>>>
>>>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Peter Crosthwaite]

On Wed, Aug 26, 2015 at 2:46 PM, John Snow <jsnow@redhat.com> wrote:
>
>
> On 08/26/2015 05:02 PM, Peter Crosthwaite wrote:
>> On Wed, Aug 26, 2015 at 1:36 PM, Alistair Francis
>> <alistair.francis@xilinx.com> wrote:
>>> On Tue, Aug 25, 2015 at 12:43 AM, Peter Crosthwaite
>>> <crosthwaitepeter@gmail.com> wrote:
>>>> On Mon, Aug 24, 2015 at 4:36 PM, Alistair Francis
>>>> <alistair.francis@xilinx.com> wrote:
>>>>> On Mon, Aug 17, 2015 at 4:37 PM, Peter Crosthwaite
>>>>> <crosthwaitepeter@gmail.com> wrote:
>>>>>> On Mon, Aug 17, 2015 at 3:33 PM, Andreas Färber <afaerber@suse.de> wrote:
>>>>>>> Am 18.08.2015 um 00:24 schrieb Alistair Francis:
>>>>>>>> On Sat, Aug 15, 2015 at 2:22 PM, Peter Crosthwaite
>>>>>>>> <crosthwaitepeter@gmail.com> wrote:
>>>>>>>>> On Mon, Jul 27, 2015 at 11:37 AM, Alistair Francis
>>>>>>>>> <alistair.francis@xilinx.com> wrote:
>>>>>>>>>> If the ObjectClass has no type return NULL instead of trying to compare
>>>>>>>>>> the type name.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> What was the issue?
>>>>>>>>
>>>>>>>> There is a seg fault in object_class_dynamic_cast() because there is
>>>>>>>> no type in the ObjectClass struct.
>>>>>>>
>>>>>>> That should never happen, ever since TYPE_OBJECT is no longer NULL.
>>>>>>>
>>>>>>>> It happens when it is trying to cast the "pci-device", which is called
>>>>>>>> from the ahci_irq_lower() function. The function is testing if the
>>>>>>>> device is a pci device, so it should return NULL if it isn't valid.
>>>>>>
>>>>>> Yes so I vaguely remember this now. It is about MSI interrupts which
>>>>>> have nothing to do with sysbus implementation. My solution was to rip
>>>>>> that PCI specific stuff out of AHCI completely in my branch. Should
>>>>>> sysbus and PCI AHCI classes install their own separate logic for this
>>>>>> part via a virtualised hook?
>>>>>>
>>>>>> On the topic though, I notice many PCI devices have this MSI specific
>>>>>> logic in them. Is it possible for devs to just treat interrupts as
>>>>>> pins and the PCI layers do the MSI vs non-MSI logic switch in core
>>>>>> layers?
>>>>>>
>>>>>> If Andreas' idea don't work this is still a core QOM bug though. I
>>>>>> think object_dynamic_cast should not have this segfault when passed a
>>>>>> non implementing object.
>>>>>>
>>>>>> Regards,
>>>>>> Peter
>>>>>>
>>>>>>>
>>>>>>> It rather sounds as if some build-time dependency is wrong, which we
>>>>>>> used to run into for the Container type before Paolo macrofied this.
>>>>>>>
>>>>>>> Please try again with a clean build - if it still occurs, we'll need a
>>>>>>> reproducible test case to investigate what is going on rather than
>>>>>>> papering over a latent bug.
>>>>>
>>>>> Hey,
>>>>>
>>>>> Sorry abut the delay, but I didn't get a chance to look at this last
>>>>> week. I tried with a clean setup and still see the seg fault.
>>>>>
>>>>> I will try to look into it more this week, but if anyone is interested
>>>>> here are the steps to reproduce:
>>>>>
>>>>> On the latest mainline QEMU, with my 2nd and 3rd patches applied
>>>>> $ ./configure --target-list="aarch64-softmmu,microblazeel-softmmu"
>>>>> --disable-pie --disable-sdl --disable-werror # This is what is
>>>>> required at work
>>>>> $ ./aarch64-softmmu/qemu-system-aarch64 -M xlnx-ep108 -display none
>>>>> -kernel ./u-boot.elf -m 8000000 -nographic -serial mon:stdio # Boot
>>>>> u-boot on QEMU
>>>>>
>>>>> The image I'm using is available at: http://1drv.ms/1NxDXLo
>>>>>
>>>>
>>>> So it's not a core bug. That container_of in ahci_lower_irq is
>>>> incorrectly assuming that the passed AHCIState * is always for a PCI,
>>>> which it is not in the sysbus case. So it's incorrectly getting the
>>>> offset of QOM the object and the QOM cast is treating some invalid
>>>> offset into the (or past) object as a QOM object base address.
>>>>
>>>> The simplest solution is a back pointer in AHCIState to the
>>>> encapsulating device (would be a DeviceState *). The container_of is
>>>> replaced with a nav of this pointer and then the conditional PCI cast
>>>> can work.
>>>
>>> This seems to fix the problem.
>>
>> I assume you have the appropriate setters for the new variable
>> elsewhere in the code as well?
>>
>>> It seems hacky though, I can't find a
>>> better way to check the validity of the PCIDevice. Any ideas?
>>>
>>
>> So there a few problems in the way of a correct solution. The caller
>> for ahci_lower_irq does not have access to the QOM object pointer,
>> it's been abstracted away by AHCIState (which is not a QOM object). So
>> you would need to replumb the call path to ahci_lower_irq to pass the
>> QOM object. This would let you drop the container_of completely.
>>
>> The next step would be to virtualise ahci_lower_irq, as this is
>> implementation dependent (assume specific devices really do need to
>> control the use of PCI MSI?), one implementation for sysbus, one for
>> PCI. This is blocked by the re-plumbing described above as the
>> virtualised called itself will need a ptr to the QOM object.
>>
>> But I think the back ptr is an acceptable solution for the meantime,
>> this is a clear bug in Sysbus AHCI and should probably even go to
>> qemu-stable.
>>
>
> I'm not intricately familiar with how the QOM plumbing works, but I can
> definitely see how assuming all AHCIState pointers come from
> AHCIPCIState is a problem...
>
> For the uninitiated, how does MSI work with Sysbus?

No such thing :) Interrupts in Sysbus shouldn't really exist and those
that do are just a thin wrapper around raw pins. The short answer is
MSI is a PCI specific concept and sysbus is an alternative to PCI.
Long answer, is any form of MSI requires some sort of transport layer
capable of messaging an interrupt controller from a device with the
device as the initiator. This is not possible in most real busses
which we use the sysbus abstraction for.

> What does a Sysbus
> AHCI device look like to a guest, and what happens if it tries to

Sysbus AHCI is basically the raw MMIO regions mapped onto the "system
bus" by the machine model. Usually this is done as static mapping. The
most common user of this is ARM (and other embedded) SoCs. The
downside is there is no standard for remapping the device or self
identification of the device (as provided by PCI standard). The
existance of the device is made known to a kernel usually by a device
tree blob.

In the Xilinx MPSoC case, the AHCI controller is on the SoC (with the
ARM processor and many other IO peripherals). There are no cards or
even inter-chip connectivites in Alistairs AHCI connection.

> utilize the functionality?
>

If you rework an exsiting PCI driver to use raw MMIO regions and
interrupts rather than bars and MSIs it usually works with minor edits
only. SDHCI, AHCI, EHCI, xHCI at least all have both PCI
implementations and real world sysbus implementations.

What I would be interested in, is it possible to push all MSI code up
to the PCI core to completely remove the need for all PCIisms in AHCI?
This seems to be the only thing that is PCI specific.

Regards,
Peter

> (Well, segfault, I guess.)
>
> If someone wants to clue in the device model newbie and send a patch my
> way, I'll take it.
>
> --js
>
>>> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>>> index 02d85fa..77e58a9 100644
>>> --- a/hw/ide/ahci.c
>>> +++ b/hw/ide/ahci.c
>>> @@ -137,8 +137,11 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
>>>  static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
>>>  {
>>>      AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
>>> -    PCIDevice *pci_dev =
>>> -        (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE);
>>> +    PCIDevice *pci_dev = NULL;
>>> +
>>> +    if (s->parent_obj) {
>>
>> I would make the parent obj compulsory for all AHCIState
>> implementations and drop the NULL guard.
>>
>>> +        pci_dev = PCI_DEVICE(d);
>>> +    }
>>>
>>>      DPRINTF(0, "lower irq\n");
>>>
>>> diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
>>> index c055d6b..ac7d2de 100644
>>> --- a/hw/ide/ahci.h
>>> +++ b/hw/ide/ahci.h
>>> @@ -287,6 +287,8 @@ struct AHCIDevice {
>>>  };
>>>
>>>  typedef struct AHCIState {
>>> +    DeviceState *parent_obj;
>>
>> This name is really for QOM inline parents. We decided a while back to
>> use "parent" for the QOM parents and "container" for non-parental
>> containers. Memory regions use the .container field for a similar
>> purpose.
>>
>> Regards,
>> Peter
>>
>>> +
>>>      AHCIDevice *dev;
>>>      AHCIControlRegs control_regs;
>>>      MemoryRegion mem;
>>>
>>> Thanks,
>>>
>>> Alistair
>>>
>>>>
>>>> Regards,
>>>> Peter
>>>>
>>>>> Thanks,
>>>>>
>>>>> Alistair
>>>>>
>>>>>>>
>>>>>>> Thanks,
>>>>>>> Andreas
>>>>>>>
>>>>>>> --
>>>>>>> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
>>>>>>> GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)
>>>>>>
>>>>
>

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Peter Maydell]

On 26 August 2015 at 23:15, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Wed, Aug 26, 2015 at 2:46 PM, John Snow <jsnow@redhat.com> wrote:
>> For the uninitiated, how does MSI work with Sysbus?
>
> No such thing :) Interrupts in Sysbus shouldn't really exist and those
> that do are just a thin wrapper around raw pins. The short answer is
> MSI is a PCI specific concept and sysbus is an alternative to PCI.

My preferred way to think about this is that the 'sysbus' device
is the raw "whatever-it-is chip" (uart, usb controller, whatever),
and you can wire that chip up directly on a board (sysbus), or wire
it up to a pci bus. (Yeah, in practice the PCI functionality is
probably on the same bit of silicon, but as a model it works
more or less.)

You can see something similar going on in our uart models:
we have a pci-serial, an isa-serial and some embedded UARTs
which all use the same core serial code but present a different
interface to the rest of the system.


> What I would be interested in, is it possible to push all MSI code up
> to the PCI core to completely remove the need for all PCIisms in AHCI?
> This seems to be the only thing that is PCI specific.

Possibly it might have to live in a pci-ahci wrapper class,
but it ought to be possible to keep it out of the common
ahci code I hope.

-- PMM

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[John Snow]

On 08/26/2015 06:15 PM, Peter Crosthwaite wrote:
> On Wed, Aug 26, 2015 at 2:46 PM, John Snow <jsnow@redhat.com> wrote:
>>
>>
>> On 08/26/2015 05:02 PM, Peter Crosthwaite wrote:

[snip]

>>>
>>> So there a few problems in the way of a correct solution. The caller
>>> for ahci_lower_irq does not have access to the QOM object pointer,
>>> it's been abstracted away by AHCIState (which is not a QOM object). So
>>> you would need to replumb the call path to ahci_lower_irq to pass the
>>> QOM object. This would let you drop the container_of completely.
>>>
>>> The next step would be to virtualise ahci_lower_irq, as this is
>>> implementation dependent (assume specific devices really do need to
>>> control the use of PCI MSI?), one implementation for sysbus, one for
>>> PCI. This is blocked by the re-plumbing described above as the
>>> virtualised called itself will need a ptr to the QOM object.
>>>
>>> But I think the back ptr is an acceptable solution for the meantime,
>>> this is a clear bug in Sysbus AHCI and should probably even go to
>>> qemu-stable.
>>>
>>
>> I'm not intricately familiar with how the QOM plumbing works, but I can
>> definitely see how assuming all AHCIState pointers come from
>> AHCIPCIState is a problem...
>>
>> For the uninitiated, how does MSI work with Sysbus?
> 
> No such thing :) Interrupts in Sysbus shouldn't really exist and those
> that do are just a thin wrapper around raw pins. The short answer is
> MSI is a PCI specific concept and sysbus is an alternative to PCI.
> Long answer, is any form of MSI requires some sort of transport layer
> capable of messaging an interrupt controller from a device with the
> device as the initiator. This is not possible in most real busses
> which we use the sysbus abstraction for.
> 

Ah, OK ... I seemed to recall there being some MSI bits in the HBA
registers, so I was confused. However, I think it's just a read-only
status bit, which allows it to just always be off for your device.

>> What does a Sysbus
>> AHCI device look like to a guest, and what happens if it tries to
> 
> Sysbus AHCI is basically the raw MMIO regions mapped onto the "system
> bus" by the machine model. Usually this is done as static mapping. The
> most common user of this is ARM (and other embedded) SoCs. The
> downside is there is no standard for remapping the device or self
> identification of the device (as provided by PCI standard). The
> existance of the device is made known to a kernel usually by a device
> tree blob.
> 
> In the Xilinx MPSoC case, the AHCI controller is on the SoC (with the
> ARM processor and many other IO peripherals). There are no cards or
> even inter-chip connectivites in Alistairs AHCI connection.
> 
>> utilize the functionality?
>>
> 
> If you rework an exsiting PCI driver to use raw MMIO regions and
> interrupts rather than bars and MSIs it usually works with minor edits
> only. SDHCI, AHCI, EHCI, xHCI at least all have both PCI
> implementations and real world sysbus implementations.
> 
> What I would be interested in, is it possible to push all MSI code up
> to the PCI core to completely remove the need for all PCIisms in AHCI?
> This seems to be the only thing that is PCI specific.

Fields that reference MSI in the AHCI spec are:

GHC.MRSM (MSI Revert To Single Message, read-only, is 0 when MSI is off)
CCC_CTL.INT (Advertises MSI vector)

You're save leaving both of these to zero, so I think there's nothing
else PCI-specific in the HBA region.

Anyway, apologies for not noticing this while I was reworking the AHCI
device!

> 
> Regards,
> Peter
> 
>> (Well, segfault, I guess.)
>>
>> If someone wants to clue in the device model newbie and send a patch my
>> way, I'll take it.
>>
>> --js
>>

[snip]

Re: [Qemu-devel] [PATCH v1 2/3] object.c: object_class_dynamic_cast return NULL if the class has no type

[Alistair Francis]

On Wed, Aug 26, 2015 at 4:11 PM, John Snow <jsnow@redhat.com> wrote:
>
>
> On 08/26/2015 06:15 PM, Peter Crosthwaite wrote:
>> On Wed, Aug 26, 2015 at 2:46 PM, John Snow <jsnow@redhat.com> wrote:
>>>
>>>
>>> On 08/26/2015 05:02 PM, Peter Crosthwaite wrote:
>
> [snip]
>
>>>>
>>>> So there a few problems in the way of a correct solution. The caller
>>>> for ahci_lower_irq does not have access to the QOM object pointer,
>>>> it's been abstracted away by AHCIState (which is not a QOM object). So
>>>> you would need to replumb the call path to ahci_lower_irq to pass the
>>>> QOM object. This would let you drop the container_of completely.

Ok, I think I have figured it out. It took me a while to get my head
around what is going on here. I'm just testing then I'll send a new
version of the series. Thanks for your help Peter.

Thanks,

Alistair

>>>>
>>>> The next step would be to virtualise ahci_lower_irq, as this is
>>>> implementation dependent (assume specific devices really do need to
>>>> control the use of PCI MSI?), one implementation for sysbus, one for
>>>> PCI. This is blocked by the re-plumbing described above as the
>>>> virtualised called itself will need a ptr to the QOM object.
>>>>
>>>> But I think the back ptr is an acceptable solution for the meantime,
>>>> this is a clear bug in Sysbus AHCI and should probably even go to
>>>> qemu-stable.
>>>>
>>>
>>> I'm not intricately familiar with how the QOM plumbing works, but I can
>>> definitely see how assuming all AHCIState pointers come from
>>> AHCIPCIState is a problem...
>>>
>>> For the uninitiated, how does MSI work with Sysbus?
>>
>> No such thing :) Interrupts in Sysbus shouldn't really exist and those
>> that do are just a thin wrapper around raw pins. The short answer is
>> MSI is a PCI specific concept and sysbus is an alternative to PCI.
>> Long answer, is any form of MSI requires some sort of transport layer
>> capable of messaging an interrupt controller from a device with the
>> device as the initiator. This is not possible in most real busses
>> which we use the sysbus abstraction for.
>>
>
> Ah, OK ... I seemed to recall there being some MSI bits in the HBA
> registers, so I was confused. However, I think it's just a read-only
> status bit, which allows it to just always be off for your device.
>
>>> What does a Sysbus
>>> AHCI device look like to a guest, and what happens if it tries to
>>
>> Sysbus AHCI is basically the raw MMIO regions mapped onto the "system
>> bus" by the machine model. Usually this is done as static mapping. The
>> most common user of this is ARM (and other embedded) SoCs. The
>> downside is there is no standard for remapping the device or self
>> identification of the device (as provided by PCI standard). The
>> existance of the device is made known to a kernel usually by a device
>> tree blob.
>>
>> In the Xilinx MPSoC case, the AHCI controller is on the SoC (with the
>> ARM processor and many other IO peripherals). There are no cards or
>> even inter-chip connectivites in Alistairs AHCI connection.
>>
>>> utilize the functionality?
>>>
>>
>> If you rework an exsiting PCI driver to use raw MMIO regions and
>> interrupts rather than bars and MSIs it usually works with minor edits
>> only. SDHCI, AHCI, EHCI, xHCI at least all have both PCI
>> implementations and real world sysbus implementations.
>>
>> What I would be interested in, is it possible to push all MSI code up
>> to the PCI core to completely remove the need for all PCIisms in AHCI?
>> This seems to be the only thing that is PCI specific.
>
> Fields that reference MSI in the AHCI spec are:
>
> GHC.MRSM (MSI Revert To Single Message, read-only, is 0 when MSI is off)
> CCC_CTL.INT (Advertises MSI vector)
>
> You're save leaving both of these to zero, so I think there's nothing
> else PCI-specific in the HBA region.
>
> Anyway, apologies for not noticing this while I was reworking the AHCI
> device!
>
>>
>> Regards,
>> Peter
>>
>>> (Well, segfault, I guess.)
>>>
>>> If someone wants to clue in the device model newbie and send a patch my
>>> way, I'll take it.
>>>
>>> --js
>>>
>
> [snip]
>