* [PATCH v5 0/2] clk: Add Artpec-6 SoC support
@ 2016-03-31 18:02 Lars Persson
2016-03-31 18:02 ` [PATCH v5 1/2] clk: add device tree binding for Artpec-6 clock controller Lars Persson
2016-03-31 18:02 ` Lars Persson
0 siblings, 2 replies; 8+ messages in thread
From: Lars Persson @ 2016-03-31 18:02 UTC (permalink / raw)
To: devicetree, linux-clk
Cc: mturquette, sboyd, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux-kernel, Lars Persson
Add clock support for the Artpec-6 SoC port. The ARM parts are merged in
4.6-rc1.
Changes since v4:
- Update the maintainer entry with the correct clock directory.
- Implement split clock registration with early clocks through CLK_OF_DECLARE
and deferrable clocks through a platform driver.
Changes since v3:
- The binding was corrected to handle two fractional divider clocks as input to
the clock controller.
- Updated clk-artpec6.c to handle a distinct fractional divider input for each
i2s clock mux.
Changes since v2:
- Moved axis,artpec6-clkctrl.h to the first patch with the DT bindings.
Changes since v1:
- The driver now provides all clocks from the main clock controller block
through one DT node.
- Added a header file for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock controller
.../devicetree/bindings/clock/artpec6.txt | 41 ++++
MAINTAINERS | 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 230 +++++++++++++++++++++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38 ++++
6 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
create mode 100644 drivers/clk/axis/Makefile
create mode 100644 drivers/clk/axis/clk-artpec6.c
create mode 100644 include/dt-bindings/clock/axis,artpec6-clkctrl.h
--
2.1.4
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 1/2] clk: add device tree binding for Artpec-6 clock controller
2016-03-31 18:02 [PATCH v5 0/2] clk: Add Artpec-6 SoC support Lars Persson
@ 2016-03-31 18:02 ` Lars Persson
2016-03-31 18:02 ` Lars Persson
1 sibling, 0 replies; 8+ messages in thread
From: Lars Persson @ 2016-03-31 18:02 UTC (permalink / raw)
To: devicetree, linux-clk
Cc: mturquette, sboyd, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux-kernel, Lars Persson
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lars Persson <larper@axis.com>
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++++++++++++++++++++++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38 ++++++++++++++++++++
2 files changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
create mode 100644 include/dt-bindings/clock/axis,artpec6-clkctrl.h
diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt b/Documentation/devicetree/bindings/clock/artpec6.txt
new file mode 100644
index 0000000..9ba9bd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/artpec6.txt
@@ -0,0 +1,41 @@
+* Clock bindings for Axis ARTPEC-6 chip
+
+The bindings are based on the clock provider binding in
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+External clocks:
+----------------
+
+There are two external inputs to the main clock controller which should be
+provided using the common clock bindings.
+- "sys_refclk": External 50 Mhz oscillator (required)
+- "i2s_refclk": Alternate audio reference clock (optional).
+
+Main clock controller
+---------------------
+
+Required properties:
+- #clock-cells: Should be <1>
+ See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
+- compatible: Should be "axis,artpec6-clkctrl"
+- reg: Must contain the base address and length of the system controller
+- clocks: Must contain a phandle entry for each clock in clock-names
+- clock-names: Must include the external oscillator ("sys_refclk"). Optional
+ ones are the audio reference clock ("i2s_refclk") and the audio fractional
+ dividers ("frac_clk0" and "frac_clk1").
+
+Examples:
+
+ext_clk: ext_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+};
+
+clkctrl: clkctrl {
+ #clock-cells = <1>;
+ compatible = "axis,artpec6-clkctrl";
+ reg = <0xf8000000 0x48>;
+ clocks = <&ext_clk>;
+ clock-names = "sys_refclk";
+};
diff --git a/include/dt-bindings/clock/axis,artpec6-clkctrl.h b/include/dt-bindings/clock/axis,artpec6-clkctrl.h
new file mode 100644
index 0000000..f9f04dc
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec6-clkctrl.h
@@ -0,0 +1,38 @@
+/*
+ * ARTPEC-6 clock controller indexes
+ *
+ * Copyright 2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+
+#define ARTPEC6_CLK_CPU 0
+#define ARTPEC6_CLK_CPU_PERIPH 1
+#define ARTPEC6_CLK_NAND_CLKA 2
+#define ARTPEC6_CLK_NAND_CLKB 3
+#define ARTPEC6_CLK_ETH_ACLK 4
+#define ARTPEC6_CLK_DMA_ACLK 5
+#define ARTPEC6_CLK_PTP_REF 6
+#define ARTPEC6_CLK_SD_PCLK 7
+#define ARTPEC6_CLK_SD_IMCLK 8
+#define ARTPEC6_CLK_I2S_HST 9
+#define ARTPEC6_CLK_I2S0_CLK 10
+#define ARTPEC6_CLK_I2S1_CLK 11
+#define ARTPEC6_CLK_UART_PCLK 12
+#define ARTPEC6_CLK_UART_REFCLK 13
+#define ARTPEC6_CLK_I2C 14
+#define ARTPEC6_CLK_SPI_PCLK 15
+#define ARTPEC6_CLK_SPI_SSPCLK 16
+#define ARTPEC6_CLK_SYS_TIMER 17
+#define ARTPEC6_CLK_FRACDIV_IN 18
+#define ARTPEC6_CLK_DBG_PCLK 19
+
+/* This must be the highest clock index plus one. */
+#define ARTPEC6_CLK_NUMCLOCKS 20
+
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v5 2/2] clk: add artpec-6 clock controller
@ 2016-03-31 18:02 ` Lars Persson
0 siblings, 0 replies; 8+ messages in thread
From: Lars Persson @ 2016-03-31 18:02 UTC (permalink / raw)
To: devicetree, linux-clk
Cc: mturquette, sboyd, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux-kernel, Lars Persson
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson <larper@axis.com>
---
MAINTAINERS | 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 230 +++++++++++++++++++++++++++++++++++++++++
4 files changed, 233 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/axis/Makefile
create mode 100644 drivers/clk/axis/clk-artpec6.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 378ebff..074e39e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -973,7 +973,7 @@ S: Maintained
L: linux-arm-kernel@axis.com
F: arch/arm/mach-artpec
F: arch/arm/boot/dts/artpec6*
-F: drivers/clk/clk-artpec6.c
+F: drivers/clk/axis
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
M: Nicolas Ferre <nicolas.ferre@atmel.com>
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 46869d6..ca9aa7b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
+obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
new file mode 100644
index 0000000..628c9d3
--- /dev/null
+++ b/drivers/clk/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
new file mode 100644
index 0000000..cf716f1
--- /dev/null
+++ b/drivers/clk/axis/clk-artpec6.c
@@ -0,0 +1,230 @@
+/*
+ * ARTPEC-6 clock initialization
+ *
+ * Copyright 2015-2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
+
+#define NUM_I2S_CLOCKS 2
+
+struct artpec6_clkctrl_drvdata {
+ struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS];
+ void __iomem *syscon_base;
+ struct clk_onecell_data clk_data;
+ spinlock_t i2scfg_lock;
+};
+
+
+static struct artpec6_clkctrl_drvdata *clkdata;
+
+static const char *i2s_clk_names[NUM_I2S_CLOCKS] = {
+ "i2s0",
+ "i2s1",
+};
+
+static const int i2s_clk_indexes[NUM_I2S_CLOCKS] = {
+ ARTPEC6_CLK_I2S0_CLK,
+ ARTPEC6_CLK_I2S1_CLK,
+};
+
+static void of_artpec6_clkctrl_setup(struct device_node *np)
+{
+ int i;
+ const char *sys_refclk_name;
+ u32 pll_mode, pll_m, pll_n;
+
+ pr_info("of_artpec6_clkctrl_setup\n");
+
+ /* Mandatory parent clock. */
+ i = of_property_match_string(np, "clock-names", "sys_refclk");
+ if (i < 0)
+ return;
+
+ sys_refclk_name = of_clk_get_parent_name(np, i);
+
+ clkdata = kzalloc(sizeof(*clkdata), GFP_KERNEL);
+ if (!clkdata)
+ return;
+
+ for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i)
+ clkdata->clk_table[i] = ERR_PTR(-EPROBE_DEFER);
+
+ clkdata->syscon_base = of_iomap(np, 0);
+
+ /* Read PLL1 factors configured by boot strap pins. */
+ pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
+ switch (pll_mode) {
+ case 0: /* DDR3-2133 mode */
+ pll_m = 4;
+ pll_n = 85;
+ break;
+ case 1: /* DDR3-1866 mode */
+ pll_m = 6;
+ pll_n = 112;
+ break;
+ case 2: /* DDR3-1600 mode */
+ pll_m = 4;
+ pll_n = 64;
+ break;
+ case 3: /* DDR3-1333 mode */
+ pll_m = 8;
+ pll_n = 106;
+ break;
+ }
+
+ clkdata->clk_table[ARTPEC6_CLK_CPU] =
+ clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
+ pll_m);
+ clkdata->clk_table[ARTPEC6_CLK_CPU_PERIPH] =
+ clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
+
+ /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
+ clkdata->clk_table[ARTPEC6_CLK_UART_PCLK] =
+ clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
+ clkdata->clk_table[ARTPEC6_CLK_UART_REFCLK] =
+ clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
+ 50000000);
+
+ clkdata->clk_table[ARTPEC6_CLK_SPI_PCLK] =
+ clk_register_fixed_factor(NULL, "spi_pclk", "cpu", 0, 1, 8);
+ clkdata->clk_table[ARTPEC6_CLK_SPI_SSPCLK] =
+ clk_register_fixed_rate(NULL, "spi_sspclk", sys_refclk_name, 0,
+ 50000000);
+
+ clkdata->clk_table[ARTPEC6_CLK_DBG_PCLK] =
+ clk_register_fixed_factor(NULL, "dbg_pclk", "cpu", 0, 1, 8);
+
+ clkdata->clk_data.clks = clkdata->clk_table;
+ clkdata->clk_data.clk_num = ARTPEC6_CLK_NUMCLOCKS;
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clkdata->clk_data);
+}
+
+CLK_OF_DECLARE(artpec6_clkctrl, "axis,artpec6-clkctrl",
+ of_artpec6_clkctrl_setup);
+
+static int artpec6_clkctrl_probe(struct platform_device *pdev)
+{
+ int propidx;
+ struct device_node *np = pdev->dev.of_node;
+ const char *sys_refclk_name;
+ const char *i2s_refclk_name = NULL;
+ const char *frac_clk_name[2] = { NULL, NULL };
+ const char *i2s_mux_parents[2] = { NULL, NULL };
+ u32 muxreg;
+ u32 i;
+
+ /* Mandatory parent clock. */
+ propidx = of_property_match_string(np, "clock-names", "sys_refclk");
+ if (propidx < 0)
+ return -EINVAL;
+
+ sys_refclk_name = of_clk_get_parent_name(np, propidx);
+
+ /* Find clock names of optional parent clocks. */
+ propidx = of_property_match_string(np, "clock-names", "i2s_refclk");
+ if (propidx >= 0)
+ i2s_refclk_name = of_clk_get_parent_name(np, propidx);
+
+ propidx = of_property_match_string(np, "clock-names", "frac_clk0");
+ if (propidx >= 0)
+ frac_clk_name[0] = of_clk_get_parent_name(np, propidx);
+ propidx = of_property_match_string(np, "clock-names", "frac_clk1");
+ if (propidx >= 0)
+ frac_clk_name[1] = of_clk_get_parent_name(np, propidx);
+
+ spin_lock_init(&clkdata->i2scfg_lock);
+
+ clkdata->clk_table[ARTPEC6_CLK_NAND_CLKA] =
+ clk_register_fixed_factor(NULL, "nand_clka", "cpu", 0, 1, 8);
+ clkdata->clk_table[ARTPEC6_CLK_NAND_CLKB] =
+ clk_register_fixed_rate(NULL, "nand_clkb", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_ETH_ACLK] =
+ clk_register_fixed_factor(NULL, "eth_aclk", "cpu", 0, 1, 4);
+ clkdata->clk_table[ARTPEC6_CLK_DMA_ACLK] =
+ clk_register_fixed_factor(NULL, "dma_aclk", "cpu", 0, 1, 4);
+ clkdata->clk_table[ARTPEC6_CLK_PTP_REF] =
+ clk_register_fixed_rate(NULL, "ptp_ref", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_SD_PCLK] =
+ clk_register_fixed_rate(NULL, "sd_pclk", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_SD_IMCLK] =
+ clk_register_fixed_rate(NULL, "sd_imclk", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_I2S_HST] =
+ clk_register_fixed_factor(NULL, "i2s_hst", "cpu", 0, 1, 8);
+
+ for (i = 0; i < NUM_I2S_CLOCKS; ++i) {
+ if (i2s_refclk_name && frac_clk_name[i]) {
+ i2s_mux_parents[0] = frac_clk_name[i];
+ i2s_mux_parents[1] = i2s_refclk_name;
+
+ clkdata->clk_table[i2s_clk_indexes[i]] =
+ clk_register_mux(NULL, i2s_clk_names[i],
+ i2s_mux_parents, 2,
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_SET_RATE_PARENT,
+ clkdata->syscon_base + 0x14, i, 1,
+ 0, &clkdata->i2scfg_lock);
+ } else if (frac_clk_name[i]) {
+ /* Lock the mux for internal clock reference. */
+ muxreg = readl(clkdata->syscon_base + 0x14);
+ muxreg &= ~BIT(i);
+ writel(muxreg, clkdata->syscon_base + 0x14);
+ clkdata->clk_table[i2s_clk_indexes[i]] =
+ clk_register_fixed_factor(NULL, i2s_clk_names[i],
+ frac_clk_name[i], 0, 1,
+ 1);
+ } else if (i2s_refclk_name) {
+ /* Lock the mux for external clock reference. */
+ muxreg = readl(clkdata->syscon_base + 0x14);
+ muxreg |= BIT(i);
+ writel(muxreg, clkdata->syscon_base + 0x14);
+ clkdata->clk_table[i2s_clk_indexes[i]] =
+ clk_register_fixed_factor(NULL, i2s_clk_names[i],
+ i2s_refclk_name, 0, 1, 1);
+ }
+ }
+
+ clkdata->clk_table[ARTPEC6_CLK_I2C] =
+ clk_register_fixed_rate(NULL, "i2c", sys_refclk_name, 0, 100000000);
+
+ clkdata->clk_table[ARTPEC6_CLK_SYS_TIMER] =
+ clk_register_fixed_rate(NULL, "timer", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_FRACDIV_IN] =
+ clk_register_fixed_rate(NULL, "fracdiv_in", sys_refclk_name, 0,
+ 600000000);
+
+ return 0;
+}
+
+static const struct of_device_id artpec_clkctrl_of_match[] = {
+ { .compatible = "axis,artpec6-clkctrl" },
+ {},
+};
+
+static struct platform_driver artpec6_clkctrl_driver = {
+ .probe = artpec6_clkctrl_probe,
+ .driver = {
+ .name = "artpec6_clkctrl",
+ .of_match_table = artpec_clkctrl_of_match,
+ },
+};
+
+builtin_platform_driver(artpec6_clkctrl_driver);
--
2.1.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v5 2/2] clk: add artpec-6 clock controller
@ 2016-03-31 18:02 ` Lars Persson
0 siblings, 0 replies; 8+ messages in thread
From: Lars Persson @ 2016-03-31 18:02 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Lars Persson
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson <larper-VrBV9hrLPhE@public.gmane.org>
---
MAINTAINERS | 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 230 +++++++++++++++++++++++++++++++++++++++++
4 files changed, 233 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/axis/Makefile
create mode 100644 drivers/clk/axis/clk-artpec6.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 378ebff..074e39e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -973,7 +973,7 @@ S: Maintained
L: linux-arm-kernel-VrBV9hrLPhE@public.gmane.org
F: arch/arm/mach-artpec
F: arch/arm/boot/dts/artpec6*
-F: drivers/clk/clk-artpec6.c
+F: drivers/clk/axis
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
M: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 46869d6..ca9aa7b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
+obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
new file mode 100644
index 0000000..628c9d3
--- /dev/null
+++ b/drivers/clk/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
new file mode 100644
index 0000000..cf716f1
--- /dev/null
+++ b/drivers/clk/axis/clk-artpec6.c
@@ -0,0 +1,230 @@
+/*
+ * ARTPEC-6 clock initialization
+ *
+ * Copyright 2015-2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
+
+#define NUM_I2S_CLOCKS 2
+
+struct artpec6_clkctrl_drvdata {
+ struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS];
+ void __iomem *syscon_base;
+ struct clk_onecell_data clk_data;
+ spinlock_t i2scfg_lock;
+};
+
+
+static struct artpec6_clkctrl_drvdata *clkdata;
+
+static const char *i2s_clk_names[NUM_I2S_CLOCKS] = {
+ "i2s0",
+ "i2s1",
+};
+
+static const int i2s_clk_indexes[NUM_I2S_CLOCKS] = {
+ ARTPEC6_CLK_I2S0_CLK,
+ ARTPEC6_CLK_I2S1_CLK,
+};
+
+static void of_artpec6_clkctrl_setup(struct device_node *np)
+{
+ int i;
+ const char *sys_refclk_name;
+ u32 pll_mode, pll_m, pll_n;
+
+ pr_info("of_artpec6_clkctrl_setup\n");
+
+ /* Mandatory parent clock. */
+ i = of_property_match_string(np, "clock-names", "sys_refclk");
+ if (i < 0)
+ return;
+
+ sys_refclk_name = of_clk_get_parent_name(np, i);
+
+ clkdata = kzalloc(sizeof(*clkdata), GFP_KERNEL);
+ if (!clkdata)
+ return;
+
+ for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i)
+ clkdata->clk_table[i] = ERR_PTR(-EPROBE_DEFER);
+
+ clkdata->syscon_base = of_iomap(np, 0);
+
+ /* Read PLL1 factors configured by boot strap pins. */
+ pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
+ switch (pll_mode) {
+ case 0: /* DDR3-2133 mode */
+ pll_m = 4;
+ pll_n = 85;
+ break;
+ case 1: /* DDR3-1866 mode */
+ pll_m = 6;
+ pll_n = 112;
+ break;
+ case 2: /* DDR3-1600 mode */
+ pll_m = 4;
+ pll_n = 64;
+ break;
+ case 3: /* DDR3-1333 mode */
+ pll_m = 8;
+ pll_n = 106;
+ break;
+ }
+
+ clkdata->clk_table[ARTPEC6_CLK_CPU] =
+ clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
+ pll_m);
+ clkdata->clk_table[ARTPEC6_CLK_CPU_PERIPH] =
+ clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
+
+ /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
+ clkdata->clk_table[ARTPEC6_CLK_UART_PCLK] =
+ clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
+ clkdata->clk_table[ARTPEC6_CLK_UART_REFCLK] =
+ clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
+ 50000000);
+
+ clkdata->clk_table[ARTPEC6_CLK_SPI_PCLK] =
+ clk_register_fixed_factor(NULL, "spi_pclk", "cpu", 0, 1, 8);
+ clkdata->clk_table[ARTPEC6_CLK_SPI_SSPCLK] =
+ clk_register_fixed_rate(NULL, "spi_sspclk", sys_refclk_name, 0,
+ 50000000);
+
+ clkdata->clk_table[ARTPEC6_CLK_DBG_PCLK] =
+ clk_register_fixed_factor(NULL, "dbg_pclk", "cpu", 0, 1, 8);
+
+ clkdata->clk_data.clks = clkdata->clk_table;
+ clkdata->clk_data.clk_num = ARTPEC6_CLK_NUMCLOCKS;
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clkdata->clk_data);
+}
+
+CLK_OF_DECLARE(artpec6_clkctrl, "axis,artpec6-clkctrl",
+ of_artpec6_clkctrl_setup);
+
+static int artpec6_clkctrl_probe(struct platform_device *pdev)
+{
+ int propidx;
+ struct device_node *np = pdev->dev.of_node;
+ const char *sys_refclk_name;
+ const char *i2s_refclk_name = NULL;
+ const char *frac_clk_name[2] = { NULL, NULL };
+ const char *i2s_mux_parents[2] = { NULL, NULL };
+ u32 muxreg;
+ u32 i;
+
+ /* Mandatory parent clock. */
+ propidx = of_property_match_string(np, "clock-names", "sys_refclk");
+ if (propidx < 0)
+ return -EINVAL;
+
+ sys_refclk_name = of_clk_get_parent_name(np, propidx);
+
+ /* Find clock names of optional parent clocks. */
+ propidx = of_property_match_string(np, "clock-names", "i2s_refclk");
+ if (propidx >= 0)
+ i2s_refclk_name = of_clk_get_parent_name(np, propidx);
+
+ propidx = of_property_match_string(np, "clock-names", "frac_clk0");
+ if (propidx >= 0)
+ frac_clk_name[0] = of_clk_get_parent_name(np, propidx);
+ propidx = of_property_match_string(np, "clock-names", "frac_clk1");
+ if (propidx >= 0)
+ frac_clk_name[1] = of_clk_get_parent_name(np, propidx);
+
+ spin_lock_init(&clkdata->i2scfg_lock);
+
+ clkdata->clk_table[ARTPEC6_CLK_NAND_CLKA] =
+ clk_register_fixed_factor(NULL, "nand_clka", "cpu", 0, 1, 8);
+ clkdata->clk_table[ARTPEC6_CLK_NAND_CLKB] =
+ clk_register_fixed_rate(NULL, "nand_clkb", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_ETH_ACLK] =
+ clk_register_fixed_factor(NULL, "eth_aclk", "cpu", 0, 1, 4);
+ clkdata->clk_table[ARTPEC6_CLK_DMA_ACLK] =
+ clk_register_fixed_factor(NULL, "dma_aclk", "cpu", 0, 1, 4);
+ clkdata->clk_table[ARTPEC6_CLK_PTP_REF] =
+ clk_register_fixed_rate(NULL, "ptp_ref", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_SD_PCLK] =
+ clk_register_fixed_rate(NULL, "sd_pclk", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_SD_IMCLK] =
+ clk_register_fixed_rate(NULL, "sd_imclk", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_I2S_HST] =
+ clk_register_fixed_factor(NULL, "i2s_hst", "cpu", 0, 1, 8);
+
+ for (i = 0; i < NUM_I2S_CLOCKS; ++i) {
+ if (i2s_refclk_name && frac_clk_name[i]) {
+ i2s_mux_parents[0] = frac_clk_name[i];
+ i2s_mux_parents[1] = i2s_refclk_name;
+
+ clkdata->clk_table[i2s_clk_indexes[i]] =
+ clk_register_mux(NULL, i2s_clk_names[i],
+ i2s_mux_parents, 2,
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_SET_RATE_PARENT,
+ clkdata->syscon_base + 0x14, i, 1,
+ 0, &clkdata->i2scfg_lock);
+ } else if (frac_clk_name[i]) {
+ /* Lock the mux for internal clock reference. */
+ muxreg = readl(clkdata->syscon_base + 0x14);
+ muxreg &= ~BIT(i);
+ writel(muxreg, clkdata->syscon_base + 0x14);
+ clkdata->clk_table[i2s_clk_indexes[i]] =
+ clk_register_fixed_factor(NULL, i2s_clk_names[i],
+ frac_clk_name[i], 0, 1,
+ 1);
+ } else if (i2s_refclk_name) {
+ /* Lock the mux for external clock reference. */
+ muxreg = readl(clkdata->syscon_base + 0x14);
+ muxreg |= BIT(i);
+ writel(muxreg, clkdata->syscon_base + 0x14);
+ clkdata->clk_table[i2s_clk_indexes[i]] =
+ clk_register_fixed_factor(NULL, i2s_clk_names[i],
+ i2s_refclk_name, 0, 1, 1);
+ }
+ }
+
+ clkdata->clk_table[ARTPEC6_CLK_I2C] =
+ clk_register_fixed_rate(NULL, "i2c", sys_refclk_name, 0, 100000000);
+
+ clkdata->clk_table[ARTPEC6_CLK_SYS_TIMER] =
+ clk_register_fixed_rate(NULL, "timer", sys_refclk_name, 0,
+ 100000000);
+ clkdata->clk_table[ARTPEC6_CLK_FRACDIV_IN] =
+ clk_register_fixed_rate(NULL, "fracdiv_in", sys_refclk_name, 0,
+ 600000000);
+
+ return 0;
+}
+
+static const struct of_device_id artpec_clkctrl_of_match[] = {
+ { .compatible = "axis,artpec6-clkctrl" },
+ {},
+};
+
+static struct platform_driver artpec6_clkctrl_driver = {
+ .probe = artpec6_clkctrl_probe,
+ .driver = {
+ .name = "artpec6_clkctrl",
+ .of_match_table = artpec_clkctrl_of_match,
+ },
+};
+
+builtin_platform_driver(artpec6_clkctrl_driver);
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v5 2/2] clk: add artpec-6 clock controller
2016-03-31 18:02 ` Lars Persson
(?)
@ 2016-04-02 1:39 ` Stephen Boyd
2016-04-04 8:24 ` Lars Persson
-1 siblings, 1 reply; 8+ messages in thread
From: Stephen Boyd @ 2016-04-02 1:39 UTC (permalink / raw)
To: Lars Persson
Cc: devicetree, linux-clk, mturquette, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, linux-kernel, Lars Persson
On 03/31, Lars Persson wrote:
> diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
> new file mode 100644
> index 0000000..628c9d3
> --- /dev/null
> +++ b/drivers/clk/axis/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
> diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
> new file mode 100644
> index 0000000..cf716f1
> --- /dev/null
> +++ b/drivers/clk/axis/clk-artpec6.c
> @@ -0,0 +1,230 @@
> +/*
> + * ARTPEC-6 clock initialization
> + *
> + * Copyright 2015-2016 Axis Comunications AB.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
Is this include used?
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
Is this include used?
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
> +
> +#define NUM_I2S_CLOCKS 2
> +
> +struct artpec6_clkctrl_drvdata {
> + struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS];
> + void __iomem *syscon_base;
> + struct clk_onecell_data clk_data;
> + spinlock_t i2scfg_lock;
> +};
> +
> +
> +static struct artpec6_clkctrl_drvdata *clkdata;
> +
> +static const char *i2s_clk_names[NUM_I2S_CLOCKS] = {
const char * const?
> + "i2s0",
> + "i2s1",
> +};
> +
> +static const int i2s_clk_indexes[NUM_I2S_CLOCKS] = {
> + ARTPEC6_CLK_I2S0_CLK,
> + ARTPEC6_CLK_I2S1_CLK,
> +};
> +
> +static void of_artpec6_clkctrl_setup(struct device_node *np)
> +{
> + int i;
> + const char *sys_refclk_name;
> + u32 pll_mode, pll_m, pll_n;
> +
> + pr_info("of_artpec6_clkctrl_setup\n");
Debug noise?
> +
> + /* Mandatory parent clock. */
> + i = of_property_match_string(np, "clock-names", "sys_refclk");
> + if (i < 0)
> + return;
> +
> + sys_refclk_name = of_clk_get_parent_name(np, i);
> +
> + clkdata = kzalloc(sizeof(*clkdata), GFP_KERNEL);
> + if (!clkdata)
> + return;
> +
> + for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i)
> + clkdata->clk_table[i] = ERR_PTR(-EPROBE_DEFER);
> +
> + clkdata->syscon_base = of_iomap(np, 0);
What if that fails?
> +
> + /* Read PLL1 factors configured by boot strap pins. */
> + pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
> + switch (pll_mode) {
> + case 0: /* DDR3-2133 mode */
> + pll_m = 4;
> + pll_n = 85;
> + break;
> + case 1: /* DDR3-1866 mode */
> + pll_m = 6;
> + pll_n = 112;
> + break;
> + case 2: /* DDR3-1600 mode */
> + pll_m = 4;
> + pll_n = 64;
> + break;
> + case 3: /* DDR3-1333 mode */
> + pll_m = 8;
> + pll_n = 106;
> + break;
> + }
> +
> + clkdata->clk_table[ARTPEC6_CLK_CPU] =
> + clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
> + pll_m);
> + clkdata->clk_table[ARTPEC6_CLK_CPU_PERIPH] =
> + clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
> +
> + /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
Shouldn't we fix that then?
> + clkdata->clk_table[ARTPEC6_CLK_UART_PCLK] =
> + clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
> + clkdata->clk_table[ARTPEC6_CLK_UART_REFCLK] =
> + clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
> + 50000000);
> +
> + clkdata->clk_table[ARTPEC6_CLK_SPI_PCLK] =
> + clk_register_fixed_factor(NULL, "spi_pclk", "cpu", 0, 1, 8);
> + clkdata->clk_table[ARTPEC6_CLK_SPI_SSPCLK] =
> + clk_register_fixed_rate(NULL, "spi_sspclk", sys_refclk_name, 0,
> + 50000000);
> +
> + clkdata->clk_table[ARTPEC6_CLK_DBG_PCLK] =
> + clk_register_fixed_factor(NULL, "dbg_pclk", "cpu", 0, 1, 8);
> +
> + clkdata->clk_data.clks = clkdata->clk_table;
> + clkdata->clk_data.clk_num = ARTPEC6_CLK_NUMCLOCKS;
> +
> + of_clk_add_provider(np, of_clk_src_onecell_get, &clkdata->clk_data);
> +}
> +
Nitpick: Drop newline here.
> +CLK_OF_DECLARE(artpec6_clkctrl, "axis,artpec6-clkctrl",
> + of_artpec6_clkctrl_setup);
> +
> +static int artpec6_clkctrl_probe(struct platform_device *pdev)
> +{
> + int propidx;
> + struct device_node *np = pdev->dev.of_node;
> + const char *sys_refclk_name;
> + const char *i2s_refclk_name = NULL;
> + const char *frac_clk_name[2] = { NULL, NULL };
> + const char *i2s_mux_parents[2] = { NULL, NULL };
Do we need to initialize this to NULL?
> + u32 muxreg;
> + u32 i;
int i please.
> +
> + /* Mandatory parent clock. */
> + propidx = of_property_match_string(np, "clock-names", "sys_refclk");
> + if (propidx < 0)
> + return -EINVAL;
> +
> + sys_refclk_name = of_clk_get_parent_name(np, propidx);
> +
> + /* Find clock names of optional parent clocks. */
> + propidx = of_property_match_string(np, "clock-names", "i2s_refclk");
> + if (propidx >= 0)
> + i2s_refclk_name = of_clk_get_parent_name(np, propidx);
> +
> + propidx = of_property_match_string(np, "clock-names", "frac_clk0");
> + if (propidx >= 0)
> + frac_clk_name[0] = of_clk_get_parent_name(np, propidx);
> + propidx = of_property_match_string(np, "clock-names", "frac_clk1");
> + if (propidx >= 0)
> + frac_clk_name[1] = of_clk_get_parent_name(np, propidx);
> +
> + spin_lock_init(&clkdata->i2scfg_lock);
> +
> + clkdata->clk_table[ARTPEC6_CLK_NAND_CLKA] =
> + clk_register_fixed_factor(NULL, "nand_clka", "cpu", 0, 1, 8);
> + clkdata->clk_table[ARTPEC6_CLK_NAND_CLKB] =
> + clk_register_fixed_rate(NULL, "nand_clkb", sys_refclk_name, 0,
> + 100000000);
> + clkdata->clk_table[ARTPEC6_CLK_ETH_ACLK] =
> + clk_register_fixed_factor(NULL, "eth_aclk", "cpu", 0, 1, 4);
> + clkdata->clk_table[ARTPEC6_CLK_DMA_ACLK] =
> + clk_register_fixed_factor(NULL, "dma_aclk", "cpu", 0, 1, 4);
> + clkdata->clk_table[ARTPEC6_CLK_PTP_REF] =
> + clk_register_fixed_rate(NULL, "ptp_ref", sys_refclk_name, 0,
> + 100000000);
> + clkdata->clk_table[ARTPEC6_CLK_SD_PCLK] =
> + clk_register_fixed_rate(NULL, "sd_pclk", sys_refclk_name, 0,
> + 100000000);
> + clkdata->clk_table[ARTPEC6_CLK_SD_IMCLK] =
> + clk_register_fixed_rate(NULL, "sd_imclk", sys_refclk_name, 0,
> + 100000000);
> + clkdata->clk_table[ARTPEC6_CLK_I2S_HST] =
> + clk_register_fixed_factor(NULL, "i2s_hst", "cpu", 0, 1, 8);
Pass device pointer for all these.
> +
> + for (i = 0; i < NUM_I2S_CLOCKS; ++i) {
> + if (i2s_refclk_name && frac_clk_name[i]) {
> + i2s_mux_parents[0] = frac_clk_name[i];
> + i2s_mux_parents[1] = i2s_refclk_name;
> +
> + clkdata->clk_table[i2s_clk_indexes[i]] =
> + clk_register_mux(NULL, i2s_clk_names[i],
Please pass the device pointer here.
> + i2s_mux_parents, 2,
> + CLK_SET_RATE_NO_REPARENT |
> + CLK_SET_RATE_PARENT,
> + clkdata->syscon_base + 0x14, i, 1,
> + 0, &clkdata->i2scfg_lock);
> + } else if (frac_clk_name[i]) {
> + /* Lock the mux for internal clock reference. */
> + muxreg = readl(clkdata->syscon_base + 0x14);
> + muxreg &= ~BIT(i);
> + writel(muxreg, clkdata->syscon_base + 0x14);
> + clkdata->clk_table[i2s_clk_indexes[i]] =
> + clk_register_fixed_factor(NULL, i2s_clk_names[i],
> + frac_clk_name[i], 0, 1,
> + 1);
> + } else if (i2s_refclk_name) {
> + /* Lock the mux for external clock reference. */
> + muxreg = readl(clkdata->syscon_base + 0x14);
> + muxreg |= BIT(i);
> + writel(muxreg, clkdata->syscon_base + 0x14);
> + clkdata->clk_table[i2s_clk_indexes[i]] =
> + clk_register_fixed_factor(NULL, i2s_clk_names[i],
> + i2s_refclk_name, 0, 1, 1);
> + }
Please assign the register result to some local variable and then
assign that local variable to clkdata->clk_table[...] once.
> + }
> +
> + clkdata->clk_table[ARTPEC6_CLK_I2C] =
> + clk_register_fixed_rate(NULL, "i2c", sys_refclk_name, 0, 100000000);
> +
> + clkdata->clk_table[ARTPEC6_CLK_SYS_TIMER] =
> + clk_register_fixed_rate(NULL, "timer", sys_refclk_name, 0,
> + 100000000);
> + clkdata->clk_table[ARTPEC6_CLK_FRACDIV_IN] =
> + clk_register_fixed_rate(NULL, "fracdiv_in", sys_refclk_name, 0,
> + 600000000);
What if any of these fail?
> +
> + return 0;
> +}
> +
> +static const struct of_device_id artpec_clkctrl_of_match[] = {
> + { .compatible = "axis,artpec6-clkctrl" },
> + {},
Nitpick: Drop ',' here so that people don't get any wrong ideas.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v5 2/2] clk: add artpec-6 clock controller
2016-04-02 1:39 ` Stephen Boyd
@ 2016-04-04 8:24 ` Lars Persson
0 siblings, 0 replies; 8+ messages in thread
From: Lars Persson @ 2016-04-04 8:24 UTC (permalink / raw)
To: Stephen Boyd
Cc: devicetree, linux-clk, mturquette, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, linux-kernel
On 04/02/2016 03:39 AM, Stephen Boyd wrote:
> On 03/31, Lars Persson wrote:
>> diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
>> new file mode 100644
>> index 0000000..628c9d3
>> --- /dev/null
>> +++ b/drivers/clk/axis/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
>> diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
>> new file mode 100644
>> index 0000000..cf716f1
>> --- /dev/null
[snip]
>
>> +
>> + /* Read PLL1 factors configured by boot strap pins. */
>> + pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
>> + switch (pll_mode) {
>> + case 0: /* DDR3-2133 mode */
>> + pll_m = 4;
>> + pll_n = 85;
>> + break;
>> + case 1: /* DDR3-1866 mode */
>> + pll_m = 6;
>> + pll_n = 112;
>> + break;
>> + case 2: /* DDR3-1600 mode */
>> + pll_m = 4;
>> + pll_n = 64;
>> + break;
>> + case 3: /* DDR3-1333 mode */
>> + pll_m = 8;
>> + pll_n = 106;
>> + break;
>> + }
>> +
>> + clkdata->clk_table[ARTPEC6_CLK_CPU] =
>> + clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
>> + pll_m);
>> + clkdata->clk_table[ARTPEC6_CLK_CPU_PERIPH] =
>> + clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
>> +
>> + /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
>
> Shouldn't we fix that then?
Marek Szyprowski recently tried to fix this, but Russel NAKed the change
due to userspace breakage:
https://lkml.org/lkml/2016/2/15/555
>
>> + clkdata->clk_table[ARTPEC6_CLK_UART_PCLK] =
>> + clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
>> + clkdata->clk_table[ARTPEC6_CLK_UART_REFCLK] =
>> + clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
>> + 50000000);
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v5 2/2] clk: add artpec-6 clock controller
@ 2016-04-04 8:24 ` Lars Persson
0 siblings, 0 replies; 8+ messages in thread
From: Lars Persson @ 2016-04-04 8:24 UTC (permalink / raw)
To: Stephen Boyd
Cc: devicetree, linux-clk, mturquette, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, linux-kernel
On 04/02/2016 03:39 AM, Stephen Boyd wrote:
> On 03/31, Lars Persson wrote:
>> diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
>> new file mode 100644
>> index 0000000..628c9d3
>> --- /dev/null
>> +++ b/drivers/clk/axis/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
>> diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
>> new file mode 100644
>> index 0000000..cf716f1
>> --- /dev/null
[snip]
>
>> +
>> + /* Read PLL1 factors configured by boot strap pins. */
>> + pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
>> + switch (pll_mode) {
>> + case 0: /* DDR3-2133 mode */
>> + pll_m = 4;
>> + pll_n = 85;
>> + break;
>> + case 1: /* DDR3-1866 mode */
>> + pll_m = 6;
>> + pll_n = 112;
>> + break;
>> + case 2: /* DDR3-1600 mode */
>> + pll_m = 4;
>> + pll_n = 64;
>> + break;
>> + case 3: /* DDR3-1333 mode */
>> + pll_m = 8;
>> + pll_n = 106;
>> + break;
>> + }
>> +
>> + clkdata->clk_table[ARTPEC6_CLK_CPU] =
>> + clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
>> + pll_m);
>> + clkdata->clk_table[ARTPEC6_CLK_CPU_PERIPH] =
>> + clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
>> +
>> + /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
>
> Shouldn't we fix that then?
Marek Szyprowski recently tried to fix this, but Russel NAKed the change
due to userspace breakage:
https://lkml.org/lkml/2016/2/15/555
>
>> + clkdata->clk_table[ARTPEC6_CLK_UART_PCLK] =
>> + clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
>> + clkdata->clk_table[ARTPEC6_CLK_UART_REFCLK] =
>> + clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
>> + 50000000);
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v5 2/2] clk: add artpec-6 clock controller
2016-04-04 8:24 ` Lars Persson
(?)
@ 2016-04-15 22:58 ` Stephen Boyd
-1 siblings, 0 replies; 8+ messages in thread
From: Stephen Boyd @ 2016-04-15 22:58 UTC (permalink / raw)
To: Lars Persson
Cc: devicetree, linux-clk, mturquette, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, linux-kernel
On 04/04, Lars Persson wrote:
>
> On 04/02/2016 03:39 AM, Stephen Boyd wrote:
> >On 03/31, Lars Persson wrote:
> >>+
> >>+ /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
> >
> >Shouldn't we fix that then?
>
> Marek Szyprowski recently tried to fix this, but Russel NAKed the
> change due to userspace breakage:
> https://lkml.org/lkml/2016/2/15/555
>
Thanks for the pointer. It looks like the discussion stalled
though... I guess I'll merge v6 assuming it's all good otherwise
and make a todo to circle back once the amba bus is fixed.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-04-15 22:59 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-31 18:02 [PATCH v5 0/2] clk: Add Artpec-6 SoC support Lars Persson
2016-03-31 18:02 ` [PATCH v5 1/2] clk: add device tree binding for Artpec-6 clock controller Lars Persson
2016-03-31 18:02 ` [PATCH v5 2/2] clk: add artpec-6 " Lars Persson
2016-03-31 18:02 ` Lars Persson
2016-04-02 1:39 ` Stephen Boyd
2016-04-04 8:24 ` Lars Persson
2016-04-04 8:24 ` Lars Persson
2016-04-15 22:58 ` Stephen Boyd
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