* [PATCH v4 0/3] pcie-designware: add iATU unroll feature
@ 2016-08-09 16:35 Joao Pinto
2016-08-09 16:35 ` [PATCH v4 1/3] pcie-designware: move definitions Joao Pinto
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Joao Pinto @ 2016-08-09 16:35 UTC (permalink / raw)
To: helgaas; +Cc: jingoohan1, linux-pci, linux-kernel, jszhang, Joao Pinto
The new DWC PCIe Core version (4.80) implements iATU in a different way.
This new mechanism is called iATU Unroll Mode. The Core still supports
the "old" mechanism calling it Legacy Mode if configured to do so, but
the standard way will be using Unroll.
This patch adds the necessary support for the mechanism and makes
some minor improvements to the existent one.
Joao Pinto (3):
pci: move definitions from header to pcie-designware.c
pci: add iATU Unroll mechanism
pcie-designware: fix typo
drivers/pci/host/pcie-designware.c | 138 ++++++++++++++++++++++++++++++++-----
drivers/pci/host/pcie-designware.h | 6 +-
2 files changed, 122 insertions(+), 22 deletions(-)
--
1.8.1.5
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/3] pcie-designware: move definitions
2016-08-09 16:35 [PATCH v4 0/3] pcie-designware: add iATU unroll feature Joao Pinto
@ 2016-08-09 16:35 ` Joao Pinto
2016-08-09 16:35 ` [PATCH v4 2/3] pcie-designware: add iATU Unroll feature Joao Pinto
2016-08-09 16:35 ` [PATCH v4 3/3] pcie-designware: fix typo Joao Pinto
2 siblings, 0 replies; 6+ messages in thread
From: Joao Pinto @ 2016-08-09 16:35 UTC (permalink / raw)
To: helgaas; +Cc: jingoohan1, linux-pci, linux-kernel, jszhang, Joao Pinto
This patch moves the sleep definitions to the *.c file like suggested
by Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
CC: Jisheng Zhang <jszhang@marvell.com>
---
changes v3->v4:
- Just to keep up with the patch version
changes v2->v3 (Bjorn Helgaas):
- Separated from the new iATU unroll mechanism patch
drivers/pci/host/pcie-designware.c | 5 +++++
drivers/pci/host/pcie-designware.h | 5 -----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 12afce1..6fb88de 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -26,6 +26,11 @@
#include "pcie-designware.h"
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES 10
+#define LINK_WAIT_USLEEP_MIN 90000
+#define LINK_WAIT_USLEEP_MAX 100000
+
/* Synopsis specific PCIE configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_MODE_MASK (0x3f << 16)
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index f437f9b..384e79b 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -22,11 +22,6 @@
#define MAX_MSI_IRQS 32
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
-/* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_USLEEP_MIN 90000
-#define LINK_WAIT_USLEEP_MAX 100000
-
struct pcie_port {
struct device *dev;
u8 root_bus_nr;
--
1.8.1.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 2/3] pcie-designware: add iATU Unroll feature
2016-08-09 16:35 [PATCH v4 0/3] pcie-designware: add iATU unroll feature Joao Pinto
2016-08-09 16:35 ` [PATCH v4 1/3] pcie-designware: move definitions Joao Pinto
@ 2016-08-09 16:35 ` Joao Pinto
2016-08-09 16:35 ` [PATCH v4 3/3] pcie-designware: fix typo Joao Pinto
2 siblings, 0 replies; 6+ messages in thread
From: Joao Pinto @ 2016-08-09 16:35 UTC (permalink / raw)
To: helgaas; +Cc: jingoohan1, linux-pci, linux-kernel, jszhang, Joao Pinto
This patch adds the support to the new iATU mechanism that will be used
from Core version 4.80, which is called iATU Unroll.
The new Cores can support the iATU Unroll or support the "old" iATU
method now called Legacy Mode. The driver is perfectly capable of
performing well for both.
In order to make sure that the iATU is really enabled a for loop was
introduced in dw_pcie_prog_outbound_atu() to improve reliability.
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
---
changes v3->v4:
- Unroll Mode is now obtained before the host initialization
- The iATU enable check loop is now returning instead of only
interrupting the loop
changes v2->v3 (Bjorn Helgaas):
- Unused *CTRL3 and *UPPR iATU Unroll registers were removed
- Inbound addr builder macro was removed to simplifiy the code
- *readl_unroll and *writel_unroll functions were simplified. Now the
scope is always outbound.
- dw_pcie_get_atu_mode changed to return the status
- iATU enable check routine was improved in dw_pcie_prog_outbound_atu()
changes v1->v2:
- Patch was breaking kernel build due to bad definition in macro funtion.
- Rebased on top of pci/next.
drivers/pci/host/pcie-designware.c | 131 ++++++++++++++++++++++++++++++++-----
drivers/pci/host/pcie-designware.h | 1 +
2 files changed, 116 insertions(+), 16 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6fb88de..3fb9036 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -31,6 +31,11 @@
#define LINK_WAIT_USLEEP_MIN 90000
#define LINK_WAIT_USLEEP_MAX 100000
+/* Parameters for the waiting for iATU enabled routine */
+#define LINK_WAIT_MAX_IATU_RETRIES 5
+#define LINK_WAIT_IATU_MIN 9000
+#define LINK_WAIT_IATU_MAX 10000
+
/* Synopsis specific PCIE configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_MODE_MASK (0x3f << 16)
@@ -75,6 +80,26 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+/*
+ * iATU unroll specific registers and definitions
+ * from 4.80 core version the address translation will be made by unroll
+ */
+
+/* Registers */
+#define PCIE_ATU_UNR_REGION_CTRL1 0x00
+#define PCIE_ATU_UNR_REGION_CTRL2 0x01
+#define PCIE_ATU_UNR_LOWER_BASE 0x02
+#define PCIE_ATU_UNR_UPPER_BASE 0x03
+#define PCIE_ATU_UNR_LIMIT 0x04
+#define PCIE_ATU_UNR_LOWER_TARGET 0x05
+#define PCIE_ATU_UNR_UPPER_TARGET 0x06
+
+/* Register address builder */
+#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register) \
+ ((0x3 << 20) | (region << 9) | \
+ (register << 2))
+/* End of Unroll specific */
+
/* PCIe Port Logic registers */
#define PLR_OFFSET 0x700
#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
@@ -136,6 +161,28 @@ static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
writel(val, pp->dbi_base + reg);
}
+static inline void dw_pcie_readl_unroll(struct pcie_port *pp,
+ u32 index, u32 reg, u32 *val)
+{
+ u32 reg_addr = PCIE_GET_ATU_OUTB_UNR_REG_ADDR(index, reg);
+
+ if (pp->ops->readl_rc)
+ pp->ops->readl_rc(pp, pp->dbi_base + reg_addr, val);
+ else
+ *val = readl(pp->dbi_base + reg_addr);
+}
+
+static inline void dw_pcie_writel_unroll(struct pcie_port *pp,
+ u32 index, u32 val, u32 reg)
+{
+ u32 reg_addr = PCIE_GET_ATU_OUTB_UNR_REG_ADDR(index, reg);
+
+ if (pp->ops->writel_rc)
+ pp->ops->writel_rc(pp, val, pp->dbi_base + reg_addr);
+ else
+ writel(val, pp->dbi_base + reg_addr);
+}
+
static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
u32 *val)
{
@@ -157,24 +204,61 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
int type, u64 cpu_addr, u64 pci_addr, u32 size)
{
- u32 val;
-
- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
- PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
- PCIE_ATU_LIMIT);
- dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
- dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
- dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+ u32 val = 0;
+ u32 retries = 0;
+
+ if (pp->iatu_unroll_status) {
+ dw_pcie_writel_unroll(pp, index,
+ lower_32_bits(cpu_addr), PCIE_ATU_UNR_LOWER_BASE);
+ dw_pcie_writel_unroll(pp, index,
+ upper_32_bits(cpu_addr), PCIE_ATU_UNR_UPPER_BASE);
+ dw_pcie_writel_unroll(pp, index,
+ lower_32_bits(cpu_addr + size - 1), PCIE_ATU_UNR_LIMIT);
+ dw_pcie_writel_unroll(pp, index,
+ lower_32_bits(pci_addr), PCIE_ATU_UNR_LOWER_TARGET);
+ dw_pcie_writel_unroll(pp, index,
+ upper_32_bits(pci_addr), PCIE_ATU_UNR_UPPER_TARGET);
+ dw_pcie_writel_unroll(pp, index,
+ type, PCIE_ATU_UNR_REGION_CTRL1);
+ dw_pcie_writel_unroll(pp, index,
+ PCIE_ATU_ENABLE, PCIE_ATU_UNR_REGION_CTRL2);
+ } else {
+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
+ PCIE_ATU_VIEWPORT);
+ dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr),
+ PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr),
+ PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
+ PCIE_ATU_LIMIT);
+ dw_pcie_writel_rc(pp, lower_32_bits(pci_addr),
+ PCIE_ATU_LOWER_TARGET);
+ dw_pcie_writel_rc(pp, upper_32_bits(pci_addr),
+ PCIE_ATU_UPPER_TARGET);
+ dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+ }
/*
- * Make sure ATU enable takes effect before any subsequent config
- * and I/O accesses.
- */
- dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
+ * Make sure ATU enable takes effect before any subsequent config
+ * and I/O accesses.
+ */
+ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
+
+ if (pp->iatu_unroll_status) {
+ dw_pcie_readl_unroll(pp, index,
+ PCIE_ATU_UNR_REGION_CTRL2, &val);
+ } else {
+ dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
+ }
+
+ if (val == PCIE_ATU_ENABLE)
+ break;
+
+ usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
+ }
+
+ dev_dbg(pp->dev, "iATU is not being enabled\n");
}
static struct irq_chip dw_msi_irq_chip = {
@@ -433,6 +517,19 @@ static const struct irq_domain_ops msi_domain_ops = {
.map = dw_pcie_msi_map,
};
+static u8 dw_pcie_get_atu_mode(struct pcie_port *pp)
+{
+ u32 val = 0;
+
+ /* Check if the iATU unroll is enabled or not */
+ dw_pcie_readl_rc(pp, PCIE_ATU_VIEWPORT, &val);
+
+ if (val == 0xFFFFFFFF)
+ return 1; /* enabled */
+
+ return 0; /* disabled */
+}
+
int dw_pcie_host_init(struct pcie_port *pp)
{
struct device_node *np = pp->dev->of_node;
@@ -552,6 +649,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (pp->ops->host_init)
pp->ops->host_init(pp);
+ pp->iatu_unroll_status = dw_pcie_get_atu_mode(pp);
+
pp->root_bus_nr = pp->busn->start;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 384e79b..354a981 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -48,6 +48,7 @@ struct pcie_port {
int msi_irq;
struct irq_domain *irq_domain;
unsigned long msi_data;
+ u8 iatu_unroll_status;
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 3/3] pcie-designware: fix typo
2016-08-09 16:35 [PATCH v4 0/3] pcie-designware: add iATU unroll feature Joao Pinto
2016-08-09 16:35 ` [PATCH v4 1/3] pcie-designware: move definitions Joao Pinto
2016-08-09 16:35 ` [PATCH v4 2/3] pcie-designware: add iATU Unroll feature Joao Pinto
@ 2016-08-09 16:35 ` Joao Pinto
2016-08-09 16:54 ` Bjorn Helgaas
2 siblings, 1 reply; 6+ messages in thread
From: Joao Pinto @ 2016-08-09 16:35 UTC (permalink / raw)
To: helgaas; +Cc: jingoohan1, linux-pci, linux-kernel, jszhang, Joao Pinto
Simple fix typo.
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
---
changes v1->v4:
- Nothing changed. Just to keep up patch set version.
drivers/pci/host/pcie-designware.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 3fb9036..7731eda 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -36,7 +36,7 @@
#define LINK_WAIT_IATU_MIN 9000
#define LINK_WAIT_IATU_MAX 10000
-/* Synopsis specific PCIE configuration registers */
+/* Synopsys specific PCIE configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_MODE_MASK (0x3f << 16)
#define PORT_LINK_MODE_1_LANES (0x1 << 16)
@@ -253,7 +253,7 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
}
if (val == PCIE_ATU_ENABLE)
- break;
+ return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
}
@@ -646,11 +646,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
+ pp->iatu_unroll_status = dw_pcie_get_atu_mode(pp);
+
if (pp->ops->host_init)
pp->ops->host_init(pp);
- pp->iatu_unroll_status = dw_pcie_get_atu_mode(pp);
-
pp->root_bus_nr = pp->busn->start;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
--
1.8.1.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 3/3] pcie-designware: fix typo
2016-08-09 16:35 ` [PATCH v4 3/3] pcie-designware: fix typo Joao Pinto
@ 2016-08-09 16:54 ` Bjorn Helgaas
2016-08-10 9:27 ` Joao Pinto
0 siblings, 1 reply; 6+ messages in thread
From: Bjorn Helgaas @ 2016-08-09 16:54 UTC (permalink / raw)
To: Joao Pinto; +Cc: jingoohan1, linux-pci, linux-kernel, jszhang
Hi Joao,
On Tue, Aug 09, 2016 at 05:35:34PM +0100, Joao Pinto wrote:
> Simple fix typo.
This patch actually does more than fix a typo. Not sure if you
intended to split this into separate patches, or to write a better
changelog for this one. If these code changes are related and we have
a good changelog, I don't mind if the typo fix is included as an
incidental change.
Bjorn
> Signed-off-by: Joao Pinto <jpinto@synopsys.com>
> ---
> changes v1->v4:
> - Nothing changed. Just to keep up patch set version.
>
> drivers/pci/host/pcie-designware.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 3fb9036..7731eda 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -36,7 +36,7 @@
> #define LINK_WAIT_IATU_MIN 9000
> #define LINK_WAIT_IATU_MAX 10000
>
> -/* Synopsis specific PCIE configuration registers */
> +/* Synopsys specific PCIE configuration registers */
> #define PCIE_PORT_LINK_CONTROL 0x710
> #define PORT_LINK_MODE_MASK (0x3f << 16)
> #define PORT_LINK_MODE_1_LANES (0x1 << 16)
> @@ -253,7 +253,7 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
> }
>
> if (val == PCIE_ATU_ENABLE)
> - break;
> + return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> }
> @@ -646,11 +646,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
> }
> }
>
> + pp->iatu_unroll_status = dw_pcie_get_atu_mode(pp);
> +
> if (pp->ops->host_init)
> pp->ops->host_init(pp);
>
> - pp->iatu_unroll_status = dw_pcie_get_atu_mode(pp);
> -
> pp->root_bus_nr = pp->busn->start;
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
> --
> 1.8.1.5
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 3/3] pcie-designware: fix typo
2016-08-09 16:54 ` Bjorn Helgaas
@ 2016-08-10 9:27 ` Joao Pinto
0 siblings, 0 replies; 6+ messages in thread
From: Joao Pinto @ 2016-08-10 9:27 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto; +Cc: jingoohan1, linux-pci, linux-kernel, jszhang
Hi Bjorn,
On 8/9/2016 5:54 PM, Bjorn Helgaas wrote:
> Hi Joao,
>
> On Tue, Aug 09, 2016 at 05:35:34PM +0100, Joao Pinto wrote:
>> Simple fix typo.
>
> This patch actually does more than fix a typo. Not sure if you
> intended to split this into separate patches, or to write a better
> changelog for this one. If these code changes are related and we have
> a good changelog, I don't mind if the typo fix is included as an
> incidental change.
Not sure what happened, but the fix typo should be in a separated patch!
I am going to send you a v5 of the patch set.
Thanks!
>
> Bjorn
>
>> Signed-off-by: Joao Pinto <jpinto@synopsys.com>
>> ---
>> changes v1->v4:
>> - Nothing changed. Just to keep up patch set version.
>>
>> drivers/pci/host/pcie-designware.c | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
>> index 3fb9036..7731eda 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -36,7 +36,7 @@
>> #define LINK_WAIT_IATU_MIN 9000
>> #define LINK_WAIT_IATU_MAX 10000
>>
>> -/* Synopsis specific PCIE configuration registers */
>> +/* Synopsys specific PCIE configuration registers */
>> #define PCIE_PORT_LINK_CONTROL 0x710
>> #define PORT_LINK_MODE_MASK (0x3f << 16)
>> #define PORT_LINK_MODE_1_LANES (0x1 << 16)
>> @@ -253,7 +253,7 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
>> }
>>
>> if (val == PCIE_ATU_ENABLE)
>> - break;
>> + return;
>>
>> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
>> }
>> @@ -646,11 +646,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
>> }
>> }
>>
>> + pp->iatu_unroll_status = dw_pcie_get_atu_mode(pp);
>> +
>> if (pp->ops->host_init)
>> pp->ops->host_init(pp);
>>
>> - pp->iatu_unroll_status = dw_pcie_get_atu_mode(pp);
>> -
>> pp->root_bus_nr = pp->busn->start;
>> if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
>> --
>> 1.8.1.5
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-08-10 18:55 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-09 16:35 [PATCH v4 0/3] pcie-designware: add iATU unroll feature Joao Pinto
2016-08-09 16:35 ` [PATCH v4 1/3] pcie-designware: move definitions Joao Pinto
2016-08-09 16:35 ` [PATCH v4 2/3] pcie-designware: add iATU Unroll feature Joao Pinto
2016-08-09 16:35 ` [PATCH v4 3/3] pcie-designware: fix typo Joao Pinto
2016-08-09 16:54 ` Bjorn Helgaas
2016-08-10 9:27 ` Joao Pinto
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