* [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds
@ 2016-09-16 13:59 Jani Nikula
2016-09-16 13:59 ` [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions Jani Nikula
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Jani Nikula @ 2016-09-16 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Only production steppings are supported, drop workarounds for anything
else. The series is split by revision so we can bikeshed if there are
steppings some people still need to use for some reason.
BR,
Jani.
Jani Nikula (5):
drm/i915/skl: drop workarounds for A0 and B0 revisions
drm/i915/skl: drop workarounds for C0 revision
drm/i915/skl: drop workarounds for D0 revision
drm/i915/skl: drop workarounds for E0 revision
drm/i915/skl: drop workarounds for F0 revision
drivers/gpu/drm/i915/intel_dp.c | 4 --
drivers/gpu/drm/i915/intel_dp_link_training.c | 3 --
drivers/gpu/drm/i915/intel_guc_loader.c | 8 ++--
drivers/gpu/drm/i915/intel_lrc.c | 23 +++++------
drivers/gpu/drm/i915/intel_pm.c | 3 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 58 +++++----------------------
6 files changed, 23 insertions(+), 76 deletions(-)
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
@ 2016-09-16 13:59 ` Jani Nikula
2016-09-19 7:59 ` Mika Kahola
2016-09-16 13:59 ` [PATCH 2/5] drm/i915/skl: drop workarounds for C0 revision Jani Nikula
` (6 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2016-09-16 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Pre-production hardware is not supported.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 4 ----
drivers/gpu/drm/i915/intel_dp_link_training.c | 3 ---
drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++---
drivers/gpu/drm/i915/intel_lrc.c | 8 +++-----
drivers/gpu/drm/i915/intel_ringbuffer.c | 21 ++++++---------------
5 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index acd0c51f74d5..b2a9eb82ac4b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1299,10 +1299,6 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
- /* WaDisableHBR2:skl */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
- return false;
-
if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
(INTEL_INFO(dev)->gen >= 9))
return true;
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index c438b02184cb..0048b520baf7 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
* Intel platforms that support HBR2 also support TPS3. TPS3 support is
* also mandatory for downstream devices that support HBR2. However, not
* all sinks follow the spec.
- *
- * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
- * supported in source but still not enabled.
*/
source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 6fd39efb7894..acc1dbdd024e 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -375,9 +375,8 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
/* Enable MIA caching. GuC clock gating is disabled. */
I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
- /* WaDisableMinuteIaClockGating:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ /* WaDisableMinuteIaClockGating:bxt */
+ if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
~GUC_ENABLE_MIA_CLOCK_GATING));
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 251143361f31..4bfa3c015e25 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -269,8 +269,7 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
engine->disable_lite_restore_wa =
- (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
(engine->id == VCS || engine->id == VCS2);
engine->ctx_desc_template = GEN8_CTX_VALID;
@@ -1068,9 +1067,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
{
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
- /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
+ /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+ if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
wa_ctx_emit(batch, index,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7a74750076c5..2faf64f9f256 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -851,15 +851,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
- /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+ /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_DG_MIRROR_FIX_ENABLE);
- /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
+ /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
GEN9_RHWO_OPTIMIZATION_DISABLE);
/*
@@ -1023,15 +1021,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
GEN8_LQSC_RO_PERF_DIS);
/* WaEnableGapsTsvCreditFix:skl */
- if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
- I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
- GEN9_GAPS_TSV_CREDIT_DISABLE));
- }
-
- /* WaDisablePowerCompilerClockGating:skl */
- if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
- WA_SET_BIT_MASKED(HIZ_CHICKEN,
- BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
+ I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+ GEN9_GAPS_TSV_CREDIT_DISABLE));
/* WaBarrierPerformanceFixDisable:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/5] drm/i915/skl: drop workarounds for C0 revision
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
2016-09-16 13:59 ` [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions Jani Nikula
@ 2016-09-16 13:59 ` Jani Nikula
2016-09-16 13:59 ` [PATCH 3/5] drm/i915/skl: drop workarounds for D0 revision Jani Nikula
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2016-09-16 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Pre-production hardware is not supported.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index acc1dbdd024e..a4e37c8db782 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -382,8 +382,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
}
/* WaC6DisallowByGfxPause*/
- if (IS_SKL_REVID(dev, 0, SKL_REVID_C0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_B0))
+ if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
if (IS_BROXTON(dev))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2faf64f9f256..474ce843de42 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -882,9 +882,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);
- /* WaDisableMaskBasedCammingInRCC:skl,bxt */
- if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
- IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+ /* WaDisableMaskBasedCammingInRCC:bxt */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/5] drm/i915/skl: drop workarounds for D0 revision
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
2016-09-16 13:59 ` [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions Jani Nikula
2016-09-16 13:59 ` [PATCH 2/5] drm/i915/skl: drop workarounds for C0 revision Jani Nikula
@ 2016-09-16 13:59 ` Jani Nikula
2016-09-16 13:59 ` [PATCH 4/5] drm/i915/skl: drop workarounds for E0 revision Jani Nikula
` (4 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2016-09-16 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Pre-production hardware is not supported.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 10 ++++------
drivers/gpu/drm/i915/intel_pm.c | 3 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++----------
3 files changed, 7 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4bfa3c015e25..e1fa76ae5642 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -994,9 +994,8 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
struct drm_i915_private *dev_priv = engine->i915;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
- /* WaDisableCtxRestoreArbitration:skl,bxt */
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+ /* WaDisableCtxRestoreArbitration:bxt */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
@@ -1095,9 +1094,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
wa_ctx_emit(batch, index, MI_NOOP);
}
- /* WaDisableCtxRestoreArbitration:skl,bxt */
- if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
+ /* WaDisableCtxRestoreArbitration:bxt */
+ if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2df06b703e3d..a860c4082eb8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5335,8 +5335,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
/* WaRsUseTimeoutMode */
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
GEN7_RC_CTL_TO_MODE |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 474ce843de42..6880082b9166 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1000,10 +1000,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
* until D0 which is the default case so this is equivalent to
* !WaDisablePerCtxtPreemptionGranularityControl:skl
*/
- if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
- I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
- _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
- }
+ I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
+ _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
@@ -1023,12 +1021,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE));
- /* WaBarrierPerformanceFixDisable:skl */
- if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FENCE_DEST_SLM_DISABLE |
- HDC_BARRIER_PERFORMANCE_DISABLE);
-
/* WaDisableSbeCacheDispatchPortSharing:skl */
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
WA_SET_BIT_MASKED(
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/5] drm/i915/skl: drop workarounds for E0 revision
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
` (2 preceding siblings ...)
2016-09-16 13:59 ` [PATCH 3/5] drm/i915/skl: drop workarounds for D0 revision Jani Nikula
@ 2016-09-16 13:59 ` Jani Nikula
2016-09-16 13:59 ` [PATCH 5/5] drm/i915/skl: drop workarounds for F0 revision Jani Nikula
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2016-09-16 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Pre-production hardware is not supported.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 5 ++---
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 --------------
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e1fa76ae5642..4bb6128dacae 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -845,13 +845,12 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
/*
- * WaDisableLSQCROPERFforOCL:skl,kbl
+ * WaDisableLSQCROPERFforOCL:kbl
* This WA is implemented in skl_init_clock_gating() but since
* this batch updates GEN8_L3SQCREG4 with default value we need to
* set this bit here to retain the WA during flush.
*/
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) ||
- IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6880082b9166..68dc27f6ba0a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1003,20 +1003,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
- /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
- I915_WRITE(FF_SLICE_CS_CHICKEN2,
- _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
- }
-
- /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
- * involving this register should also be added to WA batch as required.
- */
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
- /* WaDisableLSQCROPERFforOCL:skl */
- I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
- GEN8_LQSC_RO_PERF_DIS);
-
/* WaEnableGapsTsvCreditFix:skl */
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE));
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/5] drm/i915/skl: drop workarounds for F0 revision
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
` (3 preceding siblings ...)
2016-09-16 13:59 ` [PATCH 4/5] drm/i915/skl: drop workarounds for E0 revision Jani Nikula
@ 2016-09-16 13:59 ` Jani Nikula
2016-09-16 14:55 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: drop pre-production stepping workarounds Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2016-09-16 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Pre-production hardware is not supported.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 68dc27f6ba0a..67ea9dd5921e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1007,12 +1007,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE));
- /* WaDisableSbeCacheDispatchPortSharing:skl */
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
- WA_SET_BIT_MASKED(
- GEN7_HALF_SLICE_CHICKEN1,
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
-
/* WaDisableGafsUnitClkGating:skl */
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/skl: drop pre-production stepping workarounds
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
` (4 preceding siblings ...)
2016-09-16 13:59 ` [PATCH 5/5] drm/i915/skl: drop workarounds for F0 revision Jani Nikula
@ 2016-09-16 14:55 ` Patchwork
2016-09-22 13:24 ` [PATCH 0/5] " Paulo Zanoni
2016-09-22 13:28 ` [PATCH] drm/i915/skl: tell the user about pre-production hardware Paulo Zanoni
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2016-09-16 14:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/skl: drop pre-production stepping workarounds
URL : https://patchwork.freedesktop.org/series/12579/
State : failure
== Summary ==
Series 12579v1 drm/i915/skl: drop pre-production stepping workarounds
https://patchwork.freedesktop.org/api/1.0/series/12579/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
skip -> PASS (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-hsw-4770k)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:202 dwarn:0 dfail:0 fail:0 skip:42
fi-byt-n2820 total:244 pass:208 dwarn:0 dfail:0 fail:1 skip:35
fi-hsw-4770k total:202 pass:185 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ilk-650 total:244 pass:183 dwarn:0 dfail:0 fail:1 skip:60
fi-ivb-3520m total:244 pass:219 dwarn:0 dfail:0 fail:0 skip:25
fi-ivb-3770 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:221 dwarn:0 dfail:0 fail:1 skip:22
fi-skl-6700k total:244 pass:219 dwarn:1 dfail:0 fail:0 skip:24
fi-skl-6770hq total:244 pass:228 dwarn:1 dfail:0 fail:1 skip:14
fi-snb-2520m total:244 pass:208 dwarn:0 dfail:0 fail:0 skip:36
fi-snb-2600 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
Results at /archive/results/CI_IGT_test/Patchwork_2547/
e001a39d3a5cf1630ec4e83815794ec7ad507ef6 drm-intel-nightly: 2016y-09m-16d-11h-18m-48s UTC integration manifest
7ac19f5 drm/i915/skl: drop workarounds for F0 revision
ebcc1da drm/i915/skl: drop workarounds for E0 revision
12b16c1 drm/i915/skl: drop workarounds for D0 revision
277b193 drm/i915/skl: drop workarounds for C0 revision
0cbc8ac drm/i915/skl: drop workarounds for A0 and B0 revisions
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions
2016-09-16 13:59 ` [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions Jani Nikula
@ 2016-09-19 7:59 ` Mika Kahola
2016-09-19 8:13 ` Jani Nikula
0 siblings, 1 reply; 14+ messages in thread
From: Mika Kahola @ 2016-09-19 7:59 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On Fri, 2016-09-16 at 16:59 +0300, Jani Nikula wrote:
> Pre-production hardware is not supported.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 4 ----
> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 ---
> drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++---
> drivers/gpu/drm/i915/intel_lrc.c | 8 +++-----
> drivers/gpu/drm/i915/intel_ringbuffer.c | 21 ++++++-----------
> ----
> 5 files changed, 11 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index acd0c51f74d5..b2a9eb82ac4b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1299,10 +1299,6 @@ bool intel_dp_source_supports_hbr2(struct
> intel_dp *intel_dp)
> struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> struct drm_device *dev = dig_port->base.base.dev;
>
> - /* WaDisableHBR2:skl */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
> - return false;
> -
> if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> IS_BROADWELL(dev) ||
> (INTEL_INFO(dev)->gen >= 9))
> return true;
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index c438b02184cb..0048b520baf7 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct
> intel_dp *intel_dp)
> * Intel platforms that support HBR2 also support TPS3. TPS3
> support is
> * also mandatory for downstream devices that support HBR2.
> However, not
> * all sinks follow the spec.
> - *
> - * Due to WaDisableHBR2 SKL < B0 is the only exception where
> TPS3 is
> - * supported in source but still not enabled.
> */
> source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
> sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 6fd39efb7894..acc1dbdd024e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -375,9 +375,8 @@ static int guc_ucode_xfer(struct drm_i915_private
> *dev_priv)
> /* Enable MIA caching. GuC clock gating is disabled. */
> I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>
> - /* WaDisableMinuteIaClockGating:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + /* WaDisableMinuteIaClockGating:bxt */
> + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> I915_WRITE(GUC_SHIM_CONTROL,
> (I915_READ(GUC_SHIM_CONTROL) &
> ~GUC_ENABLE_MIA_CLOCK_
> GATING));
> }
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 251143361f31..4bfa3c015e25 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -269,8 +269,7 @@ logical_ring_init_platform_invariants(struct
> intel_engine_cs *engine)
> struct drm_i915_private *dev_priv = engine->i915;
>
> engine->disable_lite_restore_wa =
> - (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
> (engine->id == VCS || engine->id == VCS2);
>
> engine->ctx_desc_template = GEN8_CTX_VALID;
> @@ -1068,9 +1067,8 @@ static int gen9_init_perctx_bb(struct
> intel_engine_cs *engine,
> {
> uint32_t index = wa_ctx_start(wa_ctx, *offset,
> CACHELINE_DWORDS);
>
> - /*
> WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt
> */
> + if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
> wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> wa_ctx_emit_reg(batch, index,
> GEN9_SLICE_COMMON_ECO_CHICKEN0);
> wa_ctx_emit(batch, index,
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 7a74750076c5..2faf64f9f256 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -851,15 +851,13 @@ static int gen9_init_workarounds(struct
> intel_engine_cs *engine)
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>
> - /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
> - if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> GEN9_DG_MIRROR_FIX_ENABLE);
>
> - /*
> WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt
> */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> GEN9_RHWO_OPTIMIZATION_DISABLE);
> /*
> @@ -1023,15 +1021,8 @@ static int skl_init_workarounds(struct
> intel_engine_cs *engine)
> GEN8_LQSC_RO_PERF_DIS);
>
> /* WaEnableGapsTsvCreditFix:skl */
> - if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
This seems to be related to revision C0 rather than A0 or B0. Maybe we
should move this part to the patch that handles C0 revision?
> - I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL)
> |
> - GEN9_GAPS_TSV_CREDIT_DISA
> BLE));
> - }
> -
> - /* WaDisablePowerCompilerClockGating:skl */
> - if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
> - WA_SET_BIT_MASKED(HIZ_CHICKEN,
> - BDW_HIZ_POWER_COMPILER_CLOCK_GATIN
> G_DISABLE);
> + I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> + GEN9_GAPS_TSV_CREDIT_DISABLE));
>
> /* WaBarrierPerformanceFixDisable:skl */
> if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
--
Mika Kahola - Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions
2016-09-19 7:59 ` Mika Kahola
@ 2016-09-19 8:13 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2016-09-19 8:13 UTC (permalink / raw)
To: mika.kahola, intel-gfx
On Mon, 19 Sep 2016, Mika Kahola <mika.kahola@intel.com> wrote:
> On Fri, 2016-09-16 at 16:59 +0300, Jani Nikula wrote:
>> Pre-production hardware is not supported.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 4 ----
>> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 ---
>> drivers/gpu/drm/i915/intel_guc_loader.c | 5 ++---
>> drivers/gpu/drm/i915/intel_lrc.c | 8 +++-----
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 21 ++++++-----------
>> ----
>> 5 files changed, 11 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index acd0c51f74d5..b2a9eb82ac4b 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1299,10 +1299,6 @@ bool intel_dp_source_supports_hbr2(struct
>> intel_dp *intel_dp)
>> struct intel_digital_port *dig_port =
>> dp_to_dig_port(intel_dp);
>> struct drm_device *dev = dig_port->base.base.dev;
>>
>> - /* WaDisableHBR2:skl */
>> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
>> - return false;
>> -
>> if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>> IS_BROADWELL(dev) ||
>> (INTEL_INFO(dev)->gen >= 9))
>> return true;
>> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
>> b/drivers/gpu/drm/i915/intel_dp_link_training.c
>> index c438b02184cb..0048b520baf7 100644
>> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
>> @@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct
>> intel_dp *intel_dp)
>> * Intel platforms that support HBR2 also support TPS3. TPS3
>> support is
>> * also mandatory for downstream devices that support HBR2.
>> However, not
>> * all sinks follow the spec.
>> - *
>> - * Due to WaDisableHBR2 SKL < B0 is the only exception where
>> TPS3 is
>> - * supported in source but still not enabled.
>> */
>> source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
>> sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 6fd39efb7894..acc1dbdd024e 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -375,9 +375,8 @@ static int guc_ucode_xfer(struct drm_i915_private
>> *dev_priv)
>> /* Enable MIA caching. GuC clock gating is disabled. */
>> I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>>
>> - /* WaDisableMinuteIaClockGating:skl,bxt */
>> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
>> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
>> + /* WaDisableMinuteIaClockGating:bxt */
>> + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
>> I915_WRITE(GUC_SHIM_CONTROL,
>> (I915_READ(GUC_SHIM_CONTROL) &
>> ~GUC_ENABLE_MIA_CLOCK_
>> GATING));
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
>> b/drivers/gpu/drm/i915/intel_lrc.c
>> index 251143361f31..4bfa3c015e25 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -269,8 +269,7 @@ logical_ring_init_platform_invariants(struct
>> intel_engine_cs *engine)
>> struct drm_i915_private *dev_priv = engine->i915;
>>
>> engine->disable_lite_restore_wa =
>> - (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
>> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
>> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
>> (engine->id == VCS || engine->id == VCS2);
>>
>> engine->ctx_desc_template = GEN8_CTX_VALID;
>> @@ -1068,9 +1067,8 @@ static int gen9_init_perctx_bb(struct
>> intel_engine_cs *engine,
>> {
>> uint32_t index = wa_ctx_start(wa_ctx, *offset,
>> CACHELINE_DWORDS);
>>
>> - /*
>> WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
>> - if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
>> - IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
>> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt
>> */
>> + if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
>> wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
>> wa_ctx_emit_reg(batch, index,
>> GEN9_SLICE_COMMON_ECO_CHICKEN0);
>> wa_ctx_emit(batch, index,
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 7a74750076c5..2faf64f9f256 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -851,15 +851,13 @@ static int gen9_init_workarounds(struct
>> intel_engine_cs *engine)
>> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>> GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>>
>> - /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
>> - if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
>> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
>> + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
>> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
>> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
>> GEN9_DG_MIRROR_FIX_ENABLE);
>>
>> - /*
>> WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
>> - if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
>> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
>> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt
>> */
>> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
>> WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
>> GEN9_RHWO_OPTIMIZATION_DISABLE);
>> /*
>> @@ -1023,15 +1021,8 @@ static int skl_init_workarounds(struct
>> intel_engine_cs *engine)
>> GEN8_LQSC_RO_PERF_DIS);
>>
>> /* WaEnableGapsTsvCreditFix:skl */
>> - if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
> This seems to be related to revision C0 rather than A0 or B0. Maybe we
> should move this part to the patch that handles C0 revision?
Nope, this is about A0 and B0. This check is not needed when we don't
care about A0 or B0.
BR,
Jani.
>
>> - I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL)
>> |
>> - GEN9_GAPS_TSV_CREDIT_DISA
>> BLE));
>> - }
>> -
>> - /* WaDisablePowerCompilerClockGating:skl */
>> - if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
>> - WA_SET_BIT_MASKED(HIZ_CHICKEN,
>> - BDW_HIZ_POWER_COMPILER_CLOCK_GATIN
>> G_DISABLE);
>> + I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
>> + GEN9_GAPS_TSV_CREDIT_DISABLE));
>>
>> /* WaBarrierPerformanceFixDisable:skl */
>> if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
` (5 preceding siblings ...)
2016-09-16 14:55 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: drop pre-production stepping workarounds Patchwork
@ 2016-09-22 13:24 ` Paulo Zanoni
2016-09-22 15:19 ` Sarvela, Tomi P
2016-09-26 12:10 ` Jani Nikula
2016-09-22 13:28 ` [PATCH] drm/i915/skl: tell the user about pre-production hardware Paulo Zanoni
7 siblings, 2 replies; 14+ messages in thread
From: Paulo Zanoni @ 2016-09-22 13:24 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: jani.saarinen
Em Sex, 2016-09-16 às 16:59 +0300, Jani Nikula escreveu:
> Only production steppings are supported, drop workarounds for
> anything
> else. The series is split by revision so we can bikeshed if there are
> steppings some people still need to use for some reason.
Bikeshed: in patches 2 and 3 you could have added platform tags to the
workaround tags, while also adding the missing space to a
/* comment*/.
Jani S., Yann: perhaps we could try to check if our CI/QA systems still
have these machines? Just "lspci -nn | grep VGA" on the SKL systems and
check whether rev <= 5.
If we conclude our CI system doesn't include these machines:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> BR,
> Jani.
>
> Jani Nikula (5):
> drm/i915/skl: drop workarounds for A0 and B0 revisions
> drm/i915/skl: drop workarounds for C0 revision
> drm/i915/skl: drop workarounds for D0 revision
> drm/i915/skl: drop workarounds for E0 revision
> drm/i915/skl: drop workarounds for F0 revision
>
> drivers/gpu/drm/i915/intel_dp.c | 4 --
> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 --
> drivers/gpu/drm/i915/intel_guc_loader.c | 8 ++--
> drivers/gpu/drm/i915/intel_lrc.c | 23 +++++------
> drivers/gpu/drm/i915/intel_pm.c | 3 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 58 +++++----------
> ------------
> 6 files changed, 23 insertions(+), 76 deletions(-)
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] drm/i915/skl: tell the user about pre-production hardware
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
` (6 preceding siblings ...)
2016-09-22 13:24 ` [PATCH 0/5] " Paulo Zanoni
@ 2016-09-22 13:28 ` Paulo Zanoni
7 siblings, 0 replies; 14+ messages in thread
From: Paulo Zanoni @ 2016-09-22 13:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
We just removed the implementation for all the pre-production
workarounds, so now tell the user that we expect his machine to not
work properly. Also convert this to DRM_ERROR so we can more easily
spot these problems in bug reports and CI/QA runs.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bfb2efd..9c15432 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -771,6 +771,19 @@ static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
destroy_workqueue(dev_priv->wq);
}
+/*
+ * We don't keep the workarounds for pre-production hardware, so we expect our
+ * driver to fail on these machines in one way or another. A little warning on
+ * dmesg may help both the user and the bug triagers.
+ */
+static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
+{
+ if (IS_HSW_EARLY_SDV(dev_priv) ||
+ IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
+ DRM_ERROR("This is a pre-production stepping. "
+ "It may not be fully functional.\n");
+}
+
/**
* i915_driver_init_early - setup state not requiring device access
* @dev_priv: device private
@@ -838,13 +851,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
intel_device_info_dump(dev_priv);
- /* Not all pre-production machines fall into this category, only the
- * very first ones. Almost everything should work, except for maybe
- * suspend/resume. And we don't implement workarounds that affect only
- * pre-production machines. */
- if (IS_HSW_EARLY_SDV(dev_priv))
- DRM_INFO("This is an early pre-production Haswell machine. "
- "It may not be fully functional.\n");
+ intel_detect_preproduction_hw(dev_priv);
return 0;
--
2.7.4
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds
2016-09-22 13:24 ` [PATCH 0/5] " Paulo Zanoni
@ 2016-09-22 15:19 ` Sarvela, Tomi P
2016-09-22 17:11 ` Argotti, Yann
2016-09-26 12:10 ` Jani Nikula
1 sibling, 1 reply; 14+ messages in thread
From: Sarvela, Tomi P @ 2016-09-22 15:19 UTC (permalink / raw)
To: Zanoni, Paulo R, Nikula, Jani, intel-gfx; +Cc: Saarinen, Jani
> From: Zanoni, Paulo R
> Em Sex, 2016-09-16 às 16:59 +0300, Jani Nikula escreveu:
> > Only production steppings are supported, drop workarounds for
> > anything
> > else. The series is split by revision so we can bikeshed if there are
> > steppings some people still need to use for some reason.
>
> Bikeshed: in patches 2 and 3 you could have added platform tags to the
> workaround tags, while also adding the missing space to a
> /* comment*/.
>
> Jani S., Yann: perhaps we could try to check if our CI/QA systems still
> have these machines? Just "lspci -nn | grep VGA" on the SKL systems and
> check whether rev <= 5.
The CI system doesn't have any pre-production SKL machines. They were dropped as soon as we got production machines.
Tomi
> If we conclude our CI system doesn't include these machines:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Jani Nikula (5):
> > drm/i915/skl: drop workarounds for A0 and B0 revisions
> > drm/i915/skl: drop workarounds for C0 revision
> > drm/i915/skl: drop workarounds for D0 revision
> > drm/i915/skl: drop workarounds for E0 revision
> > drm/i915/skl: drop workarounds for F0 revision
> >
> > drivers/gpu/drm/i915/intel_dp.c | 4 --
> > drivers/gpu/drm/i915/intel_dp_link_training.c | 3 --
> > drivers/gpu/drm/i915/intel_guc_loader.c | 8 ++--
> > drivers/gpu/drm/i915/intel_lrc.c | 23 +++++------
> > drivers/gpu/drm/i915/intel_pm.c | 3 +-
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 58 +++++----------
> > ------------
> > 6 files changed, 23 insertions(+), 76 deletions(-)
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds
2016-09-22 15:19 ` Sarvela, Tomi P
@ 2016-09-22 17:11 ` Argotti, Yann
0 siblings, 0 replies; 14+ messages in thread
From: Argotti, Yann @ 2016-09-22 17:11 UTC (permalink / raw)
To: Sarvela, Tomi P, Zanoni, Paulo R, Nikula, Jani, intel-gfx; +Cc: Saarinen, Jani
>
> > From: Zanoni, Paulo R
> > Em Sex, 2016-09-16 às 16:59 +0300, Jani Nikula escreveu:
> > > Only production steppings are supported, drop workarounds for
> > > anything else. The series is split by revision so we can bikeshed if
> > > there are steppings some people still need to use for some reason.
> >
> > Bikeshed: in patches 2 and 3 you could have added platform tags to the
> > workaround tags, while also adding the missing space to a
> > /* comment*/.
> >
> > Jani S., Yann: perhaps we could try to check if our CI/QA systems
> > still have these machines? Just "lspci -nn | grep VGA" on the SKL
> > systems and check whether rev <= 5.
>
> The CI system doesn't have any pre-production SKL machines. They were
> dropped as soon as we got production machines.
On QA side, we have mainly switched to production machines here and remaining RVP is > 5.
Yann
>
> Tomi
>
> > If we conclude our CI system doesn't include these machines:
> > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> > > Jani Nikula (5):
> > > drm/i915/skl: drop workarounds for A0 and B0 revisions
> > > drm/i915/skl: drop workarounds for C0 revision
> > > drm/i915/skl: drop workarounds for D0 revision
> > > drm/i915/skl: drop workarounds for E0 revision
> > > drm/i915/skl: drop workarounds for F0 revision
> > >
> > > drivers/gpu/drm/i915/intel_dp.c | 4 --
> > > drivers/gpu/drm/i915/intel_dp_link_training.c | 3 --
> > > drivers/gpu/drm/i915/intel_guc_loader.c | 8 ++--
> > > drivers/gpu/drm/i915/intel_lrc.c | 23 +++++------
> > > drivers/gpu/drm/i915/intel_pm.c | 3 +-
> > > drivers/gpu/drm/i915/intel_ringbuffer.c | 58 +++++----------
> > > ------------
> > > 6 files changed, 23 insertions(+), 76 deletions(-)
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds
2016-09-22 13:24 ` [PATCH 0/5] " Paulo Zanoni
2016-09-22 15:19 ` Sarvela, Tomi P
@ 2016-09-26 12:10 ` Jani Nikula
1 sibling, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2016-09-26 12:10 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: jani.saarinen
On Thu, 22 Sep 2016, Paulo Zanoni <paulo.r.zanoni@intel.com> wrote:
> Em Sex, 2016-09-16 às 16:59 +0300, Jani Nikula escreveu:
>> Only production steppings are supported, drop workarounds for
>> anything
>> else. The series is split by revision so we can bikeshed if there are
>> steppings some people still need to use for some reason.
>
> Bikeshed: in patches 2 and 3 you could have added platform tags to the
> workaround tags, while also adding the missing space to a
> /* comment*/.
>
> Jani S., Yann: perhaps we could try to check if our CI/QA systems still
> have these machines? Just "lspci -nn | grep VGA" on the SKL systems and
> check whether rev <= 5.
>
> If we conclude our CI system doesn't include these machines:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Pushed patches 1-5, thanks for the review, and sent a separate patch to
address the bikesheds [1], along with a resend of your pre-production
hardware warning patch [2].
BR,
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/1474891672-23414-1-git-send-email-jani.nikula@intel.com
[2] http://patchwork.freedesktop.org/patch/msgid/1474891672-23414-2-git-send-email-jani.nikula@intel.com
>
>>
>> BR,
>> Jani.
>>
>> Jani Nikula (5):
>> drm/i915/skl: drop workarounds for A0 and B0 revisions
>> drm/i915/skl: drop workarounds for C0 revision
>> drm/i915/skl: drop workarounds for D0 revision
>> drm/i915/skl: drop workarounds for E0 revision
>> drm/i915/skl: drop workarounds for F0 revision
>>
>> drivers/gpu/drm/i915/intel_dp.c | 4 --
>> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 --
>> drivers/gpu/drm/i915/intel_guc_loader.c | 8 ++--
>> drivers/gpu/drm/i915/intel_lrc.c | 23 +++++------
>> drivers/gpu/drm/i915/intel_pm.c | 3 +-
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 58 +++++----------
>> ------------
>> 6 files changed, 23 insertions(+), 76 deletions(-)
>>
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2016-09-26 12:10 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-16 13:59 [PATCH 0/5] drm/i915/skl: drop pre-production stepping workarounds Jani Nikula
2016-09-16 13:59 ` [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions Jani Nikula
2016-09-19 7:59 ` Mika Kahola
2016-09-19 8:13 ` Jani Nikula
2016-09-16 13:59 ` [PATCH 2/5] drm/i915/skl: drop workarounds for C0 revision Jani Nikula
2016-09-16 13:59 ` [PATCH 3/5] drm/i915/skl: drop workarounds for D0 revision Jani Nikula
2016-09-16 13:59 ` [PATCH 4/5] drm/i915/skl: drop workarounds for E0 revision Jani Nikula
2016-09-16 13:59 ` [PATCH 5/5] drm/i915/skl: drop workarounds for F0 revision Jani Nikula
2016-09-16 14:55 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: drop pre-production stepping workarounds Patchwork
2016-09-22 13:24 ` [PATCH 0/5] " Paulo Zanoni
2016-09-22 15:19 ` Sarvela, Tomi P
2016-09-22 17:11 ` Argotti, Yann
2016-09-26 12:10 ` Jani Nikula
2016-09-22 13:28 ` [PATCH] drm/i915/skl: tell the user about pre-production hardware Paulo Zanoni
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