* [PATCH 00/10] drm/i915: add display uncore helpers
@ 2019-12-02 16:00 ` Jani Nikula
0 siblings, 0 replies; 37+ messages in thread
From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Actual v1 after the RFC https://patchwork.freedesktop.org/series/68713/
Get rid of I915_READ_FW() and I915_WRITE_FW() as part of this series.
BR,
Jani.
Jani Nikula (10):
drm/i915/gvt: use intel uncore functions for forcewake register access
drm/i915/debugfs: use intel uncore functions for forcewake register
access
drm/i915/dmc: use intel uncore functions for forcewake register access
drm/i915: add display engine uncore helpers
drm/i915/display: use intel de functions for forcewake register access
drm/i915/irq: use intel de functions for forcewake register access
drm/i915/gmbus: use intel de functions for forcewake register access
drm/i915/sprite: use intel de functions for forcewake register access
drm/i915/pm: use intel de functions for forcewake register access
drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros
drivers/gpu/drm/i915/display/intel_de.h | 72 ++++
drivers/gpu/drm/i915/display/intel_display.c | 79 +++--
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.c | 74 ++--
drivers/gpu/drm/i915/display/intel_sprite.c | 322 ++++++++++--------
drivers/gpu/drm/i915/gvt/mmio_context.c | 19 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 9 +-
drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 43 ---
drivers/gpu/drm/i915/i915_irq.c | 22 +-
drivers/gpu/drm/i915/intel_csr.c | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 7 +-
12 files changed, 371 insertions(+), 294 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_de.h
--
2.20.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 37+ messages in thread* [Intel-gfx] [PATCH 00/10] drm/i915: add display uncore helpers @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Actual v1 after the RFC https://patchwork.freedesktop.org/series/68713/ Get rid of I915_READ_FW() and I915_WRITE_FW() as part of this series. BR, Jani. Jani Nikula (10): drm/i915/gvt: use intel uncore functions for forcewake register access drm/i915/debugfs: use intel uncore functions for forcewake register access drm/i915/dmc: use intel uncore functions for forcewake register access drm/i915: add display engine uncore helpers drm/i915/display: use intel de functions for forcewake register access drm/i915/irq: use intel de functions for forcewake register access drm/i915/gmbus: use intel de functions for forcewake register access drm/i915/sprite: use intel de functions for forcewake register access drm/i915/pm: use intel de functions for forcewake register access drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros drivers/gpu/drm/i915/display/intel_de.h | 72 ++++ drivers/gpu/drm/i915/display/intel_display.c | 79 +++-- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_gmbus.c | 74 ++-- drivers/gpu/drm/i915/display/intel_sprite.c | 322 ++++++++++-------- drivers/gpu/drm/i915/gvt/mmio_context.c | 19 +- drivers/gpu/drm/i915/gvt/scheduler.c | 9 +- drivers/gpu/drm/i915/i915_debugfs.c | 14 +- drivers/gpu/drm/i915/i915_drv.h | 43 --- drivers/gpu/drm/i915/i915_irq.c | 22 +- drivers/gpu/drm/i915/intel_csr.c | 3 +- drivers/gpu/drm/i915/intel_pm.c | 7 +- 12 files changed, 371 insertions(+), 294 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_de.h -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, intel-gvt-dev Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. No functional changes. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Cc: intel-gvt-dev@lists.freedesktop.org Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/gvt/mmio_context.c | 19 ++++++++++++------- drivers/gpu/drm/i915/gvt/scheduler.c | 9 ++++++--- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index aaf15916d29a..7c76e7871beb 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -175,7 +175,8 @@ static void load_render_mocs(struct drm_i915_private *dev_priv) offset.reg = regs[ring_id]; for (i = 0; i < GEN9_MOCS_SIZE; i++) { gen9_render_mocs.control_table[ring_id][i] = - I915_READ_FW(offset); + intel_uncore_read_fw(&dev_priv->uncore, + offset); offset.reg += 4; } } @@ -183,7 +184,7 @@ static void load_render_mocs(struct drm_i915_private *dev_priv) offset.reg = 0xb020; for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { gen9_render_mocs.l3cc_table[i] = - I915_READ_FW(offset); + intel_uncore_read_fw(&dev_priv->uncore, offset); offset.reg += 4; } gen9_render_mocs.initialized = true; @@ -427,7 +428,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, new_v = gen9_render_mocs.control_table[ring_id][i]; if (old_v != new_v) - I915_WRITE_FW(offset, new_v); + intel_uncore_write_fw(&dev_priv->uncore, offset, + new_v); offset.reg += 4; } @@ -445,7 +447,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, new_v = gen9_render_mocs.l3cc_table[i]; if (old_v != new_v) - I915_WRITE_FW(l3_offset, new_v); + intel_uncore_write_fw(&dev_priv->uncore, + l3_offset, new_v); l3_offset.reg += 4; } @@ -492,13 +495,15 @@ static void switch_mmio(struct intel_vgpu *pre, // save if (pre) { - vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg); + vgpu_vreg_t(pre, mmio->reg) = intel_uncore_read_fw(&dev_priv->uncore, + mmio->reg); if (mmio->mask) vgpu_vreg_t(pre, mmio->reg) &= ~(mmio->mask << 16); old_v = vgpu_vreg_t(pre, mmio->reg); } else - old_v = mmio->value = I915_READ_FW(mmio->reg); + old_v = mmio->value = intel_uncore_read_fw(&dev_priv->uncore, + mmio->reg); // restore if (next) { @@ -526,7 +531,7 @@ static void switch_mmio(struct intel_vgpu *pre, new_v = mmio->value; } - I915_WRITE_FW(mmio->reg, new_v); + intel_uncore_write_fw(&dev_priv->uncore, mmio->reg, new_v); trace_render_mmio(pre ? pre->id : 0, next ? next->id : 0, diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 5b2a7d072ec9..e7a2c76fcdce 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -217,11 +217,14 @@ static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id) i915_reg_t reg; reg = RING_INSTDONE(ring_base); - vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore, + reg); reg = RING_ACTHD(ring_base); - vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore, + reg); reg = RING_ACTHD_UDW(ring_base); - vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore, + reg); } static int shadow_context_status_change(struct notifier_block *nb, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, intel-gvt-dev Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. No functional changes. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Cc: intel-gvt-dev@lists.freedesktop.org Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/gvt/mmio_context.c | 19 ++++++++++++------- drivers/gpu/drm/i915/gvt/scheduler.c | 9 ++++++--- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index aaf15916d29a..7c76e7871beb 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -175,7 +175,8 @@ static void load_render_mocs(struct drm_i915_private *dev_priv) offset.reg = regs[ring_id]; for (i = 0; i < GEN9_MOCS_SIZE; i++) { gen9_render_mocs.control_table[ring_id][i] = - I915_READ_FW(offset); + intel_uncore_read_fw(&dev_priv->uncore, + offset); offset.reg += 4; } } @@ -183,7 +184,7 @@ static void load_render_mocs(struct drm_i915_private *dev_priv) offset.reg = 0xb020; for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { gen9_render_mocs.l3cc_table[i] = - I915_READ_FW(offset); + intel_uncore_read_fw(&dev_priv->uncore, offset); offset.reg += 4; } gen9_render_mocs.initialized = true; @@ -427,7 +428,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, new_v = gen9_render_mocs.control_table[ring_id][i]; if (old_v != new_v) - I915_WRITE_FW(offset, new_v); + intel_uncore_write_fw(&dev_priv->uncore, offset, + new_v); offset.reg += 4; } @@ -445,7 +447,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, new_v = gen9_render_mocs.l3cc_table[i]; if (old_v != new_v) - I915_WRITE_FW(l3_offset, new_v); + intel_uncore_write_fw(&dev_priv->uncore, + l3_offset, new_v); l3_offset.reg += 4; } @@ -492,13 +495,15 @@ static void switch_mmio(struct intel_vgpu *pre, // save if (pre) { - vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg); + vgpu_vreg_t(pre, mmio->reg) = intel_uncore_read_fw(&dev_priv->uncore, + mmio->reg); if (mmio->mask) vgpu_vreg_t(pre, mmio->reg) &= ~(mmio->mask << 16); old_v = vgpu_vreg_t(pre, mmio->reg); } else - old_v = mmio->value = I915_READ_FW(mmio->reg); + old_v = mmio->value = intel_uncore_read_fw(&dev_priv->uncore, + mmio->reg); // restore if (next) { @@ -526,7 +531,7 @@ static void switch_mmio(struct intel_vgpu *pre, new_v = mmio->value; } - I915_WRITE_FW(mmio->reg, new_v); + intel_uncore_write_fw(&dev_priv->uncore, mmio->reg, new_v); trace_render_mmio(pre ? pre->id : 0, next ? next->id : 0, diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 5b2a7d072ec9..e7a2c76fcdce 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -217,11 +217,14 @@ static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id) i915_reg_t reg; reg = RING_INSTDONE(ring_base); - vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore, + reg); reg = RING_ACTHD(ring_base); - vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore, + reg); reg = RING_ACTHD_UDW(ring_base); - vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); + vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore, + reg); } static int shadow_context_status_change(struct notifier_block *nb, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access @ 2019-12-02 16:06 ` Chris Wilson 0 siblings, 0 replies; 37+ messages in thread From: Chris Wilson @ 2019-12-02 16:06 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, intel-gvt-dev Quoting Jani Nikula (2019-12-02 16:00:49) > Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using > intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. I've a patch to switch gvt over to using gt->uncore, gt->engines etc. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access @ 2019-12-02 16:06 ` Chris Wilson 0 siblings, 0 replies; 37+ messages in thread From: Chris Wilson @ 2019-12-02 16:06 UTC (permalink / raw) To: Jani Nikula, intel-gfx; +Cc: jani.nikula, intel-gvt-dev Quoting Jani Nikula (2019-12-02 16:00:49) > Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using > intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. I've a patch to switch gvt over to using gt->uncore, gt->engines etc. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access 2019-12-02 16:06 ` [Intel-gfx] " Chris Wilson (?) @ 2020-01-17 14:36 ` Jani Nikula 2020-01-17 14:47 ` Chris Wilson -1 siblings, 1 reply; 37+ messages in thread From: Jani Nikula @ 2020-01-17 14:36 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: intel-gvt-dev On Mon, 02 Dec 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote: > Quoting Jani Nikula (2019-12-02 16:00:49) >> Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using >> intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. > > I've a patch to switch gvt over to using gt->uncore, gt->engines etc. Have you posted this? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access 2020-01-17 14:36 ` Jani Nikula @ 2020-01-17 14:47 ` Chris Wilson 2020-01-17 14:50 ` Chris Wilson 0 siblings, 1 reply; 37+ messages in thread From: Chris Wilson @ 2020-01-17 14:47 UTC (permalink / raw) To: Jani Nikula, intel-gfx; +Cc: intel-gvt-dev Quoting Jani Nikula (2020-01-17 14:36:26) > On Mon, 02 Dec 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Quoting Jani Nikula (2019-12-02 16:00:49) > >> Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using > >> intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. > > > > I've a patch to switch gvt over to using gt->uncore, gt->engines etc. > > Have you posted this? A few months ago, https://patchwork.freedesktop.org/patch/336201/?series=68117&rev=1 -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access 2020-01-17 14:47 ` Chris Wilson @ 2020-01-17 14:50 ` Chris Wilson 0 siblings, 0 replies; 37+ messages in thread From: Chris Wilson @ 2020-01-17 14:50 UTC (permalink / raw) To: Jani Nikula, intel-gfx; +Cc: intel-gvt-dev Quoting Chris Wilson (2020-01-17 14:47:13) > Quoting Jani Nikula (2020-01-17 14:36:26) > > On Mon, 02 Dec 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > > Quoting Jani Nikula (2019-12-02 16:00:49) > > >> Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using > > >> intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. > > > > > > I've a patch to switch gvt over to using gt->uncore, gt->engines etc. > > > > Have you posted this? > > A few months ago, > https://patchwork.freedesktop.org/patch/336201/?series=68117&rev=1 There's a second for "drm/i915/gvt: Wean gvt off using dev_priv" that does the uncore migration after that. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 02/10] drm/i915/debugfs: use intel uncore functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. No functional changes. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index cab632791f73..42709a57b475 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1128,7 +1128,8 @@ static int gen6_drpc_info(struct seq_file *m) u32 gt_core_status, rcctl1, rc6vids = 0; u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; - gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); + gt_core_status = intel_uncore_read_fw(&dev_priv->uncore, + GEN6_GT_CORE_STATUS); trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); rcctl1 = I915_READ(GEN6_RC_CONTROL); @@ -1674,10 +1675,13 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) u32 rpdown, rpdownei; intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); - rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; - rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; - rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; - rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; + rpup = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; + rpupei = intel_uncore_read_fw(&dev_priv->uncore, + GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; + rpdown = intel_uncore_read_fw(&dev_priv->uncore, + GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; + rpdownei = intel_uncore_read_fw(&dev_priv->uncore, + GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 02/10] drm/i915/debugfs: use intel uncore functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. No functional changes. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index cab632791f73..42709a57b475 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1128,7 +1128,8 @@ static int gen6_drpc_info(struct seq_file *m) u32 gt_core_status, rcctl1, rc6vids = 0; u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; - gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); + gt_core_status = intel_uncore_read_fw(&dev_priv->uncore, + GEN6_GT_CORE_STATUS); trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); rcctl1 = I915_READ(GEN6_RC_CONTROL); @@ -1674,10 +1675,13 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) u32 rpdown, rpdownei; intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); - rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; - rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; - rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; - rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; + rpup = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; + rpupei = intel_uncore_read_fw(&dev_priv->uncore, + GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; + rpdown = intel_uncore_read_fw(&dev_priv->uncore, + GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; + rpdownei = intel_uncore_read_fw(&dev_priv->uncore, + GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH 02/10] drm/i915/debugfs: use intel uncore functions for forcewake register access @ 2019-12-02 16:14 ` Chris Wilson 0 siblings, 0 replies; 37+ messages in thread From: Chris Wilson @ 2019-12-02 16:14 UTC (permalink / raw) To: intel-gfx, Andi Shyti; +Cc: jani.nikula Quoting Jani Nikula (2019-12-02 16:00:50) > Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using > intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. > > No functional changes. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index cab632791f73..42709a57b475 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1128,7 +1128,8 @@ static int gen6_drpc_info(struct seq_file *m) > u32 gt_core_status, rcctl1, rc6vids = 0; > u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; > > - gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); > + gt_core_status = intel_uncore_read_fw(&dev_priv->uncore, > + GEN6_GT_CORE_STATUS); > trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); > > rcctl1 = I915_READ(GEN6_RC_CONTROL); > @@ -1674,10 +1675,13 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) > u32 rpdown, rpdownei; > > intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); > - rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; > - rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; > - rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; > - rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; > + rpup = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; > + rpupei = intel_uncore_read_fw(&dev_priv->uncore, > + GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; > + rpdown = intel_uncore_read_fw(&dev_priv->uncore, > + GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; > + rpdownei = intel_uncore_read_fw(&dev_priv->uncore, > + GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; > intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); These should be moved over to a intel_rps_show() as they need gt->uncore. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 02/10] drm/i915/debugfs: use intel uncore functions for forcewake register access @ 2019-12-02 16:14 ` Chris Wilson 0 siblings, 0 replies; 37+ messages in thread From: Chris Wilson @ 2019-12-02 16:14 UTC (permalink / raw) To: Jani Nikula, intel-gfx, Andi Shyti; +Cc: jani.nikula Quoting Jani Nikula (2019-12-02 16:00:50) > Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using > intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. > > No functional changes. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index cab632791f73..42709a57b475 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1128,7 +1128,8 @@ static int gen6_drpc_info(struct seq_file *m) > u32 gt_core_status, rcctl1, rc6vids = 0; > u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; > > - gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); > + gt_core_status = intel_uncore_read_fw(&dev_priv->uncore, > + GEN6_GT_CORE_STATUS); > trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); > > rcctl1 = I915_READ(GEN6_RC_CONTROL); > @@ -1674,10 +1675,13 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) > u32 rpdown, rpdownei; > > intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); > - rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; > - rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; > - rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; > - rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; > + rpup = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; > + rpupei = intel_uncore_read_fw(&dev_priv->uncore, > + GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; > + rpdown = intel_uncore_read_fw(&dev_priv->uncore, > + GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; > + rpdownei = intel_uncore_read_fw(&dev_priv->uncore, > + GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; > intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); These should be moved over to a intel_rps_show() as they need gt->uncore. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 03/10] drm/i915/dmc: use intel uncore functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 09870a31b4f0..04d860e86237 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -313,7 +313,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) preempt_disable(); for (i = 0; i < fw_size; i++) - I915_WRITE_FW(CSR_PROGRAM(i), payload[i]); + intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i), + payload[i]); preempt_enable(); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 03/10] drm/i915/dmc: use intel uncore functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 09870a31b4f0..04d860e86237 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -313,7 +313,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) preempt_disable(); for (i = 0; i < fw_size; i++) - I915_WRITE_FW(CSR_PROGRAM(i), payload[i]); + intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i), + payload[i]); preempt_enable(); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 04/10] drm/i915: add display engine uncore helpers @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi Add convenience helpers for the most common uncore operations with struct drm_i915_private * as context rather than struct intel_uncore *. The goal is to replace all instances of I915_READ(), I915_POSTING_READ(), I915_WRITE(), I915_READ_FW(), and I915_WRITE_FW() in display/ with these, to finally be able to get rid of the implicit dev_priv local parameter use. The idea is that any non-u32 reads or writes are special enough that they can use the intel_uncore_* functions directly. v2: - rename the file intel_de.h - move intel_de_wait_for_* there too - also add de fw helpers Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_de.h | 72 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 14 ---- 3 files changed, 73 insertions(+), 14 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_de.h diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h new file mode 100644 index 000000000000..00da10bf35f5 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2019 Intel Corporation + */ + +#ifndef __INTEL_DE_H__ +#define __INTEL_DE_H__ + +#include "i915_drv.h" +#include "i915_reg.h" +#include "intel_uncore.h" + +static inline u32 +intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) +{ + return intel_uncore_read(&i915->uncore, reg); +} + +static inline void +intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) +{ + intel_uncore_posting_read(&i915->uncore, reg); +} + +/* Note: read the warnings for intel_uncore_*_fw() functions! */ +static inline u32 +intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg) +{ + return intel_uncore_read_fw(&i915->uncore, reg); +} + +static inline void +intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val) +{ + intel_uncore_write(&i915->uncore, reg, val); +} + +/* Note: read the warnings for intel_uncore_*_fw() functions! */ +static inline void +intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val) +{ + intel_uncore_write_fw(&i915->uncore, reg, val); +} + +static inline void +intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) +{ + intel_uncore_rmw(&i915->uncore, reg, clear, set); +} + +static inline int +intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, u32 value, unsigned int timeout) +{ + return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout); +} + +static inline int +intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, unsigned int timeout) +{ + return intel_de_wait_for_register(i915, reg, mask, mask, timeout); +} + +static inline int +intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, unsigned int timeout) +{ + return intel_de_wait_for_register(i915, reg, mask, 0, timeout); +} + +#endif /* __INTEL_DE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 83ea04149b77..e309fce5b198 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -44,6 +44,7 @@ #include <media/cec-notifier.h> #include "i915_drv.h" +#include "intel_de.h" struct drm_printer; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 14744c114475..9150d16235ea 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2007,20 +2007,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data, #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) -/* register wait wrappers for display regs */ -#define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \ - intel_wait_for_register(&(dev_priv_)->uncore, \ - (reg_), (mask_), (value_), (timeout_)) - -#define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \ - u32 mask__ = (mask_); \ - intel_de_wait_for_register((dev_priv_), (reg_), \ - mask__, mask__, (timeout_)); \ -}) - -#define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \ - intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_)) - /* i915_mm.c */ int remap_io_mapping(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, unsigned long size, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 04/10] drm/i915: add display engine uncore helpers @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi Add convenience helpers for the most common uncore operations with struct drm_i915_private * as context rather than struct intel_uncore *. The goal is to replace all instances of I915_READ(), I915_POSTING_READ(), I915_WRITE(), I915_READ_FW(), and I915_WRITE_FW() in display/ with these, to finally be able to get rid of the implicit dev_priv local parameter use. The idea is that any non-u32 reads or writes are special enough that they can use the intel_uncore_* functions directly. v2: - rename the file intel_de.h - move intel_de_wait_for_* there too - also add de fw helpers Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_de.h | 72 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 14 ---- 3 files changed, 73 insertions(+), 14 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_de.h diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h new file mode 100644 index 000000000000..00da10bf35f5 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2019 Intel Corporation + */ + +#ifndef __INTEL_DE_H__ +#define __INTEL_DE_H__ + +#include "i915_drv.h" +#include "i915_reg.h" +#include "intel_uncore.h" + +static inline u32 +intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) +{ + return intel_uncore_read(&i915->uncore, reg); +} + +static inline void +intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) +{ + intel_uncore_posting_read(&i915->uncore, reg); +} + +/* Note: read the warnings for intel_uncore_*_fw() functions! */ +static inline u32 +intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg) +{ + return intel_uncore_read_fw(&i915->uncore, reg); +} + +static inline void +intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val) +{ + intel_uncore_write(&i915->uncore, reg, val); +} + +/* Note: read the warnings for intel_uncore_*_fw() functions! */ +static inline void +intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val) +{ + intel_uncore_write_fw(&i915->uncore, reg, val); +} + +static inline void +intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) +{ + intel_uncore_rmw(&i915->uncore, reg, clear, set); +} + +static inline int +intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, u32 value, unsigned int timeout) +{ + return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout); +} + +static inline int +intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, unsigned int timeout) +{ + return intel_de_wait_for_register(i915, reg, mask, mask, timeout); +} + +static inline int +intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, unsigned int timeout) +{ + return intel_de_wait_for_register(i915, reg, mask, 0, timeout); +} + +#endif /* __INTEL_DE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 83ea04149b77..e309fce5b198 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -44,6 +44,7 @@ #include <media/cec-notifier.h> #include "i915_drv.h" +#include "intel_de.h" struct drm_printer; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 14744c114475..9150d16235ea 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2007,20 +2007,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data, #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) -/* register wait wrappers for display regs */ -#define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \ - intel_wait_for_register(&(dev_priv_)->uncore, \ - (reg_), (mask_), (value_), (timeout_)) - -#define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \ - u32 mask__ = (mask_); \ - intel_de_wait_for_register((dev_priv_), (reg_), \ - mask__, mask__, (timeout_)); \ -}) - -#define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \ - intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_)) - /* i915_mm.c */ int remap_io_mapping(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, unsigned long size, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 04/10] drm/i915: add display engine uncore helpers 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula (?) @ 2019-12-10 13:54 ` Joonas Lahtinen 2019-12-11 6:46 ` Jani Nikula -1 siblings, 1 reply; 37+ messages in thread From: Joonas Lahtinen @ 2019-12-10 13:54 UTC (permalink / raw) To: Jani Nikula, intel-gfx; +Cc: jani.nikula, Lucas De Marchi Quoting Jani Nikula (2019-12-02 18:00:52) > Add convenience helpers for the most common uncore operations with > struct drm_i915_private * as context rather than struct intel_uncore *. > > The goal is to replace all instances of I915_READ(), > I915_POSTING_READ(), I915_WRITE(), I915_READ_FW(), and I915_WRITE_FW() > in display/ with these, to finally be able to get rid of the implicit > dev_priv local parameter use. > > The idea is that any non-u32 reads or writes are special enough that > they can use the intel_uncore_* functions directly. > > v2: > - rename the file intel_de.h > - move intel_de_wait_for_* there too > - also add de fw helpers > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_de.h | 72 +++++++++++++++++++ > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/i915_drv.h | 14 ---- > 3 files changed, 73 insertions(+), 14 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_de.h > > diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h > new file mode 100644 > index 000000000000..00da10bf35f5 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_de.h > @@ -0,0 +1,72 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2019 Intel Corporation > + */ > + > +#ifndef __INTEL_DE_H__ > +#define __INTEL_DE_H__ > + > +#include "i915_drv.h" > +#include "i915_reg.h" > +#include "intel_uncore.h" > + > +static inline u32 > +intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) Is the plan to have struct intel_de inside i915 and then have that as the prime parameter going forward? Regards, Joonas _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 04/10] drm/i915: add display engine uncore helpers 2019-12-10 13:54 ` Joonas Lahtinen @ 2019-12-11 6:46 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-11 6:46 UTC (permalink / raw) To: Joonas Lahtinen, intel-gfx; +Cc: Lucas De Marchi On Tue, 10 Dec 2019, Joonas Lahtinen <joonas.lahtinen@linux.intel.com> wrote: > Quoting Jani Nikula (2019-12-02 18:00:52) >> Add convenience helpers for the most common uncore operations with >> struct drm_i915_private * as context rather than struct intel_uncore *. >> >> The goal is to replace all instances of I915_READ(), >> I915_POSTING_READ(), I915_WRITE(), I915_READ_FW(), and I915_WRITE_FW() >> in display/ with these, to finally be able to get rid of the implicit >> dev_priv local parameter use. >> >> The idea is that any non-u32 reads or writes are special enough that >> they can use the intel_uncore_* functions directly. >> >> v2: >> - rename the file intel_de.h >> - move intel_de_wait_for_* there too >> - also add de fw helpers >> >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_de.h | 72 +++++++++++++++++++ >> .../drm/i915/display/intel_display_types.h | 1 + >> drivers/gpu/drm/i915/i915_drv.h | 14 ---- >> 3 files changed, 73 insertions(+), 14 deletions(-) >> create mode 100644 drivers/gpu/drm/i915/display/intel_de.h >> >> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h >> new file mode 100644 >> index 000000000000..00da10bf35f5 >> --- /dev/null >> +++ b/drivers/gpu/drm/i915/display/intel_de.h >> @@ -0,0 +1,72 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Copyright © 2019 Intel Corporation >> + */ >> + >> +#ifndef __INTEL_DE_H__ >> +#define __INTEL_DE_H__ >> + >> +#include "i915_drv.h" >> +#include "i915_reg.h" >> +#include "intel_uncore.h" >> + >> +static inline u32 >> +intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) > > Is the plan to have struct intel_de inside i915 and then have that as > the prime parameter going forward? No. The plan is to keep i915 as the prime parameter for display. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 05/10] drm/i915/display: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 79 +++++++++++--------- 1 file changed, 42 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 53dc310a5f6d..3149f17a034a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3954,7 +3954,8 @@ static void i9xx_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), + plane_state->color_plane[0].stride); if (INTEL_GEN(dev_priv) < 4) { /* @@ -3962,21 +3963,26 @@ static void i9xx_update_plane(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DSPSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { - I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PRIMSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); - I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0); + intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), + (y << 16) | x); } else if (INTEL_GEN(dev_priv) >= 4) { - I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset); - I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), + linear_offset); + intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), + (y << 16) | x); } /* @@ -3984,15 +3990,13 @@ static void i9xx_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - I915_WRITE_FW(DSPADDR(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -4019,11 +4023,11 @@ static void i9xx_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); else - I915_WRITE_FW(DSPADDR(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -5805,10 +5809,10 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state) id = scaler_state->scaler_id; I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); - I915_WRITE_FW(SKL_PS_VPHASE(pipe, id), - PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - I915_WRITE_FW(SKL_PS_HPHASE(pipe, id), - PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos); I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size); } @@ -11053,17 +11057,17 @@ static void i845_update_cursor(struct intel_plane *plane, if (plane->cursor.base != base || plane->cursor.size != size || plane->cursor.cntl != cntl) { - I915_WRITE_FW(CURCNTR(PIPE_A), 0); - I915_WRITE_FW(CURBASE(PIPE_A), base); - I915_WRITE_FW(CURSIZE, size); - I915_WRITE_FW(CURPOS(PIPE_A), pos); - I915_WRITE_FW(CURCNTR(PIPE_A), cntl); + intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); + intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); + intel_de_write_fw(dev_priv, CURSIZE, size); + intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); plane->cursor.base = base; plane->cursor.size = size; plane->cursor.cntl = cntl; } else { - I915_WRITE_FW(CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -11304,17 +11308,18 @@ static void i9xx_update_cursor(struct intel_plane *plane, plane->cursor.size != fbc_ctl || plane->cursor.cntl != cntl) { if (HAS_CUR_FBC(dev_priv)) - I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); - I915_WRITE_FW(CURCNTR(pipe), cntl); - I915_WRITE_FW(CURPOS(pipe), pos); - I915_WRITE_FW(CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), + fbc_ctl); + intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); + intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURBASE(pipe), base); plane->cursor.base = base; plane->cursor.size = fbc_ctl; plane->cursor.cntl = cntl; } else { - I915_WRITE_FW(CURPOS(pipe), pos); - I915_WRITE_FW(CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURBASE(pipe), base); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 05/10] drm/i915/display: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 79 +++++++++++--------- 1 file changed, 42 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 53dc310a5f6d..3149f17a034a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3954,7 +3954,8 @@ static void i9xx_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), + plane_state->color_plane[0].stride); if (INTEL_GEN(dev_priv) < 4) { /* @@ -3962,21 +3963,26 @@ static void i9xx_update_plane(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DSPSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { - I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PRIMSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); - I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0); + intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), + (y << 16) | x); } else if (INTEL_GEN(dev_priv) >= 4) { - I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset); - I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), + linear_offset); + intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), + (y << 16) | x); } /* @@ -3984,15 +3990,13 @@ static void i9xx_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - I915_WRITE_FW(DSPADDR(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -4019,11 +4023,11 @@ static void i9xx_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); else - I915_WRITE_FW(DSPADDR(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -5805,10 +5809,10 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state) id = scaler_state->scaler_id; I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); - I915_WRITE_FW(SKL_PS_VPHASE(pipe, id), - PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - I915_WRITE_FW(SKL_PS_HPHASE(pipe, id), - PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos); I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size); } @@ -11053,17 +11057,17 @@ static void i845_update_cursor(struct intel_plane *plane, if (plane->cursor.base != base || plane->cursor.size != size || plane->cursor.cntl != cntl) { - I915_WRITE_FW(CURCNTR(PIPE_A), 0); - I915_WRITE_FW(CURBASE(PIPE_A), base); - I915_WRITE_FW(CURSIZE, size); - I915_WRITE_FW(CURPOS(PIPE_A), pos); - I915_WRITE_FW(CURCNTR(PIPE_A), cntl); + intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); + intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); + intel_de_write_fw(dev_priv, CURSIZE, size); + intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); plane->cursor.base = base; plane->cursor.size = size; plane->cursor.cntl = cntl; } else { - I915_WRITE_FW(CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -11304,17 +11308,18 @@ static void i9xx_update_cursor(struct intel_plane *plane, plane->cursor.size != fbc_ctl || plane->cursor.cntl != cntl) { if (HAS_CUR_FBC(dev_priv)) - I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); - I915_WRITE_FW(CURCNTR(pipe), cntl); - I915_WRITE_FW(CURPOS(pipe), pos); - I915_WRITE_FW(CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), + fbc_ctl); + intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); + intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURBASE(pipe), base); plane->cursor.base = base; plane->cursor.size = fbc_ctl; plane->cursor.cntl = cntl; } else { - I915_WRITE_FW(CURPOS(pipe), pos); - I915_WRITE_FW(CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURBASE(pipe), base); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 06/10] drm/i915/irq: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8b338744eddf..7cd1f5ca7fce 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -624,9 +624,9 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc) * register. */ do { - high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; - low = I915_READ_FW(low_frame); - high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; + high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; + low = intel_de_read_fw(dev_priv, low_frame); + high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; } while (high1 != high2); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -683,15 +683,17 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) * pipe frame time stamp. The time stamp value * is sampled at every start of vertical blank. */ - scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); + scan_prev_time = intel_de_read_fw(dev_priv, + PIPE_FRMTMSTMP(crtc->pipe)); /* * The TIMESTAMP_CTR register has the current * time stamp value. */ - scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR); + scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); - scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); + scan_post_time = intel_de_read_fw(dev_priv, + PIPE_FRMTMSTMP(crtc->pipe)); } while (scan_post_time != scan_prev_time); scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, @@ -726,9 +728,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) vtotal /= 2; if (IS_GEN(dev_priv, 2)) - position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; + position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; else - position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; + position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; /* * On HSW, the DSL reg (0x70000) appears to return 0 if we @@ -747,7 +749,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) for (i = 0; i < 100; i++) { udelay(1); - temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; + temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; if (temp != position) { position = temp; break; @@ -818,7 +820,7 @@ bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int index, * We can split this into vertical and horizontal * scanout position. */ - position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; + position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; /* convert to pixel counts */ vbl_start *= htotal; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 06/10] drm/i915/irq: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8b338744eddf..7cd1f5ca7fce 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -624,9 +624,9 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc) * register. */ do { - high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; - low = I915_READ_FW(low_frame); - high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; + high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; + low = intel_de_read_fw(dev_priv, low_frame); + high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; } while (high1 != high2); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -683,15 +683,17 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) * pipe frame time stamp. The time stamp value * is sampled at every start of vertical blank. */ - scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); + scan_prev_time = intel_de_read_fw(dev_priv, + PIPE_FRMTMSTMP(crtc->pipe)); /* * The TIMESTAMP_CTR register has the current * time stamp value. */ - scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR); + scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); - scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); + scan_post_time = intel_de_read_fw(dev_priv, + PIPE_FRMTMSTMP(crtc->pipe)); } while (scan_post_time != scan_prev_time); scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, @@ -726,9 +728,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) vtotal /= 2; if (IS_GEN(dev_priv, 2)) - position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; + position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; else - position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; + position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; /* * On HSW, the DSL reg (0x70000) appears to return 0 if we @@ -747,7 +749,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) for (i = 0; i < 100; i++) { udelay(1); - temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; + temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; if (temp != position) { position = temp; break; @@ -818,7 +820,7 @@ bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int index, * We can split this into vertical and horizontal * scanout position. */ - position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; + position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; /* convert to pixel counts */ vbl_start *= htotal; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 07/10] drm/i915/gmbus: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. Also switch I915_READ() and I915_WRITE() over in this file while at it. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_gmbus.c | 74 ++++++++++------------ 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 3d4d19ac1d14..508308555dc6 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -143,8 +143,8 @@ to_intel_gmbus(struct i2c_adapter *i2c) void intel_gmbus_reset(struct drm_i915_private *dev_priv) { - I915_WRITE(GMBUS0, 0); - I915_WRITE(GMBUS4, 0); + intel_de_write(dev_priv, GMBUS0, 0); + intel_de_write(dev_priv, GMBUS4, 0); } static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -153,12 +153,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, u32 val; /* When using bit bashing for I2C, this bit needs to be set to 1 */ - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); if (!enable) val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; else val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); } static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -166,12 +166,12 @@ static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(SOUTH_DSPCLK_GATE_D); + val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); if (!enable) val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; else val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(SOUTH_DSPCLK_GATE_D, val); + intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); } static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -179,12 +179,12 @@ static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(GEN9_CLKGATE_DIS_4); + val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); if (!enable) val |= BXT_GMBUS_GATING_DIS; else val &= ~BXT_GMBUS_GATING_DIS; - I915_WRITE(GEN9_CLKGATE_DIS_4, val); + intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); } static u32 get_reserved(struct intel_gmbus *bus) @@ -337,14 +337,16 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) irq_en = 0; add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); - I915_WRITE_FW(GMBUS4, irq_en); + intel_de_write_fw(dev_priv, GMBUS4, irq_en); status |= GMBUS_SATOER; - ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); + ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, + 2); if (ret) - ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); + ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, + 50); - I915_WRITE_FW(GMBUS4, 0); + intel_de_write_fw(dev_priv, GMBUS4, 0); remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); if (gmbus2 & GMBUS_SATOER) @@ -366,13 +368,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) irq_enable = GMBUS_IDLE_EN; add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); - I915_WRITE_FW(GMBUS4, irq_enable); + intel_de_write_fw(dev_priv, GMBUS4, irq_enable); ret = intel_wait_for_register_fw(&dev_priv->uncore, GMBUS2, GMBUS_ACTIVE, 0, 10); - I915_WRITE_FW(GMBUS4, 0); + intel_de_write_fw(dev_priv, GMBUS4, 0); remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); return ret; @@ -404,15 +406,12 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, len++; } size = len % 256 + 256; - I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); + intel_de_write_fw(dev_priv, GMBUS0, + gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); } - I915_WRITE_FW(GMBUS1, - gmbus1_index | - GMBUS_CYCLE_WAIT | - (size << GMBUS_BYTE_COUNT_SHIFT) | - (addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_READ | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS1, + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); while (len) { int ret; u32 val, loop = 0; @@ -421,7 +420,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, if (ret) return ret; - val = I915_READ_FW(GMBUS3); + val = intel_de_read_fw(dev_priv, GMBUS3); do { if (extra_byte_added && len == 1) break; @@ -432,7 +431,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, if (burst_read && len == size - 4) /* Reset the override bit */ - I915_WRITE_FW(GMBUS0, gmbus0_reg); + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); } return 0; @@ -489,12 +488,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, len -= 1; } - I915_WRITE_FW(GMBUS3, val); - I915_WRITE_FW(GMBUS1, - gmbus1_index | GMBUS_CYCLE_WAIT | - (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | - (addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS3, val); + intel_de_write_fw(dev_priv, GMBUS1, + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); while (len) { int ret; @@ -503,7 +499,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, val |= *buf++ << (8 * loop); } while (--len && ++loop < 4); - I915_WRITE_FW(GMBUS3, val); + intel_de_write_fw(dev_priv, GMBUS3, val); ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); if (ret) @@ -568,7 +564,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, /* GMBUS5 holds 16-bit index */ if (gmbus5) - I915_WRITE_FW(GMBUS5, gmbus5); + intel_de_write_fw(dev_priv, GMBUS5, gmbus5); if (msgs[1].flags & I2C_M_RD) ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, @@ -578,7 +574,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, /* Clear GMBUS5 after each index transfer */ if (gmbus5) - I915_WRITE_FW(GMBUS5, 0); + intel_de_write_fw(dev_priv, GMBUS5, 0); return ret; } @@ -601,7 +597,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, pch_gmbus_clock_gating(dev_priv, false); retry: - I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); for (; i < num; i += inc) { inc = 1; @@ -629,7 +625,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, * a STOP on the very first cycle. To simplify the code we * unconditionally generate the STOP condition with an additional gmbus * cycle. */ - I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); /* Mark the GMBUS interface as disabled after waiting for idle. * We will re-enable it at the start of the next xfer, @@ -640,7 +636,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, adapter->name); ret = -ETIMEDOUT; } - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); ret = ret ?: i; goto out; @@ -669,9 +665,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, * of resetting the GMBUS controller and so clearing the * BUS_ERROR raised by the slave's NAK. */ - I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); - I915_WRITE_FW(GMBUS1, 0); - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); + intel_de_write_fw(dev_priv, GMBUS1, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", adapter->name, msgs[i].addr, @@ -694,7 +690,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, timeout: DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", bus->adapter.name, bus->reg0 & 0xff); - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); /* * Hardware may not support GMBUS over these pins? Try GPIO bitbanging -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 07/10] drm/i915/gmbus: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. Also switch I915_READ() and I915_WRITE() over in this file while at it. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_gmbus.c | 74 ++++++++++------------ 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 3d4d19ac1d14..508308555dc6 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -143,8 +143,8 @@ to_intel_gmbus(struct i2c_adapter *i2c) void intel_gmbus_reset(struct drm_i915_private *dev_priv) { - I915_WRITE(GMBUS0, 0); - I915_WRITE(GMBUS4, 0); + intel_de_write(dev_priv, GMBUS0, 0); + intel_de_write(dev_priv, GMBUS4, 0); } static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -153,12 +153,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, u32 val; /* When using bit bashing for I2C, this bit needs to be set to 1 */ - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); if (!enable) val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; else val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); } static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -166,12 +166,12 @@ static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(SOUTH_DSPCLK_GATE_D); + val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); if (!enable) val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; else val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(SOUTH_DSPCLK_GATE_D, val); + intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); } static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -179,12 +179,12 @@ static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(GEN9_CLKGATE_DIS_4); + val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); if (!enable) val |= BXT_GMBUS_GATING_DIS; else val &= ~BXT_GMBUS_GATING_DIS; - I915_WRITE(GEN9_CLKGATE_DIS_4, val); + intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); } static u32 get_reserved(struct intel_gmbus *bus) @@ -337,14 +337,16 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) irq_en = 0; add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); - I915_WRITE_FW(GMBUS4, irq_en); + intel_de_write_fw(dev_priv, GMBUS4, irq_en); status |= GMBUS_SATOER; - ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); + ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, + 2); if (ret) - ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); + ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, + 50); - I915_WRITE_FW(GMBUS4, 0); + intel_de_write_fw(dev_priv, GMBUS4, 0); remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); if (gmbus2 & GMBUS_SATOER) @@ -366,13 +368,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) irq_enable = GMBUS_IDLE_EN; add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); - I915_WRITE_FW(GMBUS4, irq_enable); + intel_de_write_fw(dev_priv, GMBUS4, irq_enable); ret = intel_wait_for_register_fw(&dev_priv->uncore, GMBUS2, GMBUS_ACTIVE, 0, 10); - I915_WRITE_FW(GMBUS4, 0); + intel_de_write_fw(dev_priv, GMBUS4, 0); remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); return ret; @@ -404,15 +406,12 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, len++; } size = len % 256 + 256; - I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); + intel_de_write_fw(dev_priv, GMBUS0, + gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); } - I915_WRITE_FW(GMBUS1, - gmbus1_index | - GMBUS_CYCLE_WAIT | - (size << GMBUS_BYTE_COUNT_SHIFT) | - (addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_READ | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS1, + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); while (len) { int ret; u32 val, loop = 0; @@ -421,7 +420,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, if (ret) return ret; - val = I915_READ_FW(GMBUS3); + val = intel_de_read_fw(dev_priv, GMBUS3); do { if (extra_byte_added && len == 1) break; @@ -432,7 +431,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, if (burst_read && len == size - 4) /* Reset the override bit */ - I915_WRITE_FW(GMBUS0, gmbus0_reg); + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); } return 0; @@ -489,12 +488,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, len -= 1; } - I915_WRITE_FW(GMBUS3, val); - I915_WRITE_FW(GMBUS1, - gmbus1_index | GMBUS_CYCLE_WAIT | - (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | - (addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS3, val); + intel_de_write_fw(dev_priv, GMBUS1, + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); while (len) { int ret; @@ -503,7 +499,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, val |= *buf++ << (8 * loop); } while (--len && ++loop < 4); - I915_WRITE_FW(GMBUS3, val); + intel_de_write_fw(dev_priv, GMBUS3, val); ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); if (ret) @@ -568,7 +564,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, /* GMBUS5 holds 16-bit index */ if (gmbus5) - I915_WRITE_FW(GMBUS5, gmbus5); + intel_de_write_fw(dev_priv, GMBUS5, gmbus5); if (msgs[1].flags & I2C_M_RD) ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, @@ -578,7 +574,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, /* Clear GMBUS5 after each index transfer */ if (gmbus5) - I915_WRITE_FW(GMBUS5, 0); + intel_de_write_fw(dev_priv, GMBUS5, 0); return ret; } @@ -601,7 +597,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, pch_gmbus_clock_gating(dev_priv, false); retry: - I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); for (; i < num; i += inc) { inc = 1; @@ -629,7 +625,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, * a STOP on the very first cycle. To simplify the code we * unconditionally generate the STOP condition with an additional gmbus * cycle. */ - I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); /* Mark the GMBUS interface as disabled after waiting for idle. * We will re-enable it at the start of the next xfer, @@ -640,7 +636,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, adapter->name); ret = -ETIMEDOUT; } - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); ret = ret ?: i; goto out; @@ -669,9 +665,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, * of resetting the GMBUS controller and so clearing the * BUS_ERROR raised by the slave's NAK. */ - I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); - I915_WRITE_FW(GMBUS1, 0); - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); + intel_de_write_fw(dev_priv, GMBUS1, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", adapter->name, msgs[i].addr, @@ -694,7 +690,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, timeout: DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", bus->adapter.name, bus->reg0 & 0xff); - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); /* * Hardware may not support GMBUS over these pins? Try GPIO bitbanging -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 08/10] drm/i915/sprite: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. Also switch I915_READ() and I915_WRITE() over in this file while at it. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 322 +++++++++++--------- 1 file changed, 176 insertions(+), 146 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 8394502b092d..f524b09500b1 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -434,14 +434,16 @@ skl_program_scaler(struct intel_plane *plane, uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); } - I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), - PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); - I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), - PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), - PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); - I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), + PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), + PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), + PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), + (crtc_x << 16) | crtc_y); + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), + (crtc_w << 16) | crtc_h); } /* Preoffset values for YUV to RGB Conversion */ @@ -547,28 +549,37 @@ icl_program_input_csc(struct intel_plane *plane, else csc = input_csc_matrix_lr[plane_state->hw.color_encoding]; - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) | - GOFF(csc[1])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) | - GOFF(csc[4])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) | - GOFF(csc[7])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8])); - - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), - PREOFF_YUV_TO_RGB_HI); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), + ROFF(csc[0]) | GOFF(csc[1])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), + BOFF(csc[2])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), + ROFF(csc[3]) | GOFF(csc[4])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), + BOFF(csc[5])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), + ROFF(csc[6]) | GOFF(csc[7])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), + BOFF(csc[8])); + + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), + PREOFF_YUV_TO_RGB_HI); if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), + 0); else - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), - PREOFF_YUV_TO_RGB_ME); - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), - PREOFF_YUV_TO_RGB_LO); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), + PREOFF_YUV_TO_RGB_ME); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), + PREOFF_YUV_TO_RGB_LO); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } static void @@ -621,42 +632,47 @@ skl_program_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); - I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); - I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), - (plane_state->color_plane[1].offset - surf_addr) | aux_stride); + intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride); + intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), + (src_h << 16) | src_w); + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), + (plane_state->color_plane[1].offset - surf_addr) | aux_stride); if (icl_is_hdr_plane(dev_priv, plane_id)) - I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); + intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), + plane_state->cus_ctl); if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) - I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), + plane_color_ctl); if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) icl_program_input_csc(plane, crtc_state, plane_state); skl_write_plane_wm(plane, crtc_state); - I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); - I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk); - I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax); + intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), + key->min_value); + intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk); + intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax); - I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), + (y << 16) | x); if (INTEL_GEN(dev_priv) < 11) - I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), - (plane_state->color_plane[1].y << 16) | - plane_state->color_plane[1].x); + intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + surf_addr); if (plane_state->scaler_id >= 0) skl_program_scaler(plane, crtc_state, plane_state); @@ -689,12 +705,12 @@ skl_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); if (icl_is_hdr_plane(dev_priv, plane_id)) - I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); skl_write_plane_wm(plane, crtc_state); - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -714,7 +730,7 @@ skl_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; + ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; *pipe = plane->pipe; @@ -770,23 +786,36 @@ chv_update_csc(const struct intel_plane_state *plane_state) if (!fb->format->is_yuv) return; - I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - - I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); - I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); - I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); - I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); - I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8])); - - I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0)); - I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); - I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); - - I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); - I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); - I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + + intel_de_write_fw(dev_priv, SPCSCC01(plane_id), + SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); + intel_de_write_fw(dev_priv, SPCSCC23(plane_id), + SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); + intel_de_write_fw(dev_priv, SPCSCC45(plane_id), + SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); + intel_de_write_fw(dev_priv, SPCSCC67(plane_id), + SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); + intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); + + intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), + SPCSC_IMAX(1023) | SPCSC_IMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), + SPCSC_IMAX(512) | SPCSC_IMIN(-512)); + intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id), + SPCSC_IMAX(512) | SPCSC_IMIN(-512)); + + intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); } #define SIN_0 0 @@ -825,10 +854,10 @@ vlv_update_clrc(const struct intel_plane_state *plane_state) } /* FIXME these register are single buffered :( */ - I915_WRITE_FW(SPCLRC0(pipe, plane_id), - SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); - I915_WRITE_FW(SPCLRC1(pipe, plane_id), - SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); + intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), + SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); + intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), + SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); } static void @@ -1015,10 +1044,8 @@ static void vlv_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ /* The two end points are implicit (0.0 and 1.0) */ for (i = 1; i < 8 - 1; i++) - I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1), - gamma[i] << 16 | - gamma[i] << 8 | - gamma[i]); + intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), + gamma[i] << 16 | gamma[i] << 8 | gamma[i]); } static void @@ -1051,32 +1078,37 @@ vlv_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPSTRIDE(pipe, plane_id), - plane_state->color_plane[0].stride); - I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w); - I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), + (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) chv_update_csc(plane_state); if (key->flags) { - I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value); - I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask); - I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value); + intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id), + key->min_value); + intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id), + key->channel_mask); + intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id), + key->max_value); } - I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset); - I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); + intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl); - I915_WRITE_FW(SPSURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl); + intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + sprsurf_offset); vlv_update_clrc(plane_state); vlv_update_gamma(plane_state); @@ -1095,8 +1127,8 @@ vlv_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPCNTR(pipe, plane_id), 0); - I915_WRITE_FW(SPSURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1116,7 +1148,7 @@ vlv_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; + ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; *pipe = plane->pipe; @@ -1420,19 +1452,17 @@ static void ivb_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ for (i = 0; i < 16; i++) - I915_WRITE_FW(SPRGAMC(pipe, i), - gamma[i] << 20 | - gamma[i] << 10 | - gamma[i]); - - I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]); - I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]); - I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC(pipe, i), + gamma[i] << 20 | gamma[i] << 10 | gamma[i]); + + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]); i++; - I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]); - I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]); - I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]); i++; } @@ -1472,25 +1502,27 @@ ivb_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride); - I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w); if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE_FW(SPRSCALE(pipe), sprscale); + intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale); if (key->flags) { - I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value); - I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask); - I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value); + intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value); + intel_de_write_fw(dev_priv, SPRKEYMSK(pipe), + key->channel_mask); + intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value); } /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET * register */ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x); } else { - I915_WRITE_FW(SPRLINOFF(pipe), linear_offset); - I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset); + intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x); } /* @@ -1498,9 +1530,9 @@ ivb_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(SPRCTL(pipe), sprctl); - I915_WRITE_FW(SPRSURF(pipe), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl); + intel_de_write_fw(dev_priv, SPRSURF(pipe), + intel_plane_ggtt_offset(plane_state) + sprsurf_offset); ivb_update_gamma(plane_state); @@ -1517,11 +1549,11 @@ ivb_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPRCTL(pipe), 0); + intel_de_write_fw(dev_priv, SPRCTL(pipe), 0); /* Disable the scaler */ if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE_FW(SPRSCALE(pipe), 0); - I915_WRITE_FW(SPRSURF(pipe), 0); + intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0); + intel_de_write_fw(dev_priv, SPRSURF(pipe), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1540,7 +1572,7 @@ ivb_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE; + ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE; *pipe = plane->pipe; @@ -1706,10 +1738,8 @@ static void g4x_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ /* The two end points are implicit (0.0 and 1.0) */ for (i = 1; i < 8 - 1; i++) - I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1), - gamma[i] << 16 | - gamma[i] << 8 | - gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1), + gamma[i] << 16 | gamma[i] << 8 | gamma[i]); } static void ilk_sprite_linear_gamma(u16 gamma[17]) @@ -1737,14 +1767,12 @@ static void ilk_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ for (i = 0; i < 16; i++) - I915_WRITE_FW(DVSGAMC_ILK(pipe, i), - gamma[i] << 20 | - gamma[i] << 10 | - gamma[i]); - - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]); - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]); - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i), + gamma[i] << 20 | gamma[i] << 10 | gamma[i]); + + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); i++; } @@ -1784,28 +1812,30 @@ g4x_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride); - I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); - I915_WRITE_FW(DVSSCALE(pipe), dvsscale); + intel_de_write_fw(dev_priv, DVSSTRIDE(pipe), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale); if (key->flags) { - I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value); - I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask); - I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value); + intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value); + intel_de_write_fw(dev_priv, DVSKEYMSK(pipe), + key->channel_mask); + intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value); } - I915_WRITE_FW(DVSLINOFF(pipe), linear_offset); - I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset); + intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), (y << 16) | x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DVSCNTR(pipe), dvscntr); - I915_WRITE_FW(DVSSURF(pipe), - intel_plane_ggtt_offset(plane_state) + dvssurf_offset); + intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr); + intel_de_write_fw(dev_priv, DVSSURF(pipe), + intel_plane_ggtt_offset(plane_state) + dvssurf_offset); if (IS_G4X(dev_priv)) g4x_update_gamma(plane_state); @@ -1825,10 +1855,10 @@ g4x_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DVSCNTR(pipe), 0); + intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0); /* Disable the scaler */ - I915_WRITE_FW(DVSSCALE(pipe), 0); - I915_WRITE_FW(DVSSURF(pipe), 0); + intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0); + intel_de_write_fw(dev_priv, DVSSURF(pipe), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1847,7 +1877,7 @@ g4x_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE; + ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE; *pipe = plane->pipe; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 08/10] drm/i915/sprite: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. Also switch I915_READ() and I915_WRITE() over in this file while at it. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 322 +++++++++++--------- 1 file changed, 176 insertions(+), 146 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 8394502b092d..f524b09500b1 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -434,14 +434,16 @@ skl_program_scaler(struct intel_plane *plane, uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); } - I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), - PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); - I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), - PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), - PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); - I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), + PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), + PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), + PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), + (crtc_x << 16) | crtc_y); + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), + (crtc_w << 16) | crtc_h); } /* Preoffset values for YUV to RGB Conversion */ @@ -547,28 +549,37 @@ icl_program_input_csc(struct intel_plane *plane, else csc = input_csc_matrix_lr[plane_state->hw.color_encoding]; - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) | - GOFF(csc[1])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) | - GOFF(csc[4])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) | - GOFF(csc[7])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8])); - - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), - PREOFF_YUV_TO_RGB_HI); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), + ROFF(csc[0]) | GOFF(csc[1])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), + BOFF(csc[2])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), + ROFF(csc[3]) | GOFF(csc[4])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), + BOFF(csc[5])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), + ROFF(csc[6]) | GOFF(csc[7])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), + BOFF(csc[8])); + + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), + PREOFF_YUV_TO_RGB_HI); if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), + 0); else - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), - PREOFF_YUV_TO_RGB_ME); - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), - PREOFF_YUV_TO_RGB_LO); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), + PREOFF_YUV_TO_RGB_ME); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), + PREOFF_YUV_TO_RGB_LO); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } static void @@ -621,42 +632,47 @@ skl_program_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); - I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); - I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), - (plane_state->color_plane[1].offset - surf_addr) | aux_stride); + intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride); + intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), + (src_h << 16) | src_w); + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), + (plane_state->color_plane[1].offset - surf_addr) | aux_stride); if (icl_is_hdr_plane(dev_priv, plane_id)) - I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); + intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), + plane_state->cus_ctl); if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) - I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), + plane_color_ctl); if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) icl_program_input_csc(plane, crtc_state, plane_state); skl_write_plane_wm(plane, crtc_state); - I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); - I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk); - I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax); + intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), + key->min_value); + intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk); + intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax); - I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), + (y << 16) | x); if (INTEL_GEN(dev_priv) < 11) - I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), - (plane_state->color_plane[1].y << 16) | - plane_state->color_plane[1].x); + intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + surf_addr); if (plane_state->scaler_id >= 0) skl_program_scaler(plane, crtc_state, plane_state); @@ -689,12 +705,12 @@ skl_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); if (icl_is_hdr_plane(dev_priv, plane_id)) - I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); skl_write_plane_wm(plane, crtc_state); - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -714,7 +730,7 @@ skl_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; + ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; *pipe = plane->pipe; @@ -770,23 +786,36 @@ chv_update_csc(const struct intel_plane_state *plane_state) if (!fb->format->is_yuv) return; - I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - - I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); - I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); - I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); - I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); - I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8])); - - I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0)); - I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); - I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); - - I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); - I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); - I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + + intel_de_write_fw(dev_priv, SPCSCC01(plane_id), + SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); + intel_de_write_fw(dev_priv, SPCSCC23(plane_id), + SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); + intel_de_write_fw(dev_priv, SPCSCC45(plane_id), + SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); + intel_de_write_fw(dev_priv, SPCSCC67(plane_id), + SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); + intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); + + intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), + SPCSC_IMAX(1023) | SPCSC_IMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), + SPCSC_IMAX(512) | SPCSC_IMIN(-512)); + intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id), + SPCSC_IMAX(512) | SPCSC_IMIN(-512)); + + intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); } #define SIN_0 0 @@ -825,10 +854,10 @@ vlv_update_clrc(const struct intel_plane_state *plane_state) } /* FIXME these register are single buffered :( */ - I915_WRITE_FW(SPCLRC0(pipe, plane_id), - SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); - I915_WRITE_FW(SPCLRC1(pipe, plane_id), - SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); + intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), + SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); + intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), + SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); } static void @@ -1015,10 +1044,8 @@ static void vlv_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ /* The two end points are implicit (0.0 and 1.0) */ for (i = 1; i < 8 - 1; i++) - I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1), - gamma[i] << 16 | - gamma[i] << 8 | - gamma[i]); + intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), + gamma[i] << 16 | gamma[i] << 8 | gamma[i]); } static void @@ -1051,32 +1078,37 @@ vlv_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPSTRIDE(pipe, plane_id), - plane_state->color_plane[0].stride); - I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w); - I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), + (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) chv_update_csc(plane_state); if (key->flags) { - I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value); - I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask); - I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value); + intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id), + key->min_value); + intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id), + key->channel_mask); + intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id), + key->max_value); } - I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset); - I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); + intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl); - I915_WRITE_FW(SPSURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl); + intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + sprsurf_offset); vlv_update_clrc(plane_state); vlv_update_gamma(plane_state); @@ -1095,8 +1127,8 @@ vlv_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPCNTR(pipe, plane_id), 0); - I915_WRITE_FW(SPSURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1116,7 +1148,7 @@ vlv_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; + ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; *pipe = plane->pipe; @@ -1420,19 +1452,17 @@ static void ivb_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ for (i = 0; i < 16; i++) - I915_WRITE_FW(SPRGAMC(pipe, i), - gamma[i] << 20 | - gamma[i] << 10 | - gamma[i]); - - I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]); - I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]); - I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC(pipe, i), + gamma[i] << 20 | gamma[i] << 10 | gamma[i]); + + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]); i++; - I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]); - I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]); - I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]); i++; } @@ -1472,25 +1502,27 @@ ivb_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride); - I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w); if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE_FW(SPRSCALE(pipe), sprscale); + intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale); if (key->flags) { - I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value); - I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask); - I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value); + intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value); + intel_de_write_fw(dev_priv, SPRKEYMSK(pipe), + key->channel_mask); + intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value); } /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET * register */ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x); } else { - I915_WRITE_FW(SPRLINOFF(pipe), linear_offset); - I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset); + intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x); } /* @@ -1498,9 +1530,9 @@ ivb_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(SPRCTL(pipe), sprctl); - I915_WRITE_FW(SPRSURF(pipe), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl); + intel_de_write_fw(dev_priv, SPRSURF(pipe), + intel_plane_ggtt_offset(plane_state) + sprsurf_offset); ivb_update_gamma(plane_state); @@ -1517,11 +1549,11 @@ ivb_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPRCTL(pipe), 0); + intel_de_write_fw(dev_priv, SPRCTL(pipe), 0); /* Disable the scaler */ if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE_FW(SPRSCALE(pipe), 0); - I915_WRITE_FW(SPRSURF(pipe), 0); + intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0); + intel_de_write_fw(dev_priv, SPRSURF(pipe), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1540,7 +1572,7 @@ ivb_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE; + ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE; *pipe = plane->pipe; @@ -1706,10 +1738,8 @@ static void g4x_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ /* The two end points are implicit (0.0 and 1.0) */ for (i = 1; i < 8 - 1; i++) - I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1), - gamma[i] << 16 | - gamma[i] << 8 | - gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1), + gamma[i] << 16 | gamma[i] << 8 | gamma[i]); } static void ilk_sprite_linear_gamma(u16 gamma[17]) @@ -1737,14 +1767,12 @@ static void ilk_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ for (i = 0; i < 16; i++) - I915_WRITE_FW(DVSGAMC_ILK(pipe, i), - gamma[i] << 20 | - gamma[i] << 10 | - gamma[i]); - - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]); - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]); - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i), + gamma[i] << 20 | gamma[i] << 10 | gamma[i]); + + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); i++; } @@ -1784,28 +1812,30 @@ g4x_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride); - I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); - I915_WRITE_FW(DVSSCALE(pipe), dvsscale); + intel_de_write_fw(dev_priv, DVSSTRIDE(pipe), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale); if (key->flags) { - I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value); - I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask); - I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value); + intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value); + intel_de_write_fw(dev_priv, DVSKEYMSK(pipe), + key->channel_mask); + intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value); } - I915_WRITE_FW(DVSLINOFF(pipe), linear_offset); - I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset); + intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), (y << 16) | x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DVSCNTR(pipe), dvscntr); - I915_WRITE_FW(DVSSURF(pipe), - intel_plane_ggtt_offset(plane_state) + dvssurf_offset); + intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr); + intel_de_write_fw(dev_priv, DVSSURF(pipe), + intel_plane_ggtt_offset(plane_state) + dvssurf_offset); if (IS_G4X(dev_priv)) g4x_update_gamma(plane_state); @@ -1825,10 +1855,10 @@ g4x_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DVSCNTR(pipe), 0); + intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0); /* Disable the scaler */ - I915_WRITE_FW(DVSSCALE(pipe), 0); - I915_WRITE_FW(DVSSURF(pipe), 0); + intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0); + intel_de_write_fw(dev_priv, DVSSURF(pipe), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1847,7 +1877,7 @@ g4x_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE; + ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE; *pipe = plane->pipe; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 09/10] drm/i915/pm: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index dfd0b8caabde..afd0821ab17f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5011,9 +5011,10 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, const struct skl_ddb_entry *entry) { if (entry->end) - I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start); + intel_de_write_fw(dev_priv, reg, + (entry->end - 1) << 16 | entry->start); else - I915_WRITE_FW(reg, 0); + intel_de_write_fw(dev_priv, reg, 0); } static void skl_write_wm_level(struct drm_i915_private *dev_priv, @@ -5029,7 +5030,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv, val |= level->plane_res_b; val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; - I915_WRITE_FW(reg, val); + intel_de_write_fw(dev_priv, reg, val); } void skl_write_plane_wm(struct intel_plane *plane, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 09/10] drm/i915/pm: use intel de functions for forcewake register access @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index dfd0b8caabde..afd0821ab17f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5011,9 +5011,10 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, const struct skl_ddb_entry *entry) { if (entry->end) - I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start); + intel_de_write_fw(dev_priv, reg, + (entry->end - 1) << 16 | entry->start); else - I915_WRITE_FW(reg, 0); + intel_de_write_fw(dev_priv, reg, 0); } static void skl_write_wm_level(struct drm_i915_private *dev_priv, @@ -5029,7 +5030,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv, val |= level->plane_res_b; val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; - I915_WRITE_FW(reg, val); + intel_de_write_fw(dev_priv, reg, val); } void skl_write_plane_wm(struct intel_plane *plane, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 10/10] drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula We've transitioned all users to either specific intel de uncore functions or the more generic intel uncore functions. Remove the macros. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9150d16235ea..2d19c577c02d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1978,35 +1978,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data, #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) -/* These are untraced mmio-accessors that are only valid to be used inside - * critical sections, such as inside IRQ handlers, where forcewake is explicitly - * controlled. - * - * Think twice, and think again, before using these. - * - * As an example, these accessors can possibly be used between: - * - * spin_lock_irq(&dev_priv->uncore.lock); - * intel_uncore_forcewake_get__locked(); - * - * and - * - * intel_uncore_forcewake_put__locked(); - * spin_unlock_irq(&dev_priv->uncore.lock); - * - * - * Note: some registers may not need forcewake held, so - * intel_uncore_forcewake_{get,put} can be omitted, see - * intel_uncore_forcewake_for_reg(). - * - * Certain architectures will die if the same cacheline is concurrently accessed - * by different clients (e.g. on Ivybridge). Access to registers should - * therefore generally be serialised, by either the dev_priv->uncore.lock or - * a more localised lock guarding all access to that bank of registers. - */ -#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) -#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) - /* i915_mm.c */ int remap_io_mapping(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, unsigned long size, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 10/10] drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros @ 2019-12-02 16:00 ` Jani Nikula 0 siblings, 0 replies; 37+ messages in thread From: Jani Nikula @ 2019-12-02 16:00 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula We've transitioned all users to either specific intel de uncore functions or the more generic intel uncore functions. Remove the macros. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9150d16235ea..2d19c577c02d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1978,35 +1978,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data, #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) -/* These are untraced mmio-accessors that are only valid to be used inside - * critical sections, such as inside IRQ handlers, where forcewake is explicitly - * controlled. - * - * Think twice, and think again, before using these. - * - * As an example, these accessors can possibly be used between: - * - * spin_lock_irq(&dev_priv->uncore.lock); - * intel_uncore_forcewake_get__locked(); - * - * and - * - * intel_uncore_forcewake_put__locked(); - * spin_unlock_irq(&dev_priv->uncore.lock); - * - * - * Note: some registers may not need forcewake held, so - * intel_uncore_forcewake_{get,put} can be omitted, see - * intel_uncore_forcewake_for_reg(). - * - * Certain architectures will die if the same cacheline is concurrently accessed - * by different clients (e.g. on Ivybridge). Access to registers should - * therefore generally be serialised, by either the dev_priv->uncore.lock or - * a more localised lock guarding all access to that bank of registers. - */ -#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) -#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) - /* i915_mm.c */ int remap_io_mapping(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, unsigned long size, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 37+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add display uncore helpers @ 2019-12-02 17:29 ` Patchwork 0 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2019-12-02 17:29 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: add display uncore helpers URL : https://patchwork.freedesktop.org/series/70298/ State : warning == Summary == $ dim checkpatch origin/drm-tip aa62137b3200 drm/i915/gvt: use intel uncore functions for forcewake register access -:66: ERROR:CODE_INDENT: code indent should use tabs where possible #66: FILE: drivers/gpu/drm/i915/gvt/mmio_context.c:499: +^I^I^I^I^I^I^I^I mmio->reg);$ -:66: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #66: FILE: drivers/gpu/drm/i915/gvt/mmio_context.c:499: + vgpu_vreg_t(pre, mmio->reg) = intel_uncore_read_fw(&dev_priv->uncore, + mmio->reg); -:73: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #73: FILE: drivers/gpu/drm/i915/gvt/mmio_context.c:505: + old_v = mmio->value = intel_uncore_read_fw(&dev_priv->uncore, total: 1 errors, 0 warnings, 2 checks, 77 lines checked 726cf8776bad drm/i915/debugfs: use intel uncore functions for forcewake register access 33c73c270802 drm/i915/dmc: use intel uncore functions for forcewake register access e6d3be1b2221 drm/i915: add display engine uncore helpers -:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 99 lines checked bc24ff104c6a drm/i915/display: use intel de functions for forcewake register access 9af777404acc drm/i915/irq: use intel de functions for forcewake register access -:79: WARNING:LONG_LINE: line over 100 characters #79: FILE: drivers/gpu/drm/i915/i915_irq.c:823: + position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; total: 0 errors, 1 warnings, 0 checks, 59 lines checked 180f3b87f219 drm/i915/gmbus: use intel de functions for forcewake register access -:129: WARNING:LONG_LINE: line over 100 characters #129: FILE: drivers/gpu/drm/i915/display/intel_gmbus.c:414: + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); -:163: WARNING:LONG_LINE: line over 100 characters #163: FILE: drivers/gpu/drm/i915/display/intel_gmbus.c:493: + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); total: 0 errors, 2 warnings, 0 checks, 205 lines checked b4fbec26c2bf drm/i915/sprite: use intel de functions for forcewake register access -:152: WARNING:LONG_LINE: line over 100 characters #152: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:666: + (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); total: 0 errors, 1 warnings, 0 checks, 509 lines checked 9db3c03d508b drm/i915/pm: use intel de functions for forcewake register access 0afb72393e86 drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add display uncore helpers @ 2019-12-02 17:29 ` Patchwork 0 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2019-12-02 17:29 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: add display uncore helpers URL : https://patchwork.freedesktop.org/series/70298/ State : warning == Summary == $ dim checkpatch origin/drm-tip aa62137b3200 drm/i915/gvt: use intel uncore functions for forcewake register access -:66: ERROR:CODE_INDENT: code indent should use tabs where possible #66: FILE: drivers/gpu/drm/i915/gvt/mmio_context.c:499: +^I^I^I^I^I^I^I^I mmio->reg);$ -:66: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #66: FILE: drivers/gpu/drm/i915/gvt/mmio_context.c:499: + vgpu_vreg_t(pre, mmio->reg) = intel_uncore_read_fw(&dev_priv->uncore, + mmio->reg); -:73: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #73: FILE: drivers/gpu/drm/i915/gvt/mmio_context.c:505: + old_v = mmio->value = intel_uncore_read_fw(&dev_priv->uncore, total: 1 errors, 0 warnings, 2 checks, 77 lines checked 726cf8776bad drm/i915/debugfs: use intel uncore functions for forcewake register access 33c73c270802 drm/i915/dmc: use intel uncore functions for forcewake register access e6d3be1b2221 drm/i915: add display engine uncore helpers -:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 99 lines checked bc24ff104c6a drm/i915/display: use intel de functions for forcewake register access 9af777404acc drm/i915/irq: use intel de functions for forcewake register access -:79: WARNING:LONG_LINE: line over 100 characters #79: FILE: drivers/gpu/drm/i915/i915_irq.c:823: + position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; total: 0 errors, 1 warnings, 0 checks, 59 lines checked 180f3b87f219 drm/i915/gmbus: use intel de functions for forcewake register access -:129: WARNING:LONG_LINE: line over 100 characters #129: FILE: drivers/gpu/drm/i915/display/intel_gmbus.c:414: + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); -:163: WARNING:LONG_LINE: line over 100 characters #163: FILE: drivers/gpu/drm/i915/display/intel_gmbus.c:493: + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); total: 0 errors, 2 warnings, 0 checks, 205 lines checked b4fbec26c2bf drm/i915/sprite: use intel de functions for forcewake register access -:152: WARNING:LONG_LINE: line over 100 characters #152: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:666: + (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); total: 0 errors, 1 warnings, 0 checks, 509 lines checked 9db3c03d508b drm/i915/pm: use intel de functions for forcewake register access 0afb72393e86 drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: add display uncore helpers @ 2019-12-02 18:00 ` Patchwork 0 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2019-12-02 18:00 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: add display uncore helpers URL : https://patchwork.freedesktop.org/series/70298/ State : success == Summary == CI Bug Log - changes from CI_DRM_7462 -> Patchwork_15539 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/index.html Known issues ------------ Here are the changes found in Patchwork_15539 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2] ([i915#694]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html #### Possible fixes #### * igt@i915_pm_backlight@basic-brightness: - fi-icl-dsi: [DMESG-WARN][3] ([i915#109]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-icl-dsi/igt@i915_pm_backlight@basic-brightness.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-icl-dsi/igt@i915_pm_backlight@basic-brightness.html * igt@i915_selftest@live_gem_contexts: - fi-skl-lmem: [INCOMPLETE][5] ([i915#424]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html #### Warnings #### * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-x1275: [DMESG-WARN][7] ([fdo#107139] / [i915#62] / [i915#92]) -> [DMESG-WARN][8] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 45) ------------------------------ Additional (1): fi-byt-n2820 Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7462 -> Patchwork_15539 CI-20190529: 20190529 CI_DRM_7462: 35a543255ac51154b9bcc5505779548dcde95971 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15539: 0afb72393e8605481729f9c8b24a6758805cddd1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0afb72393e86 drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros 9db3c03d508b drm/i915/pm: use intel de functions for forcewake register access b4fbec26c2bf drm/i915/sprite: use intel de functions for forcewake register access 180f3b87f219 drm/i915/gmbus: use intel de functions for forcewake register access 9af777404acc drm/i915/irq: use intel de functions for forcewake register access bc24ff104c6a drm/i915/display: use intel de functions for forcewake register access e6d3be1b2221 drm/i915: add display engine uncore helpers 33c73c270802 drm/i915/dmc: use intel uncore functions for forcewake register access 726cf8776bad drm/i915/debugfs: use intel uncore functions for forcewake register access aa62137b3200 drm/i915/gvt: use intel uncore functions for forcewake register access == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add display uncore helpers @ 2019-12-02 18:00 ` Patchwork 0 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2019-12-02 18:00 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: add display uncore helpers URL : https://patchwork.freedesktop.org/series/70298/ State : success == Summary == CI Bug Log - changes from CI_DRM_7462 -> Patchwork_15539 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/index.html Known issues ------------ Here are the changes found in Patchwork_15539 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2] ([i915#694]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html #### Possible fixes #### * igt@i915_pm_backlight@basic-brightness: - fi-icl-dsi: [DMESG-WARN][3] ([i915#109]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-icl-dsi/igt@i915_pm_backlight@basic-brightness.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-icl-dsi/igt@i915_pm_backlight@basic-brightness.html * igt@i915_selftest@live_gem_contexts: - fi-skl-lmem: [INCOMPLETE][5] ([i915#424]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html #### Warnings #### * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-x1275: [DMESG-WARN][7] ([fdo#107139] / [i915#62] / [i915#92]) -> [DMESG-WARN][8] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 45) ------------------------------ Additional (1): fi-byt-n2820 Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7462 -> Patchwork_15539 CI-20190529: 20190529 CI_DRM_7462: 35a543255ac51154b9bcc5505779548dcde95971 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15539: 0afb72393e8605481729f9c8b24a6758805cddd1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0afb72393e86 drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros 9db3c03d508b drm/i915/pm: use intel de functions for forcewake register access b4fbec26c2bf drm/i915/sprite: use intel de functions for forcewake register access 180f3b87f219 drm/i915/gmbus: use intel de functions for forcewake register access 9af777404acc drm/i915/irq: use intel de functions for forcewake register access bc24ff104c6a drm/i915/display: use intel de functions for forcewake register access e6d3be1b2221 drm/i915: add display engine uncore helpers 33c73c270802 drm/i915/dmc: use intel uncore functions for forcewake register access 726cf8776bad drm/i915/debugfs: use intel uncore functions for forcewake register access aa62137b3200 drm/i915/gvt: use intel uncore functions for forcewake register access == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: add display uncore helpers @ 2019-12-02 21:58 ` Patchwork 0 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2019-12-02 21:58 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: add display uncore helpers URL : https://patchwork.freedesktop.org/series/70298/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7462_full -> Patchwork_15539_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15539_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15539_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15539_full: ### IGT changes ### #### Possible regressions #### * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled: - shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl6/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl2/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: - shard-tglb: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html Known issues ------------ Here are the changes found in Patchwork_15539_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@vcs1-dirty-switch: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276] / [fdo#112080]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-switch.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb5/igt@gem_ctx_isolation@vcs1-dirty-switch.html * igt@gem_ctx_persistence@processes: - shard-skl: [PASS][6] -> [FAIL][7] ([i915#570]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl6/igt@gem_ctx_persistence@processes.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl5/igt@gem_ctx_persistence@processes.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +7 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb5/igt@gem_exec_parallel@vcs1-fds.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb6/igt@gem_exec_schedule@out-order-bsd2.html * igt@gem_exec_schedule@preempt-queue-chain-vebox: - shard-tglb: [PASS][12] -> [INCOMPLETE][13] ([fdo#111677]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb2/igt@gem_exec_schedule@preempt-queue-chain-vebox.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb2/igt@gem_exec_schedule@preempt-queue-chain-vebox.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive: - shard-kbl: [PASS][14] -> [INCOMPLETE][15] ([fdo#103665] / [i915#530] / [i915#640]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl7/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-hsw: [PASS][16] -> [TIMEOUT][17] ([i915#530]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_sync@basic-store-all: - shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#472]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb5/igt@gem_sync@basic-store-all.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb6/igt@gem_sync@basic-store-all.html * igt@kms_color@pipe-b-ctm-0-75: - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#109]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl4/igt@kms_color@pipe-b-ctm-0-75.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl7/igt@kms_color@pipe-b-ctm-0-75.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][22] -> [DMESG-WARN][23] ([i915#180]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic: - shard-hsw: [PASS][24] -> [SKIP][25] ([fdo#109271]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html * igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled: - shard-iclb: [PASS][26] -> [INCOMPLETE][27] ([i915#140]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb1/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][28] -> [FAIL][29] ([i915#79]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@plain-flip-fb-recreate: - shard-skl: [PASS][30] -> [FAIL][31] ([i915#34]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl2/igt@kms_flip@plain-flip-fb-recreate.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl9/igt@kms_flip@plain-flip-fb-recreate.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][32] -> [FAIL][33] ([i915#49]) +2 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-tglb: [PASS][34] -> [INCOMPLETE][35] ([i915#474]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-tglb: [PASS][36] -> [INCOMPLETE][37] ([i915#456] / [i915#460] / [i915#474]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-suspend.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render: - shard-tglb: [PASS][38] -> [FAIL][39] ([i915#49]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][40] -> [INCOMPLETE][41] ([i915#123] / [i915#140]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt: - shard-tglb: [PASS][42] -> [INCOMPLETE][43] ([fdo#112393] / [i915#435]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_plane@pixel-format-pipe-a-planes: - shard-skl: [PASS][44] -> [INCOMPLETE][45] ([fdo#112347] / [i915#648]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl8/igt@kms_plane@pixel-format-pipe-a-planes.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl4/igt@kms_plane@pixel-format-pipe-a-planes.html * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: [PASS][46] -> [INCOMPLETE][47] ([i915#648]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl7/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl10/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html * igt@kms_plane@pixel-format-pipe-b-planes: - shard-skl: [PASS][48] -> [INCOMPLETE][49] ([fdo#112391] / [i915#648]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl1/igt@kms_plane@pixel-format-pipe-b-planes.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl3/igt@kms_plane@pixel-format-pipe-b-planes.html - shard-kbl: [PASS][50] -> [INCOMPLETE][51] ([fdo#103665]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl2/igt@kms_plane@pixel-format-pipe-b-planes.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: [PASS][52] -> [INCOMPLETE][53] ([fdo#112347] / [fdo#112391] / [i915#648]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][54] -> [DMESG-WARN][55] ([i915#180]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][56] -> [FAIL][57] ([fdo#108145] / [i915#265]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][58] -> [SKIP][59] ([fdo#109441]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb6/igt@kms_psr@psr2_sprite_render.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [PASS][60] -> [INCOMPLETE][61] ([i915#69]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt@kms_vblank@pipe-d-ts-continuation-suspend: - shard-tglb: [PASS][62] -> [INCOMPLETE][63] ([i915#460]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb6/igt@kms_vblank@pipe-d-ts-continuation-suspend.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb5/igt@kms_vblank@pipe-d-ts-continuation-suspend.html #### Possible fixes #### * {igt@gem_exec_balancer@bonded-chain}: - shard-iclb: [FAIL][64] ([i915#669]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@gem_exec_balancer@bonded-chain.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb8/igt@gem_exec_balancer@bonded-chain.html * igt@gem_exec_balancer@smoke: - shard-tglb: [INCOMPLETE][66] ([fdo#111593]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb7/igt@gem_exec_balancer@smoke.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb3/igt@gem_exec_balancer@smoke.html * igt@gem_exec_parallel@vecs0-contexts: - shard-hsw: [FAIL][68] ([i915#676]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw4/igt@gem_exec_parallel@vecs0-contexts.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw2/igt@gem_exec_parallel@vecs0-contexts.html * igt@gem_exec_schedule@preempt-queue-chain-bsd1: - shard-tglb: [INCOMPLETE][70] ([fdo#111606] / [fdo#111677]) -> [PASS][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd1.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb2/igt@gem_exec_schedule@preempt-queue-chain-bsd1.html * igt@gem_exec_schedule@preempt-queue-vebox: - shard-tglb: [INCOMPLETE][72] ([fdo#111677]) -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb1/igt@gem_exec_schedule@preempt-queue-vebox.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [SKIP][74] ([fdo#112146]) -> [PASS][75] +3 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive: - shard-hsw: [TIMEOUT][76] ([i915#530]) -> [PASS][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-kbl: [FAIL][78] ([i915#520]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_wait@basic-await-all: - shard-skl: [DMESG-WARN][80] ([i915#109]) -> [PASS][81] +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl9/igt@gem_wait@basic-await-all.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl6/igt@gem_wait@basic-await-all.html * igt@kms_big_fb@x-tiled-32bpp-rotate-0: - shard-skl: [INCOMPLETE][82] ([fdo#112347]) -> [PASS][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl5/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl3/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [SKIP][84] ([fdo#109271]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html * igt@kms_draw_crc@draw-method-rgb565-blt-ytiled: - shard-skl: [INCOMPLETE][86] -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl3/igt@kms_draw_crc@draw-method-rgb565-blt-ytiled.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl6/igt@kms_draw_crc@draw-method-rgb565-blt-ytiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [FAIL][88] ([i915#49]) -> [PASS][89] +2 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-tglb: [INCOMPLETE][90] ([i915#474]) -> [PASS][91] +1 similar issue [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render: - shard-tglb: [FAIL][92] ([i915#49]) -> [PASS][93] +2 similar issues [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move: - shard-iclb: [INCOMPLETE][94] ([i915#123] / [i915#140]) -> [PASS][95] [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-kbl: [INCOMPLETE][96] ([fdo#103665] / [i915#435]) -> [PASS][97] [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [DMESG-WARN][98] ([i915#180]) -> [PASS][99] +2 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [DMESG-WARN][100] ([i915#180]) -> [PASS][101] +2 similar issues [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][102] ([fdo#108145] / [i915#265]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_suspend: - shard-tglb: [DMESG-WARN][104] ([i915#402]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb6/igt@kms_psr@psr2_suspend.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb5/igt@kms_psr@psr2_suspend.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-tglb: [INCOMPLETE][106] ([i915#456] / [i915#460]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb9/igt@kms_vblank@pipe-c-ts-continuation-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593 [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606 [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347 [fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391 [fdo#112393]: https://bugs.freedesktop.org/show_bug.cgi?id=112393 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435 [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460 [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472 [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520 [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530 [i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570 [i915#640]: https://gitlab.freedesktop.org/drm/intel/issues/640 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#669]: https://gitlab.freedesktop.org/drm/intel/issues/669 [i915#676]: https://gitlab.freedesktop.org/drm/intel/issues/676 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7462 -> Patchwork_15539 CI-20190529: 20190529 CI_DRM_7462: 35a543255ac51154b9bcc5505779548dcde95971 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15539: 0afb72393e8605481729f9c8b24a6758805cddd1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: add display uncore helpers @ 2019-12-02 21:58 ` Patchwork 0 siblings, 0 replies; 37+ messages in thread From: Patchwork @ 2019-12-02 21:58 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: add display uncore helpers URL : https://patchwork.freedesktop.org/series/70298/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7462_full -> Patchwork_15539_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15539_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15539_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15539_full: ### IGT changes ### #### Possible regressions #### * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled: - shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl6/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl2/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: - shard-tglb: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html Known issues ------------ Here are the changes found in Patchwork_15539_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@vcs1-dirty-switch: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276] / [fdo#112080]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-switch.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb5/igt@gem_ctx_isolation@vcs1-dirty-switch.html * igt@gem_ctx_persistence@processes: - shard-skl: [PASS][6] -> [FAIL][7] ([i915#570]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl6/igt@gem_ctx_persistence@processes.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl5/igt@gem_ctx_persistence@processes.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +7 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb5/igt@gem_exec_parallel@vcs1-fds.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb6/igt@gem_exec_schedule@out-order-bsd2.html * igt@gem_exec_schedule@preempt-queue-chain-vebox: - shard-tglb: [PASS][12] -> [INCOMPLETE][13] ([fdo#111677]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb2/igt@gem_exec_schedule@preempt-queue-chain-vebox.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb2/igt@gem_exec_schedule@preempt-queue-chain-vebox.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive: - shard-kbl: [PASS][14] -> [INCOMPLETE][15] ([fdo#103665] / [i915#530] / [i915#640]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl7/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-hsw: [PASS][16] -> [TIMEOUT][17] ([i915#530]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_sync@basic-store-all: - shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#472]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb5/igt@gem_sync@basic-store-all.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb6/igt@gem_sync@basic-store-all.html * igt@kms_color@pipe-b-ctm-0-75: - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#109]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl4/igt@kms_color@pipe-b-ctm-0-75.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl7/igt@kms_color@pipe-b-ctm-0-75.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][22] -> [DMESG-WARN][23] ([i915#180]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic: - shard-hsw: [PASS][24] -> [SKIP][25] ([fdo#109271]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html * igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled: - shard-iclb: [PASS][26] -> [INCOMPLETE][27] ([i915#140]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb1/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][28] -> [FAIL][29] ([i915#79]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@plain-flip-fb-recreate: - shard-skl: [PASS][30] -> [FAIL][31] ([i915#34]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl2/igt@kms_flip@plain-flip-fb-recreate.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl9/igt@kms_flip@plain-flip-fb-recreate.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][32] -> [FAIL][33] ([i915#49]) +2 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-tglb: [PASS][34] -> [INCOMPLETE][35] ([i915#474]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-tglb: [PASS][36] -> [INCOMPLETE][37] ([i915#456] / [i915#460] / [i915#474]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-suspend.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render: - shard-tglb: [PASS][38] -> [FAIL][39] ([i915#49]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][40] -> [INCOMPLETE][41] ([i915#123] / [i915#140]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt: - shard-tglb: [PASS][42] -> [INCOMPLETE][43] ([fdo#112393] / [i915#435]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_plane@pixel-format-pipe-a-planes: - shard-skl: [PASS][44] -> [INCOMPLETE][45] ([fdo#112347] / [i915#648]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl8/igt@kms_plane@pixel-format-pipe-a-planes.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl4/igt@kms_plane@pixel-format-pipe-a-planes.html * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: [PASS][46] -> [INCOMPLETE][47] ([i915#648]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl7/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl10/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html * igt@kms_plane@pixel-format-pipe-b-planes: - shard-skl: [PASS][48] -> [INCOMPLETE][49] ([fdo#112391] / [i915#648]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl1/igt@kms_plane@pixel-format-pipe-b-planes.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl3/igt@kms_plane@pixel-format-pipe-b-planes.html - shard-kbl: [PASS][50] -> [INCOMPLETE][51] ([fdo#103665]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl2/igt@kms_plane@pixel-format-pipe-b-planes.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: [PASS][52] -> [INCOMPLETE][53] ([fdo#112347] / [fdo#112391] / [i915#648]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][54] -> [DMESG-WARN][55] ([i915#180]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][56] -> [FAIL][57] ([fdo#108145] / [i915#265]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][58] -> [SKIP][59] ([fdo#109441]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb6/igt@kms_psr@psr2_sprite_render.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [PASS][60] -> [INCOMPLETE][61] ([i915#69]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt@kms_vblank@pipe-d-ts-continuation-suspend: - shard-tglb: [PASS][62] -> [INCOMPLETE][63] ([i915#460]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb6/igt@kms_vblank@pipe-d-ts-continuation-suspend.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb5/igt@kms_vblank@pipe-d-ts-continuation-suspend.html #### Possible fixes #### * {igt@gem_exec_balancer@bonded-chain}: - shard-iclb: [FAIL][64] ([i915#669]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@gem_exec_balancer@bonded-chain.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb8/igt@gem_exec_balancer@bonded-chain.html * igt@gem_exec_balancer@smoke: - shard-tglb: [INCOMPLETE][66] ([fdo#111593]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb7/igt@gem_exec_balancer@smoke.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb3/igt@gem_exec_balancer@smoke.html * igt@gem_exec_parallel@vecs0-contexts: - shard-hsw: [FAIL][68] ([i915#676]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw4/igt@gem_exec_parallel@vecs0-contexts.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw2/igt@gem_exec_parallel@vecs0-contexts.html * igt@gem_exec_schedule@preempt-queue-chain-bsd1: - shard-tglb: [INCOMPLETE][70] ([fdo#111606] / [fdo#111677]) -> [PASS][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd1.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb2/igt@gem_exec_schedule@preempt-queue-chain-bsd1.html * igt@gem_exec_schedule@preempt-queue-vebox: - shard-tglb: [INCOMPLETE][72] ([fdo#111677]) -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb1/igt@gem_exec_schedule@preempt-queue-vebox.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [SKIP][74] ([fdo#112146]) -> [PASS][75] +3 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive: - shard-hsw: [TIMEOUT][76] ([i915#530]) -> [PASS][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-kbl: [FAIL][78] ([i915#520]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_wait@basic-await-all: - shard-skl: [DMESG-WARN][80] ([i915#109]) -> [PASS][81] +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl9/igt@gem_wait@basic-await-all.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl6/igt@gem_wait@basic-await-all.html * igt@kms_big_fb@x-tiled-32bpp-rotate-0: - shard-skl: [INCOMPLETE][82] ([fdo#112347]) -> [PASS][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl5/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl3/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [SKIP][84] ([fdo#109271]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html * igt@kms_draw_crc@draw-method-rgb565-blt-ytiled: - shard-skl: [INCOMPLETE][86] -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl3/igt@kms_draw_crc@draw-method-rgb565-blt-ytiled.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl6/igt@kms_draw_crc@draw-method-rgb565-blt-ytiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [FAIL][88] ([i915#49]) -> [PASS][89] +2 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-tglb: [INCOMPLETE][90] ([i915#474]) -> [PASS][91] +1 similar issue [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render: - shard-tglb: [FAIL][92] ([i915#49]) -> [PASS][93] +2 similar issues [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move: - shard-iclb: [INCOMPLETE][94] ([i915#123] / [i915#140]) -> [PASS][95] [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-iclb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-kbl: [INCOMPLETE][96] ([fdo#103665] / [i915#435]) -> [PASS][97] [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [DMESG-WARN][98] ([i915#180]) -> [PASS][99] +2 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [DMESG-WARN][100] ([i915#180]) -> [PASS][101] +2 similar issues [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][102] ([fdo#108145] / [i915#265]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_suspend: - shard-tglb: [DMESG-WARN][104] ([i915#402]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb6/igt@kms_psr@psr2_suspend.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb5/igt@kms_psr@psr2_suspend.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-tglb: [INCOMPLETE][106] ([i915#456] / [i915#460]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7462/shard-tglb2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/shard-tglb9/igt@kms_vblank@pipe-c-ts-continuation-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593 [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606 [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347 [fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391 [fdo#112393]: https://bugs.freedesktop.org/show_bug.cgi?id=112393 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435 [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460 [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472 [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520 [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530 [i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570 [i915#640]: https://gitlab.freedesktop.org/drm/intel/issues/640 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#669]: https://gitlab.freedesktop.org/drm/intel/issues/669 [i915#676]: https://gitlab.freedesktop.org/drm/intel/issues/676 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7462 -> Patchwork_15539 CI-20190529: 20190529 CI_DRM_7462: 35a543255ac51154b9bcc5505779548dcde95971 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15539: 0afb72393e8605481729f9c8b24a6758805cddd1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15539/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2020-01-17 14:50 UTC | newest] Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-12-02 16:00 [PATCH 00/10] drm/i915: add display uncore helpers Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:00 ` [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:06 ` Chris Wilson 2019-12-02 16:06 ` [Intel-gfx] " Chris Wilson 2020-01-17 14:36 ` Jani Nikula 2020-01-17 14:47 ` Chris Wilson 2020-01-17 14:50 ` Chris Wilson 2019-12-02 16:00 ` [PATCH 02/10] drm/i915/debugfs: " Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:14 ` Chris Wilson 2019-12-02 16:14 ` [Intel-gfx] " Chris Wilson 2019-12-02 16:00 ` [PATCH 03/10] drm/i915/dmc: " Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:00 ` [PATCH 04/10] drm/i915: add display engine uncore helpers Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-10 13:54 ` Joonas Lahtinen 2019-12-11 6:46 ` Jani Nikula 2019-12-02 16:00 ` [PATCH 05/10] drm/i915/display: use intel de functions for forcewake register access Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:00 ` [PATCH 06/10] drm/i915/irq: " Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:00 ` [PATCH 07/10] drm/i915/gmbus: " Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:00 ` [PATCH 08/10] drm/i915/sprite: " Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:00 ` [PATCH 09/10] drm/i915/pm: " Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 16:00 ` [PATCH 10/10] drm/i915: remove I915_READ_FW() and I915_WRITE_FW() macros Jani Nikula 2019-12-02 16:00 ` [Intel-gfx] " Jani Nikula 2019-12-02 17:29 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add display uncore helpers Patchwork 2019-12-02 17:29 ` [Intel-gfx] " Patchwork 2019-12-02 18:00 ` ✓ Fi.CI.BAT: success " Patchwork 2019-12-02 18:00 ` [Intel-gfx] " Patchwork 2019-12-02 21:58 ` ✗ Fi.CI.IGT: failure " Patchwork 2019-12-02 21:58 ` [Intel-gfx] " Patchwork
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