From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v4 0/4] Fix some PMP implementations
Date: Fri, 24 Jul 2020 17:08:13 +0800 [thread overview]
Message-ID: <cover.1595581140.git.zong.li@sifive.com> (raw)
This patch set contains the fixes for wrong index of pmpcfg CSR on rv64,
and the pmp range in CSR function table. After 3rd version of this patch
series, we also fix the PMP issues such as wrong physical address
translation and ignoring PMP checking.
Chagned in v4:
- Refine the implementation. Suggested by Bin Meng.
- Add fix for PMP checking was ignored.
Changed in v3:
- Refine the implementation. Suggested by Bin Meng.
- Add fix for wrong pphysical address translation.
Changed in v2:
- Move out the shifting operation from loop. Suggested by Bin Meng.
Zong Li (4):
target/riscv: Fix the range of pmpcfg of CSR funcion table
target/riscv/pmp.c: Fix the index offset on RV64
target/riscv: Fix the translation of physical address
target/riscv: Change the TLB page size depends on PMP entries.
target/riscv/cpu_helper.c | 13 +++++++--
target/riscv/csr.c | 2 +-
target/riscv/pmp.c | 60 +++++++++++++++++++++++++++++++++++++++
target/riscv/pmp.h | 2 ++
4 files changed, 73 insertions(+), 4 deletions(-)
--
2.27.0
next reply other threads:[~2020-07-24 9:09 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 9:08 Zong Li [this message]
2020-07-24 9:08 ` [PATCH v4 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table Zong Li
2020-07-24 9:08 ` Zong Li
2020-07-24 9:08 ` [PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64 Zong Li
2020-07-24 9:22 ` Bin Meng
2020-07-24 9:22 ` Bin Meng
2020-07-25 15:06 ` Zong Li
2020-07-25 15:06 ` Zong Li
2020-07-24 9:08 ` [PATCH v4 3/4] target/riscv: Fix the translation of physical address Zong Li
2020-07-24 9:08 ` [PATCH v4 4/4] target/riscv: Change the TLB page size depends on PMP entries Zong Li
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