From: Zong Li <zong.li@sifive.com> To: Bin Meng <bmeng.cn@gmail.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: Re: [PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64 Date: Sat, 25 Jul 2020 23:06:27 +0800 [thread overview] Message-ID: <CANXhq0oDTLKQ-2c90h9J0G2Pj58=na2goby4u9Z3mctZRzwYOg@mail.gmail.com> (raw) In-Reply-To: <CAEUhbmX-va3wLY_aU7QYXE0ke0sn-4mfenz5Mszy+2k9NMib9A@mail.gmail.com> On Fri, Jul 24, 2020 at 5:22 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Zong, > > On Fri, Jul 24, 2020 at 5:08 PM Zong Li <zong.li@sifive.com> wrote: > > > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > > implementation, the second parameter of pmp_write_cfg is > > "reg_index * sizeof(target_ulong)", and we get the the result > > which is started from 16 if reg_index is 2, but we expect that > > it should be started from 8. Separate the implementation for > > RV32 and RV64 respectively. > > > > Signed-off-by: Zong Li <zong.li@sifive.com> > > --- > > target/riscv/pmp.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > > index 2a2b9f5363..e0161d6aab 100644 > > --- a/target/riscv/pmp.c > > +++ b/target/riscv/pmp.c > > @@ -310,6 +310,10 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, > > int i; > > uint8_t cfg_val; > > > > +#if defined(TARGET_RISCV64) > > + reg_index >>= 1; > > +#endif > > + > > trace_pmpcfg_csr_write(env->mhartid, reg_index, val); > > > > if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { > > @@ -335,6 +339,10 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) > > target_ulong cfg_val = 0; > > target_ulong val = 0; > > > > +#if defined(TARGET_RISCV64) > > + reg_index >>= 1; > > +#endif > > + > > for (i = 0; i < sizeof(target_ulong); i++) { > > val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); > > cfg_val |= (val << (i * 8)); > > -- > > It seems you missed to address my review comments in v3? reg_index > should be shifted after we call the trace function. > Sorry for that, there was something wrong in my local tree, I have been posting the 5th version patches, and hope it picks the suggestion already. Thanks. > Regards, > Bin
WARNING: multiple messages have this Message-ID (diff)
From: Zong Li <zong.li@sifive.com> To: Bin Meng <bmeng.cn@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org> Subject: Re: [PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64 Date: Sat, 25 Jul 2020 23:06:27 +0800 [thread overview] Message-ID: <CANXhq0oDTLKQ-2c90h9J0G2Pj58=na2goby4u9Z3mctZRzwYOg@mail.gmail.com> (raw) In-Reply-To: <CAEUhbmX-va3wLY_aU7QYXE0ke0sn-4mfenz5Mszy+2k9NMib9A@mail.gmail.com> On Fri, Jul 24, 2020 at 5:22 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Zong, > > On Fri, Jul 24, 2020 at 5:08 PM Zong Li <zong.li@sifive.com> wrote: > > > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > > implementation, the second parameter of pmp_write_cfg is > > "reg_index * sizeof(target_ulong)", and we get the the result > > which is started from 16 if reg_index is 2, but we expect that > > it should be started from 8. Separate the implementation for > > RV32 and RV64 respectively. > > > > Signed-off-by: Zong Li <zong.li@sifive.com> > > --- > > target/riscv/pmp.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > > index 2a2b9f5363..e0161d6aab 100644 > > --- a/target/riscv/pmp.c > > +++ b/target/riscv/pmp.c > > @@ -310,6 +310,10 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, > > int i; > > uint8_t cfg_val; > > > > +#if defined(TARGET_RISCV64) > > + reg_index >>= 1; > > +#endif > > + > > trace_pmpcfg_csr_write(env->mhartid, reg_index, val); > > > > if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { > > @@ -335,6 +339,10 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) > > target_ulong cfg_val = 0; > > target_ulong val = 0; > > > > +#if defined(TARGET_RISCV64) > > + reg_index >>= 1; > > +#endif > > + > > for (i = 0; i < sizeof(target_ulong); i++) { > > val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); > > cfg_val |= (val << (i * 8)); > > -- > > It seems you missed to address my review comments in v3? reg_index > should be shifted after we call the trace function. > Sorry for that, there was something wrong in my local tree, I have been posting the 5th version patches, and hope it picks the suggestion already. Thanks. > Regards, > Bin
next prev parent reply other threads:[~2020-07-25 15:07 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-24 9:08 [PATCH v4 0/4] Fix some PMP implementations Zong Li 2020-07-24 9:08 ` [PATCH v4 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table Zong Li 2020-07-24 9:08 ` Zong Li 2020-07-24 9:08 ` [PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64 Zong Li 2020-07-24 9:22 ` Bin Meng 2020-07-24 9:22 ` Bin Meng 2020-07-25 15:06 ` Zong Li [this message] 2020-07-25 15:06 ` Zong Li 2020-07-24 9:08 ` [PATCH v4 3/4] target/riscv: Fix the translation of physical address Zong Li 2020-07-24 9:08 ` [PATCH v4 4/4] target/riscv: Change the TLB page size depends on PMP entries Zong Li
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