* [PATCH 0/1] DTS support for PCIe on HiKey970
@ 2021-10-27 7:19 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 4+ messages in thread
From: Mauro Carvalho Chehab @ 2021-10-27 7:19 UTC (permalink / raw)
To: Wei Xu
Cc: linuxarm, mauro.chehab, Mauro Carvalho Chehab, Rob Herring,
devicetree, linux-arm-kernel, linux-kernel
Hi Xuwei,
All drivers needed to support PCIe on HiKey 970 were merged
for Kernel 5.16:
- The PHY driver went via PHY tree;
- The pcie-kirin changes went via PCI-DWC tree;
- The dt-bindings documentation went via DT tree.
The only missing piece of the puzzle is the DTS file.
It follows the documentation at:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
and it is pratically identical[1] to the second example there.
[1] The only difference is that, on the example, I had to use a
different address to avoid conflicts with the HiKey960
example - as - on both hardware - the pcie is at f4000000.
Manivannan Sadhasivam (1):
arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
hardware
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
1 file changed, 107 insertions(+)
--
2.31.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 0/1] DTS support for PCIe on HiKey970
@ 2021-10-27 7:19 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 4+ messages in thread
From: Mauro Carvalho Chehab @ 2021-10-27 7:19 UTC (permalink / raw)
To: Wei Xu
Cc: linuxarm, mauro.chehab, Mauro Carvalho Chehab, Rob Herring,
devicetree, linux-arm-kernel, linux-kernel
Hi Xuwei,
All drivers needed to support PCIe on HiKey 970 were merged
for Kernel 5.16:
- The PHY driver went via PHY tree;
- The pcie-kirin changes went via PCI-DWC tree;
- The dt-bindings documentation went via DT tree.
The only missing piece of the puzzle is the DTS file.
It follows the documentation at:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
and it is pratically identical[1] to the second example there.
[1] The only difference is that, on the example, I had to use a
different address to avoid conflicts with the HiKey960
example - as - on both hardware - the pcie is at f4000000.
Manivannan Sadhasivam (1):
arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
hardware
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
1 file changed, 107 insertions(+)
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/1] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware
2021-10-27 7:19 ` Mauro Carvalho Chehab
@ 2021-10-27 7:19 ` Mauro Carvalho Chehab
-1 siblings, 0 replies; 4+ messages in thread
From: Mauro Carvalho Chehab @ 2021-10-27 7:19 UTC (permalink / raw)
To: Wei Xu
Cc: linuxarm, mauro.chehab, Manivannan Sadhasivam, Rob Herring,
devicetree, linux-arm-kernel, linux-kernel,
Mauro Carvalho Chehab
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Add DTS bindings for the HiKey 970 board's PCIe hardware.
Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
To mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH 0/1] at: https://lore.kernel.org/all/cover.1635318674.git.mchehab+huawei@kernel.org/
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 20698cfd0637..78b41336c587 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
#clock-cells = <1>;
};
+ pmctrl: pmctrl@fff31000 {
+ compatible = "hisilicon,hi3670-pmctrl", "syscon";
+ reg = <0x0 0xfff31000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3670-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -659,6 +665,107 @@ gpio28: gpio@fff1d000 {
clock-names = "apb_pclk";
};
+ pcie_phy: pcie-phy@fc000000 {
+ compatible = "hisilicon,hi970-pcie-phy";
+ reg = <0x0 0xfc000000 0x0 0x80000>;
+
+ phy-supply = <&ldo33>;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+ clock-names = "phy_ref", "aux",
+ "apb_phy", "apb_sys",
+ "aclk";
+
+ /* vboost iboost pre post main */
+ hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+ 0xffffffff 0xffffffff
+ 0xffffffff>;
+
+ #phy-cells = <0>;
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin970-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000000>,
+ <0x0 0xfc180000 0x0 0x1000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy>;
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&gpio7 0 0>;
+ hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>,
+ <&gpio20 6 0>;
+ pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@0,0 { // Lane 0: upstream
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@1,0 { // Lane 4: M.2
+ reg = <0x0800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio3 1 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@5,0 { // Lane 5: Mini PCIe
+ reg = <0x2800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio27 4 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@7,0 { // Lane 6: Ethernet
+ reg = <0x3800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio25 2 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+ };
+ };
+
/* UFS */
ufs: ufs@ff3c0000 {
compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
--
2.31.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 1/1] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware
@ 2021-10-27 7:19 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 4+ messages in thread
From: Mauro Carvalho Chehab @ 2021-10-27 7:19 UTC (permalink / raw)
To: Wei Xu
Cc: linuxarm, mauro.chehab, Manivannan Sadhasivam, Rob Herring,
devicetree, linux-arm-kernel, linux-kernel,
Mauro Carvalho Chehab
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Add DTS bindings for the HiKey 970 board's PCIe hardware.
Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
To mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH 0/1] at: https://lore.kernel.org/all/cover.1635318674.git.mchehab+huawei@kernel.org/
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 20698cfd0637..78b41336c587 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
#clock-cells = <1>;
};
+ pmctrl: pmctrl@fff31000 {
+ compatible = "hisilicon,hi3670-pmctrl", "syscon";
+ reg = <0x0 0xfff31000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3670-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -659,6 +665,107 @@ gpio28: gpio@fff1d000 {
clock-names = "apb_pclk";
};
+ pcie_phy: pcie-phy@fc000000 {
+ compatible = "hisilicon,hi970-pcie-phy";
+ reg = <0x0 0xfc000000 0x0 0x80000>;
+
+ phy-supply = <&ldo33>;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+ clock-names = "phy_ref", "aux",
+ "apb_phy", "apb_sys",
+ "aclk";
+
+ /* vboost iboost pre post main */
+ hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+ 0xffffffff 0xffffffff
+ 0xffffffff>;
+
+ #phy-cells = <0>;
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin970-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000000>,
+ <0x0 0xfc180000 0x0 0x1000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy>;
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&gpio7 0 0>;
+ hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>,
+ <&gpio20 6 0>;
+ pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@0,0 { // Lane 0: upstream
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@1,0 { // Lane 4: M.2
+ reg = <0x0800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio3 1 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@5,0 { // Lane 5: Mini PCIe
+ reg = <0x2800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio27 4 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@7,0 { // Lane 6: Ethernet
+ reg = <0x3800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio25 2 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+ };
+ };
+
/* UFS */
ufs: ufs@ff3c0000 {
compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-10-27 7:21 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-10-27 7:19 [PATCH 0/1] DTS support for PCIe on HiKey970 Mauro Carvalho Chehab
2021-10-27 7:19 ` Mauro Carvalho Chehab
2021-10-27 7:19 ` [PATCH 1/1] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Mauro Carvalho Chehab
2021-10-27 7:19 ` Mauro Carvalho Chehab
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