* [RESEND PATCH 0/1] target/riscv: misa to ISA string conversion fix @ 2022-02-12 11:59 Tsukasa OI 2022-02-12 11:59 ` [RESEND PATCH 1/1] " Tsukasa OI 0 siblings, 1 reply; 2+ messages in thread From: Tsukasa OI @ 2022-02-12 11:59 UTC (permalink / raw) To: Tsukasa OI; +Cc: qemu-riscv S and U are misa bits but not extensions. Thus, they should not be copied to the ISA string. I am truly surprised that this patchset is the THIRD attempt to fix this longstanding problem. (1) August 2019: by Palmer Dabbelt <https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00165.html> <https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00141.html> <https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00259.html> (2) April 2021: by Emmanuel Blot <https://lists.nongnu.org/archive/html/qemu-riscv/2021-04/msg00248.html> (3) February 2022: by me (this patchset) I feel this is urgent to eliminate this bug now considering it required a workaround to RISC-V Linux kernel as I pointed out: <http://lists.infradead.org/pipermail/linux-riscv/2022-February/012252.html> Though my patchset is first developed independently, this submitted version is influenced by (2) Emmanuel Blot's patchset. Thanks to this, constant "[n]" can now be variable "[]". It also fixes an ordering issue where 'C' should be preceded by 'L' (order: 'L' -> 'C') as per the RISC-V ISA Manual (version 20191213), Table 27.1. It clarifies the role of `riscv_exts'. It's a single-letter extrension ordering list. Tsukasa OI (1): target/riscv: misa to ISA string conversion fix target/riscv/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) base-commit: 0a301624c2f4ced3331ffd5bce85b4274fe132af -- 2.32.0 ^ permalink raw reply [flat|nested] 2+ messages in thread
* [RESEND PATCH 1/1] target/riscv: misa to ISA string conversion fix 2022-02-12 11:59 [RESEND PATCH 0/1] target/riscv: misa to ISA string conversion fix Tsukasa OI @ 2022-02-12 11:59 ` Tsukasa OI 0 siblings, 0 replies; 2+ messages in thread From: Tsukasa OI @ 2022-02-12 11:59 UTC (permalink / raw) To: Tsukasa OI; +Cc: qemu-riscv Some bits in RISC-V `misa' CSR should not be reflected in the ISA string. For instance, `S' and `U' (represents existence of supervisor and user mode, respectively) in `misa' CSR must not be copied since neither `S' nor `U' are valid single-letter extensions. This commit restricts which bits to copy from `misa' CSR to ISA string with another fix: `C' extension should be preceded by `L' extension. It also clarifies that RISC-V extension order string is actually a single-letter extension order list. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> --- target/riscv/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1cb0436187..7a8d6ce104 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,7 +34,7 @@ /* RISC-V CPU definitions */ -static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; +static const char riscv_single_letter_exts[] = "IEMAFDQLCBJTPVNH"; const char * const riscv_int_regnames[] = { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", @@ -831,12 +831,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) char *riscv_isa_string(RISCVCPU *cpu) { int i; - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; + const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); char *isa_str = g_new(char, maxlen); char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); - for (i = 0; i < sizeof(riscv_exts); i++) { - if (cpu->env.misa_ext & RV(riscv_exts[i])) { - *p++ = qemu_tolower(riscv_exts[i]); + for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { + if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { + *p++ = qemu_tolower(riscv_single_letter_exts[i]); } } *p = '\0'; -- 2.32.0 ^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-02-12 11:59 UTC | newest] Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-02-12 11:59 [RESEND PATCH 0/1] target/riscv: misa to ISA string conversion fix Tsukasa OI 2022-02-12 11:59 ` [RESEND PATCH 1/1] " Tsukasa OI
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