* [PATCH v3 00/16] stmmac: Add Loongson platform support
@ 2023-08-03 11:28 Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 01/16] net: stmmac: Pass stmmac_priv and chan in some callbacks Feiyang Chen
` (16 more replies)
0 siblings, 17 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:28 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Extend stmmac functions and macros for Loongson DWMAC.
Add LS7A support for dwmac_loongson.
v2 -> v3:
* Avoid macros accessing variables that are not passed to them.
* Implement a new struct to support 64-bit DMA.
* Use feature names rather than 'lgmac' and 'dwmac_is_loongson'.
Feiyang Chen (16):
net: stmmac: Pass stmmac_priv and chan in some callbacks
net: stmmac: dwmac1000: Allow platforms to choose some register
offsets
net: stmmac: dwmac1000: Add multi-channel support
net: stmmac: dwmac1000: Add 64-bit DMA support
net: stmmac: dwmac1000: Add Loongson register definitions
net: stmmac: dwmac1000: Fix channel numbers for Loongson
net: stmmac: dwmac1000: Add multiple retries for DMA reset
net: stmmac: dwmac1000: Allow platforms to set control value
net: stmmac: Allow platforms to set irq_flags
net: stmmac: Add Loongson HWIF entry
net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe()
net: stmmac: dwmac-loongson: Add LS7A support
net: stmmac: dwmac-loongson: Add 64-bit DMA and multi-vector support
net: stmmac: dwmac-loongson: Disable flow control for GMAC
net: stmmac: dwmac-loongson: Use single queue for GMAC
net: stmmac: dwmac-loongson: Add GNET support
drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
.../net/ethernet/stmicro/stmmac/chain_mode.c | 29 +-
drivers/net/ethernet/stmicro/stmmac/common.h | 4 +
drivers/net/ethernet/stmicro/stmmac/descs.h | 7 +
.../net/ethernet/stmicro/stmmac/descs_com.h | 47 ++-
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 292 ++++++++++++++----
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 +-
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 24 +-
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 135 ++++++--
.../ethernet/stmicro/stmmac/dwmac100_core.c | 12 +-
.../ethernet/stmicro/stmmac/dwmac100_dma.c | 24 +-
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 11 +-
.../ethernet/stmicro/stmmac/dwmac4_descs.c | 17 +-
.../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 +-
.../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac_dma.h | 62 +---
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 244 +++++++++++++--
.../ethernet/stmicro/stmmac/dwxgmac2_core.c | 11 +-
.../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 17 +-
.../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 +-
.../net/ethernet/stmicro/stmmac/enh_desc.c | 38 ++-
drivers/net/ethernet/stmicro/stmmac/hwif.c | 44 ++-
drivers/net/ethernet/stmicro/stmmac/hwif.h | 71 +++--
.../net/ethernet/stmicro/stmmac/norm_desc.c | 17 +-
.../net/ethernet/stmicro/stmmac/ring_mode64.c | 159 ++++++++++
.../ethernet/stmicro/stmmac/stmmac_ethtool.c | 6 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 34 +-
include/linux/stmmac.h | 70 +++++
29 files changed, 1117 insertions(+), 304 deletions(-)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/ring_mode64.c
--
2.39.3
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 01/16] net: stmmac: Pass stmmac_priv and chan in some callbacks
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
@ 2023-08-03 11:28 ` Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 02/16] net: stmmac: dwmac1000: Allow platforms to choose some register offsets Feiyang Chen
` (15 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:28 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Loongson GMAC and GNET have many extended features. To prepare for
that, pass stmmac_priv and chan to more callbacks, and adjust the
callbacks accordingly.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../net/ethernet/stmicro/stmmac/chain_mode.c | 5 +-
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 +++---
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 9 ++-
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 8 ++-
.../ethernet/stmicro/stmmac/dwmac100_core.c | 9 ++-
.../ethernet/stmicro/stmmac/dwmac100_dma.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 11 +--
.../ethernet/stmicro/stmmac/dwmac4_descs.c | 17 ++---
.../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 ++-
.../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac_dma.h | 5 +-
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 5 +-
.../ethernet/stmicro/stmmac/dwxgmac2_core.c | 11 +--
.../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 17 ++---
.../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 +--
.../net/ethernet/stmicro/stmmac/enh_desc.c | 17 ++---
drivers/net/ethernet/stmicro/stmmac/hwif.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/hwif.h | 71 ++++++++++---------
.../net/ethernet/stmicro/stmmac/norm_desc.c | 17 ++---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +-
21 files changed, 146 insertions(+), 110 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
index fb55efd52240..a95866871f3e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
+++ b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
@@ -95,8 +95,9 @@ static unsigned int is_jumbo_frm(int len, int enh_desc)
return ret;
}
-static void init_dma_chain(void *des, dma_addr_t phy_addr,
- unsigned int size, unsigned int extend_desc)
+static void init_dma_chain(struct stmmac_priv *priv, void *des,
+ dma_addr_t phy_addr, unsigned int size,
+ unsigned int extend_desc)
{
/*
* In chained mode the des3 points to the next element in the ring.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 1e714380d125..59ea67cc7e6b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -282,7 +282,7 @@ static const struct emac_variant emac_variant_h6 = {
/* sun8i_dwmac_dma_reset() - reset the EMAC
* Called from stmmac via stmmac_dma_ops->reset
*/
-static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
+static int sun8i_dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
writel(0, ioaddr + EMAC_RX_CTL1);
writel(0, ioaddr + EMAC_TX_CTL1);
@@ -297,7 +297,7 @@ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
/* sun8i_dwmac_dma_init() - initialize the EMAC
* Called from stmmac via stmmac_dma_ops->init
*/
-static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
+static void sun8i_dwmac_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
@@ -394,7 +394,8 @@ static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,
writel(v, ioaddr + EMAC_TX_CTL1);
}
-static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
+static void sun8i_dwmac_enable_dma_transmission(struct stmmac_priv *priv,
+ void __iomem *ioaddr, u32 chan)
{
u32 v;
@@ -636,7 +637,8 @@ static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
* All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
* If addr is NULL, clear the slot
*/
-static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
+static void sun8i_dwmac_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n)
{
@@ -657,7 +659,8 @@ static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
}
}
-static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
+static void sun8i_dwmac_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr,
unsigned int reg_n)
{
@@ -680,7 +683,8 @@ static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
return 1;
}
-static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
+static void sun8i_dwmac_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = hw->pcsr;
@@ -698,13 +702,13 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
} else if (macaddrs <= hw->unicast_filter_entries) {
if (!netdev_mc_empty(dev)) {
netdev_for_each_mc_addr(ha, dev) {
- sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
+ sun8i_dwmac_set_umac_addr(priv, hw, ha->addr, i);
i++;
}
}
if (!netdev_uc_empty(dev)) {
netdev_for_each_uc_addr(ha, dev) {
- sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
+ sun8i_dwmac_set_umac_addr(priv, hw, ha->addr, i);
i++;
}
}
@@ -716,7 +720,7 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
/* Disable unused address filter slots */
while (i < hw->unicast_filter_entries)
- sun8i_dwmac_set_umac_addr(hw, NULL, i++);
+ sun8i_dwmac_set_umac_addr(priv, hw, NULL, i++);
writel(v, ioaddr + EMAC_RX_FRM_FLT);
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 3927609abc44..b52793edf62f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -94,7 +94,8 @@ static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
reg_space[i] = readl(ioaddr + i * 4);
}
-static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
+static void dwmac1000_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n)
{
@@ -103,7 +104,8 @@ static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
GMAC_ADDR_LOW(reg_n));
}
-static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
+static void dwmac1000_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr,
unsigned int reg_n)
{
@@ -137,7 +139,8 @@ static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
ioaddr + GMAC_EXTHASH_BASE + regs * 4);
}
-static void dwmac1000_set_filter(struct mac_device_info *hw,
+static void dwmac1000_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index daf79cdbd3ec..ce0e6ca6f3a2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -16,7 +16,8 @@
#include "dwmac1000.h"
#include "dwmac_dma.h"
-static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
+static void dwmac1000_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_axi *axi)
{
u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
int i;
@@ -70,7 +71,7 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
writel(value, ioaddr + DMA_AXI_BUS_MODE);
}
-static void dwmac1000_dma_init(void __iomem *ioaddr,
+static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
@@ -223,7 +224,8 @@ static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
readl(ioaddr + DMA_BUS_MODE + i * 4);
}
-static int dwmac1000_get_hw_feature(void __iomem *ioaddr,
+static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
struct dma_features *dma_cap)
{
u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
index a6e8d7bd9588..c03623edeb75 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
@@ -59,7 +59,8 @@ static int dwmac100_irq_status(struct mac_device_info *hw,
return 0;
}
-static void dwmac100_set_umac_addr(struct mac_device_info *hw,
+static void dwmac100_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n)
{
@@ -67,7 +68,8 @@ static void dwmac100_set_umac_addr(struct mac_device_info *hw,
stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}
-static void dwmac100_get_umac_addr(struct mac_device_info *hw,
+static void dwmac100_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr,
unsigned int reg_n)
{
@@ -75,7 +77,8 @@ static void dwmac100_get_umac_addr(struct mac_device_info *hw,
stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}
-static void dwmac100_set_filter(struct mac_device_info *hw,
+static void dwmac100_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
index 1c32b1788f02..e6ae230fa453 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
@@ -18,7 +18,7 @@
#include "dwmac100.h"
#include "dwmac_dma.h"
-static void dwmac100_dma_init(void __iomem *ioaddr,
+static void dwmac100_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
/* Enable Application Access by writing to DMA CSR0 */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 03b1c5a97826..536928ccacf9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -330,7 +330,8 @@ static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
writel(pmt, ioaddr + GMAC_PMT);
}
-static void dwmac4_set_umac_addr(struct mac_device_info *hw,
+static void dwmac4_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr, unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
@@ -339,7 +340,8 @@ static void dwmac4_set_umac_addr(struct mac_device_info *hw,
GMAC_ADDR_LOW(reg_n));
}
-static void dwmac4_get_umac_addr(struct mac_device_info *hw,
+static void dwmac4_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr, unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
@@ -588,7 +590,8 @@ static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
}
}
-static void dwmac4_set_filter(struct mac_device_info *hw,
+static void dwmac4_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
@@ -664,7 +667,7 @@ static void dwmac4_set_filter(struct mac_device_info *hw,
int reg = 1;
netdev_for_each_uc_addr(ha, dev) {
- dwmac4_set_umac_addr(hw, ha->addr, reg);
+ dwmac4_set_umac_addr(priv, hw, ha->addr, reg);
reg++;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
index 6a011d8633e8..cf3ba470256f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
@@ -175,7 +175,7 @@ static int dwmac4_wrback_get_rx_status(struct net_device_stats *stats,
return ret;
}
-static int dwmac4_rd_get_tx_len(struct dma_desc *p)
+static int dwmac4_rd_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
}
@@ -296,8 +296,8 @@ static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
return 0;
}
-static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
- int mode, int end, int bfsize)
+static void dwmac4_rd_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize)
{
dwmac4_set_rx_owner(p, disable_rx_ic);
}
@@ -310,9 +310,9 @@ static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
p->des3 = 0;
}
-static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own,
- bool ls, unsigned int tot_pkt_len)
+static void dwmac4_rd_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes3 = le32_to_cpu(p->des3);
@@ -462,13 +462,14 @@ static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
}
-static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
+static void dwmac4_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr)
{
p->des0 = cpu_to_le32(lower_32_bits(addr));
p->des1 = cpu_to_le32(upper_32_bits(addr));
}
-static void dwmac4_clear(struct dma_desc *p)
+static void dwmac4_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des0 = 0;
p->des1 = 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 84d3a8551b03..97dad00dc850 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -15,7 +15,8 @@
#include "dwmac4_dma.h"
#include "stmmac.h"
-static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
+static void dwmac4_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_axi *axi)
{
u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
int i;
@@ -152,7 +153,7 @@ static void dwmac410_dma_init_channel(struct stmmac_priv *priv,
ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}
-static void dwmac4_dma_init(void __iomem *ioaddr,
+static void dwmac4_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
@@ -374,7 +375,8 @@ static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv,
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
}
-static int dwmac4_get_hw_feature(void __iomem *ioaddr,
+static int dwmac4_get_hw_feature(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
struct dma_features *dma_cap)
{
u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
index 358e7dcb6a9a..aaab5ab38373 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
@@ -231,7 +231,7 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
#define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
#define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
-int dwmac4_dma_reset(void __iomem *ioaddr);
+int dwmac4_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx);
void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
index df41eac54058..161667a87f5c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
@@ -13,7 +13,7 @@
#include "dwmac4.h"
#include "stmmac.h"
-int dwmac4_dma_reset(void __iomem *ioaddr)
+int dwmac4_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
index 72672391675f..77141391bd2f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
@@ -152,7 +152,8 @@
#define NUM_DWMAC1000_DMA_REGS 23
#define NUM_DWMAC4_DMA_REGS 27
-void dwmac_enable_dma_transmission(void __iomem *ioaddr);
+void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
+ void __iomem *ioaddr, u32 chan);
void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx);
void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
@@ -167,6 +168,6 @@ void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan);
int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan, u32 dir);
-int dwmac_dma_reset(void __iomem *ioaddr);
+int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
#endif /* __DWMAC_DMA_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index 0b6f999a8305..053a8af6d0e1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -13,7 +13,7 @@
#define GMAC_HI_REG_AE 0x80000000
-int dwmac_dma_reset(void __iomem *ioaddr)
+int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
@@ -27,7 +27,8 @@ int dwmac_dma_reset(void __iomem *ioaddr)
}
/* CSR1 enables the transmit DMA to check for new descriptor */
-void dwmac_enable_dma_transmission(void __iomem *ioaddr)
+void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
+ void __iomem *ioaddr, u32 chan)
{
writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index a0c2ef8bb0ac..640c1b4a0c14 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -337,7 +337,8 @@ static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
writel(val, ioaddr + XGMAC_PMT);
}
-static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
+static void dwxgmac2_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n)
{
@@ -351,7 +352,8 @@ static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
}
-static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
+static void dwxgmac2_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr, unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
@@ -440,7 +442,8 @@ static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
}
-static void dwxgmac2_set_filter(struct mac_device_info *hw,
+static void dwxgmac2_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
@@ -485,7 +488,7 @@ static void dwxgmac2_set_filter(struct mac_device_info *hw,
int reg = 1;
netdev_for_each_uc_addr(ha, dev) {
- dwxgmac2_set_umac_addr(hw, ha->addr, reg);
+ dwxgmac2_set_umac_addr(priv, hw, ha->addr, reg);
reg++;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
index 13c347ee8be9..e6fb47563fc0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
@@ -41,7 +41,7 @@ static int dwxgmac2_get_rx_status(struct net_device_stats *stats,
return good_frame;
}
-static int dwxgmac2_get_tx_len(struct dma_desc *p)
+static int dwxgmac2_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
}
@@ -128,8 +128,8 @@ static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
return !ret;
}
-static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
- int mode, int end, int bfsize)
+static void dwxgmac2_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize)
{
dwxgmac2_set_rx_owner(p, disable_rx_ic);
}
@@ -142,9 +142,9 @@ static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)
p->des3 = 0;
}
-static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own,
- bool ls, unsigned int tot_pkt_len)
+static void dwxgmac2_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes3 = le32_to_cpu(p->des3);
@@ -241,13 +241,14 @@ static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)
p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
}
-static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
+static void dwxgmac2_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr)
{
p->des0 = cpu_to_le32(lower_32_bits(addr));
p->des1 = cpu_to_le32(upper_32_bits(addr));
}
-static void dwxgmac2_clear(struct dma_desc *p)
+static void dwxgmac2_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des0 = 0;
p->des1 = 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index 070bd912580b..5cbee9ed27f0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -8,7 +8,7 @@
#include "stmmac.h"
#include "dwxgmac2.h"
-static int dwxgmac2_dma_reset(void __iomem *ioaddr)
+static int dwxgmac2_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
u32 value = readl(ioaddr + XGMAC_DMA_MODE);
@@ -19,7 +19,7 @@ static int dwxgmac2_dma_reset(void __iomem *ioaddr)
!(value & XGMAC_SWR), 0, 100000);
}
-static void dwxgmac2_dma_init(void __iomem *ioaddr,
+static void dwxgmac2_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
@@ -81,7 +81,8 @@ static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv,
writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
}
-static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
+static void dwxgmac2_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_axi *axi)
{
u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
int i;
@@ -384,7 +385,8 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv,
return ret;
}
-static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
+static int dwxgmac2_get_hw_feature(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
struct dma_features *dma_cap)
{
u32 hw_cap;
diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
index a91d8f13a931..1932a3a8e03c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
@@ -79,7 +79,7 @@ static int enh_desc_get_tx_status(struct net_device_stats *stats,
return ret;
}
-static int enh_desc_get_tx_len(struct dma_desc *p)
+static int enh_desc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);
}
@@ -255,8 +255,8 @@ static int enh_desc_get_rx_status(struct net_device_stats *stats,
return ret;
}
-static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
- int mode, int end, int bfsize)
+static void enh_desc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize)
{
int bfsize1;
@@ -314,9 +314,9 @@ static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
enh_desc_end_tx_desc_on_ring(p, ter);
}
-static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own,
- bool ls, unsigned int tot_pkt_len)
+static void enh_desc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes0 = le32_to_cpu(p->des0);
@@ -441,12 +441,13 @@ static void enh_desc_display_ring(void *head, unsigned int size, bool rx,
pr_info("\n");
}
-static void enh_desc_set_addr(struct dma_desc *p, dma_addr_t addr)
+static void enh_desc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr)
{
p->des2 = cpu_to_le32(addr);
}
-static void enh_desc_clear(struct dma_desc *p)
+static void enh_desc_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des2 = 0;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index b8ba8f2d8041..93cead5613e3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -97,7 +97,7 @@ int stmmac_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
if (plat && plat->fix_soc_reset)
return plat->fix_soc_reset(plat, ioaddr);
- return stmmac_do_callback(priv, dma, reset, ioaddr);
+ return stmmac_do_callback(priv, dma, reset, priv, ioaddr);
}
static const struct stmmac_hwif_entry {
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
index 6ee7cf07cfd7..00be9a7003c8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
@@ -35,14 +35,14 @@ struct dma_edesc;
/* Descriptors helpers */
struct stmmac_desc_ops {
/* DMA RX descriptor ring initialization */
- void (*init_rx_desc)(struct dma_desc *p, int disable_rx_ic, int mode,
- int end, int bfsize);
+ void (*init_rx_desc)(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize);
/* DMA TX descriptor ring initialization */
void (*init_tx_desc)(struct dma_desc *p, int mode, int end);
/* Invoked by the xmit function to prepare the tx descriptor */
- void (*prepare_tx_desc)(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own, bool ls,
- unsigned int tot_pkt_len);
+ void (*prepare_tx_desc)(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len);
void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
int len2, bool tx_own, bool ls, unsigned int tcphdrlen,
unsigned int tcppayloadlen);
@@ -61,7 +61,7 @@ struct stmmac_desc_ops {
struct stmmac_extra_stats *x,
struct dma_desc *p, void __iomem *ioaddr);
/* Get the buffer size from the descriptor */
- int (*get_tx_len)(struct dma_desc *p);
+ int (*get_tx_len)(struct stmmac_priv *priv, struct dma_desc *p);
/* Handle extra events on specific interrupts hw dependent */
void (*set_rx_owner)(struct dma_desc *p, int disable_rx_ic);
/* Get the receive frame size */
@@ -87,9 +87,10 @@ struct stmmac_desc_ops {
/* set MSS via context descriptor */
void (*set_mss)(struct dma_desc *p, unsigned int mss);
/* set descriptor skbuff address */
- void (*set_addr)(struct dma_desc *p, dma_addr_t addr);
+ void (*set_addr)(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr);
/* clear descriptor */
- void (*clear)(struct dma_desc *p);
+ void (*clear)(struct stmmac_priv *priv, struct dma_desc *p);
/* RSS */
int (*get_rx_hash)(struct dma_desc *p, u32 *hash,
enum pkt_hash_types *type);
@@ -103,11 +104,11 @@ struct stmmac_desc_ops {
};
#define stmmac_init_rx_desc(__priv, __args...) \
- stmmac_do_void_callback(__priv, desc, init_rx_desc, __args)
+ stmmac_do_void_callback(__priv, desc, init_rx_desc, __priv, __args)
#define stmmac_init_tx_desc(__priv, __args...) \
stmmac_do_void_callback(__priv, desc, init_tx_desc, __args)
#define stmmac_prepare_tx_desc(__priv, __args...) \
- stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __args)
+ stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __priv, __args)
#define stmmac_prepare_tso_tx_desc(__priv, __args...) \
stmmac_do_void_callback(__priv, desc, prepare_tso_tx_desc, __args)
#define stmmac_set_tx_owner(__priv, __args...) \
@@ -123,7 +124,7 @@ struct stmmac_desc_ops {
#define stmmac_tx_status(__priv, __args...) \
stmmac_do_callback(__priv, desc, tx_status, __args)
#define stmmac_get_tx_len(__priv, __args...) \
- stmmac_do_callback(__priv, desc, get_tx_len, __args)
+ stmmac_do_callback(__priv, desc, get_tx_len, __priv, __args)
#define stmmac_set_rx_owner(__priv, __args...) \
stmmac_do_void_callback(__priv, desc, set_rx_owner, __args)
#define stmmac_get_rx_frame_len(__priv, __args...) \
@@ -145,9 +146,9 @@ struct stmmac_desc_ops {
#define stmmac_set_mss(__priv, __args...) \
stmmac_do_void_callback(__priv, desc, set_mss, __args)
#define stmmac_set_desc_addr(__priv, __args...) \
- stmmac_do_void_callback(__priv, desc, set_addr, __args)
+ stmmac_do_void_callback(__priv, desc, set_addr, __priv, __args)
#define stmmac_clear_desc(__priv, __args...) \
- stmmac_do_void_callback(__priv, desc, clear, __args)
+ stmmac_do_void_callback(__priv, desc, clear, __priv, __args)
#define stmmac_get_rx_hash(__priv, __args...) \
stmmac_do_callback(__priv, desc, get_rx_hash, __args)
#define stmmac_get_rx_header_len(__priv, __args...) \
@@ -169,9 +170,9 @@ struct dma_features;
/* Specific DMA helpers */
struct stmmac_dma_ops {
/* DMA core initialization */
- int (*reset)(void __iomem *ioaddr);
- void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
- int atds);
+ int (*reset)(struct stmmac_priv *priv, void __iomem *ioaddr);
+ void (*init)(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg, int atds);
void (*init_chan)(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, u32 chan);
void (*init_rx_chan)(struct stmmac_priv *priv, void __iomem *ioaddr,
@@ -181,7 +182,8 @@ struct stmmac_dma_ops {
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t phy, u32 chan);
/* Configure the AXI Bus Mode Register */
- void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
+ void (*axi)(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_axi *axi);
/* Dump DMA registers */
void (*dump_regs)(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 *reg_space);
@@ -194,7 +196,8 @@ struct stmmac_dma_ops {
void (*dma_diagnostic_fr)(struct net_device_stats *stats,
struct stmmac_extra_stats *x,
void __iomem *ioaddr);
- void (*enable_dma_transmission) (void __iomem *ioaddr);
+ void (*enable_dma_transmission)(struct stmmac_priv *priv,
+ void __iomem *ioaddr, u32 chan);
void (*enable_dma_irq)(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx);
void (*disable_dma_irq)(struct stmmac_priv *priv, void __iomem *ioaddr,
@@ -210,7 +213,7 @@ struct stmmac_dma_ops {
int (*dma_interrupt)(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan, u32 dir);
/* If supported then get the optional core features */
- int (*get_hw_feature)(void __iomem *ioaddr,
+ int (*get_hw_feature)(struct stmmac_priv *priv, void __iomem *ioaddr,
struct dma_features *dma_cap);
/* Program the HW RX Watchdog */
void (*rx_watchdog)(struct stmmac_priv *priv, void __iomem *ioaddr,
@@ -236,7 +239,7 @@ struct stmmac_dma_ops {
};
#define stmmac_dma_init(__priv, __args...) \
- stmmac_do_void_callback(__priv, dma, init, __args)
+ stmmac_do_void_callback(__priv, dma, init, __priv, __args)
#define stmmac_init_chan(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, init_chan, __priv, __args)
#define stmmac_init_rx_chan(__priv, __args...) \
@@ -244,7 +247,7 @@ struct stmmac_dma_ops {
#define stmmac_init_tx_chan(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, init_tx_chan, __priv, __args)
#define stmmac_axi(__priv, __args...) \
- stmmac_do_void_callback(__priv, dma, axi, __args)
+ stmmac_do_void_callback(__priv, dma, axi, __priv, __args)
#define stmmac_dump_dma_regs(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, dump_regs, __priv, __args)
#define stmmac_dma_rx_mode(__priv, __args...) \
@@ -254,7 +257,7 @@ struct stmmac_dma_ops {
#define stmmac_dma_diagnostic_fr(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, dma_diagnostic_fr, __args)
#define stmmac_enable_dma_transmission(__priv, __args...) \
- stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __args)
+ stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __priv, __args)
#define stmmac_enable_dma_irq(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, enable_dma_irq, __priv, __args)
#define stmmac_disable_dma_irq(__priv, __args...) \
@@ -270,7 +273,7 @@ struct stmmac_dma_ops {
#define stmmac_dma_interrupt_status(__priv, __args...) \
stmmac_do_callback(__priv, dma, dma_interrupt, __priv, __args)
#define stmmac_get_hw_feature(__priv, __args...) \
- stmmac_do_callback(__priv, dma, get_hw_feature, __args)
+ stmmac_do_callback(__priv, dma, get_hw_feature, __priv, __args)
#define stmmac_rx_watchdog(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, rx_watchdog, __priv, __args)
#define stmmac_set_tx_ring_len(__priv, __args...) \
@@ -340,17 +343,21 @@ struct stmmac_ops {
int (*host_mtl_irq_status)(struct stmmac_priv *priv,
struct mac_device_info *hw, u32 chan);
/* Multicast filter setting */
- void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
+ void (*set_filter)(struct stmmac_priv *priv, struct mac_device_info *hw,
+ struct net_device *dev);
/* Flow control setting */
void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time, u32 tx_cnt);
/* Set power management mode (e.g. magic frame) */
void (*pmt)(struct mac_device_info *hw, unsigned long mode);
/* Set/Get Unicast MAC addresses */
- void (*set_umac_addr)(struct mac_device_info *hw,
+ void (*set_umac_addr)(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n);
- void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
+ void (*get_umac_addr)(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
+ unsigned char *addr,
unsigned int reg_n);
void (*set_eee_mode)(struct mac_device_info *hw,
bool en_tx_lpi_clockgating);
@@ -452,15 +459,15 @@ struct stmmac_ops {
#define stmmac_host_mtl_irq_status(__priv, __args...) \
stmmac_do_callback(__priv, mac, host_mtl_irq_status, __priv, __args)
#define stmmac_set_filter(__priv, __args...) \
- stmmac_do_void_callback(__priv, mac, set_filter, __args)
+ stmmac_do_void_callback(__priv, mac, set_filter, __priv, __args)
#define stmmac_flow_ctrl(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, flow_ctrl, __args)
#define stmmac_pmt(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, pmt, __args)
#define stmmac_set_umac_addr(__priv, __args...) \
- stmmac_do_void_callback(__priv, mac, set_umac_addr, __args)
+ stmmac_do_void_callback(__priv, mac, set_umac_addr, __priv, __args)
#define stmmac_get_umac_addr(__priv, __args...) \
- stmmac_do_void_callback(__priv, mac, get_umac_addr, __args)
+ stmmac_do_void_callback(__priv, mac, get_umac_addr, __priv, __args)
#define stmmac_set_eee_mode(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, set_eee_mode, __args)
#define stmmac_reset_eee_mode(__priv, __args...) \
@@ -560,8 +567,8 @@ struct stmmac_rx_queue;
/* Helpers to manage the descriptors for chain and ring modes */
struct stmmac_mode_ops {
- void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
- unsigned int extend_desc);
+ void (*init) (struct stmmac_priv *priv, void *des, dma_addr_t phy_addr,
+ unsigned int size, unsigned int extend_desc);
unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
int (*jumbo_frm)(struct stmmac_tx_queue *tx_q, struct sk_buff *skb,
int csum);
@@ -572,7 +579,7 @@ struct stmmac_mode_ops {
};
#define stmmac_mode_init(__priv, __args...) \
- stmmac_do_void_callback(__priv, mode, init, __args)
+ stmmac_do_void_callback(__priv, mode, init, __priv, __args)
#define stmmac_is_jumbo_frm(__priv, __args...) \
stmmac_do_callback(__priv, mode, is_jumbo_frm, __args)
#define stmmac_jumbo_frm(__priv, __args...) \
diff --git a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
index 350e6670a576..22b8f27edfab 100644
--- a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
@@ -61,7 +61,7 @@ static int ndesc_get_tx_status(struct net_device_stats *stats,
return ret;
}
-static int ndesc_get_tx_len(struct dma_desc *p)
+static int ndesc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
return (le32_to_cpu(p->des1) & RDES1_BUFFER1_SIZE_MASK);
}
@@ -122,8 +122,8 @@ static int ndesc_get_rx_status(struct net_device_stats *stats,
return ret;
}
-static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
- int end, int bfsize)
+static void ndesc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize)
{
int bfsize1;
@@ -181,9 +181,9 @@ static void ndesc_release_tx_desc(struct dma_desc *p, int mode)
ndesc_end_tx_desc_on_ring(p, ter);
}
-static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own,
- bool ls, unsigned int tot_pkt_len)
+static void ndesc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes1 = le32_to_cpu(p->des1);
@@ -292,12 +292,13 @@ static void ndesc_display_ring(void *head, unsigned int size, bool rx,
pr_info("\n");
}
-static void ndesc_set_addr(struct dma_desc *p, dma_addr_t addr)
+static void ndesc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr)
{
p->des2 = cpu_to_le32(addr);
}
-static void ndesc_clear(struct dma_desc *p)
+static void ndesc_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des2 = 0;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 4727f7be4f86..e8619853b6d6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2499,7 +2499,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
true, priv->mode, true, true,
xdp_desc.len);
- stmmac_enable_dma_transmission(priv, priv->ioaddr);
+ stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
entry = tx_q->cur_tx;
@@ -4559,7 +4559,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
- stmmac_enable_dma_transmission(priv, priv->ioaddr);
+ stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
stmmac_flush_tx_descriptors(priv, queue);
stmmac_tx_timer_arm(priv, queue);
@@ -4775,7 +4775,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
priv->xstats.tx_set_ic_bit++;
}
- stmmac_enable_dma_transmission(priv, priv->ioaddr);
+ stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
tx_q->cur_tx = entry;
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 02/16] net: stmmac: dwmac1000: Allow platforms to choose some register offsets
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 01/16] net: stmmac: Pass stmmac_priv and chan in some callbacks Feiyang Chen
@ 2023-08-03 11:28 ` Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 03/16] net: stmmac: dwmac1000: Add multi-channel support Feiyang Chen
` (14 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:28 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Some platforms have dwmac1000 implementations that have a different
address space layout than the default. Add new struct dwmac_regs to
allow a platform driver to choose the appropriate register offsets.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 3 +
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 25 +++--
.../ethernet/stmicro/stmmac/dwmac100_core.c | 3 +
.../ethernet/stmicro/stmmac/dwmac100_dma.c | 22 +++--
.../net/ethernet/stmicro/stmmac/dwmac_dma.h | 55 +----------
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 97 ++++++++++++++++---
include/linux/stmmac.h | 61 ++++++++++++
7 files changed, 187 insertions(+), 79 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index b52793edf62f..6b28f08c8640 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -19,6 +19,7 @@
#include "stmmac.h"
#include "stmmac_pcs.h"
#include "dwmac1000.h"
+#include "dwmac_dma.h"
static void dwmac1000_core_init(struct mac_device_info *hw,
struct net_device *dev)
@@ -533,6 +534,8 @@ int dwmac1000_setup(struct stmmac_priv *priv)
dev_info(priv->device, "\tDWMAC1000\n");
+ priv->plat->dwmac_regs = &dwmac_default_dma_regs;
+
priv->dev->priv_flags |= IFF_UNICAST_FLT;
mac->pcsr = priv->ioaddr;
mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index ce0e6ca6f3a2..3996dea4b1e3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -15,10 +15,12 @@
#include <asm/io.h>
#include "dwmac1000.h"
#include "dwmac_dma.h"
+#include "stmmac.h"
static void dwmac1000_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_axi *axi)
{
+ const struct dwmac_dma_axi *dma_axi = priv->plat->dwmac_regs->axi;
u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
int i;
@@ -30,13 +32,13 @@ static void dwmac1000_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
if (axi->axi_xit_frm)
value |= DMA_AXI_LPI_XIT_FRM;
- value &= ~DMA_AXI_WR_OSR_LMT;
- value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) <<
- DMA_AXI_WR_OSR_LMT_SHIFT;
+ value &= ~dma_axi->wr_osr_lmt;
+ value |= (axi->axi_wr_osr_lmt & dma_axi->wr_osr_lmt_mask) <<
+ dma_axi->wr_osr_lmt_shift;
- value &= ~DMA_AXI_RD_OSR_LMT;
- value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) <<
- DMA_AXI_RD_OSR_LMT_SHIFT;
+ value &= ~dma_axi->rd_osr_lmt;
+ value |= (axi->axi_rd_osr_lmt & dma_axi->rd_osr_lmt_mask) <<
+ dma_axi->rd_osr_lmt_shift;
/* Depending on the UNDEF bit the Master AXI will perform any burst
* length according to the BLEN programmed (by default all BLEN are
@@ -74,6 +76,7 @@ static void dwmac1000_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
+ u32 mask = priv->plat->dwmac_regs->intr_ena->default_mask;
u32 value = readl(ioaddr + DMA_BUS_MODE);
int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
@@ -108,7 +111,7 @@ static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
writel(value, ioaddr + DMA_BUS_MODE);
/* Mask interrupts by writing to CSR7 */
- writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
+ writel(mask, ioaddr + DMA_INTR_ENA);
}
static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
@@ -116,8 +119,10 @@ static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_rx_phy, u32 chan)
{
+ u32 addr = priv->plat->dwmac_regs->addrs->rcv_base_addr;
+
/* RX descriptor base address list must be written into DMA CSR3 */
- writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
+ writel(lower_32_bits(dma_rx_phy), ioaddr + addr);
}
static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
@@ -125,8 +130,10 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_tx_phy, u32 chan)
{
+ u32 addr = priv->plat->dwmac_regs->addrs->tx_base_addr;
+
/* TX descriptor base address list must be written into DMA CSR4 */
- writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
+ writel(lower_32_bits(dma_tx_phy), ioaddr + addr);
}
static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
index c03623edeb75..73ee16549775 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
@@ -18,6 +18,7 @@
#include <asm/io.h>
#include "stmmac.h"
#include "dwmac100.h"
+#include "dwmac_dma.h"
static void dwmac100_core_init(struct mac_device_info *hw,
struct net_device *dev)
@@ -177,6 +178,8 @@ int dwmac100_setup(struct stmmac_priv *priv)
dev_info(priv->device, "\tDWMAC100\n");
+ priv->plat->dwmac_regs = &dwmac_default_dma_regs;
+
mac->pcsr = priv->ioaddr;
mac->link.duplex = MAC_CONTROL_F;
mac->link.speed10 = 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
index e6ae230fa453..be9e8fad69f9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
@@ -17,32 +17,39 @@
#include <asm/io.h>
#include "dwmac100.h"
#include "dwmac_dma.h"
+#include "stmmac.h"
static void dwmac100_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
+ u32 mask = priv->plat->dwmac_regs->intr_ena->default_mask;
+
/* Enable Application Access by writing to DMA CSR0 */
writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
ioaddr + DMA_BUS_MODE);
/* Mask interrupts by writing to CSR7 */
- writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
+ writel(mask, ioaddr + DMA_INTR_ENA);
}
static void dwmac100_dma_init_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_rx_phy, u32 chan)
{
+ u32 addr = priv->plat->dwmac_regs->addrs->rcv_base_addr;
+
/* RX descriptor base addr lists must be written into DMA CSR3 */
- writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
+ writel(lower_32_bits(dma_rx_phy), ioaddr + addr);
}
static void dwmac100_dma_init_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_tx_phy, u32 chan)
{
+ u32 addr = priv->plat->dwmac_regs->addrs->tx_base_addr;
+
/* TX descriptor base addr lists must be written into DMA CSR4 */
- writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
+ writel(lower_32_bits(dma_tx_phy), ioaddr + addr);
}
/* Store and Forward capability is not used at all.
@@ -69,16 +76,17 @@ static void dwmac100_dma_operation_mode_tx(struct stmmac_priv *priv,
static void dwmac100_dump_dma_regs(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 *reg_space)
{
+ const struct dwmac_dma_addrs *addrs = priv->plat->dwmac_regs->addrs;
int i;
for (i = 0; i < NUM_DWMAC100_DMA_REGS; i++)
reg_space[DMA_BUS_MODE / 4 + i] =
readl(ioaddr + DMA_BUS_MODE + i * 4);
- reg_space[DMA_CUR_TX_BUF_ADDR / 4] =
- readl(ioaddr + DMA_CUR_TX_BUF_ADDR);
- reg_space[DMA_CUR_RX_BUF_ADDR / 4] =
- readl(ioaddr + DMA_CUR_RX_BUF_ADDR);
+ reg_space[addrs->cur_tx_buf_addr / 4] =
+ readl(ioaddr + addrs->cur_tx_buf_addr);
+ reg_space[addrs->cur_rx_buf_addr / 4] =
+ readl(ioaddr + addrs->cur_rx_buf_addr);
}
/* DMA controller has two counters to track the number of the missed frames. */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
index 77141391bd2f..b2b75b5b6d50 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
@@ -15,8 +15,6 @@
#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
-#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
-#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
#define DMA_STATUS 0x00001014 /* Status Register */
#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
@@ -33,16 +31,6 @@
#define DMA_AXI_EN_LPI BIT(31)
#define DMA_AXI_LPI_XIT_FRM BIT(30)
-#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)
-#define DMA_AXI_WR_OSR_LMT_SHIFT 20
-#define DMA_AXI_WR_OSR_LMT_MASK 0xf
-#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
-#define DMA_AXI_RD_OSR_LMT_SHIFT 16
-#define DMA_AXI_RD_OSR_LMT_MASK 0xf
-
-#define DMA_AXI_OSR_MAX 0xf
-#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
- (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
#define DMA_AXI_1KBBE BIT(13)
#define DMA_AXI_AAL BIT(12)
#define DMA_AXI_BLEN256 BIT(7)
@@ -61,26 +49,20 @@
#define DMA_AXI_BURST_LEN_MASK 0x000000FE
-#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
-#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
#define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */
+#define DMA_FUNC_CONFIG 0x00001080
/* DMA Control register defines */
#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
/* DMA Normal interrupt */
-#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
-#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
- DMA_INTR_ENA_TIE)
-
/* DMA Abnormal interrupt */
-#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
@@ -91,30 +73,17 @@
#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
-#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
- DMA_INTR_ENA_UNE)
-
/* DMA default interrupt mask */
-#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
#define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE)
#define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE)
/* DMA Status register defines */
-#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */
#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
-#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
-#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
-#define DMA_STATUS_TS_SHIFT 20
-#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
-#define DMA_STATUS_RS_SHIFT 17
-#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
-#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
-#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
@@ -128,30 +97,12 @@
#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
-#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
- DMA_STATUS_AIS | \
- DMA_STATUS_FBI)
-
-#define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
- DMA_STATUS_RWT | \
- DMA_STATUS_RPS | \
- DMA_STATUS_RU | \
- DMA_STATUS_RI | \
- DMA_STATUS_OVF | \
- DMA_STATUS_MSK_COMMON)
-
-#define DMA_STATUS_MSK_TX (DMA_STATUS_ETI | \
- DMA_STATUS_UNF | \
- DMA_STATUS_TJT | \
- DMA_STATUS_TU | \
- DMA_STATUS_TPS | \
- DMA_STATUS_TI | \
- DMA_STATUS_MSK_COMMON)
-
#define NUM_DWMAC100_DMA_REGS 9
#define NUM_DWMAC1000_DMA_REGS 23
#define NUM_DWMAC4_DMA_REGS 27
+extern const struct dwmac_regs dwmac_default_dma_regs;
+
void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 chan);
void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index 053a8af6d0e1..6411be0f3612 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -10,9 +10,82 @@
#include <linux/iopoll.h>
#include "common.h"
#include "dwmac_dma.h"
+#include "stmmac.h"
#define GMAC_HI_REG_AE 0x80000000
+static const struct dwmac_dma_addrs default_dma_addrs = {
+ .rcv_base_addr = 0x0000100c,
+ .tx_base_addr = 0x00001010,
+ .cur_tx_buf_addr = 0x00001050,
+ .cur_rx_buf_addr = 0x00001054,
+};
+
+static const struct dwmac_dma_axi default_dma_axi = {
+ .wr_osr_lmt = GENMASK(23, 20),
+ .wr_osr_lmt_shift = 20,
+ .wr_osr_lmt_mask = 0xf,
+ .rd_osr_lmt = GENMASK(19, 16),
+ .rd_osr_lmt_shift = 16,
+ .rd_osr_lmt_mask = 0xf,
+ .osr_max = 0xf,
+ /* max_osr_limit = (osr_max << wr_osr_lmt_shift) |
+ * (osr_max << rd_osr_lmt_shift)
+ */
+ .max_osr_limit = (0xf << 20) | (0xf << 16),
+};
+
+static const struct dwmac_dma_intr_ena default_dma_intr_ena = {
+ .nie = 0x00010000,
+ /* normal = nie | DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE */
+ .normal = 0x00010000 | DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE,
+ .aie = 0x00008000,
+ /* abnormal = aie | DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE */
+ .abnormal = 0x00008000 | DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE,
+ /* default_mask = normal | abnormal */
+ .default_mask = (0x00010000 | DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE) |
+ (0x00008000 | DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE),
+};
+
+static const struct dwmac_dma_status default_dma_status = {
+ .glpii = 0x40000000,
+ .gpi = 0x10000000,
+ .gmi = 0x08000000,
+ .gli = 0x04000000,
+ .intr_mask = 0x1ffff,
+ .eb_mask = 0x00380000,
+ .ts_mask = 0x00700000,
+ .ts_shift = 20,
+ .rs_mask = 0x000e0000,
+ .rs_shift = 17,
+ .nis = 0x00010000,
+ .ais = 0x00008000,
+ .fbi = 0x00002000,
+ /* msk_common = nis | ais | fbi */
+ .msk_common = 0x00010000 | 0x00008000 | 0x00002000,
+ /* msk_rx = DMA_STATUS_ERI | DMA_STATUS_RWT | DMA_STATUS_RPS |
+ * DMA_STATUS_RU | DMA_STATUS_RI | DMA_STATUS_OVF |
+ * msk_common
+ */
+ .msk_rx = DMA_STATUS_ERI | DMA_STATUS_RWT | DMA_STATUS_RPS |
+ DMA_STATUS_RU | DMA_STATUS_RI | DMA_STATUS_OVF |
+ 0x00010000 | 0x00008000 | 0x00002000,
+ /* msk_tx = DMA_STATUS_ETI | DMA_STATUS_UNF | DMA_STATUS_TJT |
+ * DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_TI |
+ * msk_common
+ */
+ .msk_tx = DMA_STATUS_ETI | DMA_STATUS_UNF | DMA_STATUS_TJT |
+ DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_TI |
+ 0x00010000 | 0x00008000 | 0x00002000,
+};
+
+const struct dwmac_regs dwmac_default_dma_regs = {
+ .addrs = &default_dma_addrs,
+ .axi = &default_dma_axi,
+ .intr_ena = &default_dma_intr_ena,
+ .status = &default_dma_status,
+};
+
int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
@@ -92,8 +165,9 @@ void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
#ifdef DWMAC_DMA_DEBUG
static void show_tx_process_state(unsigned int status)
{
+ u32 status = priv->plat->dwmac_regs->status;
unsigned int state;
- state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
+ state = (status & status->ts_mask) >> status->ts_shift;
switch (state) {
case 0:
@@ -123,8 +197,9 @@ static void show_tx_process_state(unsigned int status)
static void show_rx_process_state(unsigned int status)
{
+ u32 status = priv->plat->dwmac_regs->status;
unsigned int state;
- state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
+ state = (status & status->rs_mask) >> status->rs_shift;
switch (state) {
case 0:
@@ -162,6 +237,7 @@ static void show_rx_process_state(unsigned int status)
int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan, u32 dir)
{
+ const struct dwmac_dma_status *status = priv->plat->dwmac_regs->status;
int ret = 0;
/* read the status register (CSR5) */
u32 intr_status = readl(ioaddr + DMA_STATUS);
@@ -174,12 +250,12 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
#endif
if (dir == DMA_DIR_RX)
- intr_status &= DMA_STATUS_MSK_RX;
+ intr_status &= status->msk_rx;
else if (dir == DMA_DIR_TX)
- intr_status &= DMA_STATUS_MSK_TX;
+ intr_status &= status->msk_tx;
/* ABNORMAL interrupts */
- if (unlikely(intr_status & DMA_STATUS_AIS)) {
+ if (unlikely(intr_status & status->ais)) {
if (unlikely(intr_status & DMA_STATUS_UNF)) {
ret = tx_hard_error_bump_tc;
x->tx_undeflow_irq++;
@@ -202,13 +278,13 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
x->tx_process_stopped_irq++;
ret = tx_hard_error;
}
- if (unlikely(intr_status & DMA_STATUS_FBI)) {
+ if (unlikely(intr_status & status->fbi)) {
x->fatal_bus_error_irq++;
ret = tx_hard_error;
}
}
/* TX/RX NORMAL interrupts */
- if (likely(intr_status & DMA_STATUS_NIS)) {
+ if (likely(intr_status & status->nis)) {
x->normal_irq_n++;
if (likely(intr_status & DMA_STATUS_RI)) {
u32 value = readl(ioaddr + DMA_INTR_ENA);
@@ -226,12 +302,11 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
x->rx_early_irq++;
}
/* Optional hardware blocks, interrupts should be disabled */
- if (unlikely(intr_status &
- (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
+ if (unlikely(intr_status & (status->gpi | status->gmi | status->gli)))
pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
- /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
- writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
+ /* Clear the interrupt by writing a logic 1 to the CSR5 */
+ writel((intr_status & status->intr_mask), ioaddr + DMA_STATUS);
return ret;
}
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 06090538fe2d..ab979efd57bf 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -204,6 +204,66 @@ struct dwmac4_addrs {
u32 mtl_low_cred_offset;
};
+/* DMA addresses that may be customized by a platform */
+struct dwmac_dma_addrs {
+ u32 chan_offset;
+ u32 rcv_base_addr;
+ u32 rcv_base_addr_shadow1;
+ u32 rcv_base_addr_shadow2;
+ u32 tx_base_addr;
+ u32 cur_tx_buf_addr;
+ u32 cur_rx_buf_addr;
+};
+
+/* DMA AXI registers that may be customized by a platform */
+struct dwmac_dma_axi {
+ u32 wr_osr_lmt;
+ u32 wr_osr_lmt_shift;
+ u32 wr_osr_lmt_mask;
+ u32 rd_osr_lmt;
+ u32 rd_osr_lmt_shift;
+ u32 rd_osr_lmt_mask;
+ u32 osr_max;
+ u32 max_osr_limit;
+};
+
+/* DMA normal and abnormal interrupt that may be customized by a platform */
+struct dwmac_dma_intr_ena {
+ u32 nie;
+ u32 normal;
+ u32 aie;
+ u32 abnormal;
+ u32 default_mask;
+};
+
+/* DMA Status register that may be customized by a platform */
+struct dwmac_dma_status {
+ u32 glpii;
+ u32 gpi;
+ u32 gmi;
+ u32 gli;
+ u32 intr_mask;
+ u32 eb_mask;
+ u32 ts_mask;
+ u32 ts_shift;
+ u32 rs_mask;
+ u32 rs_shift;
+ u32 nis;
+ u32 ais;
+ u32 fbi;
+ u32 msk_common;
+ u32 msk_rx;
+ u32 msk_tx;
+};
+
+/* Registers that may be customized by a platform */
+struct dwmac_regs {
+ const struct dwmac_dma_addrs *addrs;
+ const struct dwmac_dma_axi *axi;
+ const struct dwmac_dma_intr_ena *intr_ena;
+ const struct dwmac_dma_status *status;
+};
+
struct plat_stmmacenet_data {
int bus_id;
int phy_addr;
@@ -294,5 +354,6 @@ struct plat_stmmacenet_data {
bool serdes_up_after_phy_linkup;
const struct dwmac4_addrs *dwmac4_addrs;
bool has_integrated_pcs;
+ const struct dwmac_regs *dwmac_regs;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 03/16] net: stmmac: dwmac1000: Add multi-channel support
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 01/16] net: stmmac: Pass stmmac_priv and chan in some callbacks Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 02/16] net: stmmac: dwmac1000: Allow platforms to choose some register offsets Feiyang Chen
@ 2023-08-03 11:28 ` Feiyang Chen
2023-08-03 11:29 ` [PATCH v3 04/16] net: stmmac: dwmac1000: Add 64-bit DMA support Feiyang Chen
` (13 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:28 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Some platforms have dwmac1000 implementations that support multi-
channel. Extend the functions to add multi-channel support.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 70 +++++++++++++++++--
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 37 ++++++----
2 files changed, 86 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index 3996dea4b1e3..4cec78180556 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -114,15 +114,65 @@ static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
writel(mask, ioaddr + DMA_INTR_ENA);
}
+static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ u32 chan)
+{
+ u32 value;
+ int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
+ int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 mask = priv->plat->dwmac_regs->intr_ena->default_mask;
+
+ if (!priv->plat->multi_msi_en)
+ return;
+
+ /* common channel control register config */
+ value = readl(ioaddr + DMA_BUS_MODE + chan * offset);
+
+ /*
+ * Set the DMA PBL (Programmable Burst Length) mode.
+ *
+ * Note: before stmmac core 3.50 this mode bit was 4xPBL, and
+ * post 3.5 mode bit acts as 8*PBL.
+ */
+ if (dma_cfg->pblx8)
+ value |= DMA_BUS_MODE_MAXPBL;
+ value |= DMA_BUS_MODE_USP;
+ value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
+ value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
+ value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
+
+ /* Set the Fixed burst mode */
+ if (dma_cfg->fixed_burst)
+ value |= DMA_BUS_MODE_FB;
+
+ /* Mixed Burst has no effect when fb is set */
+ if (dma_cfg->mixed_burst)
+ value |= DMA_BUS_MODE_MB;
+
+ value |= DMA_BUS_MODE_ATDS;
+
+ if (dma_cfg->aal)
+ value |= DMA_BUS_MODE_AAL;
+
+ writel(value, ioaddr + DMA_BUS_MODE + chan * offset);
+
+ /* Mask interrupts by writing to CSR7 */
+ writel(mask, ioaddr + DMA_INTR_ENA + chan * offset);
+}
+
static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_rx_phy, u32 chan)
{
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
u32 addr = priv->plat->dwmac_regs->addrs->rcv_base_addr;
/* RX descriptor base address list must be written into DMA CSR3 */
- writel(lower_32_bits(dma_rx_phy), ioaddr + addr);
+ writel(lower_32_bits(dma_rx_phy), ioaddr + addr + chan * offset);
}
static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
@@ -130,10 +180,11 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_tx_phy, u32 chan)
{
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
u32 addr = priv->plat->dwmac_regs->addrs->tx_base_addr;
/* TX descriptor base address list must be written into DMA CSR4 */
- writel(lower_32_bits(dma_tx_phy), ioaddr + addr);
+ writel(lower_32_bits(dma_tx_phy), ioaddr + addr + chan * offset);
}
static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
@@ -161,7 +212,8 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
void __iomem *ioaddr, int mode,
u32 channel, int fifosz, u8 qmode)
{
- u32 csr6 = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 csr6 = readl(ioaddr + DMA_CONTROL + channel * offset);
if (mode == SF_DMA_MODE) {
pr_debug("GMAC: enable RX store and forward mode\n");
@@ -183,14 +235,15 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
/* Configure flow control based on rx fifo size */
csr6 = dwmac1000_configure_fc(csr6, fifosz);
- writel(csr6, ioaddr + DMA_CONTROL);
+ writel(csr6, ioaddr + DMA_CONTROL + channel * offset);
}
static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
void __iomem *ioaddr, int mode,
u32 channel, int fifosz, u8 qmode)
{
- u32 csr6 = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 csr6 = readl(ioaddr + DMA_CONTROL + channel * offset);
if (mode == SF_DMA_MODE) {
pr_debug("GMAC: enable TX store and forward mode\n");
@@ -217,7 +270,7 @@ static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
csr6 |= DMA_CONTROL_TTC_256;
}
- writel(csr6, ioaddr + DMA_CONTROL);
+ writel(csr6, ioaddr + DMA_CONTROL + channel * offset);
}
static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
@@ -280,12 +333,15 @@ static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
static void dwmac1000_rx_watchdog(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 riwt, u32 queue)
{
- writel(riwt, ioaddr + DMA_RX_WATCHDOG);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+
+ writel(riwt, ioaddr + DMA_RX_WATCHDOG + queue * offset);
}
const struct stmmac_dma_ops dwmac1000_dma_ops = {
.reset = dwmac_dma_reset,
.init = dwmac1000_dma_init,
+ .init_chan = dwmac1000_dma_init_channel,
.init_rx_chan = dwmac1000_dma_init_rx,
.init_tx_chan = dwmac1000_dma_init_tx,
.axi = dwmac1000_dma_axi,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index 6411be0f3612..cf9e3e7b6b3f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -103,63 +103,71 @@ int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 chan)
{
- writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+
+ writel(1, ioaddr + DMA_XMT_POLL_DEMAND + chan * offset);
}
void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx)
{
- u32 value = readl(ioaddr + DMA_INTR_ENA);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_INTR_ENA + chan * offset);
if (rx)
value |= DMA_INTR_DEFAULT_RX;
if (tx)
value |= DMA_INTR_DEFAULT_TX;
- writel(value, ioaddr + DMA_INTR_ENA);
+ writel(value, ioaddr + DMA_INTR_ENA + chan * offset);
}
void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx)
{
- u32 value = readl(ioaddr + DMA_INTR_ENA);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_INTR_ENA + chan * offset);
if (rx)
value &= ~DMA_INTR_DEFAULT_RX;
if (tx)
value &= ~DMA_INTR_DEFAULT_TX;
- writel(value, ioaddr + DMA_INTR_ENA);
+ writel(value, ioaddr + DMA_INTR_ENA + chan * offset);
}
void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_CONTROL + chan * offset);
value |= DMA_CONTROL_ST;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CONTROL + chan * offset);
}
void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_CONTROL + chan * offset);
value &= ~DMA_CONTROL_ST;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CONTROL + chan * offset);
}
void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_CONTROL + chan * offset);
value |= DMA_CONTROL_SR;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CONTROL + chan * offset);
}
void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
+ u32 value = readl(ioaddr + DMA_CONTROL + chan * offset);
value &= ~DMA_CONTROL_SR;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CONTROL + chan * offset);
}
#ifdef DWMAC_DMA_DEBUG
@@ -238,9 +246,10 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan, u32 dir)
{
const struct dwmac_dma_status *status = priv->plat->dwmac_regs->status;
+ u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
int ret = 0;
/* read the status register (CSR5) */
- u32 intr_status = readl(ioaddr + DMA_STATUS);
+ u32 intr_status = readl(ioaddr + DMA_STATUS + chan * offset);
#ifdef DWMAC_DMA_DEBUG
/* Enable it to monitor DMA rx/tx status in case of critical problems */
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 04/16] net: stmmac: dwmac1000: Add 64-bit DMA support
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (2 preceding siblings ...)
2023-08-03 11:28 ` [PATCH v3 03/16] net: stmmac: dwmac1000: Add multi-channel support Feiyang Chen
@ 2023-08-03 11:29 ` Feiyang Chen
2023-08-03 11:29 ` [PATCH v3 05/16] net: stmmac: dwmac1000: Add Loongson register definitions Feiyang Chen
` (12 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:29 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Some platforms have dwmac1000 implementations that support 64-bit
DMA. Add and extend the functions to add 64-bit DMA support.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
.../net/ethernet/stmicro/stmmac/chain_mode.c | 24 ++-
drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
drivers/net/ethernet/stmicro/stmmac/descs.h | 7 +
.../net/ethernet/stmicro/stmmac/descs_com.h | 47 +++++-
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 32 +++-
.../net/ethernet/stmicro/stmmac/enh_desc.c | 21 ++-
drivers/net/ethernet/stmicro/stmmac/hwif.c | 5 +-
.../net/ethernet/stmicro/stmmac/ring_mode64.c | 159 ++++++++++++++++++
include/linux/stmmac.h | 1 +
10 files changed, 277 insertions(+), 22 deletions(-)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/ring_mode64.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 7dd3d388068b..10f32ded2bd9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -6,7 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o \
dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
- stmmac_xdp.o \
+ stmmac_xdp.o ring_mode64.o \
$(stmmac-y)
stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
index a95866871f3e..f363a2fb56f0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
+++ b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
@@ -36,6 +36,9 @@ static int jumbo_frm(struct stmmac_tx_queue *tx_q, struct sk_buff *skb,
des2 = dma_map_single(priv->device, skb->data,
bmax, DMA_TO_DEVICE);
desc->des2 = cpu_to_le32(des2);
+ if (priv->plat->dma_cfg->dma64)
+ desc->des3 = cpu_to_le32(upper_32_bits(des2));
+
if (dma_mapping_error(priv->device, des2))
return -1;
tx_q->tx_skbuff_dma[entry].buf = des2;
@@ -54,12 +57,16 @@ static int jumbo_frm(struct stmmac_tx_queue *tx_q, struct sk_buff *skb,
(skb->data + bmax * i),
bmax, DMA_TO_DEVICE);
desc->des2 = cpu_to_le32(des2);
+ if (priv->plat->dma_cfg->dma64)
+ desc->des3 = cpu_to_le32(upper_32_bits(des2));
if (dma_mapping_error(priv->device, des2))
return -1;
tx_q->tx_skbuff_dma[entry].buf = des2;
tx_q->tx_skbuff_dma[entry].len = bmax;
stmmac_prepare_tx_desc(priv, desc, 0, bmax, csum,
- STMMAC_CHAIN_MODE, 1, false, skb->len);
+ STMMAC_CHAIN_MODE,
+ !priv->plat->dma_cfg->dma64,
+ false, skb->len);
len -= bmax;
i++;
} else {
@@ -67,6 +74,8 @@ static int jumbo_frm(struct stmmac_tx_queue *tx_q, struct sk_buff *skb,
(skb->data + bmax * i), len,
DMA_TO_DEVICE);
desc->des2 = cpu_to_le32(des2);
+ if (priv->plat->dma_cfg->dma64)
+ desc->des3 = cpu_to_le32(upper_32_bits(des2));
if (dma_mapping_error(priv->device, des2))
return -1;
tx_q->tx_skbuff_dma[entry].buf = des2;
@@ -110,7 +119,12 @@ static void init_dma_chain(struct stmmac_priv *priv, void *des,
struct dma_extended_desc *p = (struct dma_extended_desc *)des;
for (i = 0; i < (size - 1); i++) {
dma_phy += sizeof(struct dma_extended_desc);
- p->basic.des3 = cpu_to_le32((unsigned int)dma_phy);
+ if (priv->plat->dma_cfg->dma64) {
+ p->des6 = cpu_to_le32((unsigned int)dma_phy);
+ p->des7 = cpu_to_le32(upper_32_bits(dma_phy));
+ } else {
+ p->basic.des3 = cpu_to_le32((unsigned int)dma_phy);
+ }
p++;
}
p->basic.des3 = cpu_to_le32((unsigned int)phy_addr);
@@ -130,6 +144,9 @@ static void refill_desc3(struct stmmac_rx_queue *rx_q, struct dma_desc *p)
{
struct stmmac_priv *priv = rx_q->priv_data;
+ if (priv->plat->dma_cfg->dma64)
+ return;
+
if (priv->hwts_rx_en && !priv->extend_desc)
/* NOTE: Device will overwrite des3 with timestamp value if
* 1588-2002 time stamping is enabled, hence reinitialize it
@@ -146,6 +163,9 @@ static void clean_desc3(struct stmmac_tx_queue *tx_q, struct dma_desc *p)
struct stmmac_priv *priv = tx_q->priv_data;
unsigned int entry = tx_q->dirty_tx;
+ if (priv->plat->dma_cfg->dma64)
+ return;
+
if (tx_q->tx_skbuff_dma[entry].last_segment && !priv->extend_desc &&
priv->hwts_tx_en)
/* NOTE: Device will overwrite des3 with timestamp value if
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 16e67c18b6f7..90a7784f71cb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -563,6 +563,7 @@ void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
extern const struct stmmac_mode_ops ring_mode_ops;
+extern const struct stmmac_mode_ops ring_mode64_ops;
extern const struct stmmac_mode_ops chain_mode_ops;
extern const struct stmmac_desc_ops dwmac4_desc_ops;
diff --git a/drivers/net/ethernet/stmicro/stmmac/descs.h b/drivers/net/ethernet/stmicro/stmmac/descs.h
index 49d6a866244f..223b77f0271c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/descs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/descs.h
@@ -56,6 +56,9 @@
#define ERDES1_BUFFER2_SIZE_SHIFT 16
#define ERDES1_DISABLE_IC BIT(31)
+#define E64RDES1_BUFFER1_SIZE_MASK GENMASK(13, 0)
+#define E64RDES1_BUFFER2_SIZE_MASK GENMASK(29, 16)
+
/* Normal transmit descriptor defines */
/* TDES0 */
#define TDES0_DEFERRED BIT(0)
@@ -122,6 +125,10 @@
#define ETDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
#define ETDES1_BUFFER2_SIZE_SHIFT 16
+#define E64TDES1_BUFFER1_SIZE_MASK GENMASK(13, 0)
+#define E64TDES1_BUFFER2_SIZE_MASK GENMASK(28, 15)
+#define E64TDES1_BUFFER2_SIZE_SHIFT 15
+
/* Extended Receive descriptor definitions */
#define ERDES4_IP_PAYLOAD_TYPE_MASK GENMASK(6, 2)
#define ERDES4_IP_HDR_ERR BIT(3)
diff --git a/drivers/net/ethernet/stmicro/stmmac/descs_com.h b/drivers/net/ethernet/stmicro/stmmac/descs_com.h
index 40f7f2da9c5e..24f27088f7c8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/descs_com.h
+++ b/drivers/net/ethernet/stmicro/stmmac/descs_com.h
@@ -20,12 +20,18 @@
/* Enhanced descriptors */
static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end,
- int bfsize)
+ int bfsize, bool dma64)
{
- if (bfsize == BUF_SIZE_16KiB)
- p->des1 |= cpu_to_le32((BUF_SIZE_8KiB
- << ERDES1_BUFFER2_SIZE_SHIFT)
- & ERDES1_BUFFER2_SIZE_MASK);
+ if (bfsize == BUF_SIZE_16KiB) {
+ if (dma64)
+ p->des1 |= cpu_to_le32((BUF_SIZE_8KiB
+ << ERDES1_BUFFER2_SIZE_SHIFT)
+ & E64RDES1_BUFFER2_SIZE_MASK);
+ else
+ p->des1 |= cpu_to_le32((BUF_SIZE_8KiB
+ << ERDES1_BUFFER2_SIZE_SHIFT)
+ & ERDES1_BUFFER2_SIZE_MASK);
+ }
if (end)
p->des1 |= cpu_to_le32(ERDES1_END_RING);
@@ -39,7 +45,7 @@ static inline void enh_desc_end_tx_desc_on_ring(struct dma_desc *p, int end)
p->des0 &= cpu_to_le32(~ETDES0_END_RING);
}
-static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
+static inline void enh_set_tx_desc32_len_on_ring(struct dma_desc *p, int len)
{
if (unlikely(len > BUF_SIZE_4KiB)) {
p->des1 |= cpu_to_le32((((len - BUF_SIZE_4KiB)
@@ -50,6 +56,27 @@ static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
p->des1 |= cpu_to_le32((len & ETDES1_BUFFER1_SIZE_MASK));
}
+static inline void enh_set_tx_desc64_len_on_ring(struct dma_desc *p, int len)
+{
+ if (unlikely(len > BUF_SIZE_4KiB)) {
+ p->des1 |= cpu_to_le32((((len - BUF_SIZE_8KiB)
+ << E64TDES1_BUFFER2_SIZE_SHIFT)
+ & E64TDES1_BUFFER2_SIZE_MASK) | (BUF_SIZE_8KiB
+ & E64TDES1_BUFFER1_SIZE_MASK));
+ } else {
+ p->des1 |= cpu_to_le32((len & E64TDES1_BUFFER1_SIZE_MASK));
+ }
+}
+
+static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len,
+ bool dma64)
+{
+ if (dma64)
+ enh_set_tx_desc64_len_on_ring(p, len);
+ else
+ enh_set_tx_desc32_len_on_ring(p, len);
+}
+
/* Normal descriptors */
static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end, int bfsize)
{
@@ -98,9 +125,13 @@ static inline void enh_desc_end_tx_desc_on_chain(struct dma_desc *p)
p->des0 |= cpu_to_le32(ETDES0_SECOND_ADDRESS_CHAINED);
}
-static inline void enh_set_tx_desc_len_on_chain(struct dma_desc *p, int len)
+static inline void enh_set_tx_desc_len_on_chain(struct dma_desc *p, int len,
+ bool dma64)
{
- p->des1 |= cpu_to_le32(len & ETDES1_BUFFER1_SIZE_MASK);
+ if (dma64)
+ p->des1 |= cpu_to_le32(len & E64TDES1_BUFFER1_SIZE_MASK);
+ else
+ p->des1 |= cpu_to_le32(len & ETDES1_BUFFER1_SIZE_MASK);
}
/* Normal descriptors */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index 4cec78180556..4773779b7be5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -112,6 +112,9 @@ static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
/* Mask interrupts by writing to CSR7 */
writel(mask, ioaddr + DMA_INTR_ENA);
+
+ if (dma_cfg->dma64)
+ writel(0x100, ioaddr + DMA_FUNC_CONFIG);
}
static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
@@ -168,11 +171,25 @@ static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_rx_phy, u32 chan)
{
+ const struct dwmac_dma_addrs *addrs = priv->plat->dwmac_regs->addrs;
u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
- u32 addr = priv->plat->dwmac_regs->addrs->rcv_base_addr;
- /* RX descriptor base address list must be written into DMA CSR3 */
- writel(lower_32_bits(dma_rx_phy), ioaddr + addr + chan * offset);
+ if (dma_cfg->dma64) {
+ writel(lower_32_bits(dma_rx_phy), ioaddr + addrs->rcv_base_addr +
+ chan * offset);
+ writel(upper_32_bits(dma_rx_phy), ioaddr + addrs->rcv_base_addr +
+ 0x4 + chan * offset);
+ if (addrs->rcv_base_addr_shadow1)
+ writel(upper_32_bits(dma_rx_phy),
+ ioaddr + addrs->rcv_base_addr_shadow1);
+ if (addrs->rcv_base_addr_shadow2)
+ writel(upper_32_bits(dma_rx_phy),
+ ioaddr + addrs->rcv_base_addr_shadow2);
+ } else {
+ /* RX descriptor base address list must be written into DMA CSR3 */
+ writel(lower_32_bits(dma_rx_phy), ioaddr + addrs->rcv_base_addr +
+ chan * offset);
+ }
}
static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
@@ -183,8 +200,13 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
u32 offset = priv->plat->dwmac_regs->addrs->chan_offset;
u32 addr = priv->plat->dwmac_regs->addrs->tx_base_addr;
- /* TX descriptor base address list must be written into DMA CSR4 */
- writel(lower_32_bits(dma_tx_phy), ioaddr + addr + chan * offset);
+ if (dma_cfg->dma64) {
+ writel(lower_32_bits(dma_tx_phy), ioaddr + addr + chan * offset);
+ writel(upper_32_bits(dma_tx_phy), ioaddr + addr + 0x4 + chan * offset);
+ } else {
+ /* TX descriptor base address list must be written into DMA CSR4 */
+ writel(lower_32_bits(dma_tx_phy), ioaddr + addr + chan * offset);
+ }
}
static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
index 1932a3a8e03c..ee07006c97c1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
@@ -11,6 +11,7 @@
#include <linux/stmmac.h>
#include "common.h"
#include "descs_com.h"
+#include "stmmac.h"
static int enh_desc_get_tx_status(struct net_device_stats *stats,
struct stmmac_extra_stats *x,
@@ -81,7 +82,10 @@ static int enh_desc_get_tx_status(struct net_device_stats *stats,
static int enh_desc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
- return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);
+ if (priv->plat->dma_cfg->dma64)
+ return (le32_to_cpu(p->des1) & E64TDES1_BUFFER1_SIZE_MASK);
+ else
+ return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);
}
static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
@@ -263,12 +267,15 @@ static void enh_desc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
p->des0 |= cpu_to_le32(RDES0_OWN);
bfsize1 = min(bfsize, BUF_SIZE_8KiB);
- p->des1 |= cpu_to_le32(bfsize1 & ERDES1_BUFFER1_SIZE_MASK);
+ if (priv->plat->dma_cfg->dma64)
+ p->des1 |= cpu_to_le32(bfsize1 & E64RDES1_BUFFER1_SIZE_MASK);
+ else
+ p->des1 |= cpu_to_le32(bfsize1 & ERDES1_BUFFER1_SIZE_MASK);
if (mode == STMMAC_CHAIN_MODE)
ehn_desc_rx_set_on_chain(p);
else
- ehn_desc_rx_set_on_ring(p, end, bfsize);
+ ehn_desc_rx_set_on_ring(p, end, bfsize, priv->plat->dma_cfg->dma64);
if (disable_rx_ic)
p->des1 |= cpu_to_le32(ERDES1_DISABLE_IC);
@@ -321,9 +328,9 @@ static void enh_desc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *
unsigned int tdes0 = le32_to_cpu(p->des0);
if (mode == STMMAC_CHAIN_MODE)
- enh_set_tx_desc_len_on_chain(p, len);
+ enh_set_tx_desc_len_on_chain(p, len, priv->plat->dma_cfg->dma64);
else
- enh_set_tx_desc_len_on_ring(p, len);
+ enh_set_tx_desc_len_on_ring(p, len, priv->plat->dma_cfg->dma64);
if (is_fs)
tdes0 |= ETDES0_FIRST_SEGMENT;
@@ -445,11 +452,15 @@ static void enh_desc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
dma_addr_t addr)
{
p->des2 = cpu_to_le32(addr);
+ if (priv->plat->dma_cfg->dma64)
+ p->des3 = cpu_to_le32(upper_32_bits(addr));
}
static void enh_desc_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des2 = 0;
+ if (priv->plat->dma_cfg->dma64)
+ p->des3 = 0;
}
const struct stmmac_desc_ops enh_desc_ops = {
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index 93cead5613e3..c5768bbec38e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -46,7 +46,10 @@ static void stmmac_dwmac_mode_quirk(struct stmmac_priv *priv)
} else {
dev_info(priv->device, "Ring mode enabled\n");
priv->mode = STMMAC_RING_MODE;
- mac->mode = &ring_mode_ops;
+ if (priv->plat->dma_cfg->dma64)
+ mac->mode = &ring_mode64_ops;
+ else
+ mac->mode = &ring_mode_ops;
}
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/ring_mode64.c b/drivers/net/ethernet/stmicro/stmmac/ring_mode64.c
new file mode 100644
index 000000000000..ab23f1498b20
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/ring_mode64.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*******************************************************************************
+ Specialised functions for managing Ring mode
+
+ It defines all the functions used to handle the normal/enhanced
+ descriptors in case of the DMA is configured to work in chained or
+ in ring mode.
+
+ Based on code taken from ring_mode.c which is:
+
+ Copyright(C) 2011 STMicroelectronics Ltd
+
+ Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+*******************************************************************************/
+
+#include "stmmac.h"
+
+static int jumbo_frm(struct stmmac_tx_queue *tx_q, struct sk_buff *skb,
+ int csum)
+{
+ unsigned int nopaged_len = skb_headlen(skb);
+ struct stmmac_priv *priv = tx_q->priv_data;
+ unsigned int entry = tx_q->cur_tx;
+ struct dma_extended_desc *edesc;
+ unsigned int bmax, len, des2;
+ struct dma_desc *desc;
+
+ if (priv->extend_desc) {
+ edesc = tx_q->dma_etx + entry;
+ desc = (struct dma_desc *)edesc;
+ } else {
+ desc = tx_q->dma_tx + entry;
+ }
+
+ bmax = BUF_SIZE_8KiB;
+
+ len = nopaged_len - bmax * 2;
+
+ if (nopaged_len > bmax * 2) {
+ des2 = dma_map_single(priv->device, skb->data, bmax * 2,
+ DMA_TO_DEVICE);
+ desc->des2 = cpu_to_le32(des2);
+ desc->des3 = cpu_to_le32(upper_32_bits(des2));
+ if (dma_mapping_error(priv->device, des2))
+ return -1;
+
+ tx_q->tx_skbuff_dma[entry].buf = des2;
+ tx_q->tx_skbuff_dma[entry].len = bmax * 2;
+ tx_q->tx_skbuff_dma[entry].is_jumbo = true;
+
+ edesc->des6 = cpu_to_le32(des2 + bmax);
+ edesc->des7 = cpu_to_le32(upper_32_bits(des2 + bmax));
+ stmmac_prepare_tx_desc(priv, desc, 1, bmax, csum,
+ STMMAC_RING_MODE, 1, false, skb->len);
+
+ tx_q->tx_skbuff[entry] = NULL;
+ entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
+ edesc = tx_q->dma_etx + entry;
+ desc = &edesc->basic;
+
+ des2 = dma_map_single(priv->device, skb->data + bmax, len,
+ DMA_TO_DEVICE);
+ desc->des2 = cpu_to_le32(des2);
+ desc->des3 = cpu_to_le32(upper_32_bits(des2));
+ if (dma_mapping_error(priv->device, des2))
+ return -1;
+ tx_q->tx_skbuff_dma[entry].buf = des2;
+ tx_q->tx_skbuff_dma[entry].len = len;
+ tx_q->tx_skbuff_dma[entry].is_jumbo = true;
+
+ edesc->des6 = cpu_to_le32(des2 + bmax);
+ edesc->des7 = cpu_to_le32(upper_32_bits(des2 + bmax));
+ stmmac_prepare_tx_desc(priv, desc, 0, len, csum,
+ STMMAC_RING_MODE, 1, !skb_is_nonlinear(skb),
+ skb->len);
+ } else {
+ des2 = dma_map_single(priv->device, skb->data,
+ nopaged_len, DMA_TO_DEVICE);
+ desc->des2 = cpu_to_le32(des2);
+ desc->des3 = cpu_to_le32(upper_32_bits(des2));
+ if (dma_mapping_error(priv->device, des2))
+ return -1;
+ tx_q->tx_skbuff_dma[entry].buf = des2;
+ tx_q->tx_skbuff_dma[entry].len = nopaged_len;
+ tx_q->tx_skbuff_dma[entry].is_jumbo = true;
+ edesc->des6 = cpu_to_le32(des2 + bmax);
+ edesc->des7 = cpu_to_le32(upper_32_bits(des2 + bmax));
+ stmmac_prepare_tx_desc(priv, desc, 1, nopaged_len, csum,
+ STMMAC_RING_MODE, 1, !skb_is_nonlinear(skb),
+ skb->len);
+ }
+
+ tx_q->cur_tx = entry;
+
+ return entry;
+}
+
+static unsigned int is_jumbo_frm(int len, int enh_desc)
+{
+ unsigned int ret = 0;
+
+ if (len >= BUF_SIZE_4KiB)
+ ret = 1;
+
+ return ret;
+}
+
+static void refill_desc3(struct stmmac_rx_queue *rx_q, struct dma_desc *p)
+{
+ struct dma_extended_desc *edesc = (struct dma_extended_desc *)p;
+ struct stmmac_priv *priv = rx_q->priv_data;
+
+ /* Fill DES3 in case of RING mode */
+ if (priv->dma_conf.dma_buf_sz >= BUF_SIZE_8KiB) {
+ edesc->des6 = cpu_to_le32(le32_to_cpu(edesc->basic.des2) +
+ BUF_SIZE_8KiB);
+ edesc->des7 = cpu_to_le32(le32_to_cpu(edesc->basic.des3));
+ }
+}
+
+/* In ring mode we need to fill the desc3 because it is used as buffer */
+static void init_desc3(struct dma_desc *p)
+{
+ struct dma_extended_desc *edesc = (struct dma_extended_desc *)p;
+
+ edesc->des6 = cpu_to_le32(le32_to_cpu(edesc->basic.des2) +
+ BUF_SIZE_8KiB);
+ edesc->des7 = cpu_to_le32(le32_to_cpu(edesc->basic.des3));
+}
+
+static void clean_desc3(struct stmmac_tx_queue *tx_q, struct dma_desc *p)
+{
+ struct dma_extended_desc *edesc = (struct dma_extended_desc *)p;
+ unsigned int entry = tx_q->dirty_tx;
+
+ if (unlikely(tx_q->tx_skbuff_dma[entry].is_jumbo)) {
+ edesc->des6 = 0;
+ edesc->des7 = 0;
+ }
+}
+
+static int set_16kib_bfsize(int mtu)
+{
+ int ret = 0;
+
+ if (unlikely(mtu >= BUF_SIZE_8KiB))
+ ret = BUF_SIZE_16KiB;
+
+ return ret;
+}
+
+const struct stmmac_mode_ops ring_mode64_ops = {
+ .is_jumbo_frm = is_jumbo_frm,
+ .jumbo_frm = jumbo_frm,
+ .refill_desc3 = refill_desc3,
+ .init_desc3 = init_desc3,
+ .clean_desc3 = clean_desc3,
+ .set_16kib_bfsize = set_16kib_bfsize,
+};
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index ab979efd57bf..7aca9171b3a8 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -98,6 +98,7 @@ struct stmmac_dma_cfg {
bool eame;
bool multi_msi_en;
bool dche;
+ bool dma64;
};
#define AXI_BLEN 7
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 05/16] net: stmmac: dwmac1000: Add Loongson register definitions
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (3 preceding siblings ...)
2023-08-03 11:29 ` [PATCH v3 04/16] net: stmmac: dwmac1000: Add 64-bit DMA support Feiyang Chen
@ 2023-08-03 11:29 ` Feiyang Chen
2023-08-03 11:29 ` [PATCH v3 06/16] net: stmmac: dwmac1000: Fix channel numbers for Loongson Feiyang Chen
` (11 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:29 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Add definitions for Loongson platform.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/common.h | 2 +
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 7 +-
.../net/ethernet/stmicro/stmmac/dwmac_dma.h | 2 +
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 88 +++++++++++++++++++
4 files changed, 98 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 90a7784f71cb..b8e102346f87 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -29,11 +29,13 @@
/* Synopsys Core versions */
#define DWMAC_CORE_3_40 0x34
#define DWMAC_CORE_3_50 0x35
+#define DWMAC_CORE_3_70 0x37
#define DWMAC_CORE_4_00 0x40
#define DWMAC_CORE_4_10 0x41
#define DWMAC_CORE_5_00 0x50
#define DWMAC_CORE_5_10 0x51
#define DWMAC_CORE_5_20 0x52
+#define DWLGMAC_CORE_1_00 0x10
#define DWXGMAC_CORE_2_10 0x21
#define DWXLGMAC_CORE_2_00 0x20
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 6b28f08c8640..abcce58e9c29 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -534,7 +534,12 @@ int dwmac1000_setup(struct stmmac_priv *priv)
dev_info(priv->device, "\tDWMAC1000\n");
- priv->plat->dwmac_regs = &dwmac_default_dma_regs;
+ if (priv->synopsys_id == DWLGMAC_CORE_1_00)
+ priv->plat->dwmac_regs = &dwmac_loongson_dma_regs;
+ else if (priv->plat->dma_cfg->dma64)
+ priv->plat->dwmac_regs = &dwmac_loongson64_dma_regs;
+ else
+ priv->plat->dwmac_regs = &dwmac_default_dma_regs;
priv->dev->priv_flags |= IFF_UNICAST_FLT;
mac->pcsr = priv->ioaddr;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
index b2b75b5b6d50..2da5888342fa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
@@ -102,6 +102,8 @@
#define NUM_DWMAC4_DMA_REGS 27
extern const struct dwmac_regs dwmac_default_dma_regs;
+extern const struct dwmac_regs dwmac_loongson_dma_regs;
+extern const struct dwmac_regs dwmac_loongson64_dma_regs;
void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 chan);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index cf9e3e7b6b3f..fc0da4336e4e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -21,6 +21,25 @@ static const struct dwmac_dma_addrs default_dma_addrs = {
.cur_rx_buf_addr = 0x00001054,
};
+static const struct dwmac_dma_addrs loongson_dma_addrs = {
+ .chan_offset = 0x100,
+ .rcv_base_addr = 0x0000100c,
+ .tx_base_addr = 0x00001010,
+ .cur_tx_buf_addr = 0x00001050,
+ .cur_rx_buf_addr = 0x00001054,
+ .rcv_base_addr_shadow1 = 0x00001068,
+ .rcv_base_addr_shadow2 = 0x000010a8,
+};
+
+static const struct dwmac_dma_addrs loongson64_dma_addrs = {
+ .rcv_base_addr = 0x00001090,
+ .tx_base_addr = 0x00001098,
+ .cur_tx_buf_addr = 0x000010b0,
+ .cur_rx_buf_addr = 0x000010b8,
+ .rcv_base_addr_shadow1 = 0x00001068,
+ .rcv_base_addr_shadow2 = 0x000010a8,
+};
+
static const struct dwmac_dma_axi default_dma_axi = {
.wr_osr_lmt = GENMASK(23, 20),
.wr_osr_lmt_shift = 20,
@@ -35,6 +54,20 @@ static const struct dwmac_dma_axi default_dma_axi = {
.max_osr_limit = (0xf << 20) | (0xf << 16),
};
+static const struct dwmac_dma_axi loongson_dma_axi = {
+ .wr_osr_lmt = BIT(20),
+ .wr_osr_lmt_shift = 20,
+ .wr_osr_lmt_mask = 0x1,
+ .rd_osr_lmt = BIT(16),
+ .rd_osr_lmt_shift = 16,
+ .rd_osr_lmt_mask = 0x1,
+ .osr_max = 0x1,
+ /* max_osr_limit = (osr_max << wr_osr_lmt_shift) |
+ * (osr_max << rd_osr_lmt_shift)
+ */
+ .max_osr_limit = (0x1 << 20) | (0x1 << 16),
+};
+
static const struct dwmac_dma_intr_ena default_dma_intr_ena = {
.nie = 0x00010000,
/* normal = nie | DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE */
@@ -47,6 +80,18 @@ static const struct dwmac_dma_intr_ena default_dma_intr_ena = {
(0x00008000 | DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE),
};
+static const struct dwmac_dma_intr_ena loongson_dma_intr_ena = {
+ .nie = 0x00060000,
+ /* normal = nie | DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE */
+ .normal = 0x00060000 | DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE,
+ .aie = 0x00018000,
+ /* abnormal = aie | DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE */
+ .abnormal = 0x00018000 | DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE,
+ /* default_mask = normal | abnormal */
+ .default_mask = (0x00060000 | DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE) |
+ (0x00018000 | DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE),
+};
+
static const struct dwmac_dma_status default_dma_status = {
.glpii = 0x40000000,
.gpi = 0x10000000,
@@ -79,6 +124,35 @@ static const struct dwmac_dma_status default_dma_status = {
0x00010000 | 0x00008000 | 0x00002000,
};
+static const struct dwmac_dma_status loongson_dma_status = {
+ .glpii = 0x10000000,
+ .intr_mask = 0x7ffff,
+ .eb_mask = 0x0e000000,
+ .ts_mask = 0x01c00000,
+ .ts_shift = 22,
+ .rs_mask = 0x00380000,
+ .rs_shift = 19,
+ .nis = 0x00060000,
+ .ais = 0x00018000,
+ .fbi = 0x00003000,
+ /* msk_common = nis | ais | fbi */
+ .msk_common = 0x00060000 | 0x00018000 | 0x00003000,
+ /* msk_rx = DMA_STATUS_ERI | DMA_STATUS_RWT | DMA_STATUS_RPS |
+ * DMA_STATUS_RU | DMA_STATUS_RI | DMA_STATUS_OVF |
+ * msk_common
+ */
+ .msk_rx = DMA_STATUS_ERI | DMA_STATUS_RWT | DMA_STATUS_RPS |
+ DMA_STATUS_RU | DMA_STATUS_RI | DMA_STATUS_OVF |
+ 0x00060000 | 0x00018000 | 0x00003000,
+ /* msk_tx = DMA_STATUS_ETI | DMA_STATUS_UNF | DMA_STATUS_TJT |
+ * DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_TI |
+ * msk_common
+ */
+ .msk_tx = DMA_STATUS_ETI | DMA_STATUS_UNF | DMA_STATUS_TJT |
+ DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_TI |
+ 0x00060000 | 0x00018000 | 0x00003000,
+};
+
const struct dwmac_regs dwmac_default_dma_regs = {
.addrs = &default_dma_addrs,
.axi = &default_dma_axi,
@@ -86,6 +160,20 @@ const struct dwmac_regs dwmac_default_dma_regs = {
.status = &default_dma_status,
};
+const struct dwmac_regs dwmac_loongson_dma_regs = {
+ .addrs = &loongson_dma_addrs,
+ .axi = &loongson_dma_axi,
+ .intr_ena = &loongson_dma_intr_ena,
+ .status = &loongson_dma_status,
+};
+
+const struct dwmac_regs dwmac_loongson64_dma_regs = {
+ .addrs = &loongson64_dma_addrs,
+ .axi = &loongson_dma_axi,
+ .intr_ena = &default_dma_intr_ena,
+ .status = &default_dma_status,
+};
+
int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 06/16] net: stmmac: dwmac1000: Fix channel numbers for Loongson
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (4 preceding siblings ...)
2023-08-03 11:29 ` [PATCH v3 05/16] net: stmmac: dwmac1000: Add Loongson register definitions Feiyang Chen
@ 2023-08-03 11:29 ` Feiyang Chen
2023-08-03 11:29 ` [PATCH v3 07/16] net: stmmac: dwmac1000: Add multiple retries for DMA reset Feiyang Chen
` (10 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:29 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Some Loongson platforms cannot obtain the TX and RX number of channels.
Add the fix_channel_num flag for them and specify that the number of
channels is 8.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 10 ++++++++--
include/linux/stmmac.h | 1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index 4773779b7be5..f7a9559817a5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -344,8 +344,14 @@ static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
dma_cap->rx_coe_type2 = (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
dma_cap->rxfifo_over_2048 = (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
/* TX and RX number of channels */
- dma_cap->number_rx_channel = (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
- dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
+ if (priv->plat->fix_channel_num &&
+ ((hw_cap & (DMA_HW_FEAT_RXCHCNT | DMA_HW_FEAT_TXCHCNT)) >> 20) == 0) {
+ dma_cap->number_rx_channel = 8;
+ dma_cap->number_tx_channel = 8;
+ } else {
+ dma_cap->number_rx_channel = (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
+ dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
+ }
/* Alternate (enhanced) DESC mode */
dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 7aca9171b3a8..e1b9ddf83fe5 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -356,5 +356,6 @@ struct plat_stmmacenet_data {
const struct dwmac4_addrs *dwmac4_addrs;
bool has_integrated_pcs;
const struct dwmac_regs *dwmac_regs;
+ bool fix_channel_num;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 07/16] net: stmmac: dwmac1000: Add multiple retries for DMA reset
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (5 preceding siblings ...)
2023-08-03 11:29 ` [PATCH v3 06/16] net: stmmac: dwmac1000: Fix channel numbers for Loongson Feiyang Chen
@ 2023-08-03 11:29 ` Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 08/16] net: stmmac: dwmac1000: Allow platforms to set control value Feiyang Chen
` (9 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:29 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
DMA reset on some platforms may fail, so add the dma_reset_times
variable to control the number of retries.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 3 +++
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 17 +++++++++++------
include/linux/stmmac.h | 1 +
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index abcce58e9c29..ad712e337a50 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -541,6 +541,9 @@ int dwmac1000_setup(struct stmmac_priv *priv)
else
priv->plat->dwmac_regs = &dwmac_default_dma_regs;
+ if (!priv->plat->dma_reset_times)
+ priv->plat->dma_reset_times = 1;
+
priv->dev->priv_flags |= IFF_UNICAST_FLT;
mac->pcsr = priv->ioaddr;
mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index fc0da4336e4e..de1b1844bb8a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -176,15 +176,20 @@ const struct dwmac_regs dwmac_loongson64_dma_regs = {
int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
+ int err;
+ int cnt = priv->plat->dma_reset_times;
u32 value = readl(ioaddr + DMA_BUS_MODE);
- /* DMA SW reset */
- value |= DMA_BUS_MODE_SFT_RESET;
- writel(value, ioaddr + DMA_BUS_MODE);
+ do {
+ value |= DMA_BUS_MODE_SFT_RESET;
+ writel(value, ioaddr + DMA_BUS_MODE);
- return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
- !(value & DMA_BUS_MODE_SFT_RESET),
- 10000, 200000);
+ err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
+ !(value & DMA_BUS_MODE_SFT_RESET),
+ 10000, 200000);
+ } while (cnt-- && err);
+
+ return err;
}
/* CSR1 enables the transmit DMA to check for new descriptor */
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index e1b9ddf83fe5..ad2905cd226c 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -357,5 +357,6 @@ struct plat_stmmacenet_data {
bool has_integrated_pcs;
const struct dwmac_regs *dwmac_regs;
bool fix_channel_num;
+ bool dma_reset_times;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 08/16] net: stmmac: dwmac1000: Allow platforms to set control value
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (6 preceding siblings ...)
2023-08-03 11:29 ` [PATCH v3 07/16] net: stmmac: dwmac1000: Add multiple retries for DMA reset Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 09/16] net: stmmac: Allow platforms to set irq_flags Feiyang Chen
` (8 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Some platforms need extra control value to configure GMAC core, add
control_value variable for them.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 4 ++++
include/linux/stmmac.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index ad712e337a50..d1c30ca9a56a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -24,6 +24,7 @@
static void dwmac1000_core_init(struct mac_device_info *hw,
struct net_device *dev)
{
+ struct stmmac_priv *priv = netdev_priv(dev);
void __iomem *ioaddr = hw->pcsr;
u32 value = readl(ioaddr + GMAC_CONTROL);
int mtu = dev->mtu;
@@ -31,6 +32,9 @@ static void dwmac1000_core_init(struct mac_device_info *hw,
/* Configure GMAC core */
value |= GMAC_CORE_INIT;
+ if (priv->plat->control_value)
+ value |= priv->plat->control_value;
+
if (mtu > 1500)
value |= GMAC_CONTROL_2K;
if (mtu > 2000)
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index ad2905cd226c..9f6037b7b5e1 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -358,5 +358,6 @@ struct plat_stmmacenet_data {
const struct dwmac_regs *dwmac_regs;
bool fix_channel_num;
bool dma_reset_times;
+ u32 control_value;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 09/16] net: stmmac: Allow platforms to set irq_flags
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (7 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 08/16] net: stmmac: dwmac1000: Allow platforms to set control value Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 10/16] net: stmmac: Add Loongson HWIF entry Feiyang Chen
` (7 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Some platforms need extra irq flags to request irq multi msi, add
irq_flags variable for them.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 16 +++++++++-------
include/linux/stmmac.h | 1 +
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index e8619853b6d6..7abe3bb8c626 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3515,7 +3515,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
int_name = priv->int_name_mac;
sprintf(int_name, "%s:%s", dev->name, "mac");
ret = request_irq(dev->irq, stmmac_mac_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc mac MSI %d (error: %d)\n",
@@ -3532,7 +3532,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s", dev->name, "wol");
ret = request_irq(priv->wol_irq,
stmmac_mac_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc wol MSI %d (error: %d)\n",
@@ -3550,7 +3550,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s", dev->name, "lpi");
ret = request_irq(priv->lpi_irq,
stmmac_mac_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc lpi MSI %d (error: %d)\n",
@@ -3568,7 +3568,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s", dev->name, "safety-ce");
ret = request_irq(priv->sfty_ce_irq,
stmmac_safety_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc sfty ce MSI %d (error: %d)\n",
@@ -3586,7 +3586,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s", dev->name, "safety-ue");
ret = request_irq(priv->sfty_ue_irq,
stmmac_safety_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc sfty ue MSI %d (error: %d)\n",
@@ -3607,7 +3607,8 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
ret = request_irq(priv->rx_irq[i],
stmmac_msi_intr_rx,
- 0, int_name, &priv->dma_conf.rx_queue[i]);
+ priv->plat->irq_flags, int_name,
+ &priv->dma_conf.rx_queue[i]);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc rx-%d MSI %d (error: %d)\n",
@@ -3632,7 +3633,8 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
ret = request_irq(priv->tx_irq[i],
stmmac_msi_intr_tx,
- 0, int_name, &priv->dma_conf.tx_queue[i]);
+ priv->plat->irq_flags, int_name,
+ &priv->dma_conf.tx_queue[i]);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc tx-%d MSI %d (error: %d)\n",
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 9f6037b7b5e1..2b59ddbe59ea 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -359,5 +359,6 @@ struct plat_stmmacenet_data {
bool fix_channel_num;
bool dma_reset_times;
u32 control_value;
+ u32 irq_flags;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 10/16] net: stmmac: Add Loongson HWIF entry
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (8 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 09/16] net: stmmac: Allow platforms to set irq_flags Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 11/16] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe() Feiyang Chen
` (6 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Add new entries to HWIF table for Loongson.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
drivers/net/ethernet/stmicro/stmmac/hwif.c | 37 ++++++++++++++++++-
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 1 +
3 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index b8e102346f87..967652c9a6ef 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -549,6 +549,7 @@ int dwmac1000_setup(struct stmmac_priv *priv);
int dwmac4_setup(struct stmmac_priv *priv);
int dwxgmac2_setup(struct stmmac_priv *priv);
int dwxlgmac2_setup(struct stmmac_priv *priv);
+int dwmac_loongson_setup(struct stmmac_priv *priv);
void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
unsigned int high, unsigned int low);
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index c5768bbec38e..26c35ed4782d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -61,7 +61,8 @@ static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)
dev_info(priv->device, "Enhanced/Alternate descriptors\n");
/* GMAC older than 3.50 has no extended descriptors */
- if (priv->synopsys_id >= DWMAC_CORE_3_50) {
+ if (priv->synopsys_id >= DWMAC_CORE_3_50 ||
+ priv->synopsys_id == DWLGMAC_CORE_1_00) {
dev_info(priv->device, "Enabled extended descriptors\n");
priv->extend_desc = 1;
} else {
@@ -267,6 +268,40 @@ static const struct stmmac_hwif_entry {
.mmc = &dwxgmac_mmc_ops,
.setup = dwxlgmac2_setup,
.quirks = stmmac_dwxlgmac_quirks,
+ }, {
+ .gmac = true,
+ .gmac4 = false,
+ .xgmac = false,
+ .min_id = DWLGMAC_CORE_1_00,
+ .regs = {
+ .ptp_off = PTP_GMAC3_X_OFFSET,
+ .mmc_off = MMC_GMAC3_X_OFFSET,
+ },
+ .desc = NULL,
+ .dma = &dwmac1000_dma_ops,
+ .mac = &dwmac1000_ops,
+ .hwtimestamp = &stmmac_ptp,
+ .mode = NULL,
+ .tc = NULL,
+ .setup = dwmac1000_setup,
+ .quirks = stmmac_dwmac1_quirks,
+ }, {
+ .gmac = true,
+ .gmac4 = false,
+ .xgmac = false,
+ .min_id = DWMAC_CORE_3_50,
+ .regs = {
+ .ptp_off = PTP_GMAC3_X_OFFSET,
+ .mmc_off = MMC_GMAC3_X_OFFSET,
+ },
+ .desc = NULL,
+ .dma = &dwmac1000_dma_ops,
+ .mac = &dwmac1000_ops,
+ .hwtimestamp = &stmmac_ptp,
+ .mode = NULL,
+ .tc = NULL,
+ .setup = dwmac1000_setup,
+ .quirks = stmmac_dwmac1_quirks,
},
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 7abe3bb8c626..5eafb08e2332 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -6938,6 +6938,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
* riwt_off field from the platform.
*/
if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
+ (priv->synopsys_id == DWLGMAC_CORE_1_00) ||
(priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
priv->use_riwt = 1;
dev_info(priv->device,
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 11/16] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe()
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (9 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 10/16] net: stmmac: Add Loongson HWIF entry Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 12/16] net: stmmac: dwmac-loongson: Add LS7A support Feiyang Chen
` (5 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Add a setup() function to initialize data, and simplify code for
loongson_dwmac_probe().
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 89 +++++++++++--------
1 file changed, 54 insertions(+), 35 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index a25c187d3185..ff4fa74d2a11 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -9,7 +9,12 @@
#include <linux/of_irq.h>
#include "stmmac.h"
-static int loongson_default_data(struct plat_stmmacenet_data *plat)
+struct stmmac_pci_info {
+ int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
+};
+
+static void loongson_default_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
{
plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->has_gmac = 1;
@@ -34,23 +39,38 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat)
/* Disable RX queues routing by default */
plat->rx_queues_cfg[0].pkt_route = 0x0;
+}
+
+static int loongson_gmac_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ loongson_default_data(pdev, plat);
+
+ plat->multicast_filter_bins = 256;
+
+ plat->mdio_bus_data->phy_mask = 0;
- /* Default to phy auto-detection */
plat->phy_addr = -1;
+ plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
plat->dma_cfg->pbl = 32;
plat->dma_cfg->pblx8 = true;
- plat->multicast_filter_bins = 256;
return 0;
}
-static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+static struct stmmac_pci_info loongson_gmac_pci_info = {
+ .setup = loongson_gmac_data,
+};
+
+static int loongson_dwmac_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
{
+ int ret, i, bus_id, phy_mode;
struct plat_stmmacenet_data *plat;
+ struct stmmac_pci_info *info;
struct stmmac_resources res;
struct device_node *np;
- int ret, i, phy_mode;
np = dev_of_node(&pdev->dev);
@@ -59,39 +79,32 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
return -ENODEV;
}
- if (!of_device_is_compatible(np, "loongson, pci-gmac")) {
- pr_info("dwmac_loongson_pci: Incompatible OF node\n");
- return -ENODEV;
- }
-
plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
if (!plat)
return -ENOMEM;
+ plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
+ sizeof(*plat->mdio_bus_data),
+ GFP_KERNEL);
+ if (!plat->mdio_bus_data)
+ return -ENOMEM;
+
+ plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
+ GFP_KERNEL);
+ if (!plat->dma_cfg)
+ return -ENOMEM;
+
plat->mdio_node = of_get_child_by_name(np, "mdio");
if (plat->mdio_node) {
dev_info(&pdev->dev, "Found MDIO subnode\n");
-
- plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
- sizeof(*plat->mdio_bus_data),
- GFP_KERNEL);
- if (!plat->mdio_bus_data) {
- ret = -ENOMEM;
- goto err_put_node;
- }
plat->mdio_bus_data->needs_reset = true;
}
- plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
- if (!plat->dma_cfg) {
- ret = -ENOMEM;
- goto err_put_node;
- }
-
/* Enable pci device */
ret = pci_enable_device(pdev);
if (ret) {
- dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__);
+ dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
+ __func__);
goto err_put_node;
}
@@ -105,9 +118,16 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
break;
}
- plat->bus_id = of_alias_get_id(np, "ethernet");
- if (plat->bus_id < 0)
- plat->bus_id = pci_dev_id(pdev);
+ pci_set_master(pdev);
+
+ info = (struct stmmac_pci_info *)id->driver_data;
+ ret = info->setup(pdev, plat);
+ if (ret)
+ goto err_disable_device;
+
+ bus_id = of_alias_get_id(np, "ethernet");
+ if (bus_id >= 0)
+ plat->bus_id = bus_id;
phy_mode = device_get_phy_mode(&pdev->dev);
if (phy_mode < 0) {
@@ -115,14 +135,10 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
ret = phy_mode;
goto err_disable_device;
}
-
plat->phy_interface = phy_mode;
- plat->interface = PHY_INTERFACE_MODE_GMII;
- pci_set_master(pdev);
-
- loongson_default_data(plat);
pci_enable_msi(pdev);
+
memset(&res, 0, sizeof(res));
res.addr = pcim_iomap_table(pdev)[0];
@@ -135,7 +151,8 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
if (res.wol_irq < 0) {
- dev_info(&pdev->dev, "IRQ eth_wake_irq not found, using macirq\n");
+ dev_info(&pdev->dev,
+ "IRQ eth_wake_irq not found, using macirq\n");
res.wol_irq = res.irq;
}
@@ -219,8 +236,10 @@ static int __maybe_unused loongson_dwmac_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(loongson_dwmac_pm_ops, loongson_dwmac_suspend,
loongson_dwmac_resume);
+#define PCI_DEVICE_ID_LOONGSON_GMAC 0x7a03
+
static const struct pci_device_id loongson_dwmac_id_table[] = {
- { PCI_VDEVICE(LOONGSON, 0x7a03) },
+ { PCI_DEVICE_DATA(LOONGSON, GMAC, &loongson_gmac_pci_info) },
{}
};
MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table);
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 12/16] net: stmmac: dwmac-loongson: Add LS7A support
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (10 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 11/16] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe() Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 13/16] net: stmmac: dwmac-loongson: Add 64-bit DMA and multi-vector support Feiyang Chen
` (4 subsequent siblings)
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Current dwmac-loongson only support LS2K in the "probed with PCI
and configured with DT" manner. Add LS7A support on which the
devices are fully PCI (non-DT).
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 79 ++++++++++---------
1 file changed, 43 insertions(+), 36 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index ff4fa74d2a11..c7790f73fe18 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -16,6 +16,10 @@ struct stmmac_pci_info {
static void loongson_default_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
+ /* Get bus_id, this can be overloaded later */
+ plat->bus_id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+
plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->has_gmac = 1;
plat->force_sf_dma_mode = 1;
@@ -56,6 +60,9 @@ static int loongson_gmac_data(struct pci_dev *pdev,
plat->dma_cfg->pbl = 32;
plat->dma_cfg->pblx8 = true;
+ plat->clk_ref_rate = 125000000;
+ plat->clk_ptp_rate = 125000000;
+
return 0;
}
@@ -72,13 +79,6 @@ static int loongson_dwmac_probe(struct pci_dev *pdev,
struct stmmac_resources res;
struct device_node *np;
- np = dev_of_node(&pdev->dev);
-
- if (!np) {
- pr_info("dwmac_loongson_pci: No OF node\n");
- return -ENODEV;
- }
-
plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
if (!plat)
return -ENOMEM;
@@ -94,6 +94,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev,
if (!plat->dma_cfg)
return -ENOMEM;
+ np = dev_of_node(&pdev->dev);
plat->mdio_node = of_get_child_by_name(np, "mdio");
if (plat->mdio_node) {
dev_info(&pdev->dev, "Found MDIO subnode\n");
@@ -125,42 +126,48 @@ static int loongson_dwmac_probe(struct pci_dev *pdev,
if (ret)
goto err_disable_device;
- bus_id = of_alias_get_id(np, "ethernet");
- if (bus_id >= 0)
- plat->bus_id = bus_id;
+ if (np) {
+ bus_id = of_alias_get_id(np, "ethernet");
+ if (bus_id >= 0)
+ plat->bus_id = bus_id;
- phy_mode = device_get_phy_mode(&pdev->dev);
- if (phy_mode < 0) {
- dev_err(&pdev->dev, "phy_mode not found\n");
- ret = phy_mode;
- goto err_disable_device;
+ phy_mode = device_get_phy_mode(&pdev->dev);
+ if (phy_mode < 0) {
+ dev_err(&pdev->dev, "phy_mode not found\n");
+ ret = phy_mode;
+ goto err_disable_device;
+ }
+ plat->phy_interface = phy_mode;
}
- plat->phy_interface = phy_mode;
pci_enable_msi(pdev);
memset(&res, 0, sizeof(res));
res.addr = pcim_iomap_table(pdev)[0];
-
- res.irq = of_irq_get_byname(np, "macirq");
- if (res.irq < 0) {
- dev_err(&pdev->dev, "IRQ macirq not found\n");
- ret = -ENODEV;
- goto err_disable_msi;
- }
-
- res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
- if (res.wol_irq < 0) {
- dev_info(&pdev->dev,
- "IRQ eth_wake_irq not found, using macirq\n");
- res.wol_irq = res.irq;
- }
-
- res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
- if (res.lpi_irq < 0) {
- dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
- ret = -ENODEV;
- goto err_disable_msi;
+ if (np) {
+ res.irq = of_irq_get_byname(np, "macirq");
+ if (res.irq < 0) {
+ dev_err(&pdev->dev, "IRQ macirq not found\n");
+ ret = -ENODEV;
+ goto err_disable_msi;
+ }
+
+ res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
+ if (res.wol_irq < 0) {
+ dev_info(&pdev->dev,
+ "IRQ eth_wake_irq not found, using macirq\n");
+ res.wol_irq = res.irq;
+ }
+
+ res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
+ if (res.lpi_irq < 0) {
+ dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
+ ret = -ENODEV;
+ goto err_disable_msi;
+ }
+ } else {
+ res.irq = pdev->irq;
+ res.wol_irq = pdev->irq;
}
ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 13/16] net: stmmac: dwmac-loongson: Add 64-bit DMA and multi-vector support
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (11 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 12/16] net: stmmac: dwmac-loongson: Add LS7A support Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-03 14:20 ` Russell King (Oracle)
2023-08-03 11:30 ` [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC Feiyang Chen
` (3 subsequent siblings)
16 siblings, 1 reply; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Set 64-Bit DMA for specific versions. Request allocation for multi-
vector interrupts for DWLGMAC_CORE_1_00. If it fails, fallback to
request allocation for single interrupts.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 83 ++++++++++++++++++-
1 file changed, 81 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index c7790f73fe18..18bca996e1cb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -6,11 +6,15 @@
#include <linux/pci.h>
#include <linux/dmi.h>
#include <linux/device.h>
+#include <linux/interrupt.h>
#include <linux/of_irq.h>
+#include "dwmac1000.h"
#include "stmmac.h"
struct stmmac_pci_info {
int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
+ int (*config)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res);
};
static void loongson_default_data(struct pci_dev *pdev,
@@ -66,14 +70,54 @@ static int loongson_gmac_data(struct pci_dev *pdev,
return 0;
}
+static int loongson_gmac_config(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res)
+{
+ u32 version = readl(res->addr + GMAC_VERSION);
+
+ switch (version & 0xff) {
+ case DWLGMAC_CORE_1_00:
+ plat->multi_msi_en = 1;
+ plat->rx_queues_to_use = 8;
+ plat->tx_queues_to_use = 8;
+ plat->fix_channel_num = true;
+ break;
+ case DWMAC_CORE_3_50:
+ case DWMAC_CORE_3_70:
+ if (version & 0x00008000) {
+ plat->host_dma_width = 64;
+ plat->dma_cfg->dma64 = true;
+ }
+ break;
+ default:
+ break;
+ }
+
+ plat->dma_reset_times = 5;
+
+ return 0;
+}
+
static struct stmmac_pci_info loongson_gmac_pci_info = {
.setup = loongson_gmac_data,
+ .config = loongson_gmac_config,
};
+static u32 get_irq_type(struct device_node *np)
+{
+ struct of_phandle_args oirq;
+
+ if (np && of_irq_parse_one(np, 0, &oirq) == 0 && oirq.args_count == 2)
+ return oirq.args[1];
+
+ return IRQF_TRIGGER_RISING;
+}
+
static int loongson_dwmac_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
- int ret, i, bus_id, phy_mode;
+ int ret, i, bus_id, phy_mode, ch_cnt, vecs;
struct plat_stmmacenet_data *plat;
struct stmmac_pci_info *info;
struct stmmac_resources res;
@@ -170,12 +214,46 @@ static int loongson_dwmac_probe(struct pci_dev *pdev,
res.wol_irq = pdev->irq;
}
- ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
+ ret = info->config(pdev, plat, &res);
if (ret)
goto err_disable_msi;
+ if (plat->multi_msi_en) {
+ ch_cnt = plat->rx_queues_to_use;
+
+ pci_disable_msi(pdev);
+
+ res.irq = pci_irq_vector(pdev, 0);
+ res.wol_irq = res.irq;
+ vecs = roundup_pow_of_two(ch_cnt * 2 + 1);
+ if (pci_alloc_irq_vectors(pdev, vecs, vecs, PCI_IRQ_MSI) < 0) {
+ dev_info(&pdev->dev,
+ "MSI enable failed, Fallback to line interrupt\n");
+ plat->multi_msi_en = 0;
+ } else {
+ /* INT NAME | MAC | CH7 rx | CH7 tx | ... | CH0 rx | CH0 tx |
+ * --------- ----- -------- -------- ... -------- --------
+ * IRQ NUM | 0 | 1 | 2 | ... | 15 | 16 |
+ */
+ for (i = 0; i < ch_cnt; i++) {
+ res.rx_irq[ch_cnt - 1 - i] = pci_irq_vector(pdev, 1 + i * 2);
+ res.tx_irq[ch_cnt - 1 - i] = pci_irq_vector(pdev, 2 + i * 2);
+ }
+
+ plat->control_value = GMAC_CONTROL_ACS;
+ plat->irq_flags = get_irq_type(np);
+ }
+ }
+
+ ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
+ if (ret)
+ goto err_free_irq_vectors;
+
return ret;
+err_free_irq_vectors:
+ if (plat->multi_msi_en)
+ pci_free_irq_vectors(pdev);
err_disable_msi:
pci_disable_msi(pdev);
err_disable_device:
@@ -201,6 +279,7 @@ static void loongson_dwmac_remove(struct pci_dev *pdev)
break;
}
+ pci_free_irq_vectors(pdev);
pci_disable_msi(pdev);
pci_disable_device(pdev);
}
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (12 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 13/16] net: stmmac: dwmac-loongson: Add 64-bit DMA and multi-vector support Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-04 17:28 ` Jose Abreu
2023-08-04 20:38 ` Russell King (Oracle)
2023-08-03 11:30 ` [PATCH v3 15/16] net: stmmac: dwmac-loongson: Use single queue " Feiyang Chen
` (2 subsequent siblings)
16 siblings, 2 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Loongson GMAC does not support Flow Control feature. Use
disable_flow_control flag to disable it.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++++
include/linux/stmmac.h | 1 +
3 files changed, 7 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 18bca996e1cb..40eddadd0bd2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -95,6 +95,7 @@ static int loongson_gmac_config(struct pci_dev *pdev,
}
plat->dma_reset_times = 5;
+ plat->disable_flow_control = true;
return 0;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 5eafb08e2332..65ee5a681dcf 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3827,6 +3827,11 @@ static int __stmmac_open(struct net_device *dev,
__func__, ret);
goto init_phy_error;
}
+
+ if (priv->plat->disable_flow_control) {
+ phy_support_sym_pause(dev->phydev);
+ phy_set_sym_pause(dev->phydev, false, false, true);
+ }
}
/* Extra statistics */
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 2b59ddbe59ea..07570d808edb 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -360,5 +360,6 @@ struct plat_stmmacenet_data {
bool dma_reset_times;
u32 control_value;
u32 irq_flags;
+ bool disable_flow_control;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 15/16] net: stmmac: dwmac-loongson: Use single queue for GMAC
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (13 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 16/16] net: stmmac: dwmac-loongson: Add GNET support Feiyang Chen
2023-08-04 17:25 ` [PATCH v3 00/16] stmmac: Add Loongson platform support Jose Abreu
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
GMAC should use single queue, so add use_single_queue flag for it.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 +++-
include/linux/stmmac.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 40eddadd0bd2..d3ade3ae9014 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -96,6 +96,7 @@ static int loongson_gmac_config(struct pci_dev *pdev,
plat->dma_reset_times = 5;
plat->disable_flow_control = true;
+ plat->use_single_queue = true;
return 0;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 65ee5a681dcf..692f41a7a175 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -6063,9 +6063,11 @@ static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
struct net_device *sb_dev)
{
+ struct stmmac_priv *priv = netdev_priv(dev);
int gso = skb_shinfo(skb)->gso_type;
- if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
+ if ((gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) ||
+ priv->plat->use_single_queue) {
/*
* There is no way to determine the number of TSO/USO
* capable Queues. Let's use always the Queue 0
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 07570d808edb..9afee011839a 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -361,5 +361,6 @@ struct plat_stmmacenet_data {
u32 control_value;
u32 irq_flags;
bool disable_flow_control;
+ bool use_single_queue;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 16/16] net: stmmac: dwmac-loongson: Add GNET support
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (14 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 15/16] net: stmmac: dwmac-loongson: Use single queue " Feiyang Chen
@ 2023-08-03 11:30 ` Feiyang Chen
2023-08-04 17:25 ` [PATCH v3 00/16] stmmac: Add Loongson platform support Jose Abreu
16 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-03 11:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai
Cc: Feiyang Chen, linux, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
Add GNET support. Current GNET does not support half duplex mode.
and GNET on LS7A only supports ANE when speed is set to 1000M, and
GNET on LS2K should use single queue.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 67 +++++++++++++++++++
.../ethernet/stmicro/stmmac/stmmac_ethtool.c | 6 ++
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
include/linux/stmmac.h | 2 +
4 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index d3ade3ae9014..712fede3c4b7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -106,6 +106,71 @@ static struct stmmac_pci_info loongson_gmac_pci_info = {
.config = loongson_gmac_config,
};
+static void loongson_gnet_fix_speed(void *priv, unsigned int speed)
+{
+ struct net_device *ndev = dev_get_drvdata(priv);
+ struct stmmac_priv *ptr = netdev_priv(ndev);
+
+ /* The controller and PHY don't work well together.
+ * We need to use the PS bit to check if the controller's status
+ * is correct and reset PHY if necessary.
+ */
+ if (speed == SPEED_1000)
+ if (readl(ptr->ioaddr + MAC_CTRL_REG) & (1 << 15) /* PS */)
+ phy_restart_aneg(ndev->phydev);
+}
+
+static int loongson_gnet_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ loongson_default_data(pdev, plat);
+
+ plat->multicast_filter_bins = 256;
+
+ plat->mdio_bus_data->phy_mask = 0xfffffffb;
+
+ plat->phy_addr = 2;
+ plat->phy_interface = PHY_INTERFACE_MODE_INTERNAL;
+
+ plat->bsp_priv = &pdev->dev;
+ plat->fix_mac_speed = loongson_gnet_fix_speed;
+
+ plat->dma_cfg->pbl = 32;
+ plat->dma_cfg->pblx8 = true;
+
+ plat->clk_ref_rate = 125000000;
+ plat->clk_ptp_rate = 125000000;
+
+ return 0;
+}
+
+static int loongson_gnet_config(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res)
+{
+ plat->dma_reset_times = 5;
+
+ switch (pdev->revision) {
+ case 0x00:
+ plat->disable_half_duplex = true;
+ plat->disable_force_1000 = true;
+ break;
+ case 0x01:
+ plat->disable_half_duplex = true;
+ plat->use_single_queue = true;
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static struct stmmac_pci_info loongson_gnet_pci_info = {
+ .setup = loongson_gnet_data,
+ .config = loongson_gnet_config,
+};
+
static u32 get_irq_type(struct device_node *np)
{
struct of_phandle_args oirq;
@@ -325,9 +390,11 @@ static SIMPLE_DEV_PM_OPS(loongson_dwmac_pm_ops, loongson_dwmac_suspend,
loongson_dwmac_resume);
#define PCI_DEVICE_ID_LOONGSON_GMAC 0x7a03
+#define PCI_DEVICE_ID_LOONGSON_GNET 0x7a13
static const struct pci_device_id loongson_dwmac_id_table[] = {
{ PCI_DEVICE_DATA(LOONGSON, GMAC, &loongson_gmac_pci_info) },
+ { PCI_DEVICE_DATA(LOONGSON, GNET, &loongson_gnet_pci_info) },
{}
};
MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index 2ae73ab842d4..066f42ecf832 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -404,6 +404,12 @@ stmmac_ethtool_set_link_ksettings(struct net_device *dev,
return 0;
}
+ if (priv->plat->disable_force_1000) {
+ if (cmd->base.speed == SPEED_1000 &&
+ cmd->base.autoneg != AUTONEG_ENABLE)
+ return -EOPNOTSUPP;
+ }
+
return phylink_ethtool_ksettings_set(priv->phylink, cmd);
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 692f41a7a175..6797b1742391 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1240,7 +1240,7 @@ static int stmmac_phy_setup(struct stmmac_priv *priv)
}
/* Half-Duplex can only work with single queue */
- if (priv->plat->tx_queues_to_use > 1)
+ if (priv->plat->tx_queues_to_use > 1 || priv->plat->disable_half_duplex)
priv->phylink_config.mac_capabilities &=
~(MAC_10HD | MAC_100HD | MAC_1000HD);
priv->phylink_config.mac_managed_pm = true;
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 9afee011839a..18b4ef614d25 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -362,5 +362,7 @@ struct plat_stmmacenet_data {
u32 irq_flags;
bool disable_flow_control;
bool use_single_queue;
+ bool disable_half_duplex;
+ bool disable_force_1000;
};
#endif
--
2.39.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 13/16] net: stmmac: dwmac-loongson: Add 64-bit DMA and multi-vector support
2023-08-03 11:30 ` [PATCH v3 13/16] net: stmmac: dwmac-loongson: Add 64-bit DMA and multi-vector support Feiyang Chen
@ 2023-08-03 14:20 ` Russell King (Oracle)
2023-08-03 15:42 ` Andrew Lunn
0 siblings, 1 reply; 25+ messages in thread
From: Russell King (Oracle) @ 2023-08-03 14:20 UTC (permalink / raw)
To: Feiyang Chen
Cc: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai, dongbiao, loongson-kernel, netdev, loongarch,
chris.chenfeiyang
On Thu, Aug 03, 2023 at 07:30:34PM +0800, Feiyang Chen wrote:
> Set 64-Bit DMA for specific versions. Request allocation for multi-
> vector interrupts for DWLGMAC_CORE_1_00. If it fails, fallback to
> request allocation for single interrupts.
>
> Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
> ---
> .../ethernet/stmicro/stmmac/dwmac-loongson.c | 83 ++++++++++++++++++-
> 1 file changed, 81 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
> index c7790f73fe18..18bca996e1cb 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
> @@ -6,11 +6,15 @@
> #include <linux/pci.h>
> #include <linux/dmi.h>
> #include <linux/device.h>
> +#include <linux/interrupt.h>
> #include <linux/of_irq.h>
> +#include "dwmac1000.h"
> #include "stmmac.h"
>
> struct stmmac_pci_info {
> int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
> + int (*config)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat,
> + struct stmmac_resources *res);
> };
>
> static void loongson_default_data(struct pci_dev *pdev,
> @@ -66,14 +70,54 @@ static int loongson_gmac_data(struct pci_dev *pdev,
> return 0;
> }
>
> +static int loongson_gmac_config(struct pci_dev *pdev,
> + struct plat_stmmacenet_data *plat,
> + struct stmmac_resources *res)
> +{
> + u32 version = readl(res->addr + GMAC_VERSION);
> +
> + switch (version & 0xff) {
> + case DWLGMAC_CORE_1_00:
> + plat->multi_msi_en = 1;
> + plat->rx_queues_to_use = 8;
> + plat->tx_queues_to_use = 8;
> + plat->fix_channel_num = true;
> + break;
> + case DWMAC_CORE_3_50:
> + case DWMAC_CORE_3_70:
> + if (version & 0x00008000) {
> + plat->host_dma_width = 64;
> + plat->dma_cfg->dma64 = true;
> + }
> + break;
> + default:
> + break;
> + }
> +
> + plat->dma_reset_times = 5;
> +
> + return 0;
> +}
> +
> static struct stmmac_pci_info loongson_gmac_pci_info = {
> .setup = loongson_gmac_data,
> + .config = loongson_gmac_config,
> };
>
> +static u32 get_irq_type(struct device_node *np)
> +{
> + struct of_phandle_args oirq;
> +
> + if (np && of_irq_parse_one(np, 0, &oirq) == 0 && oirq.args_count == 2)
> + return oirq.args[1];
> +
> + return IRQF_TRIGGER_RISING;
> +}
> +
I do wish that there was some IRQ maintainer I could bounce this over to
for them to comment on, because I don't believe that this should be
necessary in any driver - the irq subsystem should configure the IRQ
accordingly before the driver is probed.
But since I don't know that code, and can't be bothered at this point
to read through it and DT yet again, I don't feel qualified to comment
on this...
Maybe someone else can be bothered to comment on it...
If not, then I suppose it will have to do as-is, and maybe someone at
a later date can fix it if it needs fixing.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 13/16] net: stmmac: dwmac-loongson: Add 64-bit DMA and multi-vector support
2023-08-03 14:20 ` Russell King (Oracle)
@ 2023-08-03 15:42 ` Andrew Lunn
0 siblings, 0 replies; 25+ messages in thread
From: Andrew Lunn @ 2023-08-03 15:42 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Feiyang Chen, hkallweit1, peppe.cavallaro, alexandre.torgue,
joabreu, chenhuacai, dongbiao, loongson-kernel, netdev,
loongarch, chris.chenfeiyang
> > +static u32 get_irq_type(struct device_node *np)
> > +{
> > + struct of_phandle_args oirq;
> > +
> > + if (np && of_irq_parse_one(np, 0, &oirq) == 0 && oirq.args_count == 2)
> > + return oirq.args[1];
> > +
> > + return IRQF_TRIGGER_RISING;
> > +}
> > +
>
> I do wish that there was some IRQ maintainer I could bounce this over to
> for them to comment on, because I don't believe that this should be
> necessary in any driver - the irq subsystem should configure the IRQ
> accordingly before the driver is probed.
I agree with you, this is very likely to be wrong.
Feiyang, please look at other drivers and copy with they do.
Andrew
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH v3 00/16] stmmac: Add Loongson platform support
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
` (15 preceding siblings ...)
2023-08-03 11:30 ` [PATCH v3 16/16] net: stmmac: dwmac-loongson: Add GNET support Feiyang Chen
@ 2023-08-04 17:25 ` Jose Abreu
2023-08-05 6:14 ` Feiyang Chen
16 siblings, 1 reply; 25+ messages in thread
From: Jose Abreu @ 2023-08-04 17:25 UTC (permalink / raw)
To: Feiyang Chen, andrew, hkallweit1, peppe.cavallaro,
alexandre.torgue, chenhuacai
Cc: linux, dongbiao, loongson-kernel, netdev, loongarch,
chris.chenfeiyang, Jose Abreu
From: Feiyang Chen <chenfeiyang@loongson.cn>
Date: Thu, Aug 03, 2023 at 12:28:02
> Extend stmmac functions and macros for Loongson DWMAC.
> Add LS7A support for dwmac_loongson.
>
> v2 -> v3:
> * Avoid macros accessing variables that are not passed to them.
> * Implement a new struct to support 64-bit DMA.
> * Use feature names rather than 'lgmac' and 'dwmac_is_loongson'.
This is still mixing up with HWIF.
As I tried to highlight before, if you are using a custom IP,
you need custom callbacks.
As far as I saw, you are mixing dwmac1000_core with
Loongson registers, which is not what I believe is the best approach.
I understand that stmmac is confusing and needs a lot of revamp.
Perhaps we can switch to regmaps first? This way you would have
a lot more flexibility.
Thanks,
Jose
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC
2023-08-03 11:30 ` [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC Feiyang Chen
@ 2023-08-04 17:28 ` Jose Abreu
2023-08-05 6:15 ` Feiyang Chen
2023-08-04 20:38 ` Russell King (Oracle)
1 sibling, 1 reply; 25+ messages in thread
From: Jose Abreu @ 2023-08-04 17:28 UTC (permalink / raw)
To: Feiyang Chen, andrew, hkallweit1, peppe.cavallaro,
alexandre.torgue, chenhuacai
Cc: linux, dongbiao, loongson-kernel, netdev, loongarch,
chris.chenfeiyang, Jose Abreu
From: Feiyang Chen <chenfeiyang@loongson.cn>
Date: Thu, Aug 03, 2023 at 12:30:35
> --- a/include/linux/stmmac.h
> +++ b/include/linux/stmmac.h
> @@ -360,5 +360,6 @@ struct plat_stmmacenet_data {
> bool dma_reset_times;
> u32 control_value;
> u32 irq_flags;
> + bool disable_flow_control;
> };
> #endif
This (and other patches of this series) use a bool flag instead of the
Recently added bitfield flags, can you please switch to the bitfield flags?
Thanks,
Jose
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC
2023-08-03 11:30 ` [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC Feiyang Chen
2023-08-04 17:28 ` Jose Abreu
@ 2023-08-04 20:38 ` Russell King (Oracle)
2023-08-05 6:15 ` Feiyang Chen
1 sibling, 1 reply; 25+ messages in thread
From: Russell King (Oracle) @ 2023-08-04 20:38 UTC (permalink / raw)
To: Feiyang Chen
Cc: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
chenhuacai, dongbiao, loongson-kernel, netdev, loongarch,
chris.chenfeiyang
On Thu, Aug 03, 2023 at 07:30:35PM +0800, Feiyang Chen wrote:
> +
> + if (priv->plat->disable_flow_control) {
> + phy_support_sym_pause(dev->phydev);
> + phy_set_sym_pause(dev->phydev, false, false, true);
> + }
Given that stmmac uses phylink, control over the PHY is given over to
phylink to manage on the driver's behalf. Therefore, the above is not
very useful.
The correct way to deal with this is via
priv->phylink_config.mac_capabilities
in stmmac_phy_setup().
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 00/16] stmmac: Add Loongson platform support
2023-08-04 17:25 ` [PATCH v3 00/16] stmmac: Add Loongson platform support Jose Abreu
@ 2023-08-05 6:14 ` Feiyang Chen
0 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-05 6:14 UTC (permalink / raw)
To: Jose Abreu
Cc: Feiyang Chen, andrew, hkallweit1, peppe.cavallaro,
alexandre.torgue, chenhuacai, linux, dongbiao, loongson-kernel,
netdev, loongarch
On Sat, Aug 5, 2023 at 1:26 AM Jose Abreu <Jose.Abreu@synopsys.com> wrote:
>
> From: Feiyang Chen <chenfeiyang@loongson.cn>
> Date: Thu, Aug 03, 2023 at 12:28:02
>
> > Extend stmmac functions and macros for Loongson DWMAC.
> > Add LS7A support for dwmac_loongson.
> >
> > v2 -> v3:
> > * Avoid macros accessing variables that are not passed to them.
> > * Implement a new struct to support 64-bit DMA.
> > * Use feature names rather than 'lgmac' and 'dwmac_is_loongson'.
>
> This is still mixing up with HWIF.
>
> As I tried to highlight before, if you are using a custom IP,
> you need custom callbacks.
>
> As far as I saw, you are mixing dwmac1000_core with
> Loongson registers, which is not what I believe is the best approach.
>
Hi, Jose,
The problem we encounter is that we have three different layouts of
register maps. To avoid mixing up with HWIF, we should use three sets
of callbacks with rather similar logic. Maybe I can extract the common
code blocks to functions, create two additional sets of callbacks,
namely dwmac1000_loongson and dwmac1000_loongson64, and then have the
three sets share these functions?
> I understand that stmmac is confusing and needs a lot of revamp.
> Perhaps we can switch to regmaps first? This way you would have
> a lot more flexibility.
>
If we switch to regmaps, we still need three sets, and I think I need
to revamp more :)
Thanks,
Feiyang
> Thanks,
> Jose
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC
2023-08-04 17:28 ` Jose Abreu
@ 2023-08-05 6:15 ` Feiyang Chen
0 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-05 6:15 UTC (permalink / raw)
To: Jose Abreu
Cc: Feiyang Chen, andrew, hkallweit1, peppe.cavallaro,
alexandre.torgue, chenhuacai, linux, dongbiao, loongson-kernel,
netdev, loongarch
On Sat, Aug 5, 2023 at 1:29 AM Jose Abreu <Jose.Abreu@synopsys.com> wrote:
>
> From: Feiyang Chen <chenfeiyang@loongson.cn>
> Date: Thu, Aug 03, 2023 at 12:30:35
>
> > --- a/include/linux/stmmac.h
> > +++ b/include/linux/stmmac.h
> > @@ -360,5 +360,6 @@ struct plat_stmmacenet_data {
> > bool dma_reset_times;
> > u32 control_value;
> > u32 irq_flags;
> > + bool disable_flow_control;
> > };
> > #endif
>
> This (and other patches of this series) use a bool flag instead of the
> Recently added bitfield flags, can you please switch to the bitfield flags?
>
Hi, Jose,
OK.
Thanks,
Feiyang
> Thanks,
> Jose
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC
2023-08-04 20:38 ` Russell King (Oracle)
@ 2023-08-05 6:15 ` Feiyang Chen
0 siblings, 0 replies; 25+ messages in thread
From: Feiyang Chen @ 2023-08-05 6:15 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Feiyang Chen, andrew, hkallweit1, peppe.cavallaro,
alexandre.torgue, joabreu, chenhuacai, dongbiao, loongson-kernel,
netdev, loongarch
On Sat, Aug 5, 2023 at 4:38 AM Russell King (Oracle)
<linux@armlinux.org.uk> wrote:
>
> On Thu, Aug 03, 2023 at 07:30:35PM +0800, Feiyang Chen wrote:
> > +
> > + if (priv->plat->disable_flow_control) {
> > + phy_support_sym_pause(dev->phydev);
> > + phy_set_sym_pause(dev->phydev, false, false, true);
> > + }
>
> Given that stmmac uses phylink, control over the PHY is given over to
> phylink to manage on the driver's behalf. Therefore, the above is not
> very useful.
>
> The correct way to deal with this is via
> priv->phylink_config.mac_capabilities
>
> in stmmac_phy_setup().
Hi, Russell,
OK.
Thanks,
Feiyang
>
> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2023-08-05 6:16 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-03 11:28 [PATCH v3 00/16] stmmac: Add Loongson platform support Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 01/16] net: stmmac: Pass stmmac_priv and chan in some callbacks Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 02/16] net: stmmac: dwmac1000: Allow platforms to choose some register offsets Feiyang Chen
2023-08-03 11:28 ` [PATCH v3 03/16] net: stmmac: dwmac1000: Add multi-channel support Feiyang Chen
2023-08-03 11:29 ` [PATCH v3 04/16] net: stmmac: dwmac1000: Add 64-bit DMA support Feiyang Chen
2023-08-03 11:29 ` [PATCH v3 05/16] net: stmmac: dwmac1000: Add Loongson register definitions Feiyang Chen
2023-08-03 11:29 ` [PATCH v3 06/16] net: stmmac: dwmac1000: Fix channel numbers for Loongson Feiyang Chen
2023-08-03 11:29 ` [PATCH v3 07/16] net: stmmac: dwmac1000: Add multiple retries for DMA reset Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 08/16] net: stmmac: dwmac1000: Allow platforms to set control value Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 09/16] net: stmmac: Allow platforms to set irq_flags Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 10/16] net: stmmac: Add Loongson HWIF entry Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 11/16] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe() Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 12/16] net: stmmac: dwmac-loongson: Add LS7A support Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 13/16] net: stmmac: dwmac-loongson: Add 64-bit DMA and multi-vector support Feiyang Chen
2023-08-03 14:20 ` Russell King (Oracle)
2023-08-03 15:42 ` Andrew Lunn
2023-08-03 11:30 ` [PATCH v3 14/16] net: stmmac: dwmac-loongson: Disable flow control for GMAC Feiyang Chen
2023-08-04 17:28 ` Jose Abreu
2023-08-05 6:15 ` Feiyang Chen
2023-08-04 20:38 ` Russell King (Oracle)
2023-08-05 6:15 ` Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 15/16] net: stmmac: dwmac-loongson: Use single queue " Feiyang Chen
2023-08-03 11:30 ` [PATCH v3 16/16] net: stmmac: dwmac-loongson: Add GNET support Feiyang Chen
2023-08-04 17:25 ` [PATCH v3 00/16] stmmac: Add Loongson platform support Jose Abreu
2023-08-05 6:14 ` Feiyang Chen
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