* [PATCH v5 0/9] stmmac: Add Loongson platform support
@ 2023-11-10 9:08 Yanteng Si
2023-11-10 9:23 ` [PATCH v5 1/9] net: stmmac: Pass stmmac_priv and chan in some callbacks Yanteng Si
` (9 more replies)
0 siblings, 10 replies; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:08 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, loongson-kernel, netdev, loongarch,
chris.chenfeiyang
v4 -> v5:
* Remove an ugly and useless patch (fix channel number).
* Remove the non-standard dma64 driver code, and also remove
the HWIF entries, since the associated custom callbacks no
longer exist.
* Refer to Serge's suggestion: Update the dwmac1000_dma.c to
support the multi-DMA-channels controller setup.
See:
v4: <https://lore.kernel.org/loongarch/cover.1692696115.git.chenfeiyang@loongson.cn/>
v3: <https://lore.kernel.org/loongarch/cover.1691047285.git.chenfeiyang@loongson.cn/>
v2: <https://lore.kernel.org/loongarch/cover.1690439335.git.chenfeiyang@loongson.cn/>
v1: <https://lore.kernel.org/loongarch/cover.1689215889.git.chenfeiyang@loongson.cn/>
Yanteng Si (9):
net: stmmac: Pass stmmac_priv and chan in some callbacks
net: stmmac: Allow platforms to set irq_flags
net: stmmac: Add Loongson DWGMAC definitions
net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe()
net: stmmac: dwmac-loongson: Add full PCI support
net: stmmac: dwmac-loongson: Add MSI support
net: stmmac: dwmac-loongson: Add GNET support
net: stmmac: dwmac-loongson: Disable flow control for GMAC
net: stmmac: Disable coe for some Loongson GNET
.../net/ethernet/stmicro/stmmac/chain_mode.c | 5 +-
drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 324 ++++++++++++++----
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 +-
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 9 +-
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 71 +++-
.../ethernet/stmicro/stmmac/dwmac100_core.c | 9 +-
.../ethernet/stmicro/stmmac/dwmac100_dma.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 11 +-
.../ethernet/stmicro/stmmac/dwmac4_descs.c | 17 +-
.../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 +-
.../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac_dma.h | 62 +++-
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 44 +--
.../ethernet/stmicro/stmmac/dwxgmac2_core.c | 11 +-
.../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 17 +-
.../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 +-
.../net/ethernet/stmicro/stmmac/enh_desc.c | 17 +-
drivers/net/ethernet/stmicro/stmmac/hwif.c | 10 +-
drivers/net/ethernet/stmicro/stmmac/hwif.h | 71 ++--
.../net/ethernet/stmicro/stmmac/norm_desc.c | 17 +-
.../ethernet/stmicro/stmmac/stmmac_ethtool.c | 6 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 30 +-
include/linux/stmmac.h | 4 +
25 files changed, 563 insertions(+), 219 deletions(-)
--
2.31.4
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 1/9] net: stmmac: Pass stmmac_priv and chan in some callbacks
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
@ 2023-11-10 9:23 ` Yanteng Si
2023-11-13 15:16 ` Serge Semin
2023-11-10 9:25 ` [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags Yanteng Si
` (8 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:23 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Loongson GMAC and GNET have some special features. To prepare for that,
pass stmmac_priv and chan to more callbacks, and adjust the callbacks
accordingly.
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
.../net/ethernet/stmicro/stmmac/chain_mode.c | 5 +-
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 +++---
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 9 ++-
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 8 ++-
.../ethernet/stmicro/stmmac/dwmac100_core.c | 9 ++-
.../ethernet/stmicro/stmmac/dwmac100_dma.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 11 +--
.../ethernet/stmicro/stmmac/dwmac4_descs.c | 17 ++---
.../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 ++-
.../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac_dma.h | 5 +-
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 5 +-
.../ethernet/stmicro/stmmac/dwxgmac2_core.c | 11 +--
.../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 17 ++---
.../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 +--
.../net/ethernet/stmicro/stmmac/enh_desc.c | 17 ++---
drivers/net/ethernet/stmicro/stmmac/hwif.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/hwif.h | 71 ++++++++++---------
.../net/ethernet/stmicro/stmmac/norm_desc.c | 17 ++---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +-
21 files changed, 146 insertions(+), 110 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
index fb55efd52240..a95866871f3e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
+++ b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
@@ -95,8 +95,9 @@ static unsigned int is_jumbo_frm(int len, int enh_desc)
return ret;
}
-static void init_dma_chain(void *des, dma_addr_t phy_addr,
- unsigned int size, unsigned int extend_desc)
+static void init_dma_chain(struct stmmac_priv *priv, void *des,
+ dma_addr_t phy_addr, unsigned int size,
+ unsigned int extend_desc)
{
/*
* In chained mode the des3 points to the next element in the ring.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 137741b94122..2d3f0848cacb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -283,7 +283,7 @@ static const struct emac_variant emac_variant_h6 = {
/* sun8i_dwmac_dma_reset() - reset the EMAC
* Called from stmmac via stmmac_dma_ops->reset
*/
-static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
+static int sun8i_dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
writel(0, ioaddr + EMAC_RX_CTL1);
writel(0, ioaddr + EMAC_TX_CTL1);
@@ -298,7 +298,7 @@ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
/* sun8i_dwmac_dma_init() - initialize the EMAC
* Called from stmmac via stmmac_dma_ops->init
*/
-static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
+static void sun8i_dwmac_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
@@ -395,7 +395,8 @@ static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,
writel(v, ioaddr + EMAC_TX_CTL1);
}
-static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
+static void sun8i_dwmac_enable_dma_transmission(struct stmmac_priv *priv,
+ void __iomem *ioaddr, u32 chan)
{
u32 v;
@@ -643,7 +644,8 @@ static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
* All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
* If addr is NULL, clear the slot
*/
-static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
+static void sun8i_dwmac_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n)
{
@@ -664,7 +666,8 @@ static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
}
}
-static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
+static void sun8i_dwmac_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr,
unsigned int reg_n)
{
@@ -687,7 +690,8 @@ static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
return 1;
}
-static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
+static void sun8i_dwmac_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = hw->pcsr;
@@ -705,13 +709,13 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
} else if (macaddrs <= hw->unicast_filter_entries) {
if (!netdev_mc_empty(dev)) {
netdev_for_each_mc_addr(ha, dev) {
- sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
+ sun8i_dwmac_set_umac_addr(priv, hw, ha->addr, i);
i++;
}
}
if (!netdev_uc_empty(dev)) {
netdev_for_each_uc_addr(ha, dev) {
- sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
+ sun8i_dwmac_set_umac_addr(priv, hw, ha->addr, i);
i++;
}
}
@@ -723,7 +727,7 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
/* Disable unused address filter slots */
while (i < hw->unicast_filter_entries)
- sun8i_dwmac_set_umac_addr(hw, NULL, i++);
+ sun8i_dwmac_set_umac_addr(priv, hw, NULL, i++);
writel(v, ioaddr + EMAC_RX_FRM_FLT);
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 3927609abc44..b52793edf62f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -94,7 +94,8 @@ static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
reg_space[i] = readl(ioaddr + i * 4);
}
-static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
+static void dwmac1000_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n)
{
@@ -103,7 +104,8 @@ static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
GMAC_ADDR_LOW(reg_n));
}
-static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
+static void dwmac1000_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr,
unsigned int reg_n)
{
@@ -137,7 +139,8 @@ static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
ioaddr + GMAC_EXTHASH_BASE + regs * 4);
}
-static void dwmac1000_set_filter(struct mac_device_info *hw,
+static void dwmac1000_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index daf79cdbd3ec..ce0e6ca6f3a2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -16,7 +16,8 @@
#include "dwmac1000.h"
#include "dwmac_dma.h"
-static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
+static void dwmac1000_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_axi *axi)
{
u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
int i;
@@ -70,7 +71,7 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
writel(value, ioaddr + DMA_AXI_BUS_MODE);
}
-static void dwmac1000_dma_init(void __iomem *ioaddr,
+static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
@@ -223,7 +224,8 @@ static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
readl(ioaddr + DMA_BUS_MODE + i * 4);
}
-static int dwmac1000_get_hw_feature(void __iomem *ioaddr,
+static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
struct dma_features *dma_cap)
{
u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
index a6e8d7bd9588..c03623edeb75 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
@@ -59,7 +59,8 @@ static int dwmac100_irq_status(struct mac_device_info *hw,
return 0;
}
-static void dwmac100_set_umac_addr(struct mac_device_info *hw,
+static void dwmac100_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n)
{
@@ -67,7 +68,8 @@ static void dwmac100_set_umac_addr(struct mac_device_info *hw,
stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}
-static void dwmac100_get_umac_addr(struct mac_device_info *hw,
+static void dwmac100_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr,
unsigned int reg_n)
{
@@ -75,7 +77,8 @@ static void dwmac100_get_umac_addr(struct mac_device_info *hw,
stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}
-static void dwmac100_set_filter(struct mac_device_info *hw,
+static void dwmac100_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
index dea270f60cc3..105e7d4d798f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
@@ -18,7 +18,7 @@
#include "dwmac100.h"
#include "dwmac_dma.h"
-static void dwmac100_dma_init(void __iomem *ioaddr,
+static void dwmac100_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
/* Enable Application Access by writing to DMA CSR0 */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index c6ff1fa0e04d..5e9b393ad7b3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -335,7 +335,8 @@ static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
writel(pmt, ioaddr + GMAC_PMT);
}
-static void dwmac4_set_umac_addr(struct mac_device_info *hw,
+static void dwmac4_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr, unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
@@ -344,7 +345,8 @@ static void dwmac4_set_umac_addr(struct mac_device_info *hw,
GMAC_ADDR_LOW(reg_n));
}
-static void dwmac4_get_umac_addr(struct mac_device_info *hw,
+static void dwmac4_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr, unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
@@ -593,7 +595,8 @@ static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
}
}
-static void dwmac4_set_filter(struct mac_device_info *hw,
+static void dwmac4_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
@@ -669,7 +672,7 @@ static void dwmac4_set_filter(struct mac_device_info *hw,
int reg = 1;
netdev_for_each_uc_addr(ha, dev) {
- dwmac4_set_umac_addr(hw, ha->addr, reg);
+ dwmac4_set_umac_addr(priv, hw, ha->addr, reg);
reg++;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
index 89a14084c611..bd3084efc808 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
@@ -169,7 +169,7 @@ static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
return ret;
}
-static int dwmac4_rd_get_tx_len(struct dma_desc *p)
+static int dwmac4_rd_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
}
@@ -290,8 +290,8 @@ static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
return 0;
}
-static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
- int mode, int end, int bfsize)
+static void dwmac4_rd_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize)
{
dwmac4_set_rx_owner(p, disable_rx_ic);
}
@@ -304,9 +304,9 @@ static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
p->des3 = 0;
}
-static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own,
- bool ls, unsigned int tot_pkt_len)
+static void dwmac4_rd_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes3 = le32_to_cpu(p->des3);
@@ -456,13 +456,14 @@ static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
}
-static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
+static void dwmac4_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr)
{
p->des0 = cpu_to_le32(lower_32_bits(addr));
p->des1 = cpu_to_le32(upper_32_bits(addr));
}
-static void dwmac4_clear(struct dma_desc *p)
+static void dwmac4_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des0 = 0;
p->des1 = 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 84d3a8551b03..97dad00dc850 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -15,7 +15,8 @@
#include "dwmac4_dma.h"
#include "stmmac.h"
-static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
+static void dwmac4_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_axi *axi)
{
u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
int i;
@@ -152,7 +153,7 @@ static void dwmac410_dma_init_channel(struct stmmac_priv *priv,
ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}
-static void dwmac4_dma_init(void __iomem *ioaddr,
+static void dwmac4_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
@@ -374,7 +375,8 @@ static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv,
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
}
-static int dwmac4_get_hw_feature(void __iomem *ioaddr,
+static int dwmac4_get_hw_feature(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
struct dma_features *dma_cap)
{
u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
index 358e7dcb6a9a..aaab5ab38373 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
@@ -231,7 +231,7 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
#define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
#define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
-int dwmac4_dma_reset(void __iomem *ioaddr);
+int dwmac4_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx);
void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
index 9470d3fd2ded..1191f0c1d7f1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
@@ -13,7 +13,7 @@
#include "dwmac4.h"
#include "stmmac.h"
-int dwmac4_dma_reset(void __iomem *ioaddr)
+int dwmac4_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
index 72672391675f..77141391bd2f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
@@ -152,7 +152,8 @@
#define NUM_DWMAC1000_DMA_REGS 23
#define NUM_DWMAC4_DMA_REGS 27
-void dwmac_enable_dma_transmission(void __iomem *ioaddr);
+void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
+ void __iomem *ioaddr, u32 chan);
void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx);
void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
@@ -167,6 +168,6 @@ void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan);
int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan, u32 dir);
-int dwmac_dma_reset(void __iomem *ioaddr);
+int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
#endif /* __DWMAC_DMA_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index 7907d62d3437..0cb337ffb7ac 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -14,7 +14,7 @@
#define GMAC_HI_REG_AE 0x80000000
-int dwmac_dma_reset(void __iomem *ioaddr)
+int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
u32 value = readl(ioaddr + DMA_BUS_MODE);
@@ -28,7 +28,8 @@ int dwmac_dma_reset(void __iomem *ioaddr)
}
/* CSR1 enables the transmit DMA to check for new descriptor */
-void dwmac_enable_dma_transmission(void __iomem *ioaddr)
+void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
+ void __iomem *ioaddr, u32 chan)
{
writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index 453e88b75be0..a993591e05bd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -375,7 +375,8 @@ static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
writel(val, ioaddr + XGMAC_PMT);
}
-static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
+static void dwxgmac2_set_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n)
{
@@ -389,7 +390,8 @@ static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
}
-static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
+static void dwxgmac2_get_umac_addr(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
unsigned char *addr, unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
@@ -478,7 +480,8 @@ static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
}
-static void dwxgmac2_set_filter(struct mac_device_info *hw,
+static void dwxgmac2_set_filter(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
@@ -523,7 +526,7 @@ static void dwxgmac2_set_filter(struct mac_device_info *hw,
int reg = 1;
netdev_for_each_uc_addr(ha, dev) {
- dwxgmac2_set_umac_addr(hw, ha->addr, reg);
+ dwxgmac2_set_umac_addr(priv, hw, ha->addr, reg);
reg++;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
index fc82862a612c..cefcbabab2c0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
@@ -39,7 +39,7 @@ static int dwxgmac2_get_rx_status(struct stmmac_extra_stats *x,
return good_frame;
}
-static int dwxgmac2_get_tx_len(struct dma_desc *p)
+static int dwxgmac2_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
}
@@ -126,8 +126,8 @@ static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
return !ret;
}
-static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
- int mode, int end, int bfsize)
+static void dwxgmac2_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize)
{
dwxgmac2_set_rx_owner(p, disable_rx_ic);
}
@@ -140,9 +140,9 @@ static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)
p->des3 = 0;
}
-static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own,
- bool ls, unsigned int tot_pkt_len)
+static void dwxgmac2_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes3 = le32_to_cpu(p->des3);
@@ -239,13 +239,14 @@ static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)
p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
}
-static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
+static void dwxgmac2_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr)
{
p->des0 = cpu_to_le32(lower_32_bits(addr));
p->des1 = cpu_to_le32(upper_32_bits(addr));
}
-static void dwxgmac2_clear(struct dma_desc *p)
+static void dwxgmac2_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des0 = 0;
p->des1 = 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index 3cde695fec91..4d1dc6d7eacb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -8,7 +8,7 @@
#include "stmmac.h"
#include "dwxgmac2.h"
-static int dwxgmac2_dma_reset(void __iomem *ioaddr)
+static int dwxgmac2_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
u32 value = readl(ioaddr + XGMAC_DMA_MODE);
@@ -19,7 +19,7 @@ static int dwxgmac2_dma_reset(void __iomem *ioaddr)
!(value & XGMAC_SWR), 0, 100000);
}
-static void dwxgmac2_dma_init(void __iomem *ioaddr,
+static void dwxgmac2_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds)
{
u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
@@ -81,7 +81,8 @@ static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv,
writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
}
-static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
+static void dwxgmac2_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_axi *axi)
{
u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
int i;
@@ -386,7 +387,8 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv,
return ret;
}
-static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
+static int dwxgmac2_get_hw_feature(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
struct dma_features *dma_cap)
{
u32 hw_cap;
diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
index 937b7a0466fc..43ae8c7defe1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
@@ -76,7 +76,7 @@ static int enh_desc_get_tx_status(struct stmmac_extra_stats *x,
return ret;
}
-static int enh_desc_get_tx_len(struct dma_desc *p)
+static int enh_desc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);
}
@@ -249,8 +249,8 @@ static int enh_desc_get_rx_status(struct stmmac_extra_stats *x,
return ret;
}
-static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
- int mode, int end, int bfsize)
+static void enh_desc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize)
{
int bfsize1;
@@ -308,9 +308,9 @@ static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
enh_desc_end_tx_desc_on_ring(p, ter);
}
-static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own,
- bool ls, unsigned int tot_pkt_len)
+static void enh_desc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes0 = le32_to_cpu(p->des0);
@@ -435,12 +435,13 @@ static void enh_desc_display_ring(void *head, unsigned int size, bool rx,
pr_info("\n");
}
-static void enh_desc_set_addr(struct dma_desc *p, dma_addr_t addr)
+static void enh_desc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr)
{
p->des2 = cpu_to_le32(addr);
}
-static void enh_desc_clear(struct dma_desc *p)
+static void enh_desc_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des2 = 0;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index b8ba8f2d8041..93cead5613e3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -97,7 +97,7 @@ int stmmac_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
if (plat && plat->fix_soc_reset)
return plat->fix_soc_reset(plat, ioaddr);
- return stmmac_do_callback(priv, dma, reset, ioaddr);
+ return stmmac_do_callback(priv, dma, reset, priv, ioaddr);
}
static const struct stmmac_hwif_entry {
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
index b95d3e137813..fd63713fcaa1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
@@ -35,14 +35,14 @@ struct dma_edesc;
/* Descriptors helpers */
struct stmmac_desc_ops {
/* DMA RX descriptor ring initialization */
- void (*init_rx_desc)(struct dma_desc *p, int disable_rx_ic, int mode,
- int end, int bfsize);
+ void (*init_rx_desc)(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize);
/* DMA TX descriptor ring initialization */
void (*init_tx_desc)(struct dma_desc *p, int mode, int end);
/* Invoked by the xmit function to prepare the tx descriptor */
- void (*prepare_tx_desc)(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own, bool ls,
- unsigned int tot_pkt_len);
+ void (*prepare_tx_desc)(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len);
void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
int len2, bool tx_own, bool ls, unsigned int tcphdrlen,
unsigned int tcppayloadlen);
@@ -60,7 +60,7 @@ struct stmmac_desc_ops {
int (*tx_status)(struct stmmac_extra_stats *x,
struct dma_desc *p, void __iomem *ioaddr);
/* Get the buffer size from the descriptor */
- int (*get_tx_len)(struct dma_desc *p);
+ int (*get_tx_len)(struct stmmac_priv *priv, struct dma_desc *p);
/* Handle extra events on specific interrupts hw dependent */
void (*set_rx_owner)(struct dma_desc *p, int disable_rx_ic);
/* Get the receive frame size */
@@ -84,9 +84,10 @@ struct stmmac_desc_ops {
/* set MSS via context descriptor */
void (*set_mss)(struct dma_desc *p, unsigned int mss);
/* set descriptor skbuff address */
- void (*set_addr)(struct dma_desc *p, dma_addr_t addr);
+ void (*set_addr)(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr);
/* clear descriptor */
- void (*clear)(struct dma_desc *p);
+ void (*clear)(struct stmmac_priv *priv, struct dma_desc *p);
/* RSS */
int (*get_rx_hash)(struct dma_desc *p, u32 *hash,
enum pkt_hash_types *type);
@@ -100,11 +101,11 @@ struct stmmac_desc_ops {
};
#define stmmac_init_rx_desc(__priv, __args...) \
- stmmac_do_void_callback(__priv, desc, init_rx_desc, __args)
+ stmmac_do_void_callback(__priv, desc, init_rx_desc, __priv, __args)
#define stmmac_init_tx_desc(__priv, __args...) \
stmmac_do_void_callback(__priv, desc, init_tx_desc, __args)
#define stmmac_prepare_tx_desc(__priv, __args...) \
- stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __args)
+ stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __priv, __args)
#define stmmac_prepare_tso_tx_desc(__priv, __args...) \
stmmac_do_void_callback(__priv, desc, prepare_tso_tx_desc, __args)
#define stmmac_set_tx_owner(__priv, __args...) \
@@ -120,7 +121,7 @@ struct stmmac_desc_ops {
#define stmmac_tx_status(__priv, __args...) \
stmmac_do_callback(__priv, desc, tx_status, __args)
#define stmmac_get_tx_len(__priv, __args...) \
- stmmac_do_callback(__priv, desc, get_tx_len, __args)
+ stmmac_do_callback(__priv, desc, get_tx_len, __priv, __args)
#define stmmac_set_rx_owner(__priv, __args...) \
stmmac_do_void_callback(__priv, desc, set_rx_owner, __args)
#define stmmac_get_rx_frame_len(__priv, __args...) \
@@ -142,9 +143,9 @@ struct stmmac_desc_ops {
#define stmmac_set_mss(__priv, __args...) \
stmmac_do_void_callback(__priv, desc, set_mss, __args)
#define stmmac_set_desc_addr(__priv, __args...) \
- stmmac_do_void_callback(__priv, desc, set_addr, __args)
+ stmmac_do_void_callback(__priv, desc, set_addr, __priv, __args)
#define stmmac_clear_desc(__priv, __args...) \
- stmmac_do_void_callback(__priv, desc, clear, __args)
+ stmmac_do_void_callback(__priv, desc, clear, __priv, __args)
#define stmmac_get_rx_hash(__priv, __args...) \
stmmac_do_callback(__priv, desc, get_rx_hash, __args)
#define stmmac_get_rx_header_len(__priv, __args...) \
@@ -166,9 +167,9 @@ struct dma_features;
/* Specific DMA helpers */
struct stmmac_dma_ops {
/* DMA core initialization */
- int (*reset)(void __iomem *ioaddr);
- void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
- int atds);
+ int (*reset)(struct stmmac_priv *priv, void __iomem *ioaddr);
+ void (*init)(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg, int atds);
void (*init_chan)(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, u32 chan);
void (*init_rx_chan)(struct stmmac_priv *priv, void __iomem *ioaddr,
@@ -178,7 +179,8 @@ struct stmmac_dma_ops {
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t phy, u32 chan);
/* Configure the AXI Bus Mode Register */
- void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
+ void (*axi)(struct stmmac_priv *priv, void __iomem *ioaddr,
+ struct stmmac_axi *axi);
/* Dump DMA registers */
void (*dump_regs)(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 *reg_space);
@@ -190,7 +192,8 @@ struct stmmac_dma_ops {
/* To track extra statistic (if supported) */
void (*dma_diagnostic_fr)(struct stmmac_extra_stats *x,
void __iomem *ioaddr);
- void (*enable_dma_transmission) (void __iomem *ioaddr);
+ void (*enable_dma_transmission)(struct stmmac_priv *priv,
+ void __iomem *ioaddr, u32 chan);
void (*enable_dma_irq)(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx);
void (*disable_dma_irq)(struct stmmac_priv *priv, void __iomem *ioaddr,
@@ -206,7 +209,7 @@ struct stmmac_dma_ops {
int (*dma_interrupt)(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan, u32 dir);
/* If supported then get the optional core features */
- int (*get_hw_feature)(void __iomem *ioaddr,
+ int (*get_hw_feature)(struct stmmac_priv *priv, void __iomem *ioaddr,
struct dma_features *dma_cap);
/* Program the HW RX Watchdog */
void (*rx_watchdog)(struct stmmac_priv *priv, void __iomem *ioaddr,
@@ -232,7 +235,7 @@ struct stmmac_dma_ops {
};
#define stmmac_dma_init(__priv, __args...) \
- stmmac_do_void_callback(__priv, dma, init, __args)
+ stmmac_do_void_callback(__priv, dma, init, __priv, __args)
#define stmmac_init_chan(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, init_chan, __priv, __args)
#define stmmac_init_rx_chan(__priv, __args...) \
@@ -240,7 +243,7 @@ struct stmmac_dma_ops {
#define stmmac_init_tx_chan(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, init_tx_chan, __priv, __args)
#define stmmac_axi(__priv, __args...) \
- stmmac_do_void_callback(__priv, dma, axi, __args)
+ stmmac_do_void_callback(__priv, dma, axi, __priv, __args)
#define stmmac_dump_dma_regs(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, dump_regs, __priv, __args)
#define stmmac_dma_rx_mode(__priv, __args...) \
@@ -250,7 +253,7 @@ struct stmmac_dma_ops {
#define stmmac_dma_diagnostic_fr(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, dma_diagnostic_fr, __args)
#define stmmac_enable_dma_transmission(__priv, __args...) \
- stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __args)
+ stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __priv, __args)
#define stmmac_enable_dma_irq(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, enable_dma_irq, __priv, __args)
#define stmmac_disable_dma_irq(__priv, __args...) \
@@ -266,7 +269,7 @@ struct stmmac_dma_ops {
#define stmmac_dma_interrupt_status(__priv, __args...) \
stmmac_do_callback(__priv, dma, dma_interrupt, __priv, __args)
#define stmmac_get_hw_feature(__priv, __args...) \
- stmmac_do_callback(__priv, dma, get_hw_feature, __args)
+ stmmac_do_callback(__priv, dma, get_hw_feature, __priv, __args)
#define stmmac_rx_watchdog(__priv, __args...) \
stmmac_do_void_callback(__priv, dma, rx_watchdog, __priv, __args)
#define stmmac_set_tx_ring_len(__priv, __args...) \
@@ -338,17 +341,21 @@ struct stmmac_ops {
int (*host_mtl_irq_status)(struct stmmac_priv *priv,
struct mac_device_info *hw, u32 chan);
/* Multicast filter setting */
- void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
+ void (*set_filter)(struct stmmac_priv *priv, struct mac_device_info *hw,
+ struct net_device *dev);
/* Flow control setting */
void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time, u32 tx_cnt);
/* Set power management mode (e.g. magic frame) */
void (*pmt)(struct mac_device_info *hw, unsigned long mode);
/* Set/Get Unicast MAC addresses */
- void (*set_umac_addr)(struct mac_device_info *hw,
+ void (*set_umac_addr)(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
const unsigned char *addr,
unsigned int reg_n);
- void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
+ void (*get_umac_addr)(struct stmmac_priv *priv,
+ struct mac_device_info *hw,
+ unsigned char *addr,
unsigned int reg_n);
void (*set_eee_mode)(struct mac_device_info *hw,
bool en_tx_lpi_clockgating);
@@ -452,15 +459,15 @@ struct stmmac_ops {
#define stmmac_host_mtl_irq_status(__priv, __args...) \
stmmac_do_callback(__priv, mac, host_mtl_irq_status, __priv, __args)
#define stmmac_set_filter(__priv, __args...) \
- stmmac_do_void_callback(__priv, mac, set_filter, __args)
+ stmmac_do_void_callback(__priv, mac, set_filter, __priv, __args)
#define stmmac_flow_ctrl(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, flow_ctrl, __args)
#define stmmac_pmt(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, pmt, __args)
#define stmmac_set_umac_addr(__priv, __args...) \
- stmmac_do_void_callback(__priv, mac, set_umac_addr, __args)
+ stmmac_do_void_callback(__priv, mac, set_umac_addr, __priv, __args)
#define stmmac_get_umac_addr(__priv, __args...) \
- stmmac_do_void_callback(__priv, mac, get_umac_addr, __args)
+ stmmac_do_void_callback(__priv, mac, get_umac_addr, __priv, __args)
#define stmmac_set_eee_mode(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, set_eee_mode, __args)
#define stmmac_reset_eee_mode(__priv, __args...) \
@@ -563,8 +570,8 @@ struct stmmac_rx_queue;
/* Helpers to manage the descriptors for chain and ring modes */
struct stmmac_mode_ops {
- void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
- unsigned int extend_desc);
+ void (*init)(struct stmmac_priv *priv, void *des, dma_addr_t phy_addr,
+ unsigned int size, unsigned int extend_desc);
unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
int (*jumbo_frm)(struct stmmac_tx_queue *tx_q, struct sk_buff *skb,
int csum);
@@ -575,7 +582,7 @@ struct stmmac_mode_ops {
};
#define stmmac_mode_init(__priv, __args...) \
- stmmac_do_void_callback(__priv, mode, init, __args)
+ stmmac_do_void_callback(__priv, mode, init, __priv, __args)
#define stmmac_is_jumbo_frm(__priv, __args...) \
stmmac_do_callback(__priv, mode, is_jumbo_frm, __args)
#define stmmac_jumbo_frm(__priv, __args...) \
diff --git a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
index 68a7cfcb1d8f..5fb3103db5cd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
@@ -57,7 +57,7 @@ static int ndesc_get_tx_status(struct stmmac_extra_stats *x,
return ret;
}
-static int ndesc_get_tx_len(struct dma_desc *p)
+static int ndesc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
{
return (le32_to_cpu(p->des1) & RDES1_BUFFER1_SIZE_MASK);
}
@@ -115,8 +115,8 @@ static int ndesc_get_rx_status(struct stmmac_extra_stats *x,
return ret;
}
-static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
- int end, int bfsize)
+static void ndesc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int disable_rx_ic, int mode, int end, int bfsize)
{
int bfsize1;
@@ -174,9 +174,9 @@ static void ndesc_release_tx_desc(struct dma_desc *p, int mode)
ndesc_end_tx_desc_on_ring(p, ter);
}
-static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
- bool csum_flag, int mode, bool tx_own,
- bool ls, unsigned int tot_pkt_len)
+static void ndesc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
+ int is_fs, int len, bool csum_flag, int mode,
+ bool tx_own, bool ls, unsigned int tot_pkt_len)
{
unsigned int tdes1 = le32_to_cpu(p->des1);
@@ -285,12 +285,13 @@ static void ndesc_display_ring(void *head, unsigned int size, bool rx,
pr_info("\n");
}
-static void ndesc_set_addr(struct dma_desc *p, dma_addr_t addr)
+static void ndesc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
+ dma_addr_t addr)
{
p->des2 = cpu_to_le32(addr);
}
-static void ndesc_clear(struct dma_desc *p)
+static void ndesc_clear(struct stmmac_priv *priv, struct dma_desc *p)
{
p->des2 = 0;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 3e50fd53a617..132d4f679b95 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2509,7 +2509,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
true, priv->mode, true, true,
xdp_desc.len);
- stmmac_enable_dma_transmission(priv, priv->ioaddr);
+ stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
entry = tx_q->cur_tx;
@@ -4615,7 +4615,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
- stmmac_enable_dma_transmission(priv, priv->ioaddr);
+ stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
stmmac_flush_tx_descriptors(priv, queue);
stmmac_tx_timer_arm(priv, queue);
@@ -4835,7 +4835,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
}
- stmmac_enable_dma_transmission(priv, priv->ioaddr);
+ stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
tx_q->cur_tx = entry;
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
2023-11-10 9:23 ` [PATCH v5 1/9] net: stmmac: Pass stmmac_priv and chan in some callbacks Yanteng Si
@ 2023-11-10 9:25 ` Yanteng Si
2023-11-11 19:51 ` Andrew Lunn
2023-11-10 9:25 ` [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions Yanteng Si
` (7 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:25 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Some platforms need extra irq flags when request multi msi, add
irq_flags variable for them.
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 16 +++++++++-------
include/linux/stmmac.h | 1 +
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 132d4f679b95..7371713c116d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3552,7 +3552,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
int_name = priv->int_name_mac;
sprintf(int_name, "%s:%s", dev->name, "mac");
ret = request_irq(dev->irq, stmmac_mac_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc mac MSI %d (error: %d)\n",
@@ -3569,7 +3569,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s", dev->name, "wol");
ret = request_irq(priv->wol_irq,
stmmac_mac_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc wol MSI %d (error: %d)\n",
@@ -3587,7 +3587,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s", dev->name, "lpi");
ret = request_irq(priv->lpi_irq,
stmmac_mac_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc lpi MSI %d (error: %d)\n",
@@ -3605,7 +3605,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s", dev->name, "safety-ce");
ret = request_irq(priv->sfty_ce_irq,
stmmac_safety_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc sfty ce MSI %d (error: %d)\n",
@@ -3623,7 +3623,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s", dev->name, "safety-ue");
ret = request_irq(priv->sfty_ue_irq,
stmmac_safety_interrupt,
- 0, int_name, dev);
+ priv->plat->irq_flags, int_name, dev);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc sfty ue MSI %d (error: %d)\n",
@@ -3644,7 +3644,8 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
ret = request_irq(priv->rx_irq[i],
stmmac_msi_intr_rx,
- 0, int_name, &priv->dma_conf.rx_queue[i]);
+ priv->plat->irq_flags, int_name,
+ &priv->dma_conf.rx_queue[i]);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc rx-%d MSI %d (error: %d)\n",
@@ -3669,7 +3670,8 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
ret = request_irq(priv->tx_irq[i],
stmmac_msi_intr_tx,
- 0, int_name, &priv->dma_conf.tx_queue[i]);
+ priv->plat->irq_flags, int_name,
+ &priv->dma_conf.tx_queue[i]);
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc tx-%d MSI %d (error: %d)\n",
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 0b4658a7eceb..664a0e1cefc2 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -312,5 +312,6 @@ struct plat_stmmacenet_data {
int msi_tx_base_vec;
const struct dwmac4_addrs *dwmac4_addrs;
unsigned int flags;
+ unsigned int irq_flags;
};
#endif
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
2023-11-10 9:23 ` [PATCH v5 1/9] net: stmmac: Pass stmmac_priv and chan in some callbacks Yanteng Si
2023-11-10 9:25 ` [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags Yanteng Si
@ 2023-11-10 9:25 ` Yanteng Si
2023-11-11 20:07 ` Andrew Lunn
2023-11-13 15:05 ` Serge Semin
2023-11-10 9:25 ` [PATCH v5 4/9] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe() Yanteng Si
` (6 subsequent siblings)
9 siblings, 2 replies; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:25 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Loongson platforms use a DWGMAC which supports multi-channel.
There are two types of Loongson DWGMAC. The first type shares the same
register definitions and has similar logic as dwmac1000. The second type
uses several different register definitions.
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 63 ++++++++++++++++---
.../net/ethernet/stmicro/stmmac/dwmac_dma.h | 57 ++++++++++++++++-
.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 39 ++++++------
drivers/net/ethernet/stmicro/stmmac/hwif.c | 3 +-
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +
6 files changed, 133 insertions(+), 32 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index e3f650e88f82..e01584fe9efa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -34,6 +34,7 @@
#define DWMAC_CORE_5_00 0x50
#define DWMAC_CORE_5_10 0x51
#define DWMAC_CORE_5_20 0x52
+#define DWGMAC_CORE_1_00 0x10
#define DWXGMAC_CORE_2_10 0x21
#define DWXGMAC_CORE_2_20 0x22
#define DWXLGMAC_CORE_2_00 0x20
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index ce0e6ca6f3a2..234d30c5a836 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -12,7 +12,8 @@
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/
-#include <asm/io.h>
+#include <linux/io.h>
+#include "stmmac.h"
#include "dwmac1000.h"
#include "dwmac_dma.h"
@@ -111,13 +112,58 @@ static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
}
+static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg, u32 chan)
+{
+ u32 value;
+ int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
+ int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
+
+ if (!(priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN))
+ return;
+
+ /* common channel control register config */
+ value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan));
+
+ /* Set the DMA PBL (Programmable Burst Length) mode.
+ *
+ * Note: before stmmac core 3.50 this mode bit was 4xPBL, and
+ * post 3.5 mode bit acts as 8*PBL.
+ */
+ if (dma_cfg->pblx8)
+ value |= DMA_BUS_MODE_MAXPBL;
+ value |= DMA_BUS_MODE_USP;
+ value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
+ value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
+ value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
+
+ /* Set the Fixed burst mode */
+ if (dma_cfg->fixed_burst)
+ value |= DMA_BUS_MODE_FB;
+
+ /* Mixed Burst has no effect when fb is set */
+ if (dma_cfg->mixed_burst)
+ value |= DMA_BUS_MODE_MB;
+
+ value |= DMA_BUS_MODE_ATDS;
+
+ if (dma_cfg->aal)
+ value |= DMA_BUS_MODE_AAL;
+
+ writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
+
+ /* Mask interrupts by writing to CSR7 */
+ writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(chan));
+}
+
static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg,
dma_addr_t dma_rx_phy, u32 chan)
{
/* RX descriptor base address list must be written into DMA CSR3 */
- writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
+ writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RCV_BASE_ADDR(chan));
}
static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
@@ -126,7 +172,7 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
dma_addr_t dma_tx_phy, u32 chan)
{
/* TX descriptor base address list must be written into DMA CSR4 */
- writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
+ writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
}
static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
@@ -154,7 +200,7 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
void __iomem *ioaddr, int mode,
u32 channel, int fifosz, u8 qmode)
{
- u32 csr6 = readl(ioaddr + DMA_CONTROL);
+ u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
if (mode == SF_DMA_MODE) {
pr_debug("GMAC: enable RX store and forward mode\n");
@@ -176,14 +222,14 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
/* Configure flow control based on rx fifo size */
csr6 = dwmac1000_configure_fc(csr6, fifosz);
- writel(csr6, ioaddr + DMA_CONTROL);
+ writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
}
static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
void __iomem *ioaddr, int mode,
u32 channel, int fifosz, u8 qmode)
{
- u32 csr6 = readl(ioaddr + DMA_CONTROL);
+ u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
if (mode == SF_DMA_MODE) {
pr_debug("GMAC: enable TX store and forward mode\n");
@@ -210,7 +256,7 @@ static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
csr6 |= DMA_CONTROL_TTC_256;
}
- writel(csr6, ioaddr + DMA_CONTROL);
+ writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
}
static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
@@ -273,12 +319,13 @@ static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
static void dwmac1000_rx_watchdog(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 riwt, u32 queue)
{
- writel(riwt, ioaddr + DMA_RX_WATCHDOG);
+ writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
}
const struct stmmac_dma_ops dwmac1000_dma_ops = {
.reset = dwmac_dma_reset,
.init = dwmac1000_dma_init,
+ .init_chan = dwmac1000_dma_init_channel,
.init_rx_chan = dwmac1000_dma_init_rx,
.init_tx_chan = dwmac1000_dma_init_tx,
.axi = dwmac1000_dma_axi,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
index 77141391bd2f..90464e1c9649 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
@@ -76,8 +76,15 @@
#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
+#define DMA_INTR_ENA_NIE_LOONGSON 0x00060000 /* Loongson Normal Summary */
+
+#ifdef CONFIG_DWMAC_LOONGSON
+#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE_LOONGSON | DMA_INTR_ENA_NIE | \
+ DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE)
+#else
#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
DMA_INTR_ENA_TIE)
+#endif
/* DMA Abnormal interrupt */
#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
@@ -91,8 +98,15 @@
#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
+#define DMA_INTR_ENA_AIE_LOONGSON 0x00018000 /* Loongson Abnormal Summary */
+
+#ifdef CONFIG_DWMAC_LOONGSON
+#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE_LOONGSON | DMA_INTR_ENA_AIE | \
+ DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
+#else
#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
DMA_INTR_ENA_UNE)
+#endif
/* DMA default interrupt mask */
#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
@@ -128,9 +142,29 @@
#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
-#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
- DMA_STATUS_AIS | \
- DMA_STATUS_FBI)
+#define DMA_STATUS_TX_NIS_LOONGSON 0x00040000 /* Normal Tx Interrupt Summary */
+#define DMA_STATUS_RX_NIS_LOONGSON 0x00020000 /* Normal Rx Interrupt Summary */
+#define DMA_STATUS_TX_AIS_LOONGSON 0x00010000 /* Abnormal Tx Interrupt Summary */
+#define DMA_STATUS_RX_AIS_LOONGSON 0x00008000 /* Abnormal Rx Interrupt Summary */
+#define DMA_STATUS_TX_FBI_LOONGSON 0x00002000 /* Fatal Tx Bus Error Interrupt */
+#define DMA_STATUS_RX_FBI_LOONGSON 0x00001000 /* Fatal Rx Bus Error Interrupt */
+
+#ifdef CONFIG_DWMAC_LOONGSON
+#define DMA_NOR_INTR_STATUS (DMA_STATUS_TX_NIS_LOONGSON | DMA_STATUS_RX_NIS_LOONGSON)
+#define DMA_ABNOR_INTR_STATUS (DMA_STATUS_TX_AIS_LOONGSON | DMA_STATUS_RX_AIS_LOONGSON)
+#define DMA_FB_INTR_STATUS (DMA_STATUS_TX_FBI_LOONGSON | DMA_STATUS_RX_FBI_LOONGSON)
+#else
+#define DMA_NOR_INTR_STATUS DMA_STATUS_NIS
+#define DMA_ABNOR_INTR_STATUS DMA_STATUS_AIS
+#define DMA_FB_INTR_STATUS DMA_STATUS_FBI
+#endif
+
+#define DMA_INTR_STATUS (DMA_STATUS_GPI | \
+ DMA_STATUS_GMI | \
+ DMA_STATUS_GLI)
+#define DMA_STATUS_MSK_COMMON (DMA_NOR_INTR_STATUS | \
+ DMA_ABNOR_INTR_STATUS | \
+ DMA_FB_INTR_STATUS)
#define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
DMA_STATUS_RWT | \
@@ -148,6 +182,9 @@
DMA_STATUS_TI | \
DMA_STATUS_MSK_COMMON)
+/* Following DMA defines are chanels oriented */
+#define DMA_CHAN_OFFSET 0x100
+
#define NUM_DWMAC100_DMA_REGS 9
#define NUM_DWMAC1000_DMA_REGS 23
#define NUM_DWMAC4_DMA_REGS 27
@@ -170,4 +207,18 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan, u32 dir);
int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
+static inline u32 dma_chan_base_addr(u32 base, u32 chan)
+{
+ return base + chan * DMA_CHAN_OFFSET;
+}
+
+#define DMA_CHAN_XMT_POLL_DEMAND(chan) dma_chan_base_addr(DMA_XMT_POLL_DEMAND, chan)
+#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
+#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
+#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
+#define DMA_CHAN_BUS_MODE(chan) dma_chan_base_addr(DMA_BUS_MODE, chan)
+#define DMA_CHAN_RCV_BASE_ADDR(chan) dma_chan_base_addr(DMA_RCV_BASE_ADDR, chan)
+#define DMA_CHAN_TX_BASE_ADDR(chan) dma_chan_base_addr(DMA_TX_BASE_ADDR, chan)
+#define DMA_CHAN_RX_WATCHDOG(chan) dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
+
#endif /* __DWMAC_DMA_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index 0cb337ffb7ac..c36aec97bbb5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -31,63 +31,63 @@ int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
void __iomem *ioaddr, u32 chan)
{
- writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
+ writel(1, ioaddr + DMA_CHAN_XMT_POLL_DEMAND(chan));
}
void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx)
{
- u32 value = readl(ioaddr + DMA_INTR_ENA);
+ u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
if (rx)
value |= DMA_INTR_DEFAULT_RX;
if (tx)
value |= DMA_INTR_DEFAULT_TX;
- writel(value, ioaddr + DMA_INTR_ENA);
+ writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
}
void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx)
{
- u32 value = readl(ioaddr + DMA_INTR_ENA);
+ u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
if (rx)
value &= ~DMA_INTR_DEFAULT_RX;
if (tx)
value &= ~DMA_INTR_DEFAULT_TX;
- writel(value, ioaddr + DMA_INTR_ENA);
+ writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
}
void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
value |= DMA_CONTROL_ST;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
}
void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
value &= ~DMA_CONTROL_ST;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
}
void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
value |= DMA_CONTROL_SR;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
}
void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
{
- u32 value = readl(ioaddr + DMA_CONTROL);
+ u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
value &= ~DMA_CONTROL_SR;
- writel(value, ioaddr + DMA_CONTROL);
+ writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
}
#ifdef DWMAC_DMA_DEBUG
@@ -167,7 +167,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan];
int ret = 0;
/* read the status register (CSR5) */
- u32 intr_status = readl(ioaddr + DMA_STATUS);
+ u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
#ifdef DWMAC_DMA_DEBUG
/* Enable it to monitor DMA rx/tx status in case of critical problems */
@@ -182,7 +182,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
intr_status &= DMA_STATUS_MSK_TX;
/* ABNORMAL interrupts */
- if (unlikely(intr_status & DMA_STATUS_AIS)) {
+ if (unlikely(intr_status & DMA_ABNOR_INTR_STATUS)) {
if (unlikely(intr_status & DMA_STATUS_UNF)) {
ret = tx_hard_error_bump_tc;
x->tx_undeflow_irq++;
@@ -205,13 +205,13 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
x->tx_process_stopped_irq++;
ret = tx_hard_error;
}
- if (unlikely(intr_status & DMA_STATUS_FBI)) {
+ if (unlikely(intr_status & DMA_FB_INTR_STATUS)) {
x->fatal_bus_error_irq++;
ret = tx_hard_error;
}
}
/* TX/RX NORMAL interrupts */
- if (likely(intr_status & DMA_STATUS_NIS)) {
+ if (likely(intr_status & DMA_NOR_INTR_STATUS)) {
if (likely(intr_status & DMA_STATUS_RI)) {
u32 value = readl(ioaddr + DMA_INTR_ENA);
/* to schedule NAPI on real RIE event. */
@@ -232,12 +232,11 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
x->rx_early_irq++;
}
/* Optional hardware blocks, interrupts should be disabled */
- if (unlikely(intr_status &
- (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
+ if (unlikely(intr_status & DMA_INTR_STATUS))
pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
/* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
- writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
+ writel((intr_status & 0x7ffff), ioaddr + DMA_CHAN_STATUS(chan));
return ret;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index 93cead5613e3..e5e7ac03459d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -58,7 +58,8 @@ static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)
dev_info(priv->device, "Enhanced/Alternate descriptors\n");
/* GMAC older than 3.50 has no extended descriptors */
- if (priv->synopsys_id >= DWMAC_CORE_3_50) {
+ if (priv->synopsys_id >= DWMAC_CORE_3_50 ||
+ priv->synopsys_id == DWGMAC_CORE_1_00) {
dev_info(priv->device, "Enabled extended descriptors\n");
priv->extend_desc = 1;
} else {
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 7371713c116d..aafc75fa14a0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -7062,6 +7062,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
/* dwmac-sun8i only work in chain mode */
if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
chain_mode = 1;
+
priv->chain_mode = chain_mode;
/* Initialize HW Interface */
@@ -7142,6 +7143,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
* riwt_off field from the platform.
*/
if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
+ (priv->synopsys_id == DWGMAC_CORE_1_00) ||
(priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
priv->use_riwt = 1;
dev_info(priv->device,
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 4/9] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe()
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
` (2 preceding siblings ...)
2023-11-10 9:25 ` [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions Yanteng Si
@ 2023-11-10 9:25 ` Yanteng Si
2023-11-11 20:19 ` Andrew Lunn
2023-11-10 9:27 ` [PATCH v5 5/9] net: stmmac: dwmac-loongson: Add full PCI support Yanteng Si
` (5 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:25 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Add a setup() function to initialize data, and simplify code for
loongson_dwmac_probe().
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 87 +++++++++++--------
1 file changed, 53 insertions(+), 34 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 2cd6fce5c993..56d1fd8c61e1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -9,7 +9,12 @@
#include <linux/of_irq.h>
#include "stmmac.h"
-static int loongson_default_data(struct plat_stmmacenet_data *plat)
+struct stmmac_pci_info {
+ int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
+};
+
+static void loongson_default_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
{
plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->has_gmac = 1;
@@ -34,23 +39,38 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat)
/* Disable RX queues routing by default */
plat->rx_queues_cfg[0].pkt_route = 0x0;
+}
+
+static int loongson_gmac_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ loongson_default_data(pdev, plat);
+
+ plat->multicast_filter_bins = 256;
+
+ plat->mdio_bus_data->phy_mask = 0;
- /* Default to phy auto-detection */
plat->phy_addr = -1;
+ plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
plat->dma_cfg->pbl = 32;
plat->dma_cfg->pblx8 = true;
- plat->multicast_filter_bins = 256;
return 0;
}
-static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+static struct stmmac_pci_info loongson_gmac_pci_info = {
+ .setup = loongson_gmac_data,
+};
+
+static int loongson_dwmac_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
{
+ int ret, i, bus_id, phy_mode;
struct plat_stmmacenet_data *plat;
+ struct stmmac_pci_info *info;
struct stmmac_resources res;
struct device_node *np;
- int ret, i, phy_mode;
np = dev_of_node(&pdev->dev);
@@ -59,39 +79,32 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
return -ENODEV;
}
- if (!of_device_is_compatible(np, "loongson, pci-gmac")) {
- pr_info("dwmac_loongson_pci: Incompatible OF node\n");
- return -ENODEV;
- }
-
plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
if (!plat)
return -ENOMEM;
+ plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
+ sizeof(*plat->mdio_bus_data),
+ GFP_KERNEL);
+ if (!plat->mdio_bus_data)
+ return -ENOMEM;
+
+ plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
+ GFP_KERNEL);
+ if (!plat->dma_cfg)
+ return -ENOMEM;
+
plat->mdio_node = of_get_child_by_name(np, "mdio");
if (plat->mdio_node) {
dev_info(&pdev->dev, "Found MDIO subnode\n");
-
- plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
- sizeof(*plat->mdio_bus_data),
- GFP_KERNEL);
- if (!plat->mdio_bus_data) {
- ret = -ENOMEM;
- goto err_put_node;
- }
plat->mdio_bus_data->needs_reset = true;
}
- plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
- if (!plat->dma_cfg) {
- ret = -ENOMEM;
- goto err_put_node;
- }
-
/* Enable pci device */
ret = pci_enable_device(pdev);
if (ret) {
- dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__);
+ dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
+ __func__);
goto err_put_node;
}
@@ -105,9 +118,16 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
break;
}
- plat->bus_id = of_alias_get_id(np, "ethernet");
- if (plat->bus_id < 0)
- plat->bus_id = pci_dev_id(pdev);
+ pci_set_master(pdev);
+
+ info = (struct stmmac_pci_info *)id->driver_data;
+ ret = info->setup(pdev, plat);
+ if (ret)
+ goto err_disable_device;
+
+ bus_id = of_alias_get_id(np, "ethernet");
+ if (bus_id >= 0)
+ plat->bus_id = bus_id;
phy_mode = device_get_phy_mode(&pdev->dev);
if (phy_mode < 0) {
@@ -117,11 +137,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
}
plat->phy_interface = phy_mode;
- plat->mac_interface = PHY_INTERFACE_MODE_GMII;
- pci_set_master(pdev);
-
- loongson_default_data(plat);
pci_enable_msi(pdev);
memset(&res, 0, sizeof(res));
res.addr = pcim_iomap_table(pdev)[0];
@@ -135,7 +151,8 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
if (res.wol_irq < 0) {
- dev_info(&pdev->dev, "IRQ eth_wake_irq not found, using macirq\n");
+ dev_info(&pdev->dev,
+ "IRQ eth_wake_irq not found, using macirq\n");
res.wol_irq = res.irq;
}
@@ -219,8 +236,10 @@ static int __maybe_unused loongson_dwmac_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(loongson_dwmac_pm_ops, loongson_dwmac_suspend,
loongson_dwmac_resume);
+#define PCI_DEVICE_ID_LOONGSON_GMAC 0x7a03
+
static const struct pci_device_id loongson_dwmac_id_table[] = {
- { PCI_VDEVICE(LOONGSON, 0x7a03) },
+ { PCI_DEVICE_DATA(LOONGSON, GMAC, &loongson_gmac_pci_info) },
{}
};
MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table);
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 5/9] net: stmmac: dwmac-loongson: Add full PCI support
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
` (3 preceding siblings ...)
2023-11-10 9:25 ` [PATCH v5 4/9] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe() Yanteng Si
@ 2023-11-10 9:27 ` Yanteng Si
2023-11-11 20:24 ` Andrew Lunn
2023-11-10 9:27 ` [PATCH v5 6/9] net: stmmac: dwmac-loongson: Add MSI support Yanteng Si
` (4 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:27 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Current dwmac-loongson only support LS2K in the "probed with PCI and
configured with DT" manner. Add LS7A support on which the devices are
fully PCI (non-DT).
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 79 ++++++++++---------
1 file changed, 43 insertions(+), 36 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 56d1fd8c61e1..0d79104d7fd3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -16,6 +16,10 @@ struct stmmac_pci_info {
static void loongson_default_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
+ /* Get bus_id, this can be overloaded later */
+ plat->bus_id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+
plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->has_gmac = 1;
plat->force_sf_dma_mode = 1;
@@ -56,6 +60,9 @@ static int loongson_gmac_data(struct pci_dev *pdev,
plat->dma_cfg->pbl = 32;
plat->dma_cfg->pblx8 = true;
+ plat->clk_ref_rate = 125000000;
+ plat->clk_ptp_rate = 125000000;
+
return 0;
}
@@ -72,13 +79,6 @@ static int loongson_dwmac_probe(struct pci_dev *pdev,
struct stmmac_resources res;
struct device_node *np;
- np = dev_of_node(&pdev->dev);
-
- if (!np) {
- pr_info("dwmac_loongson_pci: No OF node\n");
- return -ENODEV;
- }
-
plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
if (!plat)
return -ENOMEM;
@@ -94,6 +94,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev,
if (!plat->dma_cfg)
return -ENOMEM;
+ np = dev_of_node(&pdev->dev);
plat->mdio_node = of_get_child_by_name(np, "mdio");
if (plat->mdio_node) {
dev_info(&pdev->dev, "Found MDIO subnode\n");
@@ -125,42 +126,48 @@ static int loongson_dwmac_probe(struct pci_dev *pdev,
if (ret)
goto err_disable_device;
- bus_id = of_alias_get_id(np, "ethernet");
- if (bus_id >= 0)
- plat->bus_id = bus_id;
+ if (np) {
+ bus_id = of_alias_get_id(np, "ethernet");
+ if (bus_id >= 0)
+ plat->bus_id = bus_id;
- phy_mode = device_get_phy_mode(&pdev->dev);
- if (phy_mode < 0) {
- dev_err(&pdev->dev, "phy_mode not found\n");
- ret = phy_mode;
- goto err_disable_device;
+ phy_mode = device_get_phy_mode(&pdev->dev);
+ if (phy_mode < 0) {
+ dev_err(&pdev->dev, "phy_mode not found\n");
+ ret = phy_mode;
+ goto err_disable_device;
+ }
+ plat->phy_interface = phy_mode;
}
- plat->phy_interface = phy_mode;
-
pci_enable_msi(pdev);
memset(&res, 0, sizeof(res));
res.addr = pcim_iomap_table(pdev)[0];
- res.irq = of_irq_get_byname(np, "macirq");
- if (res.irq < 0) {
- dev_err(&pdev->dev, "IRQ macirq not found\n");
- ret = -ENODEV;
- goto err_disable_msi;
- }
-
- res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
- if (res.wol_irq < 0) {
- dev_info(&pdev->dev,
- "IRQ eth_wake_irq not found, using macirq\n");
- res.wol_irq = res.irq;
- }
-
- res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
- if (res.lpi_irq < 0) {
- dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
- ret = -ENODEV;
- goto err_disable_msi;
+ if (np) {
+ res.irq = of_irq_get_byname(np, "macirq");
+ if (res.irq < 0) {
+ dev_err(&pdev->dev, "IRQ macirq not found\n");
+ ret = -ENODEV;
+ goto err_disable_msi;
+ }
+
+ res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
+ if (res.wol_irq < 0) {
+ dev_info(&pdev->dev,
+ "IRQ eth_wake_irq not found, using macirq\n");
+ res.wol_irq = res.irq;
+ }
+
+ res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
+ if (res.lpi_irq < 0) {
+ dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
+ ret = -ENODEV;
+ goto err_disable_msi;
+ }
+ } else {
+ res.irq = pdev->irq;
+ res.wol_irq = pdev->irq;
}
ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 6/9] net: stmmac: dwmac-loongson: Add MSI support
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
` (4 preceding siblings ...)
2023-11-10 9:27 ` [PATCH v5 5/9] net: stmmac: dwmac-loongson: Add full PCI support Yanteng Si
@ 2023-11-10 9:27 ` Yanteng Si
2023-11-10 9:27 ` [PATCH v5 7/9] net: stmmac: dwmac-loongson: Add GNET support Yanteng Si
` (3 subsequent siblings)
9 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:27 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Request allocation for MSI for specific versions.
Some features of Loongson platforms are bound to the GMAC_VERSION
register. We have to read its value in order to get the correct channel
number.
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 143 ++++++++++++++----
1 file changed, 113 insertions(+), 30 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 0d79104d7fd3..a23735371b35 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -11,8 +11,96 @@
struct stmmac_pci_info {
int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
+ int (*config)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res, struct device_node *np);
};
+static u32 get_irq_type(struct device_node *np)
+{
+ struct of_phandle_args oirq;
+
+ if (np && of_irq_parse_one(np, 0, &oirq) == 0 && oirq.args_count == 2)
+ return oirq.args[1];
+
+ return IRQF_TRIGGER_RISING;
+}
+
+static int loongson_dwmac_config_legacy(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res,
+ struct device_node *np)
+{
+ if (np) {
+ res->irq = of_irq_get_byname(np, "macirq");
+ if (res->irq < 0) {
+ dev_err(&pdev->dev, "IRQ macirq not found\n");
+ return -ENODEV;
+ }
+
+ res->wol_irq = of_irq_get_byname(np, "eth_wake_irq");
+ if (res->wol_irq < 0) {
+ dev_info(&pdev->dev,
+ "IRQ eth_wake_irq not found, using macirq\n");
+ res->wol_irq = res->irq;
+ }
+
+ res->lpi_irq = of_irq_get_byname(np, "eth_lpi");
+ if (res->lpi_irq < 0) {
+ dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
+ return -ENODEV;
+ }
+ } else {
+ res->irq = pdev->irq;
+ res->wol_irq = res->irq;
+ }
+
+ plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN;
+ dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
+ __func__);
+
+ return 0;
+}
+
+static int loongson_dwmac_config_multi_msi(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res,
+ struct device_node *np,
+ int channel_num)
+{
+ int i, ret, vecs;
+
+ vecs = roundup_pow_of_two(channel_num * 2 + 1);
+ ret = pci_alloc_irq_vectors(pdev, vecs, vecs, PCI_IRQ_MSI);
+ if (ret < 0) {
+ dev_info(&pdev->dev,
+ "MSI enable failed, Fallback to legacy interrupt\n");
+ return loongson_dwmac_config_legacy(pdev, plat, res, np);
+ }
+
+ plat->rx_queues_to_use = channel_num;
+ plat->tx_queues_to_use = channel_num;
+ plat->irq_flags = get_irq_type(np);
+
+ res->irq = pci_irq_vector(pdev, 0);
+ res->wol_irq = res->irq;
+
+ /* INT NAME | MAC | CH7 rx | CH7 tx | ... | CH0 rx | CH0 tx |
+ * --------- ----- -------- -------- ... -------- --------
+ * IRQ NUM | 0 | 1 | 2 | ... | 15 | 16 |
+ */
+ for (i = 0; i < channel_num; i++) {
+ res->rx_irq[channel_num - 1 - i] =
+ pci_irq_vector(pdev, 1 + i * 2);
+ res->tx_irq[channel_num - 1 - i] =
+ pci_irq_vector(pdev, 2 + i * 2);
+ }
+
+ plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
+ dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
+
+ return 0;
+}
+
static void loongson_default_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
@@ -66,8 +154,29 @@ static int loongson_gmac_data(struct pci_dev *pdev,
return 0;
}
+static int loongson_gmac_config(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res,
+ struct device_node *np)
+{
+ int ret;
+ u32 version = readl(res->addr + GMAC_VERSION);
+
+ switch (version & 0xff) {
+ case DWGMAC_CORE_1_00:
+ ret = loongson_dwmac_config_multi_msi(pdev, plat, res, np, 8);
+ break;
+ default:
+ ret = loongson_dwmac_config_legacy(pdev, plat, res, np);
+ break;
+ }
+
+ return ret;
+}
+
static struct stmmac_pci_info loongson_gmac_pci_info = {
.setup = loongson_gmac_data,
+ .config = loongson_gmac_config,
};
static int loongson_dwmac_probe(struct pci_dev *pdev,
@@ -140,44 +249,19 @@ static int loongson_dwmac_probe(struct pci_dev *pdev,
plat->phy_interface = phy_mode;
}
- pci_enable_msi(pdev);
memset(&res, 0, sizeof(res));
res.addr = pcim_iomap_table(pdev)[0];
- if (np) {
- res.irq = of_irq_get_byname(np, "macirq");
- if (res.irq < 0) {
- dev_err(&pdev->dev, "IRQ macirq not found\n");
- ret = -ENODEV;
- goto err_disable_msi;
- }
-
- res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
- if (res.wol_irq < 0) {
- dev_info(&pdev->dev,
- "IRQ eth_wake_irq not found, using macirq\n");
- res.wol_irq = res.irq;
- }
-
- res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
- if (res.lpi_irq < 0) {
- dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
- ret = -ENODEV;
- goto err_disable_msi;
- }
- } else {
- res.irq = pdev->irq;
- res.wol_irq = pdev->irq;
- }
+ ret = info->config(pdev, plat, &res, np);
+ if (ret)
+ goto err_disable_device;
ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
if (ret)
- goto err_disable_msi;
+ goto err_disable_device;
return ret;
-err_disable_msi:
- pci_disable_msi(pdev);
err_disable_device:
pci_disable_device(pdev);
err_put_node:
@@ -201,7 +285,6 @@ static void loongson_dwmac_remove(struct pci_dev *pdev)
break;
}
- pci_disable_msi(pdev);
pci_disable_device(pdev);
}
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 7/9] net: stmmac: dwmac-loongson: Add GNET support
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
` (5 preceding siblings ...)
2023-11-10 9:27 ` [PATCH v5 6/9] net: stmmac: dwmac-loongson: Add MSI support Yanteng Si
@ 2023-11-10 9:27 ` Yanteng Si
2023-11-10 9:27 ` [PATCH v5 8/9] net: stmmac: dwmac-loongson: Disable flow control for GMAC Yanteng Si
` (2 subsequent siblings)
9 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:27 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Add Loongson GNET (GMAC with PHY) support. Current GNET does not support
half duplex mode, and GNET on LS7A only supports ANE when speed is set to
1000M.
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
.../ethernet/stmicro/stmmac/dwmac-loongson.c | 79 +++++++++++++++++++
.../ethernet/stmicro/stmmac/stmmac_ethtool.c | 6 ++
include/linux/stmmac.h | 2 +
3 files changed, 87 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index a23735371b35..575ec2d96741 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -179,6 +179,83 @@ static struct stmmac_pci_info loongson_gmac_pci_info = {
.config = loongson_gmac_config,
};
+static void loongson_gnet_fix_speed(void *priv, unsigned int speed, unsigned int mode)
+{
+ struct net_device *ndev = dev_get_drvdata(priv);
+ struct stmmac_priv *ptr = netdev_priv(ndev);
+
+ /* The controller and PHY don't work well together.
+ * We need to use the PS bit to check if the controller's status
+ * is correct and reset PHY if necessary.
+ */
+ if (speed == SPEED_1000)
+ if (readl(ptr->ioaddr + MAC_CTRL_REG) & (1 << 15) /* PS */)
+ phy_restart_aneg(ndev->phydev);
+}
+
+static int loongson_gnet_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ loongson_default_data(pdev, plat);
+
+ plat->multicast_filter_bins = 256;
+
+ plat->mdio_bus_data->phy_mask = 0xfffffffb;
+
+ plat->phy_addr = 2;
+ plat->phy_interface = PHY_INTERFACE_MODE_INTERNAL;
+
+ plat->bsp_priv = &pdev->dev;
+ plat->fix_mac_speed = loongson_gnet_fix_speed;
+
+ plat->dma_cfg->pbl = 32;
+ plat->dma_cfg->pblx8 = true;
+
+ plat->clk_ref_rate = 125000000;
+ plat->clk_ptp_rate = 125000000;
+
+ return 0;
+}
+
+static int loongson_gnet_config(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res,
+ struct device_node *np)
+{
+ int ret;
+ u32 version = readl(res->addr + GMAC_VERSION);
+
+ switch (version & 0xff) {
+ case DWGMAC_CORE_1_00:
+ ret = loongson_dwmac_config_multi_msi(pdev, plat, res, np, 8);
+ break;
+ default:
+ ret = loongson_dwmac_config_legacy(pdev, plat, res, np);
+ break;
+ }
+
+ switch (pdev->revision) {
+ case 0x00:
+ plat->flags |=
+ FIELD_PREP(STMMAC_FLAG_DISABLE_HALF_DUPLEX, 1) |
+ FIELD_PREP(STMMAC_FLAG_DISABLE_FORCE_1000, 1);
+ break;
+ case 0x01:
+ plat->flags |=
+ FIELD_PREP(STMMAC_FLAG_DISABLE_HALF_DUPLEX, 1);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static struct stmmac_pci_info loongson_gnet_pci_info = {
+ .setup = loongson_gnet_data,
+ .config = loongson_gnet_config,
+};
+
static int loongson_dwmac_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
@@ -327,9 +404,11 @@ static SIMPLE_DEV_PM_OPS(loongson_dwmac_pm_ops, loongson_dwmac_suspend,
loongson_dwmac_resume);
#define PCI_DEVICE_ID_LOONGSON_GMAC 0x7a03
+#define PCI_DEVICE_ID_LOONGSON_GNET 0x7a13
static const struct pci_device_id loongson_dwmac_id_table[] = {
{ PCI_DEVICE_DATA(LOONGSON, GMAC, &loongson_gmac_pci_info) },
+ { PCI_DEVICE_DATA(LOONGSON, GNET, &loongson_gnet_pci_info) },
{}
};
MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index f628411ae4ae..646a1af12705 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -410,6 +410,12 @@ stmmac_ethtool_set_link_ksettings(struct net_device *dev,
return 0;
}
+ if (FIELD_GET(STMMAC_FLAG_DISABLE_FORCE_1000, priv->plat->flags)) {
+ if (cmd->base.speed == SPEED_1000 &&
+ cmd->base.autoneg != AUTONEG_ENABLE)
+ return -EOPNOTSUPP;
+ }
+
return phylink_ethtool_ksettings_set(priv->phylink, cmd);
}
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 664a0e1cefc2..2b8f5dc09920 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -220,6 +220,8 @@ struct dwmac4_addrs {
#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10)
#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(11)
#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12)
+#define STMMAC_FLAG_DISABLE_HALF_DUPLEX BIT(13)
+#define STMMAC_FLAG_DISABLE_FORCE_1000 BIT(14)
struct plat_stmmacenet_data {
int bus_id;
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 8/9] net: stmmac: dwmac-loongson: Disable flow control for GMAC
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
` (6 preceding siblings ...)
2023-11-10 9:27 ` [PATCH v5 7/9] net: stmmac: dwmac-loongson: Add GNET support Yanteng Si
@ 2023-11-10 9:27 ` Yanteng Si
2023-11-10 9:30 ` [PATCH v5 9/9] net: stmmac: Disable coe for some Loongson GNET Yanteng Si
2023-11-10 20:38 ` [PATCH v5 0/9] stmmac: Add Loongson platform support Jakub Kicinski
9 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:27 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Loongson GMAC does not support Flow Control feature. Set flags to
disable it.
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 2 ++
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++---
include/linux/stmmac.h | 1 +
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 575ec2d96741..306b8d53e19c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -171,6 +171,8 @@ static int loongson_gmac_config(struct pci_dev *pdev,
break;
}
+ plat->flags |= FIELD_PREP(STMMAC_FLAG_DISABLE_FLOW_CONTROL, 1);
+
return ret;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index aafc75fa14a0..b5cbdbdabebd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1235,9 +1235,9 @@ static int stmmac_phy_setup(struct stmmac_priv *priv)
xpcs_get_interfaces(priv->hw->xpcs,
priv->phylink_config.supported_interfaces);
- priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
- MAC_10FD | MAC_100FD |
- MAC_1000FD;
+ priv->phylink_config.mac_capabilities = MAC_10FD | MAC_100FD | MAC_1000FD;
+ if (!FIELD_GET(STMMAC_FLAG_DISABLE_FLOW_CONTROL, priv->plat->flags))
+ priv->phylink_config.mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE;
stmmac_set_half_duplex(priv);
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 2b8f5dc09920..f3e1b68c2946 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -222,6 +222,7 @@ struct dwmac4_addrs {
#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12)
#define STMMAC_FLAG_DISABLE_HALF_DUPLEX BIT(13)
#define STMMAC_FLAG_DISABLE_FORCE_1000 BIT(14)
+#define STMMAC_FLAG_DISABLE_FLOW_CONTROL BIT(15)
struct plat_stmmacenet_data {
int bus_id;
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 9/9] net: stmmac: Disable coe for some Loongson GNET
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
` (7 preceding siblings ...)
2023-11-10 9:27 ` [PATCH v5 8/9] net: stmmac: dwmac-loongson: Disable flow control for GMAC Yanteng Si
@ 2023-11-10 9:30 ` Yanteng Si
2023-11-10 20:38 ` [PATCH v5 0/9] stmmac: Add Loongson platform support Jakub Kicinski
9 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-11-10 9:30 UTC (permalink / raw)
To: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu
Cc: Yanteng Si, fancer.lancer, Jose.Abreu, chenhuacai, linux,
dongbiao, guyinggang, netdev, loongarch, chris.chenfeiyang
Some chips of Loongson GNET does not support coe, so disable them.
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
---
drivers/net/ethernet/stmicro/stmmac/hwif.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index e5e7ac03459d..c1ea68514acc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -72,6 +72,11 @@ static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)
mac->desc = &ndesc_ops;
}
+ if (priv->synopsys_id == DWGMAC_CORE_1_00) {
+ priv->plat->tx_coe = 0;
+ priv->plat->rx_coe = STMMAC_RX_COE_NONE;
+ }
+
stmmac_dwmac_mode_quirk(priv);
return 0;
}
--
2.31.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/9] stmmac: Add Loongson platform support
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
` (8 preceding siblings ...)
2023-11-10 9:30 ` [PATCH v5 9/9] net: stmmac: Disable coe for some Loongson GNET Yanteng Si
@ 2023-11-10 20:38 ` Jakub Kicinski
9 siblings, 0 replies; 32+ messages in thread
From: Jakub Kicinski @ 2023-11-10 20:38 UTC (permalink / raw)
To: Yanteng Si
Cc: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, loongson-kernel, netdev, loongarch,
chris.chenfeiyang
On Fri, 10 Nov 2023 17:08:44 +0800 Yanteng Si wrote:
> v4: <https://lore.kernel.org/loongarch/cover.1692696115.git.chenfeiyang@loongson.cn/>
> v3: <https://lore.kernel.org/loongarch/cover.1691047285.git.chenfeiyang@loongson.cn/>
> v2: <https://lore.kernel.org/loongarch/cover.1690439335.git.chenfeiyang@loongson.cn/>
> v1: <https://lore.kernel.org/loongarch/cover.1689215889.git.chenfeiyang@loongson.cn/>
## Form letter - net-next-closed
The merge window for v6.7 has begun and we have already posted our pull
request. Therefore net-next is closed for new drivers, features, code
refactoring and optimizations. We are currently accepting bug fixes only.
Please repost when net-next reopens after Nov 12th.
RFC patches sent for review only are obviously welcome at any time.
See: https://www.kernel.org/doc/html/next/process/maintainer-netdev.html#development-cycle
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags
2023-11-10 9:25 ` [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags Yanteng Si
@ 2023-11-11 19:51 ` Andrew Lunn
2023-11-21 12:01 ` Yanteng Si
0 siblings, 1 reply; 32+ messages in thread
From: Andrew Lunn @ 2023-11-11 19:51 UTC (permalink / raw)
To: Yanteng Si
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
On Fri, Nov 10, 2023 at 05:25:41PM +0800, Yanteng Si wrote:
> Some platforms need extra irq flags when request multi msi, add
> irq_flags variable for them.
It would be nice to document what flags are needed.
You also seem to be pass the same flags to all instances of
request_irq. However, the flags should be specific to one irq. So you
need irq_irq_flags, wol_irq_flags, lpi_irq_flags, etc.
Andrew
---
pw-bot: cr
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-10 9:25 ` [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions Yanteng Si
@ 2023-11-11 20:07 ` Andrew Lunn
2023-11-21 9:55 ` Yanteng Si
2023-11-13 15:05 ` Serge Semin
1 sibling, 1 reply; 32+ messages in thread
From: Andrew Lunn @ 2023-11-11 20:07 UTC (permalink / raw)
To: Yanteng Si
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
> +#ifdef CONFIG_DWMAC_LOONGSON
> +#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE_LOONGSON | DMA_INTR_ENA_AIE | \
> + DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
> +#else
> #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
> DMA_INTR_ENA_UNE)
> +#endif
The aim is to produce one kernel which runs on all possible
variants. So we don't like to see this sort of #ifdef. Please try to
remove them.
> @@ -167,7 +167,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan];
> int ret = 0;
> /* read the status register (CSR5) */
> - u32 intr_status = readl(ioaddr + DMA_STATUS);
> + u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
>
Please break this patch up. Changes like the above are simple to
understand. So have one patch which just adds these macros and makes
use of them.
> #ifdef DWMAC_DMA_DEBUG
> /* Enable it to monitor DMA rx/tx status in case of critical problems */
> @@ -182,7 +182,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> intr_status &= DMA_STATUS_MSK_TX;
>
> /* ABNORMAL interrupts */
> - if (unlikely(intr_status & DMA_STATUS_AIS)) {
> + if (unlikely(intr_status & DMA_ABNOR_INTR_STATUS)) {
However, this is not obviously correct. You need to explain in the
commit message why this change is needed.
Lots of small patches make the understanding easier.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 7371713c116d..aafc75fa14a0 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -7062,6 +7062,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
> /* dwmac-sun8i only work in chain mode */
> if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
> chain_mode = 1;
> +
> priv->chain_mode = chain_mode;
Please avoid white space changes.
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 4/9] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe()
2023-11-10 9:25 ` [PATCH v5 4/9] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe() Yanteng Si
@ 2023-11-11 20:19 ` Andrew Lunn
2023-12-10 1:46 ` Yanteng Si
0 siblings, 1 reply; 32+ messages in thread
From: Andrew Lunn @ 2023-11-11 20:19 UTC (permalink / raw)
To: Yanteng Si
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
On Fri, Nov 10, 2023 at 05:25:43PM +0800, Yanteng Si wrote:
> Add a setup() function to initialize data, and simplify code for
> loongson_dwmac_probe().
This does not look like a refactoring patch. Such patches just move
code around, but otherwise leave the code alone. There are real
changes in here.
> - if (!of_device_is_compatible(np, "loongson, pci-gmac")) {
> - pr_info("dwmac_loongson_pci: Incompatible OF node\n");
> - return -ENODEV;
> - }
> -
This just disappears. Why is it no longer needed?
> plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
> if (!plat)
> return -ENOMEM;
>
> + plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
> + sizeof(*plat->mdio_bus_data),
> + GFP_KERNEL);
> + if (!plat->mdio_bus_data)
> + return -ENOMEM;
> +
> + plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
> + GFP_KERNEL);
> + if (!plat->dma_cfg)
> + return -ENOMEM;
> +
> plat->mdio_node = of_get_child_by_name(np, "mdio");
> if (plat->mdio_node) {
> dev_info(&pdev->dev, "Found MDIO subnode\n");
> -
> - plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
> - sizeof(*plat->mdio_bus_data),
> - GFP_KERNEL);
> - if (!plat->mdio_bus_data) {
> - ret = -ENOMEM;
> - goto err_put_node;
> - }
MDIO was conditional, but now is mandatory. Why?
> if (ret) {
> - dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__);
> + dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
> + __func__);
Changes like this are a distraction. The reviewer is trying to
understand what has changed and why. If you want to make white space
changes, please do it in a patch of its own.
Please break this patch up into lots of smaller parts, each with a
good commit messaged explaining what is going on, and importantly,
why.
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 5/9] net: stmmac: dwmac-loongson: Add full PCI support
2023-11-10 9:27 ` [PATCH v5 5/9] net: stmmac: dwmac-loongson: Add full PCI support Yanteng Si
@ 2023-11-11 20:24 ` Andrew Lunn
2023-12-11 8:47 ` Yanteng Si
0 siblings, 1 reply; 32+ messages in thread
From: Andrew Lunn @ 2023-11-11 20:24 UTC (permalink / raw)
To: Yanteng Si
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
> - res.irq = of_irq_get_byname(np, "macirq");
> - if (res.irq < 0) {
> - dev_err(&pdev->dev, "IRQ macirq not found\n");
> - ret = -ENODEV;
> - goto err_disable_msi;
> - }
> -
> - res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
> - if (res.wol_irq < 0) {
> - dev_info(&pdev->dev,
> - "IRQ eth_wake_irq not found, using macirq\n");
> - res.wol_irq = res.irq;
> - }
> -
> - res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
> - if (res.lpi_irq < 0) {
> - dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
> - ret = -ENODEV;
> - goto err_disable_msi;
> + if (np) {
> + res.irq = of_irq_get_byname(np, "macirq");
> + if (res.irq < 0) {
> + dev_err(&pdev->dev, "IRQ macirq not found\n");
> + ret = -ENODEV;
> + goto err_disable_msi;
> + }
> +
> + res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
> + if (res.wol_irq < 0) {
> + dev_info(&pdev->dev,
> + "IRQ eth_wake_irq not found, using macirq\n");
> + res.wol_irq = res.irq;
> + }
> +
> + res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
> + if (res.lpi_irq < 0) {
> + dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
> + ret = -ENODEV;
> + goto err_disable_msi;
> + }
This is where a refactoring patch is useful. Have one patch which
moves this code into a helper function. The commit message can say it
just moves code around, but there is no functional change. The second
patch then moves the call to the helper inside the if (np).
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-10 9:25 ` [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions Yanteng Si
2023-11-11 20:07 ` Andrew Lunn
@ 2023-11-13 15:05 ` Serge Semin
1 sibling, 0 replies; 32+ messages in thread
From: Serge Semin @ 2023-11-13 15:05 UTC (permalink / raw)
To: Yanteng Si
Cc: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
Jose.Abreu, chenhuacai, linux, dongbiao, guyinggang, netdev,
loongarch, chris.chenfeiyang
On Fri, Nov 10, 2023 at 05:25:42PM +0800, Yanteng Si wrote:
> Loongson platforms use a DWGMAC which supports multi-channel.
>
> There are two types of Loongson DWGMAC. The first type shares the same
> register definitions and has similar logic as dwmac1000. The second type
> uses several different register definitions.
>
> Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
> Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
> Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
> ---
> drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
> .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 63 ++++++++++++++++---
> .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 57 ++++++++++++++++-
> .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 39 ++++++------
> drivers/net/ethernet/stmicro/stmmac/hwif.c | 3 +-
> .../net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +
> 6 files changed, 133 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
> index e3f650e88f82..e01584fe9efa 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/common.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
> @@ -34,6 +34,7 @@
> #define DWMAC_CORE_5_00 0x50
> #define DWMAC_CORE_5_10 0x51
> #define DWMAC_CORE_5_20 0x52
> +#define DWGMAC_CORE_1_00 0x10
Name is ambiguous. All of the DWMAC_CORE_* macro above also refer to
the DW GMACs. Moreover generic DW MAC IP-core v1 I guess never existed
in a way the driver expects it. So IMO it would be better for you to
drop this and just add a new flag to the plat_stmmacenet_data
structure (extended_desc or has_lson/STMMAC_FLAG_HAS_LSON).
* One more time took a look at the plat_stmmacenet_data structure and
* scared of the mess it has evolved to.
> #define DWXGMAC_CORE_2_10 0x21
> #define DWXGMAC_CORE_2_20 0x22
> #define DWXLGMAC_CORE_2_00 0x20
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> index ce0e6ca6f3a2..234d30c5a836 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> @@ -12,7 +12,8 @@
> Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> *******************************************************************************/
>
> -#include <asm/io.h>
> +#include <linux/io.h>
> +#include "stmmac.h"
> #include "dwmac1000.h"
> #include "dwmac_dma.h"
>
> @@ -111,13 +112,58 @@ static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
> writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
> }
>
> +static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
> + void __iomem *ioaddr,
> + struct stmmac_dma_cfg *dma_cfg, u32 chan)
> +{
> + u32 value;
> + int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
> + int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
> +
> + if (!(priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN))
> + return;
Use dma_cfg->multi_msi_en in a way it's done in the DW GMAC v4*
module. Also note this flag isn't something that should block all the
DMA-channel-specific setups. It's intended to activate the per-channel
IRQs instead of raising the generic MAC IRQ for all the events.
> +
> + /* common channel control register config */
> + value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan));
> +
> + /* Set the DMA PBL (Programmable Burst Length) mode.
> + *
> + * Note: before stmmac core 3.50 this mode bit was 4xPBL, and
> + * post 3.5 mode bit acts as 8*PBL.
> + */
> + if (dma_cfg->pblx8)
> + value |= DMA_BUS_MODE_MAXPBL;
> + value |= DMA_BUS_MODE_USP;
> + value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
> + value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
> + value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
> +
> + /* Set the Fixed burst mode */
> + if (dma_cfg->fixed_burst)
> + value |= DMA_BUS_MODE_FB;
> +
> + /* Mixed Burst has no effect when fb is set */
> + if (dma_cfg->mixed_burst)
> + value |= DMA_BUS_MODE_MB;
> +
> + value |= DMA_BUS_MODE_ATDS;
> +
> + if (dma_cfg->aal)
> + value |= DMA_BUS_MODE_AAL;
> +
> + writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
> +
> + /* Mask interrupts by writing to CSR7 */
> + writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(chan));
> +}
This is just a multi-channel copy of the dwmac1000_dma_init(). Please
factor out all the channel-specific setups to the
dwmac1000_dma_init_channel() method and all the generic setups (if
any) to the dwmac1000_dma_init() function.
> +
> static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
> void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg,
> dma_addr_t dma_rx_phy, u32 chan)
> {
> /* RX descriptor base address list must be written into DMA CSR3 */
> - writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
> + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RCV_BASE_ADDR(chan));
> }
>
> static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
> @@ -126,7 +172,7 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
> dma_addr_t dma_tx_phy, u32 chan)
> {
> /* TX descriptor base address list must be written into DMA CSR4 */
> - writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
> + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
> }
>
> static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
> @@ -154,7 +200,7 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
> void __iomem *ioaddr, int mode,
> u32 channel, int fifosz, u8 qmode)
> {
> - u32 csr6 = readl(ioaddr + DMA_CONTROL);
> + u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
>
> if (mode == SF_DMA_MODE) {
> pr_debug("GMAC: enable RX store and forward mode\n");
> @@ -176,14 +222,14 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
> /* Configure flow control based on rx fifo size */
> csr6 = dwmac1000_configure_fc(csr6, fifosz);
>
> - writel(csr6, ioaddr + DMA_CONTROL);
> + writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
> }
>
> static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
> void __iomem *ioaddr, int mode,
> u32 channel, int fifosz, u8 qmode)
> {
> - u32 csr6 = readl(ioaddr + DMA_CONTROL);
> + u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
>
> if (mode == SF_DMA_MODE) {
> pr_debug("GMAC: enable TX store and forward mode\n");
> @@ -210,7 +256,7 @@ static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
> csr6 |= DMA_CONTROL_TTC_256;
> }
>
> - writel(csr6, ioaddr + DMA_CONTROL);
> + writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
> }
>
> static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
> @@ -273,12 +319,13 @@ static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
> static void dwmac1000_rx_watchdog(struct stmmac_priv *priv,
> void __iomem *ioaddr, u32 riwt, u32 queue)
> {
> - writel(riwt, ioaddr + DMA_RX_WATCHDOG);
> + writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
> }
>
> const struct stmmac_dma_ops dwmac1000_dma_ops = {
> .reset = dwmac_dma_reset,
> .init = dwmac1000_dma_init,
> + .init_chan = dwmac1000_dma_init_channel,
> .init_rx_chan = dwmac1000_dma_init_rx,
> .init_tx_chan = dwmac1000_dma_init_tx,
> .axi = dwmac1000_dma_axi,
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> index 77141391bd2f..90464e1c9649 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> @@ -76,8 +76,15 @@
> #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
> #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
>
> +#define DMA_INTR_ENA_NIE_LOONGSON 0x00060000 /* Loongson Normal Summary */
> +
> +#ifdef CONFIG_DWMAC_LOONGSON
> +#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE_LOONGSON | DMA_INTR_ENA_NIE | \
Emm, I don't understand this:
DMA_INTR_ENA_NIE = 0x00010000
DMA_INTR_ENA_NIE_LOONGSON = 0x00060000
What are these additional NIE flags and why do you call them also NIE?
> + DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE)
> +#else
> #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
> DMA_INTR_ENA_TIE)
> +#endif
>
> /* DMA Abnormal interrupt */
> #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
> @@ -91,8 +98,15 @@
> #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
> #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
>
> +#define DMA_INTR_ENA_AIE_LOONGSON 0x00018000 /* Loongson Abnormal Summary */
> +
> +#ifdef CONFIG_DWMAC_LOONGSON
> +#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE_LOONGSON | DMA_INTR_ENA_AIE | \
Similarly I don't understand this.
DMA_INTR_ENA_AIE = 0x00008000
DMA_INTR_ENA_AIE_LOONGSON = 0x00018000
so it's Loongson-specific needs normal DMA_INTR_ENA_AIE and some
additional flag enabled. What is the meaning of that flag?
> + DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
> +#else
> #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
> DMA_INTR_ENA_UNE)
> +#endif
>
> /* DMA default interrupt mask */
> #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
> @@ -128,9 +142,29 @@
> #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
> #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
>
> -#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
> - DMA_STATUS_AIS | \
> - DMA_STATUS_FBI)
> +#define DMA_STATUS_TX_NIS_LOONGSON 0x00040000 /* Normal Tx Interrupt Summary */
> +#define DMA_STATUS_RX_NIS_LOONGSON 0x00020000 /* Normal Rx Interrupt Summary */
> +#define DMA_STATUS_TX_AIS_LOONGSON 0x00010000 /* Abnormal Tx Interrupt Summary */
> +#define DMA_STATUS_RX_AIS_LOONGSON 0x00008000 /* Abnormal Rx Interrupt Summary */
> +#define DMA_STATUS_TX_FBI_LOONGSON 0x00002000 /* Fatal Tx Bus Error Interrupt */
> +#define DMA_STATUS_RX_FBI_LOONGSON 0x00001000 /* Fatal Rx Bus Error Interrupt */
> +
> +#ifdef CONFIG_DWMAC_LOONGSON
> +#define DMA_NOR_INTR_STATUS (DMA_STATUS_TX_NIS_LOONGSON | DMA_STATUS_RX_NIS_LOONGSON)
> +#define DMA_ABNOR_INTR_STATUS (DMA_STATUS_TX_AIS_LOONGSON | DMA_STATUS_RX_AIS_LOONGSON)
> +#define DMA_FB_INTR_STATUS (DMA_STATUS_TX_FBI_LOONGSON | DMA_STATUS_RX_FBI_LOONGSON)
> +#else
> +#define DMA_NOR_INTR_STATUS DMA_STATUS_NIS
> +#define DMA_ABNOR_INTR_STATUS DMA_STATUS_AIS
> +#define DMA_FB_INTR_STATUS DMA_STATUS_FBI
> +#endif
In addition to what said Andrew, this looks incorrect since the
Loongson flags intersect the generic status flags. So it seems like
at least the statistics handling or the
show_rx_process_state()/show_tx_process_state() won't work correctly.
-Serge(y)
> +
> +#define DMA_INTR_STATUS (DMA_STATUS_GPI | \
> + DMA_STATUS_GMI | \
> + DMA_STATUS_GLI)
> +#define DMA_STATUS_MSK_COMMON (DMA_NOR_INTR_STATUS | \
> + DMA_ABNOR_INTR_STATUS | \
> + DMA_FB_INTR_STATUS)
>
> #define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
> DMA_STATUS_RWT | \
> @@ -148,6 +182,9 @@
> DMA_STATUS_TI | \
> DMA_STATUS_MSK_COMMON)
>
> +/* Following DMA defines are chanels oriented */
> +#define DMA_CHAN_OFFSET 0x100
> +
> #define NUM_DWMAC100_DMA_REGS 9
> #define NUM_DWMAC1000_DMA_REGS 23
> #define NUM_DWMAC4_DMA_REGS 27
> @@ -170,4 +207,18 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_extra_stats *x, u32 chan, u32 dir);
> int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
>
> +static inline u32 dma_chan_base_addr(u32 base, u32 chan)
> +{
> + return base + chan * DMA_CHAN_OFFSET;
> +}
> +
> +#define DMA_CHAN_XMT_POLL_DEMAND(chan) dma_chan_base_addr(DMA_XMT_POLL_DEMAND, chan)
> +#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
> +#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
> +#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
> +#define DMA_CHAN_BUS_MODE(chan) dma_chan_base_addr(DMA_BUS_MODE, chan)
> +#define DMA_CHAN_RCV_BASE_ADDR(chan) dma_chan_base_addr(DMA_RCV_BASE_ADDR, chan)
> +#define DMA_CHAN_TX_BASE_ADDR(chan) dma_chan_base_addr(DMA_TX_BASE_ADDR, chan)
> +#define DMA_CHAN_RX_WATCHDOG(chan) dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
> +
> #endif /* __DWMAC_DMA_H__ */
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> index 0cb337ffb7ac..c36aec97bbb5 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> @@ -31,63 +31,63 @@ int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
> void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
> void __iomem *ioaddr, u32 chan)
> {
> - writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
> + writel(1, ioaddr + DMA_CHAN_XMT_POLL_DEMAND(chan));
> }
>
> void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan, bool rx, bool tx)
> {
> - u32 value = readl(ioaddr + DMA_INTR_ENA);
> + u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
>
> if (rx)
> value |= DMA_INTR_DEFAULT_RX;
> if (tx)
> value |= DMA_INTR_DEFAULT_TX;
>
> - writel(value, ioaddr + DMA_INTR_ENA);
> + writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
> }
>
> void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan, bool rx, bool tx)
> {
> - u32 value = readl(ioaddr + DMA_INTR_ENA);
> + u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
>
> if (rx)
> value &= ~DMA_INTR_DEFAULT_RX;
> if (tx)
> value &= ~DMA_INTR_DEFAULT_TX;
>
> - writel(value, ioaddr + DMA_INTR_ENA);
> + writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
> }
>
> void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_CONTROL);
> + u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> value |= DMA_CONTROL_ST;
> - writel(value, ioaddr + DMA_CONTROL);
> + writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> }
>
> void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_CONTROL);
> + u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> value &= ~DMA_CONTROL_ST;
> - writel(value, ioaddr + DMA_CONTROL);
> + writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> }
>
> void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_CONTROL);
> + u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> value |= DMA_CONTROL_SR;
> - writel(value, ioaddr + DMA_CONTROL);
> + writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> }
>
> void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_CONTROL);
> + u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> value &= ~DMA_CONTROL_SR;
> - writel(value, ioaddr + DMA_CONTROL);
> + writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> }
>
> #ifdef DWMAC_DMA_DEBUG
> @@ -167,7 +167,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan];
> int ret = 0;
> /* read the status register (CSR5) */
> - u32 intr_status = readl(ioaddr + DMA_STATUS);
> + u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
>
> #ifdef DWMAC_DMA_DEBUG
> /* Enable it to monitor DMA rx/tx status in case of critical problems */
> @@ -182,7 +182,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> intr_status &= DMA_STATUS_MSK_TX;
>
> /* ABNORMAL interrupts */
> - if (unlikely(intr_status & DMA_STATUS_AIS)) {
> + if (unlikely(intr_status & DMA_ABNOR_INTR_STATUS)) {
> if (unlikely(intr_status & DMA_STATUS_UNF)) {
> ret = tx_hard_error_bump_tc;
> x->tx_undeflow_irq++;
> @@ -205,13 +205,13 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> x->tx_process_stopped_irq++;
> ret = tx_hard_error;
> }
> - if (unlikely(intr_status & DMA_STATUS_FBI)) {
> + if (unlikely(intr_status & DMA_FB_INTR_STATUS)) {
> x->fatal_bus_error_irq++;
> ret = tx_hard_error;
> }
> }
> /* TX/RX NORMAL interrupts */
> - if (likely(intr_status & DMA_STATUS_NIS)) {
> + if (likely(intr_status & DMA_NOR_INTR_STATUS)) {
> if (likely(intr_status & DMA_STATUS_RI)) {
> u32 value = readl(ioaddr + DMA_INTR_ENA);
> /* to schedule NAPI on real RIE event. */
> @@ -232,12 +232,11 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> x->rx_early_irq++;
> }
> /* Optional hardware blocks, interrupts should be disabled */
> - if (unlikely(intr_status &
> - (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
> + if (unlikely(intr_status & DMA_INTR_STATUS))
> pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
>
> /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
> - writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
> + writel((intr_status & 0x7ffff), ioaddr + DMA_CHAN_STATUS(chan));
>
> return ret;
> }
> diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
> index 93cead5613e3..e5e7ac03459d 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
> @@ -58,7 +58,8 @@ static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)
> dev_info(priv->device, "Enhanced/Alternate descriptors\n");
>
> /* GMAC older than 3.50 has no extended descriptors */
> - if (priv->synopsys_id >= DWMAC_CORE_3_50) {
> + if (priv->synopsys_id >= DWMAC_CORE_3_50 ||
> + priv->synopsys_id == DWGMAC_CORE_1_00) {
> dev_info(priv->device, "Enabled extended descriptors\n");
> priv->extend_desc = 1;
> } else {
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 7371713c116d..aafc75fa14a0 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -7062,6 +7062,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
> /* dwmac-sun8i only work in chain mode */
> if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
> chain_mode = 1;
> +
> priv->chain_mode = chain_mode;
>
> /* Initialize HW Interface */
> @@ -7142,6 +7143,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
> * riwt_off field from the platform.
> */
> if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
> + (priv->synopsys_id == DWGMAC_CORE_1_00) ||
> (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
> priv->use_riwt = 1;
> dev_info(priv->device,
> --
> 2.31.4
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 1/9] net: stmmac: Pass stmmac_priv and chan in some callbacks
2023-11-10 9:23 ` [PATCH v5 1/9] net: stmmac: Pass stmmac_priv and chan in some callbacks Yanteng Si
@ 2023-11-13 15:16 ` Serge Semin
2023-12-05 11:16 ` Yanteng Si
0 siblings, 1 reply; 32+ messages in thread
From: Serge Semin @ 2023-11-13 15:16 UTC (permalink / raw)
To: Yanteng Si
Cc: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
Jose.Abreu, chenhuacai, linux, dongbiao, guyinggang, netdev,
loongarch, chris.chenfeiyang
On Fri, Nov 10, 2023 at 05:23:18PM +0800, Yanteng Si wrote:
> Loongson GMAC and GNET have some special features. To prepare for that,
> pass stmmac_priv and chan to more callbacks, and adjust the callbacks
> accordingly.
I might have missed something, but I failed to see why you need the
most of these changes. At the very least your implementation doesn't
require the prototypes being converted to accepting the stmmac_priv
pointer. Please drop all of such redundant changes and leave only the
required one. AFAICS based on the further patches the only required
are the channel ID arguments.
-Serge(y)
>
> Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
> Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
> Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
> ---
> .../net/ethernet/stmicro/stmmac/chain_mode.c | 5 +-
> .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 +++---
> .../ethernet/stmicro/stmmac/dwmac1000_core.c | 9 ++-
> .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 8 ++-
> .../ethernet/stmicro/stmmac/dwmac100_core.c | 9 ++-
> .../ethernet/stmicro/stmmac/dwmac100_dma.c | 2 +-
> .../net/ethernet/stmicro/stmmac/dwmac4_core.c | 11 +--
> .../ethernet/stmicro/stmmac/dwmac4_descs.c | 17 ++---
> .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 ++-
> .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 2 +-
> .../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 2 +-
> .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 5 +-
> .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 5 +-
> .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 11 +--
> .../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 17 ++---
> .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 +--
> .../net/ethernet/stmicro/stmmac/enh_desc.c | 17 ++---
> drivers/net/ethernet/stmicro/stmmac/hwif.c | 2 +-
> drivers/net/ethernet/stmicro/stmmac/hwif.h | 71 ++++++++++---------
> .../net/ethernet/stmicro/stmmac/norm_desc.c | 17 ++---
> .../net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +-
> 21 files changed, 146 insertions(+), 110 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
> index fb55efd52240..a95866871f3e 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
> @@ -95,8 +95,9 @@ static unsigned int is_jumbo_frm(int len, int enh_desc)
> return ret;
> }
>
> -static void init_dma_chain(void *des, dma_addr_t phy_addr,
> - unsigned int size, unsigned int extend_desc)
> +static void init_dma_chain(struct stmmac_priv *priv, void *des,
> + dma_addr_t phy_addr, unsigned int size,
> + unsigned int extend_desc)
> {
> /*
> * In chained mode the des3 points to the next element in the ring.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> index 137741b94122..2d3f0848cacb 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> @@ -283,7 +283,7 @@ static const struct emac_variant emac_variant_h6 = {
> /* sun8i_dwmac_dma_reset() - reset the EMAC
> * Called from stmmac via stmmac_dma_ops->reset
> */
> -static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
> +static int sun8i_dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
> {
> writel(0, ioaddr + EMAC_RX_CTL1);
> writel(0, ioaddr + EMAC_TX_CTL1);
> @@ -298,7 +298,7 @@ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
> /* sun8i_dwmac_dma_init() - initialize the EMAC
> * Called from stmmac via stmmac_dma_ops->init
> */
> -static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
> +static void sun8i_dwmac_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg, int atds)
> {
> writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
> @@ -395,7 +395,8 @@ static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,
> writel(v, ioaddr + EMAC_TX_CTL1);
> }
>
> -static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
> +static void sun8i_dwmac_enable_dma_transmission(struct stmmac_priv *priv,
> + void __iomem *ioaddr, u32 chan)
> {
> u32 v;
>
> @@ -643,7 +644,8 @@ static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
> * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
> * If addr is NULL, clear the slot
> */
> -static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
> +static void sun8i_dwmac_set_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> const unsigned char *addr,
> unsigned int reg_n)
> {
> @@ -664,7 +666,8 @@ static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
> }
> }
>
> -static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
> +static void sun8i_dwmac_get_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> unsigned char *addr,
> unsigned int reg_n)
> {
> @@ -687,7 +690,8 @@ static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
> return 1;
> }
>
> -static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
> +static void sun8i_dwmac_set_filter(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> struct net_device *dev)
> {
> void __iomem *ioaddr = hw->pcsr;
> @@ -705,13 +709,13 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
> } else if (macaddrs <= hw->unicast_filter_entries) {
> if (!netdev_mc_empty(dev)) {
> netdev_for_each_mc_addr(ha, dev) {
> - sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
> + sun8i_dwmac_set_umac_addr(priv, hw, ha->addr, i);
> i++;
> }
> }
> if (!netdev_uc_empty(dev)) {
> netdev_for_each_uc_addr(ha, dev) {
> - sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
> + sun8i_dwmac_set_umac_addr(priv, hw, ha->addr, i);
> i++;
> }
> }
> @@ -723,7 +727,7 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
>
> /* Disable unused address filter slots */
> while (i < hw->unicast_filter_entries)
> - sun8i_dwmac_set_umac_addr(hw, NULL, i++);
> + sun8i_dwmac_set_umac_addr(priv, hw, NULL, i++);
>
> writel(v, ioaddr + EMAC_RX_FRM_FLT);
> }
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
> index 3927609abc44..b52793edf62f 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
> @@ -94,7 +94,8 @@ static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
> reg_space[i] = readl(ioaddr + i * 4);
> }
>
> -static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
> +static void dwmac1000_set_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> const unsigned char *addr,
> unsigned int reg_n)
> {
> @@ -103,7 +104,8 @@ static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
> GMAC_ADDR_LOW(reg_n));
> }
>
> -static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
> +static void dwmac1000_get_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> unsigned char *addr,
> unsigned int reg_n)
> {
> @@ -137,7 +139,8 @@ static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
> ioaddr + GMAC_EXTHASH_BASE + regs * 4);
> }
>
> -static void dwmac1000_set_filter(struct mac_device_info *hw,
> +static void dwmac1000_set_filter(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> struct net_device *dev)
> {
> void __iomem *ioaddr = (void __iomem *)dev->base_addr;
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> index daf79cdbd3ec..ce0e6ca6f3a2 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> @@ -16,7 +16,8 @@
> #include "dwmac1000.h"
> #include "dwmac_dma.h"
>
> -static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
> +static void dwmac1000_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
> + struct stmmac_axi *axi)
> {
> u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
> int i;
> @@ -70,7 +71,7 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
> writel(value, ioaddr + DMA_AXI_BUS_MODE);
> }
>
> -static void dwmac1000_dma_init(void __iomem *ioaddr,
> +static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg, int atds)
> {
> u32 value = readl(ioaddr + DMA_BUS_MODE);
> @@ -223,7 +224,8 @@ static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
> readl(ioaddr + DMA_BUS_MODE + i * 4);
> }
>
> -static int dwmac1000_get_hw_feature(void __iomem *ioaddr,
> +static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
> + void __iomem *ioaddr,
> struct dma_features *dma_cap)
> {
> u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
> index a6e8d7bd9588..c03623edeb75 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
> @@ -59,7 +59,8 @@ static int dwmac100_irq_status(struct mac_device_info *hw,
> return 0;
> }
>
> -static void dwmac100_set_umac_addr(struct mac_device_info *hw,
> +static void dwmac100_set_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> const unsigned char *addr,
> unsigned int reg_n)
> {
> @@ -67,7 +68,8 @@ static void dwmac100_set_umac_addr(struct mac_device_info *hw,
> stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
> }
>
> -static void dwmac100_get_umac_addr(struct mac_device_info *hw,
> +static void dwmac100_get_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> unsigned char *addr,
> unsigned int reg_n)
> {
> @@ -75,7 +77,8 @@ static void dwmac100_get_umac_addr(struct mac_device_info *hw,
> stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
> }
>
> -static void dwmac100_set_filter(struct mac_device_info *hw,
> +static void dwmac100_set_filter(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> struct net_device *dev)
> {
> void __iomem *ioaddr = (void __iomem *)dev->base_addr;
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
> index dea270f60cc3..105e7d4d798f 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
> @@ -18,7 +18,7 @@
> #include "dwmac100.h"
> #include "dwmac_dma.h"
>
> -static void dwmac100_dma_init(void __iomem *ioaddr,
> +static void dwmac100_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg, int atds)
> {
> /* Enable Application Access by writing to DMA CSR0 */
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
> index c6ff1fa0e04d..5e9b393ad7b3 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
> @@ -335,7 +335,8 @@ static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
> writel(pmt, ioaddr + GMAC_PMT);
> }
>
> -static void dwmac4_set_umac_addr(struct mac_device_info *hw,
> +static void dwmac4_set_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> const unsigned char *addr, unsigned int reg_n)
> {
> void __iomem *ioaddr = hw->pcsr;
> @@ -344,7 +345,8 @@ static void dwmac4_set_umac_addr(struct mac_device_info *hw,
> GMAC_ADDR_LOW(reg_n));
> }
>
> -static void dwmac4_get_umac_addr(struct mac_device_info *hw,
> +static void dwmac4_get_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> unsigned char *addr, unsigned int reg_n)
> {
> void __iomem *ioaddr = hw->pcsr;
> @@ -593,7 +595,8 @@ static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
> }
> }
>
> -static void dwmac4_set_filter(struct mac_device_info *hw,
> +static void dwmac4_set_filter(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> struct net_device *dev)
> {
> void __iomem *ioaddr = (void __iomem *)dev->base_addr;
> @@ -669,7 +672,7 @@ static void dwmac4_set_filter(struct mac_device_info *hw,
> int reg = 1;
>
> netdev_for_each_uc_addr(ha, dev) {
> - dwmac4_set_umac_addr(hw, ha->addr, reg);
> + dwmac4_set_umac_addr(priv, hw, ha->addr, reg);
> reg++;
> }
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
> index 89a14084c611..bd3084efc808 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
> @@ -169,7 +169,7 @@ static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
> return ret;
> }
>
> -static int dwmac4_rd_get_tx_len(struct dma_desc *p)
> +static int dwmac4_rd_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
> {
> return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
> }
> @@ -290,8 +290,8 @@ static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
> return 0;
> }
>
> -static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
> - int mode, int end, int bfsize)
> +static void dwmac4_rd_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
> + int disable_rx_ic, int mode, int end, int bfsize)
> {
> dwmac4_set_rx_owner(p, disable_rx_ic);
> }
> @@ -304,9 +304,9 @@ static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
> p->des3 = 0;
> }
>
> -static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
> - bool csum_flag, int mode, bool tx_own,
> - bool ls, unsigned int tot_pkt_len)
> +static void dwmac4_rd_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
> + int is_fs, int len, bool csum_flag, int mode,
> + bool tx_own, bool ls, unsigned int tot_pkt_len)
> {
> unsigned int tdes3 = le32_to_cpu(p->des3);
>
> @@ -456,13 +456,14 @@ static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
> p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
> }
>
> -static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
> +static void dwmac4_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
> + dma_addr_t addr)
> {
> p->des0 = cpu_to_le32(lower_32_bits(addr));
> p->des1 = cpu_to_le32(upper_32_bits(addr));
> }
>
> -static void dwmac4_clear(struct dma_desc *p)
> +static void dwmac4_clear(struct stmmac_priv *priv, struct dma_desc *p)
> {
> p->des0 = 0;
> p->des1 = 0;
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
> index 84d3a8551b03..97dad00dc850 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
> @@ -15,7 +15,8 @@
> #include "dwmac4_dma.h"
> #include "stmmac.h"
>
> -static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
> +static void dwmac4_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
> + struct stmmac_axi *axi)
> {
> u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
> int i;
> @@ -152,7 +153,7 @@ static void dwmac410_dma_init_channel(struct stmmac_priv *priv,
> ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
> }
>
> -static void dwmac4_dma_init(void __iomem *ioaddr,
> +static void dwmac4_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg, int atds)
> {
> u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
> @@ -374,7 +375,8 @@ static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv,
> writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
> }
>
> -static int dwmac4_get_hw_feature(void __iomem *ioaddr,
> +static int dwmac4_get_hw_feature(struct stmmac_priv *priv,
> + void __iomem *ioaddr,
> struct dma_features *dma_cap)
> {
> u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
> index 358e7dcb6a9a..aaab5ab38373 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
> @@ -231,7 +231,7 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
> #define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
> #define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
>
> -int dwmac4_dma_reset(void __iomem *ioaddr);
> +int dwmac4_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
> void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan, bool rx, bool tx);
> void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
> index 9470d3fd2ded..1191f0c1d7f1 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
> @@ -13,7 +13,7 @@
> #include "dwmac4.h"
> #include "stmmac.h"
>
> -int dwmac4_dma_reset(void __iomem *ioaddr)
> +int dwmac4_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
> {
> u32 value = readl(ioaddr + DMA_BUS_MODE);
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> index 72672391675f..77141391bd2f 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> @@ -152,7 +152,8 @@
> #define NUM_DWMAC1000_DMA_REGS 23
> #define NUM_DWMAC4_DMA_REGS 27
>
> -void dwmac_enable_dma_transmission(void __iomem *ioaddr);
> +void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
> + void __iomem *ioaddr, u32 chan);
> void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan, bool rx, bool tx);
> void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
> @@ -167,6 +168,6 @@ void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan);
> int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_extra_stats *x, u32 chan, u32 dir);
> -int dwmac_dma_reset(void __iomem *ioaddr);
> +int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
>
> #endif /* __DWMAC_DMA_H__ */
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> index 7907d62d3437..0cb337ffb7ac 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> @@ -14,7 +14,7 @@
>
> #define GMAC_HI_REG_AE 0x80000000
>
> -int dwmac_dma_reset(void __iomem *ioaddr)
> +int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
> {
> u32 value = readl(ioaddr + DMA_BUS_MODE);
>
> @@ -28,7 +28,8 @@ int dwmac_dma_reset(void __iomem *ioaddr)
> }
>
> /* CSR1 enables the transmit DMA to check for new descriptor */
> -void dwmac_enable_dma_transmission(void __iomem *ioaddr)
> +void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
> + void __iomem *ioaddr, u32 chan)
> {
> writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
> }
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> index 453e88b75be0..a993591e05bd 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> @@ -375,7 +375,8 @@ static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
> writel(val, ioaddr + XGMAC_PMT);
> }
>
> -static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
> +static void dwxgmac2_set_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> const unsigned char *addr,
> unsigned int reg_n)
> {
> @@ -389,7 +390,8 @@ static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
> writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
> }
>
> -static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
> +static void dwxgmac2_get_umac_addr(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> unsigned char *addr, unsigned int reg_n)
> {
> void __iomem *ioaddr = hw->pcsr;
> @@ -478,7 +480,8 @@ static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
> writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
> }
>
> -static void dwxgmac2_set_filter(struct mac_device_info *hw,
> +static void dwxgmac2_set_filter(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> struct net_device *dev)
> {
> void __iomem *ioaddr = (void __iomem *)dev->base_addr;
> @@ -523,7 +526,7 @@ static void dwxgmac2_set_filter(struct mac_device_info *hw,
> int reg = 1;
>
> netdev_for_each_uc_addr(ha, dev) {
> - dwxgmac2_set_umac_addr(hw, ha->addr, reg);
> + dwxgmac2_set_umac_addr(priv, hw, ha->addr, reg);
> reg++;
> }
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
> index fc82862a612c..cefcbabab2c0 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
> @@ -39,7 +39,7 @@ static int dwxgmac2_get_rx_status(struct stmmac_extra_stats *x,
> return good_frame;
> }
>
> -static int dwxgmac2_get_tx_len(struct dma_desc *p)
> +static int dwxgmac2_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
> {
> return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
> }
> @@ -126,8 +126,8 @@ static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
> return !ret;
> }
>
> -static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
> - int mode, int end, int bfsize)
> +static void dwxgmac2_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
> + int disable_rx_ic, int mode, int end, int bfsize)
> {
> dwxgmac2_set_rx_owner(p, disable_rx_ic);
> }
> @@ -140,9 +140,9 @@ static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)
> p->des3 = 0;
> }
>
> -static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
> - bool csum_flag, int mode, bool tx_own,
> - bool ls, unsigned int tot_pkt_len)
> +static void dwxgmac2_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
> + int is_fs, int len, bool csum_flag, int mode,
> + bool tx_own, bool ls, unsigned int tot_pkt_len)
> {
> unsigned int tdes3 = le32_to_cpu(p->des3);
>
> @@ -239,13 +239,14 @@ static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)
> p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
> }
>
> -static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
> +static void dwxgmac2_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
> + dma_addr_t addr)
> {
> p->des0 = cpu_to_le32(lower_32_bits(addr));
> p->des1 = cpu_to_le32(upper_32_bits(addr));
> }
>
> -static void dwxgmac2_clear(struct dma_desc *p)
> +static void dwxgmac2_clear(struct stmmac_priv *priv, struct dma_desc *p)
> {
> p->des0 = 0;
> p->des1 = 0;
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> index 3cde695fec91..4d1dc6d7eacb 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> @@ -8,7 +8,7 @@
> #include "stmmac.h"
> #include "dwxgmac2.h"
>
> -static int dwxgmac2_dma_reset(void __iomem *ioaddr)
> +static int dwxgmac2_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
> {
> u32 value = readl(ioaddr + XGMAC_DMA_MODE);
>
> @@ -19,7 +19,7 @@ static int dwxgmac2_dma_reset(void __iomem *ioaddr)
> !(value & XGMAC_SWR), 0, 100000);
> }
>
> -static void dwxgmac2_dma_init(void __iomem *ioaddr,
> +static void dwxgmac2_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg, int atds)
> {
> u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
> @@ -81,7 +81,8 @@ static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv,
> writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
> }
>
> -static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
> +static void dwxgmac2_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
> + struct stmmac_axi *axi)
> {
> u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
> int i;
> @@ -386,7 +387,8 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv,
> return ret;
> }
>
> -static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
> +static int dwxgmac2_get_hw_feature(struct stmmac_priv *priv,
> + void __iomem *ioaddr,
> struct dma_features *dma_cap)
> {
> u32 hw_cap;
> diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
> index 937b7a0466fc..43ae8c7defe1 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
> @@ -76,7 +76,7 @@ static int enh_desc_get_tx_status(struct stmmac_extra_stats *x,
> return ret;
> }
>
> -static int enh_desc_get_tx_len(struct dma_desc *p)
> +static int enh_desc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
> {
> return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);
> }
> @@ -249,8 +249,8 @@ static int enh_desc_get_rx_status(struct stmmac_extra_stats *x,
> return ret;
> }
>
> -static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
> - int mode, int end, int bfsize)
> +static void enh_desc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
> + int disable_rx_ic, int mode, int end, int bfsize)
> {
> int bfsize1;
>
> @@ -308,9 +308,9 @@ static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
> enh_desc_end_tx_desc_on_ring(p, ter);
> }
>
> -static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
> - bool csum_flag, int mode, bool tx_own,
> - bool ls, unsigned int tot_pkt_len)
> +static void enh_desc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
> + int is_fs, int len, bool csum_flag, int mode,
> + bool tx_own, bool ls, unsigned int tot_pkt_len)
> {
> unsigned int tdes0 = le32_to_cpu(p->des0);
>
> @@ -435,12 +435,13 @@ static void enh_desc_display_ring(void *head, unsigned int size, bool rx,
> pr_info("\n");
> }
>
> -static void enh_desc_set_addr(struct dma_desc *p, dma_addr_t addr)
> +static void enh_desc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
> + dma_addr_t addr)
> {
> p->des2 = cpu_to_le32(addr);
> }
>
> -static void enh_desc_clear(struct dma_desc *p)
> +static void enh_desc_clear(struct stmmac_priv *priv, struct dma_desc *p)
> {
> p->des2 = 0;
> }
> diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
> index b8ba8f2d8041..93cead5613e3 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
> @@ -97,7 +97,7 @@ int stmmac_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
> if (plat && plat->fix_soc_reset)
> return plat->fix_soc_reset(plat, ioaddr);
>
> - return stmmac_do_callback(priv, dma, reset, ioaddr);
> + return stmmac_do_callback(priv, dma, reset, priv, ioaddr);
> }
>
> static const struct stmmac_hwif_entry {
> diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
> index b95d3e137813..fd63713fcaa1 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
> @@ -35,14 +35,14 @@ struct dma_edesc;
> /* Descriptors helpers */
> struct stmmac_desc_ops {
> /* DMA RX descriptor ring initialization */
> - void (*init_rx_desc)(struct dma_desc *p, int disable_rx_ic, int mode,
> - int end, int bfsize);
> + void (*init_rx_desc)(struct stmmac_priv *priv, struct dma_desc *p,
> + int disable_rx_ic, int mode, int end, int bfsize);
> /* DMA TX descriptor ring initialization */
> void (*init_tx_desc)(struct dma_desc *p, int mode, int end);
> /* Invoked by the xmit function to prepare the tx descriptor */
> - void (*prepare_tx_desc)(struct dma_desc *p, int is_fs, int len,
> - bool csum_flag, int mode, bool tx_own, bool ls,
> - unsigned int tot_pkt_len);
> + void (*prepare_tx_desc)(struct stmmac_priv *priv, struct dma_desc *p,
> + int is_fs, int len, bool csum_flag, int mode,
> + bool tx_own, bool ls, unsigned int tot_pkt_len);
> void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
> int len2, bool tx_own, bool ls, unsigned int tcphdrlen,
> unsigned int tcppayloadlen);
> @@ -60,7 +60,7 @@ struct stmmac_desc_ops {
> int (*tx_status)(struct stmmac_extra_stats *x,
> struct dma_desc *p, void __iomem *ioaddr);
> /* Get the buffer size from the descriptor */
> - int (*get_tx_len)(struct dma_desc *p);
> + int (*get_tx_len)(struct stmmac_priv *priv, struct dma_desc *p);
> /* Handle extra events on specific interrupts hw dependent */
> void (*set_rx_owner)(struct dma_desc *p, int disable_rx_ic);
> /* Get the receive frame size */
> @@ -84,9 +84,10 @@ struct stmmac_desc_ops {
> /* set MSS via context descriptor */
> void (*set_mss)(struct dma_desc *p, unsigned int mss);
> /* set descriptor skbuff address */
> - void (*set_addr)(struct dma_desc *p, dma_addr_t addr);
> + void (*set_addr)(struct stmmac_priv *priv, struct dma_desc *p,
> + dma_addr_t addr);
> /* clear descriptor */
> - void (*clear)(struct dma_desc *p);
> + void (*clear)(struct stmmac_priv *priv, struct dma_desc *p);
> /* RSS */
> int (*get_rx_hash)(struct dma_desc *p, u32 *hash,
> enum pkt_hash_types *type);
> @@ -100,11 +101,11 @@ struct stmmac_desc_ops {
> };
>
> #define stmmac_init_rx_desc(__priv, __args...) \
> - stmmac_do_void_callback(__priv, desc, init_rx_desc, __args)
> + stmmac_do_void_callback(__priv, desc, init_rx_desc, __priv, __args)
> #define stmmac_init_tx_desc(__priv, __args...) \
> stmmac_do_void_callback(__priv, desc, init_tx_desc, __args)
> #define stmmac_prepare_tx_desc(__priv, __args...) \
> - stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __args)
> + stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __priv, __args)
> #define stmmac_prepare_tso_tx_desc(__priv, __args...) \
> stmmac_do_void_callback(__priv, desc, prepare_tso_tx_desc, __args)
> #define stmmac_set_tx_owner(__priv, __args...) \
> @@ -120,7 +121,7 @@ struct stmmac_desc_ops {
> #define stmmac_tx_status(__priv, __args...) \
> stmmac_do_callback(__priv, desc, tx_status, __args)
> #define stmmac_get_tx_len(__priv, __args...) \
> - stmmac_do_callback(__priv, desc, get_tx_len, __args)
> + stmmac_do_callback(__priv, desc, get_tx_len, __priv, __args)
> #define stmmac_set_rx_owner(__priv, __args...) \
> stmmac_do_void_callback(__priv, desc, set_rx_owner, __args)
> #define stmmac_get_rx_frame_len(__priv, __args...) \
> @@ -142,9 +143,9 @@ struct stmmac_desc_ops {
> #define stmmac_set_mss(__priv, __args...) \
> stmmac_do_void_callback(__priv, desc, set_mss, __args)
> #define stmmac_set_desc_addr(__priv, __args...) \
> - stmmac_do_void_callback(__priv, desc, set_addr, __args)
> + stmmac_do_void_callback(__priv, desc, set_addr, __priv, __args)
> #define stmmac_clear_desc(__priv, __args...) \
> - stmmac_do_void_callback(__priv, desc, clear, __args)
> + stmmac_do_void_callback(__priv, desc, clear, __priv, __args)
> #define stmmac_get_rx_hash(__priv, __args...) \
> stmmac_do_callback(__priv, desc, get_rx_hash, __args)
> #define stmmac_get_rx_header_len(__priv, __args...) \
> @@ -166,9 +167,9 @@ struct dma_features;
> /* Specific DMA helpers */
> struct stmmac_dma_ops {
> /* DMA core initialization */
> - int (*reset)(void __iomem *ioaddr);
> - void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
> - int atds);
> + int (*reset)(struct stmmac_priv *priv, void __iomem *ioaddr);
> + void (*init)(struct stmmac_priv *priv, void __iomem *ioaddr,
> + struct stmmac_dma_cfg *dma_cfg, int atds);
> void (*init_chan)(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg, u32 chan);
> void (*init_rx_chan)(struct stmmac_priv *priv, void __iomem *ioaddr,
> @@ -178,7 +179,8 @@ struct stmmac_dma_ops {
> struct stmmac_dma_cfg *dma_cfg,
> dma_addr_t phy, u32 chan);
> /* Configure the AXI Bus Mode Register */
> - void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
> + void (*axi)(struct stmmac_priv *priv, void __iomem *ioaddr,
> + struct stmmac_axi *axi);
> /* Dump DMA registers */
> void (*dump_regs)(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 *reg_space);
> @@ -190,7 +192,8 @@ struct stmmac_dma_ops {
> /* To track extra statistic (if supported) */
> void (*dma_diagnostic_fr)(struct stmmac_extra_stats *x,
> void __iomem *ioaddr);
> - void (*enable_dma_transmission) (void __iomem *ioaddr);
> + void (*enable_dma_transmission)(struct stmmac_priv *priv,
> + void __iomem *ioaddr, u32 chan);
> void (*enable_dma_irq)(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan, bool rx, bool tx);
> void (*disable_dma_irq)(struct stmmac_priv *priv, void __iomem *ioaddr,
> @@ -206,7 +209,7 @@ struct stmmac_dma_ops {
> int (*dma_interrupt)(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_extra_stats *x, u32 chan, u32 dir);
> /* If supported then get the optional core features */
> - int (*get_hw_feature)(void __iomem *ioaddr,
> + int (*get_hw_feature)(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct dma_features *dma_cap);
> /* Program the HW RX Watchdog */
> void (*rx_watchdog)(struct stmmac_priv *priv, void __iomem *ioaddr,
> @@ -232,7 +235,7 @@ struct stmmac_dma_ops {
> };
>
> #define stmmac_dma_init(__priv, __args...) \
> - stmmac_do_void_callback(__priv, dma, init, __args)
> + stmmac_do_void_callback(__priv, dma, init, __priv, __args)
> #define stmmac_init_chan(__priv, __args...) \
> stmmac_do_void_callback(__priv, dma, init_chan, __priv, __args)
> #define stmmac_init_rx_chan(__priv, __args...) \
> @@ -240,7 +243,7 @@ struct stmmac_dma_ops {
> #define stmmac_init_tx_chan(__priv, __args...) \
> stmmac_do_void_callback(__priv, dma, init_tx_chan, __priv, __args)
> #define stmmac_axi(__priv, __args...) \
> - stmmac_do_void_callback(__priv, dma, axi, __args)
> + stmmac_do_void_callback(__priv, dma, axi, __priv, __args)
> #define stmmac_dump_dma_regs(__priv, __args...) \
> stmmac_do_void_callback(__priv, dma, dump_regs, __priv, __args)
> #define stmmac_dma_rx_mode(__priv, __args...) \
> @@ -250,7 +253,7 @@ struct stmmac_dma_ops {
> #define stmmac_dma_diagnostic_fr(__priv, __args...) \
> stmmac_do_void_callback(__priv, dma, dma_diagnostic_fr, __args)
> #define stmmac_enable_dma_transmission(__priv, __args...) \
> - stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __args)
> + stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __priv, __args)
> #define stmmac_enable_dma_irq(__priv, __args...) \
> stmmac_do_void_callback(__priv, dma, enable_dma_irq, __priv, __args)
> #define stmmac_disable_dma_irq(__priv, __args...) \
> @@ -266,7 +269,7 @@ struct stmmac_dma_ops {
> #define stmmac_dma_interrupt_status(__priv, __args...) \
> stmmac_do_callback(__priv, dma, dma_interrupt, __priv, __args)
> #define stmmac_get_hw_feature(__priv, __args...) \
> - stmmac_do_callback(__priv, dma, get_hw_feature, __args)
> + stmmac_do_callback(__priv, dma, get_hw_feature, __priv, __args)
> #define stmmac_rx_watchdog(__priv, __args...) \
> stmmac_do_void_callback(__priv, dma, rx_watchdog, __priv, __args)
> #define stmmac_set_tx_ring_len(__priv, __args...) \
> @@ -338,17 +341,21 @@ struct stmmac_ops {
> int (*host_mtl_irq_status)(struct stmmac_priv *priv,
> struct mac_device_info *hw, u32 chan);
> /* Multicast filter setting */
> - void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
> + void (*set_filter)(struct stmmac_priv *priv, struct mac_device_info *hw,
> + struct net_device *dev);
> /* Flow control setting */
> void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
> unsigned int fc, unsigned int pause_time, u32 tx_cnt);
> /* Set power management mode (e.g. magic frame) */
> void (*pmt)(struct mac_device_info *hw, unsigned long mode);
> /* Set/Get Unicast MAC addresses */
> - void (*set_umac_addr)(struct mac_device_info *hw,
> + void (*set_umac_addr)(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> const unsigned char *addr,
> unsigned int reg_n);
> - void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
> + void (*get_umac_addr)(struct stmmac_priv *priv,
> + struct mac_device_info *hw,
> + unsigned char *addr,
> unsigned int reg_n);
> void (*set_eee_mode)(struct mac_device_info *hw,
> bool en_tx_lpi_clockgating);
> @@ -452,15 +459,15 @@ struct stmmac_ops {
> #define stmmac_host_mtl_irq_status(__priv, __args...) \
> stmmac_do_callback(__priv, mac, host_mtl_irq_status, __priv, __args)
> #define stmmac_set_filter(__priv, __args...) \
> - stmmac_do_void_callback(__priv, mac, set_filter, __args)
> + stmmac_do_void_callback(__priv, mac, set_filter, __priv, __args)
> #define stmmac_flow_ctrl(__priv, __args...) \
> stmmac_do_void_callback(__priv, mac, flow_ctrl, __args)
> #define stmmac_pmt(__priv, __args...) \
> stmmac_do_void_callback(__priv, mac, pmt, __args)
> #define stmmac_set_umac_addr(__priv, __args...) \
> - stmmac_do_void_callback(__priv, mac, set_umac_addr, __args)
> + stmmac_do_void_callback(__priv, mac, set_umac_addr, __priv, __args)
> #define stmmac_get_umac_addr(__priv, __args...) \
> - stmmac_do_void_callback(__priv, mac, get_umac_addr, __args)
> + stmmac_do_void_callback(__priv, mac, get_umac_addr, __priv, __args)
> #define stmmac_set_eee_mode(__priv, __args...) \
> stmmac_do_void_callback(__priv, mac, set_eee_mode, __args)
> #define stmmac_reset_eee_mode(__priv, __args...) \
> @@ -563,8 +570,8 @@ struct stmmac_rx_queue;
>
> /* Helpers to manage the descriptors for chain and ring modes */
> struct stmmac_mode_ops {
> - void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
> - unsigned int extend_desc);
> + void (*init)(struct stmmac_priv *priv, void *des, dma_addr_t phy_addr,
> + unsigned int size, unsigned int extend_desc);
> unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
> int (*jumbo_frm)(struct stmmac_tx_queue *tx_q, struct sk_buff *skb,
> int csum);
> @@ -575,7 +582,7 @@ struct stmmac_mode_ops {
> };
>
> #define stmmac_mode_init(__priv, __args...) \
> - stmmac_do_void_callback(__priv, mode, init, __args)
> + stmmac_do_void_callback(__priv, mode, init, __priv, __args)
> #define stmmac_is_jumbo_frm(__priv, __args...) \
> stmmac_do_callback(__priv, mode, is_jumbo_frm, __args)
> #define stmmac_jumbo_frm(__priv, __args...) \
> diff --git a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
> index 68a7cfcb1d8f..5fb3103db5cd 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
> @@ -57,7 +57,7 @@ static int ndesc_get_tx_status(struct stmmac_extra_stats *x,
> return ret;
> }
>
> -static int ndesc_get_tx_len(struct dma_desc *p)
> +static int ndesc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
> {
> return (le32_to_cpu(p->des1) & RDES1_BUFFER1_SIZE_MASK);
> }
> @@ -115,8 +115,8 @@ static int ndesc_get_rx_status(struct stmmac_extra_stats *x,
> return ret;
> }
>
> -static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
> - int end, int bfsize)
> +static void ndesc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
> + int disable_rx_ic, int mode, int end, int bfsize)
> {
> int bfsize1;
>
> @@ -174,9 +174,9 @@ static void ndesc_release_tx_desc(struct dma_desc *p, int mode)
> ndesc_end_tx_desc_on_ring(p, ter);
> }
>
> -static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
> - bool csum_flag, int mode, bool tx_own,
> - bool ls, unsigned int tot_pkt_len)
> +static void ndesc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
> + int is_fs, int len, bool csum_flag, int mode,
> + bool tx_own, bool ls, unsigned int tot_pkt_len)
> {
> unsigned int tdes1 = le32_to_cpu(p->des1);
>
> @@ -285,12 +285,13 @@ static void ndesc_display_ring(void *head, unsigned int size, bool rx,
> pr_info("\n");
> }
>
> -static void ndesc_set_addr(struct dma_desc *p, dma_addr_t addr)
> +static void ndesc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
> + dma_addr_t addr)
> {
> p->des2 = cpu_to_le32(addr);
> }
>
> -static void ndesc_clear(struct dma_desc *p)
> +static void ndesc_clear(struct stmmac_priv *priv, struct dma_desc *p)
> {
> p->des2 = 0;
> }
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 3e50fd53a617..132d4f679b95 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -2509,7 +2509,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
> true, priv->mode, true, true,
> xdp_desc.len);
>
> - stmmac_enable_dma_transmission(priv, priv->ioaddr);
> + stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
>
> tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
> entry = tx_q->cur_tx;
> @@ -4615,7 +4615,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
>
> netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
>
> - stmmac_enable_dma_transmission(priv, priv->ioaddr);
> + stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
>
> stmmac_flush_tx_descriptors(priv, queue);
> stmmac_tx_timer_arm(priv, queue);
> @@ -4835,7 +4835,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
> u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
> }
>
> - stmmac_enable_dma_transmission(priv, priv->ioaddr);
> + stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
>
> entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
> tx_q->cur_tx = entry;
> --
> 2.31.4
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-11 20:07 ` Andrew Lunn
@ 2023-11-21 9:55 ` Yanteng Si
2023-11-22 3:39 ` Andrew Lunn
0 siblings, 1 reply; 32+ messages in thread
From: Yanteng Si @ 2023-11-21 9:55 UTC (permalink / raw)
To: Andrew Lunn
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
Hi Andrew,
在 2023/11/12 04:07, Andrew Lunn 写道:
>> +#ifdef CONFIG_DWMAC_LOONGSON
>> +#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE_LOONGSON | DMA_INTR_ENA_AIE | \
>> + DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
>> +#else
>> #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
>> DMA_INTR_ENA_UNE)
>> +#endif
> The aim is to produce one kernel which runs on all possible
> variants. So we don't like to see this sort of #ifdef. Please try to
> remove them.
We now run into a tricky problem: we only have a few register
definitions(DMA_XXX_LOONGSON)
that are not the same as the dwmac1000 register definition.
In this case, if we use these "#ifdef", it will reuse most of the
dwmac1000 code to
reduce maintenance stress, at the cost of sacrificing a little
readability; If we created
a new xxx_dma.h, it would add a new set of code similar to dwmac1000,
which is exactly
what the v4 patch did, which was great for readability, but it also made
the code more
maintenance stress, and we got reviews complaining in v4. That is, we
need to find a
balance between readability and maintainability.
however， we haven't yet come up with a way to do both, so it would be
great if you
could give us some advice on this.
v4:<https://lore.kernel.org/loongarch/cover.1692696115.git.chenfeiyang@loongson.cn/>
>
>> @@ -167,7 +167,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan];
>> int ret = 0;
>> /* read the status register (CSR5) */
>> - u32 intr_status = readl(ioaddr + DMA_STATUS);
>> + u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
>>
> Please break this patch up. Changes like the above are simple to
> understand. So have one patch which just adds these macros and makes
> use of them.
OK!
>
>> #ifdef DWMAC_DMA_DEBUG
>> /* Enable it to monitor DMA rx/tx status in case of critical problems */
>> @@ -182,7 +182,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
>> intr_status &= DMA_STATUS_MSK_TX;
>>
>> /* ABNORMAL interrupts */
>> - if (unlikely(intr_status & DMA_STATUS_AIS)) {
>> + if (unlikely(intr_status & DMA_ABNOR_INTR_STATUS)) {
> However, this is not obviously correct. You need to explain in the
> commit message why this change is needed.
>
> Lots of small patches make the understanding easier.
Because Loongson has two AIS, so:
#ifdef CONFIG_DWMAC_LOONGSON
...
#define DMA_ABNOR_INTR_STATUS (DMA_STATUS_TX_AIS_LOONGSON |
DMA_STATUS_RX_AIS_LOONGSON)
...
#else
...
#define DMA_ABNOR_INTR_STATUS DMA_STATUS_AIS
...
#endif
>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> index 7371713c116d..aafc75fa14a0 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> @@ -7062,6 +7062,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
>> /* dwmac-sun8i only work in chain mode */
>> if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
>> chain_mode = 1;
>> +
>> priv->chain_mode = chain_mode;
> Please avoid white space changes.
OK!
Thanks for your review!
Thanks,
Yanteng
>
> Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags
2023-11-11 19:51 ` Andrew Lunn
@ 2023-11-21 12:01 ` Yanteng Si
2023-11-21 13:59 ` Andrew Lunn
0 siblings, 1 reply; 32+ messages in thread
From: Yanteng Si @ 2023-11-21 12:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
在 2023/11/12 03:51, Andrew Lunn 写道:
> On Fri, Nov 10, 2023 at 05:25:41PM +0800, Yanteng Si wrote:
>> Some platforms need extra irq flags when request multi msi, add
>> irq_flags variable for them.
> It would be nice to document what flags are needed.
>
> You also seem to be pass the same flags to all instances of
> request_irq. However, the flags should be specific to one irq. So you
> need irq_irq_flags, wol_irq_flags, lpi_irq_flags, etc.
It is a trigger type.
Thanks,
Yanteng
>
>
> Andrew
>
> ---
> pw-bot: cr
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags
2023-11-21 12:01 ` Yanteng Si
@ 2023-11-21 13:59 ` Andrew Lunn
2023-11-24 12:49 ` Yanteng Si
0 siblings, 1 reply; 32+ messages in thread
From: Andrew Lunn @ 2023-11-21 13:59 UTC (permalink / raw)
To: Yanteng Si
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
On Tue, Nov 21, 2023 at 08:01:53PM +0800, Yanteng Si wrote:
>
> 在 2023/11/12 03:51, Andrew Lunn 写道:
> > On Fri, Nov 10, 2023 at 05:25:41PM +0800, Yanteng Si wrote:
> > > Some platforms need extra irq flags when request multi msi, add
> > > irq_flags variable for them.
> > It would be nice to document what flags are needed.
> >
> > You also seem to be pass the same flags to all instances of
> > request_irq. However, the flags should be specific to one irq. So you
> > need irq_irq_flags, wol_irq_flags, lpi_irq_flags, etc.
>
> It is a trigger type.
Yes, i figure that out eventually. But it would be good to state it
here.
And trigger type, edge verses level, rising vs falling, is a per
interrupt property. So you do need the flag per interrupt.
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-21 9:55 ` Yanteng Si
@ 2023-11-22 3:39 ` Andrew Lunn
2023-11-22 4:02 ` Xi Ruoyao
2023-11-24 13:14 ` Yanteng Si
0 siblings, 2 replies; 32+ messages in thread
From: Andrew Lunn @ 2023-11-22 3:39 UTC (permalink / raw)
To: Yanteng Si
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
On Tue, Nov 21, 2023 at 05:55:24PM +0800, Yanteng Si wrote:
> Hi Andrew,
>
> 在 2023/11/12 04:07, Andrew Lunn 写道:
> > > +#ifdef CONFIG_DWMAC_LOONGSON
> > > +#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE_LOONGSON | DMA_INTR_ENA_AIE | \
> > > + DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
> > > +#else
> > > #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
> > > DMA_INTR_ENA_UNE)
> > > +#endif
> > The aim is to produce one kernel which runs on all possible
> > variants. So we don't like to see this sort of #ifdef. Please try to
> > remove them.
>
> We now run into a tricky problem: we only have a few register
> definitions(DMA_XXX_LOONGSON)
>
> that are not the same as the dwmac1000 register definition.
What does DMA_INTR_ENA_AIE_LOONGSON do? This seems like an interrupt
mask, and this is enabling an interrupt source? However, i don't see
this bit being tested in any interrupt status register? Or is it
hiding in one of the other patches?
This is where lots of small patches, with good descriptions helps.
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-22 3:39 ` Andrew Lunn
@ 2023-11-22 4:02 ` Xi Ruoyao
2023-11-24 13:14 ` Yanteng Si
1 sibling, 0 replies; 32+ messages in thread
From: Xi Ruoyao @ 2023-11-22 4:02 UTC (permalink / raw)
To: Andrew Lunn, Yanteng Si
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
On Wed, 2023-11-22 at 04:39 +0100, Andrew Lunn wrote:
> On Tue, Nov 21, 2023 at 05:55:24PM +0800, Yanteng Si wrote:
> > Hi Andrew,
> >
> > 在 2023/11/12 04:07, Andrew Lunn 写道:
> > > > +#ifdef CONFIG_DWMAC_LOONGSON
> > > > +#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE_LOONGSON | DMA_INTR_ENA_AIE | \
> > > > + DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
> > > > +#else
> > > > #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
> > > > DMA_INTR_ENA_UNE)
> > > > +#endif
> > > The aim is to produce one kernel which runs on all possible
> > > variants. So we don't like to see this sort of #ifdef. Please try to
> > > remove them.
> >
> > We now run into a tricky problem: we only have a few register
> > definitions(DMA_XXX_LOONGSON)
> >
> > that are not the same as the dwmac1000 register definition.
You need to determine to use Loongson register or general dwmac1000
register definition at *runtime*, not *compile time*.
Or when people enable CONFIG_DWMAC_LOONGSON (for a release build of
kernel in a mainstream distro the maintainers often enable as many
drivers as possible) they'll suddenly find their dwmac1000's are broken
and we'll get many bug reports.
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags
2023-11-21 13:59 ` Andrew Lunn
@ 2023-11-24 12:49 ` Yanteng Si
0 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-11-24 12:49 UTC (permalink / raw)
To: Andrew Lunn
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
在 2023/11/21 21:59, Andrew Lunn 写道:
> Yes, i figure that out eventually. But it would be good to state it
> here.
>
> And trigger type, edge verses level, rising vs falling, is a per
> interrupt property. So you do need the flag per interrupt.
I see.
We decided to remove it in the next patch version, and to be honest, the
flag
is not being used at the moment, I have test it on the machine in the
last two
days. Thanks to this, I was able to make the first patch a bit smaller
as well.
Thanks for your review!
Thanks,
Yanteng
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-22 3:39 ` Andrew Lunn
2023-11-22 4:02 ` Xi Ruoyao
@ 2023-11-24 13:14 ` Yanteng Si
2023-11-24 14:51 ` Andrew Lunn
1 sibling, 1 reply; 32+ messages in thread
From: Yanteng Si @ 2023-11-24 13:14 UTC (permalink / raw)
To: Andrew Lunn
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
在 2023/11/22 11:39, Andrew Lunn 写道:
> On Tue, Nov 21, 2023 at 05:55:24PM +0800, Yanteng Si wrote:
>> Hi Andrew,
>>
>> 在 2023/11/12 04:07, Andrew Lunn 写道:
>>>> +#ifdef CONFIG_DWMAC_LOONGSON
>>>> +#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE_LOONGSON | DMA_INTR_ENA_AIE | \
>>>> + DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
>>>> +#else
>>>> #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
>>>> DMA_INTR_ENA_UNE)
>>>> +#endif
>>> The aim is to produce one kernel which runs on all possible
>>> variants. So we don't like to see this sort of #ifdef. Please try to
>>> remove them.
>> We now run into a tricky problem: we only have a few register
>> definitions(DMA_XXX_LOONGSON)
>>
>> that are not the same as the dwmac1000 register definition.
> What does DMA_INTR_ENA_AIE_LOONGSON do? This seems like an interrupt
> mask, and this is enabling an interrupt source? However, i don't see
> this bit being tested in any interrupt status register? Or is it
> hiding in one of the other patches?
In general, we split one into two.
the details are as follows：
DMA_INTR_ENA_NIE = DMA_INTR_ENA_NIE_LOONGSON= DMA_INTR_ENA_TX_NIE +
DMA_INTR_ENA_RX_NIE
DMA_INTR_ENA_AIE = DMA_INTR_ENA_AIE_LOONGSON= DMA_INTR_ENA_TX_AIE +
DMA_INTR_ENA_RX_AIE
DMA_STATUS_NIS = DMA_STATUS_TX_NIS_LOONGSON + DMA_STATUS_RX_NIS_LOONGSON
DMA_STATUS_AIS = DMA_STATUS_TX_AIS_LOONGSON + DMA_STATUS_RX_AIS_LOONGSON
DMA_STATUS_FBI = DMA_STATUS_TX_FBI_LOONGSON + DMA_STATUS_RX_FBI_LOONGSON
>
> This is where lots of small patches, with good descriptions helps.
Ok, thanks for your advice, I will try to split it in the next version.
Thanks,
Yanteng
>
> Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-24 13:14 ` Yanteng Si
@ 2023-11-24 14:51 ` Andrew Lunn
2023-11-24 16:44 ` Serge Semin
0 siblings, 1 reply; 32+ messages in thread
From: Andrew Lunn @ 2023-11-24 14:51 UTC (permalink / raw)
To: Yanteng Si
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
> In general, we split one into two.
>
> the details are as follows：
>
> DMA_INTR_ENA_NIE = DMA_INTR_ENA_NIE_LOONGSON= DMA_INTR_ENA_TX_NIE +
> DMA_INTR_ENA_RX_NIE
What does the documentation from Synopsys say about the bit you have
used for DMA_INTR_ENA_NIE_LOONGSON? Is it marked as being usable by IP
integrators for whatever they want, or is it marked as reserved?
I'm just wondering if we are heading towards a problem when the next
version of this IP assigns the bit to mean something else.
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-24 14:51 ` Andrew Lunn
@ 2023-11-24 16:44 ` Serge Semin
2023-11-26 12:25 ` Yanteng Si
0 siblings, 1 reply; 32+ messages in thread
From: Serge Semin @ 2023-11-24 16:44 UTC (permalink / raw)
To: Andrew Lunn
Cc: Yanteng Si, hkallweit1, peppe.cavallaro, alexandre.torgue,
joabreu, Jose.Abreu, chenhuacai, linux, dongbiao, guyinggang,
netdev, loongarch, chris.chenfeiyang
On Fri, Nov 24, 2023 at 03:51:08PM +0100, Andrew Lunn wrote:
> > In general, we split one into two.
> >
> > the details are as follows：
> >
> > DMA_INTR_ENA_NIE = DMA_INTR_ENA_NIE_LOONGSON= DMA_INTR_ENA_TX_NIE +
> > DMA_INTR_ENA_RX_NIE
>
> What does the documentation from Synopsys say about the bit you have
> used for DMA_INTR_ENA_NIE_LOONGSON? Is it marked as being usable by IP
> integrators for whatever they want, or is it marked as reserved?
>
> I'm just wondering if we are heading towards a problem when the next
> version of this IP assigns the bit to mean something else.
That's what I started to figure out in my initial message:
Link: https://lore.kernel.org/netdev/gxods3yclaqkrud6jxhvcjm67vfp5zmuoxjlr6llcddny7zwsr@473g74uk36xn/
but Yanteng for some reason ignored all my comments.
Anyway AFAICS this Loongson GMAC has NIE and AIE flags defined differently:
DW GMAC: NIE - BIT(16) - all non-fatal Tx and Rx errors,
AIE - BIT(15) - all fatal Tx, Rx and Bus errors.
Loongson GMAC: NIE - BIT(18) | BIT(17) - one flag for Tx and another for Rx errors.
AIE - BIT(16) | BIT(15) - Tx, Rx and don't know about the Bus errors.
So the Loongson GMAC has not only NIE/AIE flags re-defined, but
also get to occupy two reserved in the generic DW GMAC bits: BIT(18) and BIT(17).
Moreover Yanteng in his patch defines DMA_INTR_NORMAL as a combination
of both _generic_ DW and Loongson-specific NIE flags and
DMA_INTR_ABNORMAL as a combination of both _generic_ DW and
Loongson-specific AIE flags. At the very least it doesn't look
correct, since _generic_ DW GMAC NIE flag BIT(16) is defined as a part
of the Loongson GMAC AIE flags set.
-Serge(y)
>
> Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-24 16:44 ` Serge Semin
@ 2023-11-26 12:25 ` Yanteng Si
2023-11-27 11:32 ` Serge Semin
0 siblings, 1 reply; 32+ messages in thread
From: Yanteng Si @ 2023-11-26 12:25 UTC (permalink / raw)
To: Serge Semin, Andrew Lunn
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
Jose.Abreu, chenhuacai, linux, dongbiao, guyinggang, netdev,
loongarch, chris.chenfeiyang
在 2023/11/25 00:44, Serge Semin 写道:
> On Fri, Nov 24, 2023 at 03:51:08PM +0100, Andrew Lunn wrote:
>>> In general, we split one into two.
>>>
>>> the details are as follows：
>>>
>>> DMA_INTR_ENA_NIE = DMA_INTR_ENA_NIE_LOONGSON= DMA_INTR_ENA_TX_NIE +
>>> DMA_INTR_ENA_RX_NIE
>> What does the documentation from Synopsys say about the bit you have
>> used for DMA_INTR_ENA_NIE_LOONGSON? Is it marked as being usable by IP
>> integrators for whatever they want, or is it marked as reserved?
>>
>> I'm just wondering if we are heading towards a problem when the next
>> version of this IP assigns the bit to mean something else.
> That's what I started to figure out in my initial message:
> Link: https://lore.kernel.org/netdev/gxods3yclaqkrud6jxhvcjm67vfp5zmuoxjlr6llcddny7zwsr@473g74uk36xn/
> but Yanteng for some reason ignored all my comments.
Sorry, I always keep your review comments in mind, and even this version
of the patch is
largely based on your previous comments. Please give me some more time
and I promise
to answer your comments before the next patch is made.
>
> Anyway AFAICS this Loongson GMAC has NIE and AIE flags defined differently:
> DW GMAC: NIE - BIT(16) - all non-fatal Tx and Rx errors,
> AIE - BIT(15) - all fatal Tx, Rx and Bus errors.
> Loongson GMAC: NIE - BIT(18) | BIT(17) - one flag for Tx and another for Rx errors.
> AIE - BIT(16) | BIT(15) - Tx, Rx and don't know about the Bus errors.
> So the Loongson GMAC has not only NIE/AIE flags re-defined, but
> also get to occupy two reserved in the generic DW GMAC bits: BIT(18) and BIT(17).
>
> Moreover Yanteng in his patch defines DMA_INTR_NORMAL as a combination
> of both _generic_ DW and Loongson-specific NIE flags and
> DMA_INTR_ABNORMAL as a combination of both _generic_ DW and
> Loongson-specific AIE flags. At the very least it doesn't look
> correct, since _generic_ DW GMAC NIE flag BIT(16) is defined as a part
> of the Loongson GMAC AIE flags set.
We will consider this seriously, please give us some more time, and of
course, we
are looking forward to your opinions on this problem.
I hope you can accept my apologies, Please allow me to say sorry again.
Thanks for your review!
Thanks,
Yanteng
>
> -Serge(y)
>
>> Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-26 12:25 ` Yanteng Si
@ 2023-11-27 11:32 ` Serge Semin
2023-11-29 10:29 ` Yanteng Si
0 siblings, 1 reply; 32+ messages in thread
From: Serge Semin @ 2023-11-27 11:32 UTC (permalink / raw)
To: Yanteng Si
Cc: Andrew Lunn, hkallweit1, peppe.cavallaro, alexandre.torgue,
joabreu, Jose.Abreu, chenhuacai, linux, dongbiao, guyinggang,
netdev, loongarch, chris.chenfeiyang
Yanteng
On Sun, Nov 26, 2023 at 08:25:13PM +0800, Yanteng Si wrote:
>
> 在 2023/11/25 00:44, Serge Semin 写道:
> > On Fri, Nov 24, 2023 at 03:51:08PM +0100, Andrew Lunn wrote:
> > > > In general, we split one into two.
> > > >
> > > > the details are as follows：
> > > >
> > > > DMA_INTR_ENA_NIE = DMA_INTR_ENA_NIE_LOONGSON= DMA_INTR_ENA_TX_NIE +
> > > > DMA_INTR_ENA_RX_NIE
> > > What does the documentation from Synopsys say about the bit you have
> > > used for DMA_INTR_ENA_NIE_LOONGSON? Is it marked as being usable by IP
> > > integrators for whatever they want, or is it marked as reserved?
> > >
> > > I'm just wondering if we are heading towards a problem when the next
> > > version of this IP assigns the bit to mean something else.
> > That's what I started to figure out in my initial message:
> > Link: https://lore.kernel.org/netdev/gxods3yclaqkrud6jxhvcjm67vfp5zmuoxjlr6llcddny7zwsr@473g74uk36xn/
> > but Yanteng for some reason ignored all my comments.
>
> Sorry, I always keep your review comments in mind, and even this version of
> the patch is
>
> largely based on your previous comments. Please give me some more time and I
> promise
>
> to answer your comments before the next patch is made.
>
> >
> > Anyway AFAICS this Loongson GMAC has NIE and AIE flags defined differently:
> > DW GMAC: NIE - BIT(16) - all non-fatal Tx and Rx errors,
> > AIE - BIT(15) - all fatal Tx, Rx and Bus errors.
> > Loongson GMAC: NIE - BIT(18) | BIT(17) - one flag for Tx and another for Rx errors.
> > AIE - BIT(16) | BIT(15) - Tx, Rx and don't know about the Bus errors.
> > So the Loongson GMAC has not only NIE/AIE flags re-defined, but
> > also get to occupy two reserved in the generic DW GMAC bits: BIT(18) and BIT(17).
> >
> > Moreover Yanteng in his patch defines DMA_INTR_NORMAL as a combination
> > of both _generic_ DW and Loongson-specific NIE flags and
> > DMA_INTR_ABNORMAL as a combination of both _generic_ DW and
> > Loongson-specific AIE flags. At the very least it doesn't look
> > correct, since _generic_ DW GMAC NIE flag BIT(16) is defined as a part
> > of the Loongson GMAC AIE flags set.
>
> We will consider this seriously, please give us some more time, and of
> course, we
>
> are looking forward to your opinions on this problem.
>
>
> I hope you can accept my apologies, Please allow me to say sorry again.
Thanks for your response. No worries. I keep following this thread and
sending my comments because the changes here deeply concerns our
hardware. Besides the driver already looks unreasonably
overcomplicated and weakly structured in a lot of aspects. I bet
nobody here wants it to be having even more clumsy parts. That's why
all the "irritating" comments and nitpicks.
Anyway regarding the Loongson Multi-channels GMAC IRQs based on all
your info in the previous replies I guess what could be an acceptable
solution (with the subsystem/driver maintainers blessing) is something
like this:
1. Add new platform feature flag:
include/linux/stmmac.h:
+#define STMMAC_FLAG_HAS_LSMC BIT(13)
2. Update the stmmac_dma_ops.init() callback prototype to accepting
a pointer to the stmmac_priv instance:
drivers/net/ethernet/stmicro/stmmac/hwif.h:
void (*init)(struct stmmac_priv *priv, void __iomem *ioaddr,
struct stmmac_dma_cfg *dma_cfg, int atds);
+drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c ...
+drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c ...
+drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c ...
+drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c ...
!!!+drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c ...
3. Add the IRQs macros specific to the LoongSon Multi-channels GMAC:
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h:
+#define DMA_INTR_ENA_LS_NIE 0x00060000 /* Normal Loongson Tx/Rx Summary */
#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
...
+#define DMA_INTR_LS_NORMAL (DMA_INTR_ENA_LS_NIE | DMA_INTR_ENA_RIE | \
DMA_INTR_ENA_TIE)
#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
DMA_INTR_ENA_TIE)
...
+#define DMA_INTR_ENA_LS_AIE 0x00018000 /* Abnormal Loongson Tx/Rx Summary */
#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
...
define DMA_INTR_LS_ABNORMAL (DMA_INTR_ENA_LS_AIE | DMA_INTR_ENA_FBE | \
DMA_INTR_ENA_UNE)
#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
DMA_INTR_ENA_UNE)
...
#define DMA_INTR_LS_DEFAULT_MASK (DMA_INTR_LS_NORMAL | DMA_INTR_LS_ABNORMAL)
#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
etc for the DMA_STATUS_TX_*, DMA_STATUS_RX_* macros.
4. Update the DW GMAC DMA init() method to be activating all the
Normal and Abnormal Loongson-specific IRQs:
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c:
if (priv->plat->flags & STMMAC_FLAG_HAS_LSMC)
writel(DMA_INTR_LS_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
else
writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
5. Make sure your low-level driver sets the STMMAC_FLAG_HAS_LSMC flag
in the plat_stmmacenet_data structure instance.
Note 1. For the sake of consistency a similar update can be provided
for the dwmac_enable_dma_irq()/dwmac_disable_dma_irq() methods and
the DMA_INTR_DEFAULT_RX/DMA_INTR_DEFAULT_TX macros seeing your device
is able to disable/enable the xfer-specific summary IRQs. But it
doesn't look like required seeing the driver won't raise the summary
IRQs if no respective xfer IRQ is enabled. Most importantly this
update would add additional code to the Tx/Rx paths, which in a tiny
bit measure may affect the other platforms perf. So it's better to
avoid it if possible.
Note 2. The STMMAC_FLAG_HAS_LSMC flag might be utilized to tweak up
the other generic parts of the STMMAC driver.
Noet 3. An alternative to the step 3 above could be to define two
additional plat_stmmacenet_data fields like: dma_def_intr_mask,
dma_nor_stat, dma_abnor_stat, which would be initialized in the
stmmac_probe() method with the currently defined
DMA_INTR_DEFAULT_MASK, DMA_NOR_INTR_STATUS and DMA_ABNOR_INTR_STATUS
macros if they haven't been initialized by the low-level drivers.
These fields could be then used in the respective DMA IRQ init and
handler methods. I don't know which solution is better. At the first
glance this one might be even better than what is described in step 3.
Note 4. The solution above will also cover the Andrew's note of having
the kernel which runs on all possible variants.
-Serge(y)
>
>
> Thanks for your review!
>
>
> Thanks,
>
> Yanteng
>
> >
> > -Serge(y)
> >
> > > Andrew
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
2023-11-27 11:32 ` Serge Semin
@ 2023-11-29 10:29 ` Yanteng Si
0 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-11-29 10:29 UTC (permalink / raw)
To: Serge Semin
Cc: Andrew Lunn, hkallweit1, peppe.cavallaro, alexandre.torgue,
joabreu, Jose.Abreu, chenhuacai, linux, dongbiao, guyinggang,
netdev, loongarch, chris.chenfeiyang
在 2023/11/27 19:32, Serge Semin 写道:
> Yanteng
>
> On Sun, Nov 26, 2023 at 08:25:13PM +0800, Yanteng Si wrote:
>> 在 2023/11/25 00:44, Serge Semin 写道:
>>> On Fri, Nov 24, 2023 at 03:51:08PM +0100, Andrew Lunn wrote:
>>>>> In general, we split one into two.
>>>>>
>>>>> the details are as follows：
>>>>>
>>>>> DMA_INTR_ENA_NIE = DMA_INTR_ENA_NIE_LOONGSON= DMA_INTR_ENA_TX_NIE +
>>>>> DMA_INTR_ENA_RX_NIE
>>>> What does the documentation from Synopsys say about the bit you have
>>>> used for DMA_INTR_ENA_NIE_LOONGSON? Is it marked as being usable by IP
>>>> integrators for whatever they want, or is it marked as reserved?
>>>>
>>>> I'm just wondering if we are heading towards a problem when the next
>>>> version of this IP assigns the bit to mean something else.
>>> That's what I started to figure out in my initial message:
>>> Link: https://lore.kernel.org/netdev/gxods3yclaqkrud6jxhvcjm67vfp5zmuoxjlr6llcddny7zwsr@473g74uk36xn/
>>> but Yanteng for some reason ignored all my comments.
>> Sorry, I always keep your review comments in mind, and even this version of
>> the patch is
>>
>> largely based on your previous comments. Please give me some more time and I
>> promise
>>
>> to answer your comments before the next patch is made.
>>
>>> Anyway AFAICS this Loongson GMAC has NIE and AIE flags defined differently:
>>> DW GMAC: NIE - BIT(16) - all non-fatal Tx and Rx errors,
>>> AIE - BIT(15) - all fatal Tx, Rx and Bus errors.
>>> Loongson GMAC: NIE - BIT(18) | BIT(17) - one flag for Tx and another for Rx errors.
>>> AIE - BIT(16) | BIT(15) - Tx, Rx and don't know about the Bus errors.
>>> So the Loongson GMAC has not only NIE/AIE flags re-defined, but
>>> also get to occupy two reserved in the generic DW GMAC bits: BIT(18) and BIT(17).
>>>
>>> Moreover Yanteng in his patch defines DMA_INTR_NORMAL as a combination
>>> of both _generic_ DW and Loongson-specific NIE flags and
>>> DMA_INTR_ABNORMAL as a combination of both _generic_ DW and
>>> Loongson-specific AIE flags. At the very least it doesn't look
>>> correct, since _generic_ DW GMAC NIE flag BIT(16) is defined as a part
>>> of the Loongson GMAC AIE flags set.
>> We will consider this seriously, please give us some more time, and of
>> course, we
>>
>> are looking forward to your opinions on this problem.
>>
>>
>> I hope you can accept my apologies, Please allow me to say sorry again.
> Thanks for your response. No worries. I keep following this thread and
> sending my comments because the changes here deeply concerns our
> hardware. Besides the driver already looks unreasonably
> overcomplicated and weakly structured in a lot of aspects. I bet
> nobody here wants it to be having even more clumsy parts. That's why
> all the "irritating" comments and nitpicks.
I get it.
>
> Anyway regarding the Loongson Multi-channels GMAC IRQs based on all
> your info in the previous replies I guess what could be an acceptable
> solution (with the subsystem/driver maintainers blessing) is something
> like this:
Okay, thank you, I will try them one by one and report the results in time.
Thanks for your advice！
Thanks,
Yanteng
>
> 1. Add new platform feature flag:
> include/linux/stmmac.h:
> +#define STMMAC_FLAG_HAS_LSMC BIT(13)
>
> 2. Update the stmmac_dma_ops.init() callback prototype to accepting
> a pointer to the stmmac_priv instance:
> drivers/net/ethernet/stmicro/stmmac/hwif.h:
> void (*init)(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg, int atds);
> +drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c ...
> +drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c ...
> +drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c ...
> +drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c ...
> !!!+drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c ...
>
> 3. Add the IRQs macros specific to the LoongSon Multi-channels GMAC:
> drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h:
> +#define DMA_INTR_ENA_LS_NIE 0x00060000 /* Normal Loongson Tx/Rx Summary */
> #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
> ...
>
> +#define DMA_INTR_LS_NORMAL (DMA_INTR_ENA_LS_NIE | DMA_INTR_ENA_RIE | \
> DMA_INTR_ENA_TIE)
> #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
> DMA_INTR_ENA_TIE)
> ...
> +#define DMA_INTR_ENA_LS_AIE 0x00018000 /* Abnormal Loongson Tx/Rx Summary */
> #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
> ...
> define DMA_INTR_LS_ABNORMAL (DMA_INTR_ENA_LS_AIE | DMA_INTR_ENA_FBE | \
> DMA_INTR_ENA_UNE)
> #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
> DMA_INTR_ENA_UNE)
> ...
> #define DMA_INTR_LS_DEFAULT_MASK (DMA_INTR_LS_NORMAL | DMA_INTR_LS_ABNORMAL)
> #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
>
> etc for the DMA_STATUS_TX_*, DMA_STATUS_RX_* macros.
>
> 4. Update the DW GMAC DMA init() method to be activating all the
> Normal and Abnormal Loongson-specific IRQs:
> drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c:
> if (priv->plat->flags & STMMAC_FLAG_HAS_LSMC)
> writel(DMA_INTR_LS_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
> else
> writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
>
> 5. Make sure your low-level driver sets the STMMAC_FLAG_HAS_LSMC flag
> in the plat_stmmacenet_data structure instance.
>
> Note 1. For the sake of consistency a similar update can be provided
> for the dwmac_enable_dma_irq()/dwmac_disable_dma_irq() methods and
> the DMA_INTR_DEFAULT_RX/DMA_INTR_DEFAULT_TX macros seeing your device
> is able to disable/enable the xfer-specific summary IRQs. But it
> doesn't look like required seeing the driver won't raise the summary
> IRQs if no respective xfer IRQ is enabled. Most importantly this
> update would add additional code to the Tx/Rx paths, which in a tiny
> bit measure may affect the other platforms perf. So it's better to
> avoid it if possible.
>
> Note 2. The STMMAC_FLAG_HAS_LSMC flag might be utilized to tweak up
> the other generic parts of the STMMAC driver.
>
> Noet 3. An alternative to the step 3 above could be to define two
> additional plat_stmmacenet_data fields like: dma_def_intr_mask,
> dma_nor_stat, dma_abnor_stat, which would be initialized in the
> stmmac_probe() method with the currently defined
> DMA_INTR_DEFAULT_MASK, DMA_NOR_INTR_STATUS and DMA_ABNOR_INTR_STATUS
> macros if they haven't been initialized by the low-level drivers.
> These fields could be then used in the respective DMA IRQ init and
> handler methods. I don't know which solution is better. At the first
> glance this one might be even better than what is described in step 3.
>
> Note 4. The solution above will also cover the Andrew's note of having
> the kernel which runs on all possible variants.
>
> -Serge(y)
>
>>
>> Thanks for your review!
>>
>>
>> Thanks,
>>
>> Yanteng
>>
>>> -Serge(y)
>>>
>>>> Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 1/9] net: stmmac: Pass stmmac_priv and chan in some callbacks
2023-11-13 15:16 ` Serge Semin
@ 2023-12-05 11:16 ` Yanteng Si
0 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-12-05 11:16 UTC (permalink / raw)
To: Serge Semin
Cc: andrew, hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
Jose.Abreu, chenhuacai, linux, dongbiao, guyinggang, netdev,
loongarch, chris.chenfeiyang
在 2023/11/13 23:16, Serge Semin 写道:
> On Fri, Nov 10, 2023 at 05:23:18PM +0800, Yanteng Si wrote:
>> Loongson GMAC and GNET have some special features. To prepare for that,
>> pass stmmac_priv and chan to more callbacks, and adjust the callbacks
>> accordingly.
> I might have missed something, but I failed to see why you need the
> most of these changes. At the very least your implementation doesn't
> require the prototypes being converted to accepting the stmmac_priv
> pointer. Please drop all of such redundant changes and leave only the
> required one. AFAICS based on the further patches the only required
> are the channel ID arguments.
OK!
I have removed most of it, and now it looks like this:
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h | 3 ++-
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 3 ++-
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/hwif.h | 11 ++++++-----
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++---
in the next version.
Thanks,
Yanteng
>
> -Serge(y)
>
>> Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
>> Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
>> Signed-off-by: Yinggang Gu <guyinggang@loongson.cn>
>> ---
>> .../net/ethernet/stmicro/stmmac/chain_mode.c | 5 +-
>> .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 +++---
>> .../ethernet/stmicro/stmmac/dwmac1000_core.c | 9 ++-
>> .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 8 ++-
>> .../ethernet/stmicro/stmmac/dwmac100_core.c | 9 ++-
>> .../ethernet/stmicro/stmmac/dwmac100_dma.c | 2 +-
>> .../net/ethernet/stmicro/stmmac/dwmac4_core.c | 11 +--
>> .../ethernet/stmicro/stmmac/dwmac4_descs.c | 17 ++---
>> .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 ++-
>> .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 2 +-
>> .../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 2 +-
>> .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 5 +-
>> .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 5 +-
>> .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 11 +--
>> .../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 17 ++---
>> .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 +--
>> .../net/ethernet/stmicro/stmmac/enh_desc.c | 17 ++---
>> drivers/net/ethernet/stmicro/stmmac/hwif.c | 2 +-
>> drivers/net/ethernet/stmicro/stmmac/hwif.h | 71 ++++++++++---------
>> .../net/ethernet/stmicro/stmmac/norm_desc.c | 17 ++---
>> .../net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +-
>> 21 files changed, 146 insertions(+), 110 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
>> index fb55efd52240..a95866871f3e 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
>> @@ -95,8 +95,9 @@ static unsigned int is_jumbo_frm(int len, int enh_desc)
>> return ret;
>> }
>>
>> -static void init_dma_chain(void *des, dma_addr_t phy_addr,
>> - unsigned int size, unsigned int extend_desc)
>> +static void init_dma_chain(struct stmmac_priv *priv, void *des,
>> + dma_addr_t phy_addr, unsigned int size,
>> + unsigned int extend_desc)
>> {
>> /*
>> * In chained mode the des3 points to the next element in the ring.
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
>> index 137741b94122..2d3f0848cacb 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
>> @@ -283,7 +283,7 @@ static const struct emac_variant emac_variant_h6 = {
>> /* sun8i_dwmac_dma_reset() - reset the EMAC
>> * Called from stmmac via stmmac_dma_ops->reset
>> */
>> -static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
>> +static int sun8i_dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
>> {
>> writel(0, ioaddr + EMAC_RX_CTL1);
>> writel(0, ioaddr + EMAC_TX_CTL1);
>> @@ -298,7 +298,7 @@ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
>> /* sun8i_dwmac_dma_init() - initialize the EMAC
>> * Called from stmmac via stmmac_dma_ops->init
>> */
>> -static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
>> +static void sun8i_dwmac_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_dma_cfg *dma_cfg, int atds)
>> {
>> writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
>> @@ -395,7 +395,8 @@ static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,
>> writel(v, ioaddr + EMAC_TX_CTL1);
>> }
>>
>> -static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
>> +static void sun8i_dwmac_enable_dma_transmission(struct stmmac_priv *priv,
>> + void __iomem *ioaddr, u32 chan)
>> {
>> u32 v;
>>
>> @@ -643,7 +644,8 @@ static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
>> * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
>> * If addr is NULL, clear the slot
>> */
>> -static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
>> +static void sun8i_dwmac_set_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> const unsigned char *addr,
>> unsigned int reg_n)
>> {
>> @@ -664,7 +666,8 @@ static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
>> }
>> }
>>
>> -static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
>> +static void sun8i_dwmac_get_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> unsigned char *addr,
>> unsigned int reg_n)
>> {
>> @@ -687,7 +690,8 @@ static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
>> return 1;
>> }
>>
>> -static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
>> +static void sun8i_dwmac_set_filter(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> struct net_device *dev)
>> {
>> void __iomem *ioaddr = hw->pcsr;
>> @@ -705,13 +709,13 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
>> } else if (macaddrs <= hw->unicast_filter_entries) {
>> if (!netdev_mc_empty(dev)) {
>> netdev_for_each_mc_addr(ha, dev) {
>> - sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
>> + sun8i_dwmac_set_umac_addr(priv, hw, ha->addr, i);
>> i++;
>> }
>> }
>> if (!netdev_uc_empty(dev)) {
>> netdev_for_each_uc_addr(ha, dev) {
>> - sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
>> + sun8i_dwmac_set_umac_addr(priv, hw, ha->addr, i);
>> i++;
>> }
>> }
>> @@ -723,7 +727,7 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
>>
>> /* Disable unused address filter slots */
>> while (i < hw->unicast_filter_entries)
>> - sun8i_dwmac_set_umac_addr(hw, NULL, i++);
>> + sun8i_dwmac_set_umac_addr(priv, hw, NULL, i++);
>>
>> writel(v, ioaddr + EMAC_RX_FRM_FLT);
>> }
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
>> index 3927609abc44..b52793edf62f 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
>> @@ -94,7 +94,8 @@ static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
>> reg_space[i] = readl(ioaddr + i * 4);
>> }
>>
>> -static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
>> +static void dwmac1000_set_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> const unsigned char *addr,
>> unsigned int reg_n)
>> {
>> @@ -103,7 +104,8 @@ static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
>> GMAC_ADDR_LOW(reg_n));
>> }
>>
>> -static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
>> +static void dwmac1000_get_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> unsigned char *addr,
>> unsigned int reg_n)
>> {
>> @@ -137,7 +139,8 @@ static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
>> ioaddr + GMAC_EXTHASH_BASE + regs * 4);
>> }
>>
>> -static void dwmac1000_set_filter(struct mac_device_info *hw,
>> +static void dwmac1000_set_filter(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> struct net_device *dev)
>> {
>> void __iomem *ioaddr = (void __iomem *)dev->base_addr;
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
>> index daf79cdbd3ec..ce0e6ca6f3a2 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
>> @@ -16,7 +16,8 @@
>> #include "dwmac1000.h"
>> #include "dwmac_dma.h"
>>
>> -static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
>> +static void dwmac1000_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
>> + struct stmmac_axi *axi)
>> {
>> u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
>> int i;
>> @@ -70,7 +71,7 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
>> writel(value, ioaddr + DMA_AXI_BUS_MODE);
>> }
>>
>> -static void dwmac1000_dma_init(void __iomem *ioaddr,
>> +static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_dma_cfg *dma_cfg, int atds)
>> {
>> u32 value = readl(ioaddr + DMA_BUS_MODE);
>> @@ -223,7 +224,8 @@ static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
>> readl(ioaddr + DMA_BUS_MODE + i * 4);
>> }
>>
>> -static int dwmac1000_get_hw_feature(void __iomem *ioaddr,
>> +static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
>> + void __iomem *ioaddr,
>> struct dma_features *dma_cap)
>> {
>> u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
>> index a6e8d7bd9588..c03623edeb75 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
>> @@ -59,7 +59,8 @@ static int dwmac100_irq_status(struct mac_device_info *hw,
>> return 0;
>> }
>>
>> -static void dwmac100_set_umac_addr(struct mac_device_info *hw,
>> +static void dwmac100_set_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> const unsigned char *addr,
>> unsigned int reg_n)
>> {
>> @@ -67,7 +68,8 @@ static void dwmac100_set_umac_addr(struct mac_device_info *hw,
>> stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
>> }
>>
>> -static void dwmac100_get_umac_addr(struct mac_device_info *hw,
>> +static void dwmac100_get_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> unsigned char *addr,
>> unsigned int reg_n)
>> {
>> @@ -75,7 +77,8 @@ static void dwmac100_get_umac_addr(struct mac_device_info *hw,
>> stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
>> }
>>
>> -static void dwmac100_set_filter(struct mac_device_info *hw,
>> +static void dwmac100_set_filter(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> struct net_device *dev)
>> {
>> void __iomem *ioaddr = (void __iomem *)dev->base_addr;
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
>> index dea270f60cc3..105e7d4d798f 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
>> @@ -18,7 +18,7 @@
>> #include "dwmac100.h"
>> #include "dwmac_dma.h"
>>
>> -static void dwmac100_dma_init(void __iomem *ioaddr,
>> +static void dwmac100_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_dma_cfg *dma_cfg, int atds)
>> {
>> /* Enable Application Access by writing to DMA CSR0 */
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
>> index c6ff1fa0e04d..5e9b393ad7b3 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
>> @@ -335,7 +335,8 @@ static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
>> writel(pmt, ioaddr + GMAC_PMT);
>> }
>>
>> -static void dwmac4_set_umac_addr(struct mac_device_info *hw,
>> +static void dwmac4_set_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> const unsigned char *addr, unsigned int reg_n)
>> {
>> void __iomem *ioaddr = hw->pcsr;
>> @@ -344,7 +345,8 @@ static void dwmac4_set_umac_addr(struct mac_device_info *hw,
>> GMAC_ADDR_LOW(reg_n));
>> }
>>
>> -static void dwmac4_get_umac_addr(struct mac_device_info *hw,
>> +static void dwmac4_get_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> unsigned char *addr, unsigned int reg_n)
>> {
>> void __iomem *ioaddr = hw->pcsr;
>> @@ -593,7 +595,8 @@ static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
>> }
>> }
>>
>> -static void dwmac4_set_filter(struct mac_device_info *hw,
>> +static void dwmac4_set_filter(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> struct net_device *dev)
>> {
>> void __iomem *ioaddr = (void __iomem *)dev->base_addr;
>> @@ -669,7 +672,7 @@ static void dwmac4_set_filter(struct mac_device_info *hw,
>> int reg = 1;
>>
>> netdev_for_each_uc_addr(ha, dev) {
>> - dwmac4_set_umac_addr(hw, ha->addr, reg);
>> + dwmac4_set_umac_addr(priv, hw, ha->addr, reg);
>> reg++;
>> }
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
>> index 89a14084c611..bd3084efc808 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
>> @@ -169,7 +169,7 @@ static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
>> return ret;
>> }
>>
>> -static int dwmac4_rd_get_tx_len(struct dma_desc *p)
>> +static int dwmac4_rd_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
>> {
>> return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
>> }
>> @@ -290,8 +290,8 @@ static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
>> return 0;
>> }
>>
>> -static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
>> - int mode, int end, int bfsize)
>> +static void dwmac4_rd_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
>> + int disable_rx_ic, int mode, int end, int bfsize)
>> {
>> dwmac4_set_rx_owner(p, disable_rx_ic);
>> }
>> @@ -304,9 +304,9 @@ static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
>> p->des3 = 0;
>> }
>>
>> -static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
>> - bool csum_flag, int mode, bool tx_own,
>> - bool ls, unsigned int tot_pkt_len)
>> +static void dwmac4_rd_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
>> + int is_fs, int len, bool csum_flag, int mode,
>> + bool tx_own, bool ls, unsigned int tot_pkt_len)
>> {
>> unsigned int tdes3 = le32_to_cpu(p->des3);
>>
>> @@ -456,13 +456,14 @@ static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
>> p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
>> }
>>
>> -static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
>> +static void dwmac4_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
>> + dma_addr_t addr)
>> {
>> p->des0 = cpu_to_le32(lower_32_bits(addr));
>> p->des1 = cpu_to_le32(upper_32_bits(addr));
>> }
>>
>> -static void dwmac4_clear(struct dma_desc *p)
>> +static void dwmac4_clear(struct stmmac_priv *priv, struct dma_desc *p)
>> {
>> p->des0 = 0;
>> p->des1 = 0;
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
>> index 84d3a8551b03..97dad00dc850 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
>> @@ -15,7 +15,8 @@
>> #include "dwmac4_dma.h"
>> #include "stmmac.h"
>>
>> -static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
>> +static void dwmac4_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
>> + struct stmmac_axi *axi)
>> {
>> u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
>> int i;
>> @@ -152,7 +153,7 @@ static void dwmac410_dma_init_channel(struct stmmac_priv *priv,
>> ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
>> }
>>
>> -static void dwmac4_dma_init(void __iomem *ioaddr,
>> +static void dwmac4_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_dma_cfg *dma_cfg, int atds)
>> {
>> u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
>> @@ -374,7 +375,8 @@ static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv,
>> writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
>> }
>>
>> -static int dwmac4_get_hw_feature(void __iomem *ioaddr,
>> +static int dwmac4_get_hw_feature(struct stmmac_priv *priv,
>> + void __iomem *ioaddr,
>> struct dma_features *dma_cap)
>> {
>> u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
>> index 358e7dcb6a9a..aaab5ab38373 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
>> @@ -231,7 +231,7 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
>> #define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
>> #define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
>>
>> -int dwmac4_dma_reset(void __iomem *ioaddr);
>> +int dwmac4_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
>> void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
>> u32 chan, bool rx, bool tx);
>> void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
>> index 9470d3fd2ded..1191f0c1d7f1 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
>> @@ -13,7 +13,7 @@
>> #include "dwmac4.h"
>> #include "stmmac.h"
>>
>> -int dwmac4_dma_reset(void __iomem *ioaddr)
>> +int dwmac4_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
>> {
>> u32 value = readl(ioaddr + DMA_BUS_MODE);
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
>> index 72672391675f..77141391bd2f 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
>> @@ -152,7 +152,8 @@
>> #define NUM_DWMAC1000_DMA_REGS 23
>> #define NUM_DWMAC4_DMA_REGS 27
>>
>> -void dwmac_enable_dma_transmission(void __iomem *ioaddr);
>> +void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
>> + void __iomem *ioaddr, u32 chan);
>> void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
>> u32 chan, bool rx, bool tx);
>> void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
>> @@ -167,6 +168,6 @@ void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
>> u32 chan);
>> int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_extra_stats *x, u32 chan, u32 dir);
>> -int dwmac_dma_reset(void __iomem *ioaddr);
>> +int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
>>
>> #endif /* __DWMAC_DMA_H__ */
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
>> index 7907d62d3437..0cb337ffb7ac 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
>> @@ -14,7 +14,7 @@
>>
>> #define GMAC_HI_REG_AE 0x80000000
>>
>> -int dwmac_dma_reset(void __iomem *ioaddr)
>> +int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
>> {
>> u32 value = readl(ioaddr + DMA_BUS_MODE);
>>
>> @@ -28,7 +28,8 @@ int dwmac_dma_reset(void __iomem *ioaddr)
>> }
>>
>> /* CSR1 enables the transmit DMA to check for new descriptor */
>> -void dwmac_enable_dma_transmission(void __iomem *ioaddr)
>> +void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
>> + void __iomem *ioaddr, u32 chan)
>> {
>> writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
>> }
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
>> index 453e88b75be0..a993591e05bd 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
>> @@ -375,7 +375,8 @@ static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
>> writel(val, ioaddr + XGMAC_PMT);
>> }
>>
>> -static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
>> +static void dwxgmac2_set_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> const unsigned char *addr,
>> unsigned int reg_n)
>> {
>> @@ -389,7 +390,8 @@ static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
>> writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
>> }
>>
>> -static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
>> +static void dwxgmac2_get_umac_addr(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> unsigned char *addr, unsigned int reg_n)
>> {
>> void __iomem *ioaddr = hw->pcsr;
>> @@ -478,7 +480,8 @@ static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
>> writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
>> }
>>
>> -static void dwxgmac2_set_filter(struct mac_device_info *hw,
>> +static void dwxgmac2_set_filter(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> struct net_device *dev)
>> {
>> void __iomem *ioaddr = (void __iomem *)dev->base_addr;
>> @@ -523,7 +526,7 @@ static void dwxgmac2_set_filter(struct mac_device_info *hw,
>> int reg = 1;
>>
>> netdev_for_each_uc_addr(ha, dev) {
>> - dwxgmac2_set_umac_addr(hw, ha->addr, reg);
>> + dwxgmac2_set_umac_addr(priv, hw, ha->addr, reg);
>> reg++;
>> }
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
>> index fc82862a612c..cefcbabab2c0 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
>> @@ -39,7 +39,7 @@ static int dwxgmac2_get_rx_status(struct stmmac_extra_stats *x,
>> return good_frame;
>> }
>>
>> -static int dwxgmac2_get_tx_len(struct dma_desc *p)
>> +static int dwxgmac2_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
>> {
>> return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
>> }
>> @@ -126,8 +126,8 @@ static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
>> return !ret;
>> }
>>
>> -static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
>> - int mode, int end, int bfsize)
>> +static void dwxgmac2_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
>> + int disable_rx_ic, int mode, int end, int bfsize)
>> {
>> dwxgmac2_set_rx_owner(p, disable_rx_ic);
>> }
>> @@ -140,9 +140,9 @@ static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)
>> p->des3 = 0;
>> }
>>
>> -static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
>> - bool csum_flag, int mode, bool tx_own,
>> - bool ls, unsigned int tot_pkt_len)
>> +static void dwxgmac2_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
>> + int is_fs, int len, bool csum_flag, int mode,
>> + bool tx_own, bool ls, unsigned int tot_pkt_len)
>> {
>> unsigned int tdes3 = le32_to_cpu(p->des3);
>>
>> @@ -239,13 +239,14 @@ static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)
>> p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
>> }
>>
>> -static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
>> +static void dwxgmac2_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
>> + dma_addr_t addr)
>> {
>> p->des0 = cpu_to_le32(lower_32_bits(addr));
>> p->des1 = cpu_to_le32(upper_32_bits(addr));
>> }
>>
>> -static void dwxgmac2_clear(struct dma_desc *p)
>> +static void dwxgmac2_clear(struct stmmac_priv *priv, struct dma_desc *p)
>> {
>> p->des0 = 0;
>> p->des1 = 0;
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
>> index 3cde695fec91..4d1dc6d7eacb 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
>> @@ -8,7 +8,7 @@
>> #include "stmmac.h"
>> #include "dwxgmac2.h"
>>
>> -static int dwxgmac2_dma_reset(void __iomem *ioaddr)
>> +static int dwxgmac2_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
>> {
>> u32 value = readl(ioaddr + XGMAC_DMA_MODE);
>>
>> @@ -19,7 +19,7 @@ static int dwxgmac2_dma_reset(void __iomem *ioaddr)
>> !(value & XGMAC_SWR), 0, 100000);
>> }
>>
>> -static void dwxgmac2_dma_init(void __iomem *ioaddr,
>> +static void dwxgmac2_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_dma_cfg *dma_cfg, int atds)
>> {
>> u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
>> @@ -81,7 +81,8 @@ static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv,
>> writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
>> }
>>
>> -static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
>> +static void dwxgmac2_dma_axi(struct stmmac_priv *priv, void __iomem *ioaddr,
>> + struct stmmac_axi *axi)
>> {
>> u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
>> int i;
>> @@ -386,7 +387,8 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv,
>> return ret;
>> }
>>
>> -static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
>> +static int dwxgmac2_get_hw_feature(struct stmmac_priv *priv,
>> + void __iomem *ioaddr,
>> struct dma_features *dma_cap)
>> {
>> u32 hw_cap;
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
>> index 937b7a0466fc..43ae8c7defe1 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
>> @@ -76,7 +76,7 @@ static int enh_desc_get_tx_status(struct stmmac_extra_stats *x,
>> return ret;
>> }
>>
>> -static int enh_desc_get_tx_len(struct dma_desc *p)
>> +static int enh_desc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
>> {
>> return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);
>> }
>> @@ -249,8 +249,8 @@ static int enh_desc_get_rx_status(struct stmmac_extra_stats *x,
>> return ret;
>> }
>>
>> -static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
>> - int mode, int end, int bfsize)
>> +static void enh_desc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
>> + int disable_rx_ic, int mode, int end, int bfsize)
>> {
>> int bfsize1;
>>
>> @@ -308,9 +308,9 @@ static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
>> enh_desc_end_tx_desc_on_ring(p, ter);
>> }
>>
>> -static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
>> - bool csum_flag, int mode, bool tx_own,
>> - bool ls, unsigned int tot_pkt_len)
>> +static void enh_desc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
>> + int is_fs, int len, bool csum_flag, int mode,
>> + bool tx_own, bool ls, unsigned int tot_pkt_len)
>> {
>> unsigned int tdes0 = le32_to_cpu(p->des0);
>>
>> @@ -435,12 +435,13 @@ static void enh_desc_display_ring(void *head, unsigned int size, bool rx,
>> pr_info("\n");
>> }
>>
>> -static void enh_desc_set_addr(struct dma_desc *p, dma_addr_t addr)
>> +static void enh_desc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
>> + dma_addr_t addr)
>> {
>> p->des2 = cpu_to_le32(addr);
>> }
>>
>> -static void enh_desc_clear(struct dma_desc *p)
>> +static void enh_desc_clear(struct stmmac_priv *priv, struct dma_desc *p)
>> {
>> p->des2 = 0;
>> }
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
>> index b8ba8f2d8041..93cead5613e3 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
>> @@ -97,7 +97,7 @@ int stmmac_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
>> if (plat && plat->fix_soc_reset)
>> return plat->fix_soc_reset(plat, ioaddr);
>>
>> - return stmmac_do_callback(priv, dma, reset, ioaddr);
>> + return stmmac_do_callback(priv, dma, reset, priv, ioaddr);
>> }
>>
>> static const struct stmmac_hwif_entry {
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
>> index b95d3e137813..fd63713fcaa1 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
>> @@ -35,14 +35,14 @@ struct dma_edesc;
>> /* Descriptors helpers */
>> struct stmmac_desc_ops {
>> /* DMA RX descriptor ring initialization */
>> - void (*init_rx_desc)(struct dma_desc *p, int disable_rx_ic, int mode,
>> - int end, int bfsize);
>> + void (*init_rx_desc)(struct stmmac_priv *priv, struct dma_desc *p,
>> + int disable_rx_ic, int mode, int end, int bfsize);
>> /* DMA TX descriptor ring initialization */
>> void (*init_tx_desc)(struct dma_desc *p, int mode, int end);
>> /* Invoked by the xmit function to prepare the tx descriptor */
>> - void (*prepare_tx_desc)(struct dma_desc *p, int is_fs, int len,
>> - bool csum_flag, int mode, bool tx_own, bool ls,
>> - unsigned int tot_pkt_len);
>> + void (*prepare_tx_desc)(struct stmmac_priv *priv, struct dma_desc *p,
>> + int is_fs, int len, bool csum_flag, int mode,
>> + bool tx_own, bool ls, unsigned int tot_pkt_len);
>> void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
>> int len2, bool tx_own, bool ls, unsigned int tcphdrlen,
>> unsigned int tcppayloadlen);
>> @@ -60,7 +60,7 @@ struct stmmac_desc_ops {
>> int (*tx_status)(struct stmmac_extra_stats *x,
>> struct dma_desc *p, void __iomem *ioaddr);
>> /* Get the buffer size from the descriptor */
>> - int (*get_tx_len)(struct dma_desc *p);
>> + int (*get_tx_len)(struct stmmac_priv *priv, struct dma_desc *p);
>> /* Handle extra events on specific interrupts hw dependent */
>> void (*set_rx_owner)(struct dma_desc *p, int disable_rx_ic);
>> /* Get the receive frame size */
>> @@ -84,9 +84,10 @@ struct stmmac_desc_ops {
>> /* set MSS via context descriptor */
>> void (*set_mss)(struct dma_desc *p, unsigned int mss);
>> /* set descriptor skbuff address */
>> - void (*set_addr)(struct dma_desc *p, dma_addr_t addr);
>> + void (*set_addr)(struct stmmac_priv *priv, struct dma_desc *p,
>> + dma_addr_t addr);
>> /* clear descriptor */
>> - void (*clear)(struct dma_desc *p);
>> + void (*clear)(struct stmmac_priv *priv, struct dma_desc *p);
>> /* RSS */
>> int (*get_rx_hash)(struct dma_desc *p, u32 *hash,
>> enum pkt_hash_types *type);
>> @@ -100,11 +101,11 @@ struct stmmac_desc_ops {
>> };
>>
>> #define stmmac_init_rx_desc(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, desc, init_rx_desc, __args)
>> + stmmac_do_void_callback(__priv, desc, init_rx_desc, __priv, __args)
>> #define stmmac_init_tx_desc(__priv, __args...) \
>> stmmac_do_void_callback(__priv, desc, init_tx_desc, __args)
>> #define stmmac_prepare_tx_desc(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __args)
>> + stmmac_do_void_callback(__priv, desc, prepare_tx_desc, __priv, __args)
>> #define stmmac_prepare_tso_tx_desc(__priv, __args...) \
>> stmmac_do_void_callback(__priv, desc, prepare_tso_tx_desc, __args)
>> #define stmmac_set_tx_owner(__priv, __args...) \
>> @@ -120,7 +121,7 @@ struct stmmac_desc_ops {
>> #define stmmac_tx_status(__priv, __args...) \
>> stmmac_do_callback(__priv, desc, tx_status, __args)
>> #define stmmac_get_tx_len(__priv, __args...) \
>> - stmmac_do_callback(__priv, desc, get_tx_len, __args)
>> + stmmac_do_callback(__priv, desc, get_tx_len, __priv, __args)
>> #define stmmac_set_rx_owner(__priv, __args...) \
>> stmmac_do_void_callback(__priv, desc, set_rx_owner, __args)
>> #define stmmac_get_rx_frame_len(__priv, __args...) \
>> @@ -142,9 +143,9 @@ struct stmmac_desc_ops {
>> #define stmmac_set_mss(__priv, __args...) \
>> stmmac_do_void_callback(__priv, desc, set_mss, __args)
>> #define stmmac_set_desc_addr(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, desc, set_addr, __args)
>> + stmmac_do_void_callback(__priv, desc, set_addr, __priv, __args)
>> #define stmmac_clear_desc(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, desc, clear, __args)
>> + stmmac_do_void_callback(__priv, desc, clear, __priv, __args)
>> #define stmmac_get_rx_hash(__priv, __args...) \
>> stmmac_do_callback(__priv, desc, get_rx_hash, __args)
>> #define stmmac_get_rx_header_len(__priv, __args...) \
>> @@ -166,9 +167,9 @@ struct dma_features;
>> /* Specific DMA helpers */
>> struct stmmac_dma_ops {
>> /* DMA core initialization */
>> - int (*reset)(void __iomem *ioaddr);
>> - void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
>> - int atds);
>> + int (*reset)(struct stmmac_priv *priv, void __iomem *ioaddr);
>> + void (*init)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> + struct stmmac_dma_cfg *dma_cfg, int atds);
>> void (*init_chan)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_dma_cfg *dma_cfg, u32 chan);
>> void (*init_rx_chan)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> @@ -178,7 +179,8 @@ struct stmmac_dma_ops {
>> struct stmmac_dma_cfg *dma_cfg,
>> dma_addr_t phy, u32 chan);
>> /* Configure the AXI Bus Mode Register */
>> - void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
>> + void (*axi)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> + struct stmmac_axi *axi);
>> /* Dump DMA registers */
>> void (*dump_regs)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> u32 *reg_space);
>> @@ -190,7 +192,8 @@ struct stmmac_dma_ops {
>> /* To track extra statistic (if supported) */
>> void (*dma_diagnostic_fr)(struct stmmac_extra_stats *x,
>> void __iomem *ioaddr);
>> - void (*enable_dma_transmission) (void __iomem *ioaddr);
>> + void (*enable_dma_transmission)(struct stmmac_priv *priv,
>> + void __iomem *ioaddr, u32 chan);
>> void (*enable_dma_irq)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> u32 chan, bool rx, bool tx);
>> void (*disable_dma_irq)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> @@ -206,7 +209,7 @@ struct stmmac_dma_ops {
>> int (*dma_interrupt)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct stmmac_extra_stats *x, u32 chan, u32 dir);
>> /* If supported then get the optional core features */
>> - int (*get_hw_feature)(void __iomem *ioaddr,
>> + int (*get_hw_feature)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> struct dma_features *dma_cap);
>> /* Program the HW RX Watchdog */
>> void (*rx_watchdog)(struct stmmac_priv *priv, void __iomem *ioaddr,
>> @@ -232,7 +235,7 @@ struct stmmac_dma_ops {
>> };
>>
>> #define stmmac_dma_init(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, dma, init, __args)
>> + stmmac_do_void_callback(__priv, dma, init, __priv, __args)
>> #define stmmac_init_chan(__priv, __args...) \
>> stmmac_do_void_callback(__priv, dma, init_chan, __priv, __args)
>> #define stmmac_init_rx_chan(__priv, __args...) \
>> @@ -240,7 +243,7 @@ struct stmmac_dma_ops {
>> #define stmmac_init_tx_chan(__priv, __args...) \
>> stmmac_do_void_callback(__priv, dma, init_tx_chan, __priv, __args)
>> #define stmmac_axi(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, dma, axi, __args)
>> + stmmac_do_void_callback(__priv, dma, axi, __priv, __args)
>> #define stmmac_dump_dma_regs(__priv, __args...) \
>> stmmac_do_void_callback(__priv, dma, dump_regs, __priv, __args)
>> #define stmmac_dma_rx_mode(__priv, __args...) \
>> @@ -250,7 +253,7 @@ struct stmmac_dma_ops {
>> #define stmmac_dma_diagnostic_fr(__priv, __args...) \
>> stmmac_do_void_callback(__priv, dma, dma_diagnostic_fr, __args)
>> #define stmmac_enable_dma_transmission(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __args)
>> + stmmac_do_void_callback(__priv, dma, enable_dma_transmission, __priv, __args)
>> #define stmmac_enable_dma_irq(__priv, __args...) \
>> stmmac_do_void_callback(__priv, dma, enable_dma_irq, __priv, __args)
>> #define stmmac_disable_dma_irq(__priv, __args...) \
>> @@ -266,7 +269,7 @@ struct stmmac_dma_ops {
>> #define stmmac_dma_interrupt_status(__priv, __args...) \
>> stmmac_do_callback(__priv, dma, dma_interrupt, __priv, __args)
>> #define stmmac_get_hw_feature(__priv, __args...) \
>> - stmmac_do_callback(__priv, dma, get_hw_feature, __args)
>> + stmmac_do_callback(__priv, dma, get_hw_feature, __priv, __args)
>> #define stmmac_rx_watchdog(__priv, __args...) \
>> stmmac_do_void_callback(__priv, dma, rx_watchdog, __priv, __args)
>> #define stmmac_set_tx_ring_len(__priv, __args...) \
>> @@ -338,17 +341,21 @@ struct stmmac_ops {
>> int (*host_mtl_irq_status)(struct stmmac_priv *priv,
>> struct mac_device_info *hw, u32 chan);
>> /* Multicast filter setting */
>> - void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
>> + void (*set_filter)(struct stmmac_priv *priv, struct mac_device_info *hw,
>> + struct net_device *dev);
>> /* Flow control setting */
>> void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
>> unsigned int fc, unsigned int pause_time, u32 tx_cnt);
>> /* Set power management mode (e.g. magic frame) */
>> void (*pmt)(struct mac_device_info *hw, unsigned long mode);
>> /* Set/Get Unicast MAC addresses */
>> - void (*set_umac_addr)(struct mac_device_info *hw,
>> + void (*set_umac_addr)(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> const unsigned char *addr,
>> unsigned int reg_n);
>> - void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
>> + void (*get_umac_addr)(struct stmmac_priv *priv,
>> + struct mac_device_info *hw,
>> + unsigned char *addr,
>> unsigned int reg_n);
>> void (*set_eee_mode)(struct mac_device_info *hw,
>> bool en_tx_lpi_clockgating);
>> @@ -452,15 +459,15 @@ struct stmmac_ops {
>> #define stmmac_host_mtl_irq_status(__priv, __args...) \
>> stmmac_do_callback(__priv, mac, host_mtl_irq_status, __priv, __args)
>> #define stmmac_set_filter(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, mac, set_filter, __args)
>> + stmmac_do_void_callback(__priv, mac, set_filter, __priv, __args)
>> #define stmmac_flow_ctrl(__priv, __args...) \
>> stmmac_do_void_callback(__priv, mac, flow_ctrl, __args)
>> #define stmmac_pmt(__priv, __args...) \
>> stmmac_do_void_callback(__priv, mac, pmt, __args)
>> #define stmmac_set_umac_addr(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, mac, set_umac_addr, __args)
>> + stmmac_do_void_callback(__priv, mac, set_umac_addr, __priv, __args)
>> #define stmmac_get_umac_addr(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, mac, get_umac_addr, __args)
>> + stmmac_do_void_callback(__priv, mac, get_umac_addr, __priv, __args)
>> #define stmmac_set_eee_mode(__priv, __args...) \
>> stmmac_do_void_callback(__priv, mac, set_eee_mode, __args)
>> #define stmmac_reset_eee_mode(__priv, __args...) \
>> @@ -563,8 +570,8 @@ struct stmmac_rx_queue;
>>
>> /* Helpers to manage the descriptors for chain and ring modes */
>> struct stmmac_mode_ops {
>> - void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
>> - unsigned int extend_desc);
>> + void (*init)(struct stmmac_priv *priv, void *des, dma_addr_t phy_addr,
>> + unsigned int size, unsigned int extend_desc);
>> unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
>> int (*jumbo_frm)(struct stmmac_tx_queue *tx_q, struct sk_buff *skb,
>> int csum);
>> @@ -575,7 +582,7 @@ struct stmmac_mode_ops {
>> };
>>
>> #define stmmac_mode_init(__priv, __args...) \
>> - stmmac_do_void_callback(__priv, mode, init, __args)
>> + stmmac_do_void_callback(__priv, mode, init, __priv, __args)
>> #define stmmac_is_jumbo_frm(__priv, __args...) \
>> stmmac_do_callback(__priv, mode, is_jumbo_frm, __args)
>> #define stmmac_jumbo_frm(__priv, __args...) \
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
>> index 68a7cfcb1d8f..5fb3103db5cd 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
>> @@ -57,7 +57,7 @@ static int ndesc_get_tx_status(struct stmmac_extra_stats *x,
>> return ret;
>> }
>>
>> -static int ndesc_get_tx_len(struct dma_desc *p)
>> +static int ndesc_get_tx_len(struct stmmac_priv *priv, struct dma_desc *p)
>> {
>> return (le32_to_cpu(p->des1) & RDES1_BUFFER1_SIZE_MASK);
>> }
>> @@ -115,8 +115,8 @@ static int ndesc_get_rx_status(struct stmmac_extra_stats *x,
>> return ret;
>> }
>>
>> -static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
>> - int end, int bfsize)
>> +static void ndesc_init_rx_desc(struct stmmac_priv *priv, struct dma_desc *p,
>> + int disable_rx_ic, int mode, int end, int bfsize)
>> {
>> int bfsize1;
>>
>> @@ -174,9 +174,9 @@ static void ndesc_release_tx_desc(struct dma_desc *p, int mode)
>> ndesc_end_tx_desc_on_ring(p, ter);
>> }
>>
>> -static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
>> - bool csum_flag, int mode, bool tx_own,
>> - bool ls, unsigned int tot_pkt_len)
>> +static void ndesc_prepare_tx_desc(struct stmmac_priv *priv, struct dma_desc *p,
>> + int is_fs, int len, bool csum_flag, int mode,
>> + bool tx_own, bool ls, unsigned int tot_pkt_len)
>> {
>> unsigned int tdes1 = le32_to_cpu(p->des1);
>>
>> @@ -285,12 +285,13 @@ static void ndesc_display_ring(void *head, unsigned int size, bool rx,
>> pr_info("\n");
>> }
>>
>> -static void ndesc_set_addr(struct dma_desc *p, dma_addr_t addr)
>> +static void ndesc_set_addr(struct stmmac_priv *priv, struct dma_desc *p,
>> + dma_addr_t addr)
>> {
>> p->des2 = cpu_to_le32(addr);
>> }
>>
>> -static void ndesc_clear(struct dma_desc *p)
>> +static void ndesc_clear(struct stmmac_priv *priv, struct dma_desc *p)
>> {
>> p->des2 = 0;
>> }
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> index 3e50fd53a617..132d4f679b95 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> @@ -2509,7 +2509,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
>> true, priv->mode, true, true,
>> xdp_desc.len);
>>
>> - stmmac_enable_dma_transmission(priv, priv->ioaddr);
>> + stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
>>
>> tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
>> entry = tx_q->cur_tx;
>> @@ -4615,7 +4615,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
>>
>> netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
>>
>> - stmmac_enable_dma_transmission(priv, priv->ioaddr);
>> + stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
>>
>> stmmac_flush_tx_descriptors(priv, queue);
>> stmmac_tx_timer_arm(priv, queue);
>> @@ -4835,7 +4835,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
>> u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
>> }
>>
>> - stmmac_enable_dma_transmission(priv, priv->ioaddr);
>> + stmmac_enable_dma_transmission(priv, priv->ioaddr, queue);
>>
>> entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
>> tx_q->cur_tx = entry;
>> --
>> 2.31.4
>>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 4/9] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe()
2023-11-11 20:19 ` Andrew Lunn
@ 2023-12-10 1:46 ` Yanteng Si
0 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-12-10 1:46 UTC (permalink / raw)
To: Andrew Lunn
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
在 2023/11/12 04:19, Andrew Lunn 写道:
> On Fri, Nov 10, 2023 at 05:25:43PM +0800, Yanteng Si wrote:
>> Add a setup() function to initialize data, and simplify code for
>> loongson_dwmac_probe().
> This does not look like a refactoring patch. Such patches just move
> code around, but otherwise leave the code alone. There are real
> changes in here.
>
>> - if (!of_device_is_compatible(np, "loongson, pci-gmac")) {
>> - pr_info("dwmac_loongson_pci: Incompatible OF node\n");
>> - return -ENODEV;
>> - }
>> -
> This just disappears. Why is it no longer needed?
>
>
>> plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
>> if (!plat)
>> return -ENOMEM;
>>
>> + plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
>> + sizeof(*plat->mdio_bus_data),
>> + GFP_KERNEL);
>> + if (!plat->mdio_bus_data)
>> + return -ENOMEM;
>> +
>> + plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
>> + GFP_KERNEL);
>> + if (!plat->dma_cfg)
>> + return -ENOMEM;
>> +
>> plat->mdio_node = of_get_child_by_name(np, "mdio");
>> if (plat->mdio_node) {
>> dev_info(&pdev->dev, "Found MDIO subnode\n");
>> -
>> - plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
>> - sizeof(*plat->mdio_bus_data),
>> - GFP_KERNEL);
>> - if (!plat->mdio_bus_data) {
>> - ret = -ENOMEM;
>> - goto err_put_node;
>> - }
> MDIO was conditional, but now is mandatory. Why?
>
>> if (ret) {
>> - dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__);
>> + dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
>> + __func__);
> Changes like this are a distraction. The reviewer is trying to
> understand what has changed and why. If you want to make white space
> changes, please do it in a patch of its own.
>
> Please break this patch up into lots of smaller parts, each with a
> good commit messaged explaining what is going on, and importantly,
> why.
OK,Iwillgiveitatry.
Thanks,
Yanteng
>
> Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 5/9] net: stmmac: dwmac-loongson: Add full PCI support
2023-11-11 20:24 ` Andrew Lunn
@ 2023-12-11 8:47 ` Yanteng Si
0 siblings, 0 replies; 32+ messages in thread
From: Yanteng Si @ 2023-12-11 8:47 UTC (permalink / raw)
To: Andrew Lunn
Cc: hkallweit1, peppe.cavallaro, alexandre.torgue, joabreu,
fancer.lancer, Jose.Abreu, chenhuacai, linux, dongbiao,
guyinggang, netdev, loongarch, chris.chenfeiyang
在 2023/11/12 04:24, Andrew Lunn 写道:
>> - res.irq = of_irq_get_byname(np, "macirq");
>> - if (res.irq < 0) {
>> - dev_err(&pdev->dev, "IRQ macirq not found\n");
>> - ret = -ENODEV;
>> - goto err_disable_msi;
>> - }
>> -
>> - res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
>> - if (res.wol_irq < 0) {
>> - dev_info(&pdev->dev,
>> - "IRQ eth_wake_irq not found, using macirq\n");
>> - res.wol_irq = res.irq;
>> - }
>> -
>> - res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
>> - if (res.lpi_irq < 0) {
>> - dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
>> - ret = -ENODEV;
>> - goto err_disable_msi;
>> + if (np) {
>> + res.irq = of_irq_get_byname(np, "macirq");
>> + if (res.irq < 0) {
>> + dev_err(&pdev->dev, "IRQ macirq not found\n");
>> + ret = -ENODEV;
>> + goto err_disable_msi;
>> + }
>> +
>> + res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
>> + if (res.wol_irq < 0) {
>> + dev_info(&pdev->dev,
>> + "IRQ eth_wake_irq not found, using macirq\n");
>> + res.wol_irq = res.irq;
>> + }
>> +
>> + res.lpi_irq = of_irq_get_byname(np, "eth_lpi");
>> + if (res.lpi_irq < 0) {
>> + dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
>> + ret = -ENODEV;
>> + goto err_disable_msi;
>> + }
> This is where a refactoring patch is useful. Have one patch which
> moves this code into a helper function. The commit message can say it
> just moves code around, but there is no functional change. The second
> patch then moves the call to the helper inside the if (np).
Thanks for your advice!
In fact, we have already done this in <[PATCH v5 6/9] net: stmmac:
dwmac-loongson: Add MSI support>, and the function is
loongson_dwmac_config_legacy().
Thanks,
Yanteng
>
> Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2023-12-11 9:57 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-10 9:08 [PATCH v5 0/9] stmmac: Add Loongson platform support Yanteng Si
2023-11-10 9:23 ` [PATCH v5 1/9] net: stmmac: Pass stmmac_priv and chan in some callbacks Yanteng Si
2023-11-13 15:16 ` Serge Semin
2023-12-05 11:16 ` Yanteng Si
2023-11-10 9:25 ` [PATCH v5 2/9] net: stmmac: Allow platforms to set irq_flags Yanteng Si
2023-11-11 19:51 ` Andrew Lunn
2023-11-21 12:01 ` Yanteng Si
2023-11-21 13:59 ` Andrew Lunn
2023-11-24 12:49 ` Yanteng Si
2023-11-10 9:25 ` [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions Yanteng Si
2023-11-11 20:07 ` Andrew Lunn
2023-11-21 9:55 ` Yanteng Si
2023-11-22 3:39 ` Andrew Lunn
2023-11-22 4:02 ` Xi Ruoyao
2023-11-24 13:14 ` Yanteng Si
2023-11-24 14:51 ` Andrew Lunn
2023-11-24 16:44 ` Serge Semin
2023-11-26 12:25 ` Yanteng Si
2023-11-27 11:32 ` Serge Semin
2023-11-29 10:29 ` Yanteng Si
2023-11-13 15:05 ` Serge Semin
2023-11-10 9:25 ` [PATCH v5 4/9] net: stmmac: dwmac-loongson: Refactor code for loongson_dwmac_probe() Yanteng Si
2023-11-11 20:19 ` Andrew Lunn
2023-12-10 1:46 ` Yanteng Si
2023-11-10 9:27 ` [PATCH v5 5/9] net: stmmac: dwmac-loongson: Add full PCI support Yanteng Si
2023-11-11 20:24 ` Andrew Lunn
2023-12-11 8:47 ` Yanteng Si
2023-11-10 9:27 ` [PATCH v5 6/9] net: stmmac: dwmac-loongson: Add MSI support Yanteng Si
2023-11-10 9:27 ` [PATCH v5 7/9] net: stmmac: dwmac-loongson: Add GNET support Yanteng Si
2023-11-10 9:27 ` [PATCH v5 8/9] net: stmmac: dwmac-loongson: Disable flow control for GMAC Yanteng Si
2023-11-10 9:30 ` [PATCH v5 9/9] net: stmmac: Disable coe for some Loongson GNET Yanteng Si
2023-11-10 20:38 ` [PATCH v5 0/9] stmmac: Add Loongson platform support Jakub Kicinski
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