* [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978
@ 2022-11-23 18:36 Matt Atwood
2022-11-23 18:36 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663 Matt Atwood
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Matt Atwood @ 2022-11-23 18:36 UTC (permalink / raw)
To: intel-gfx
Wa_18018764978 applies to specific steppings of DG2 (G10 C0+,
G11 and G12 A0+). Clean up style in function at the same time.
Bspec: 66622
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 80a979e6f6be..74379d3c5a4d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -457,6 +457,9 @@
#define GEN8_L3CNTLREG _MMIO(0x7034)
#define GEN8_ERRDETBCTRL (1 << 9)
+#define PSS_MODE2 _MMIO(0x703c)
+#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
+
#define GEN7_SC_INSTDONE _MMIO(0x7100)
#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2afb4f80a954..870db5a202dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_14014947963:dg2 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
- IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+ IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
+ /* Wa_18018764978:dg2 */
+ if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+ IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+ wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
+
/* Wa_15010599737:dg2 */
wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
}
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663 2022-11-23 18:36 [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 Matt Atwood @ 2022-11-23 18:36 ` Matt Atwood 2022-11-23 19:47 ` Gustavo Sousa 2022-11-23 19:45 ` [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 Gustavo Sousa 2022-11-23 20:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] " Patchwork 2 siblings, 1 reply; 10+ messages in thread From: Matt Atwood @ 2022-11-23 18:36 UTC (permalink / raw) To: intel-gfx Wa_18019271663 applies to all DG2 steppings and skus. Bspec: 66622 Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ++++--- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 74379d3c5a4d..784152548472 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -429,9 +429,10 @@ #define RC_OP_FLUSH_ENABLE (1 << 0) #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) -#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) -#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) +#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) #define GEN7_GT_MODE _MMIO(0x7008) #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 870db5a202dd..1b0e40e68a9d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_15010599737:dg2 */ wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); + + /* Wa_18019271663:dg2 */ + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); } static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, -- 2.38.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663 2022-11-23 18:36 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663 Matt Atwood @ 2022-11-23 19:47 ` Gustavo Sousa 0 siblings, 0 replies; 10+ messages in thread From: Gustavo Sousa @ 2022-11-23 19:47 UTC (permalink / raw) To: Matt Atwood, intel-gfx On Wed, Nov 23, 2022 at 10:36:48AM -0800, Matt Atwood wrote: > Wa_18019271663 applies to all DG2 steppings and skus. > > Bspec: 66622 > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ++++--- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 74379d3c5a4d..784152548472 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -429,9 +429,10 @@ > #define RC_OP_FLUSH_ENABLE (1 << 0) > #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) > #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ > -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) > -#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) > -#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) > +#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) > +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) > +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) > +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) > > #define GEN7_GT_MODE _MMIO(0x7008) > #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 870db5a202dd..1b0e40e68a9d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > /* Wa_15010599737:dg2 */ > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > + > + /* Wa_18019271663:dg2 */ > + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > } > > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, > -- > 2.38.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 2022-11-23 18:36 [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 Matt Atwood 2022-11-23 18:36 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663 Matt Atwood @ 2022-11-23 19:45 ` Gustavo Sousa 2022-11-28 18:26 ` Matt Roper 2022-11-23 20:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] " Patchwork 2 siblings, 1 reply; 10+ messages in thread From: Gustavo Sousa @ 2022-11-23 19:45 UTC (permalink / raw) To: Matt Atwood, intel-gfx On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote: > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, > G11 and G12 A0+). Clean up style in function at the same time. > > Bspec: 66622 > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 80a979e6f6be..74379d3c5a4d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -457,6 +457,9 @@ > #define GEN8_L3CNTLREG _MMIO(0x7034) > #define GEN8_ERRDETBCTRL (1 << 9) > > +#define PSS_MODE2 _MMIO(0x703c) > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > + > #define GEN7_SC_INSTDONE _MMIO(0x7100) > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 2afb4f80a954..870db5a202dd 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > /* Wa_14014947963:dg2 */ > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || > - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); > > + /* Wa_18018764978:dg2 */ > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > + > /* Wa_15010599737:dg2 */ > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > } > -- > 2.38.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 2022-11-23 19:45 ` [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 Gustavo Sousa @ 2022-11-28 18:26 ` Matt Roper 2023-01-18 9:54 ` Tvrtko Ursulin 0 siblings, 1 reply; 10+ messages in thread From: Matt Roper @ 2022-11-28 18:26 UTC (permalink / raw) To: Gustavo Sousa; +Cc: intel-gfx On Wed, Nov 23, 2022 at 04:45:25PM -0300, Gustavo Sousa wrote: > On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote: > > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, > > G11 and G12 A0+). Clean up style in function at the same time. > > > > Bspec: 66622 > > > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > > Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Both patches applied to drm-intel-gt-next. Thanks for the patches and review. Matt > > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++++- > > 2 files changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 80a979e6f6be..74379d3c5a4d 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -457,6 +457,9 @@ > > #define GEN8_L3CNTLREG _MMIO(0x7034) > > #define GEN8_ERRDETBCTRL (1 << 9) > > > > +#define PSS_MODE2 _MMIO(0x703c) > > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > > + > > #define GEN7_SC_INSTDONE _MMIO(0x7100) > > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 2afb4f80a954..870db5a202dd 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > > > /* Wa_14014947963:dg2 */ > > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || > > - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); > > > > + /* Wa_18018764978:dg2 */ > > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > > + > > /* Wa_15010599737:dg2 */ > > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > > } > > -- > > 2.38.1 > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 2022-11-28 18:26 ` Matt Roper @ 2023-01-18 9:54 ` Tvrtko Ursulin 2023-01-18 17:01 ` Rodrigo Vivi 0 siblings, 1 reply; 10+ messages in thread From: Tvrtko Ursulin @ 2023-01-18 9:54 UTC (permalink / raw) To: Matt Roper, Gustavo Sousa; +Cc: intel-gfx, Rodrigo Vivi On 28/11/2022 18:26, Matt Roper wrote: > On Wed, Nov 23, 2022 at 04:45:25PM -0300, Gustavo Sousa wrote: >> On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote: >>> Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, >>> G11 and G12 A0+). Clean up style in function at the same time. >>> >>> Bspec: 66622 >>> >>> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> >> >> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > > Both patches applied to drm-intel-gt-next. Thanks for the patches and > review. Do these need to be sent to 6.2 fixes, given DG2 is out of force probe there? Regards, Tvrtko >>> --- >>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ >>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++++- >>> 2 files changed, 9 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >>> index 80a979e6f6be..74379d3c5a4d 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h >>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >>> @@ -457,6 +457,9 @@ >>> #define GEN8_L3CNTLREG _MMIO(0x7034) >>> #define GEN8_ERRDETBCTRL (1 << 9) >>> >>> +#define PSS_MODE2 _MMIO(0x703c) >>> +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) >>> + >>> #define GEN7_SC_INSTDONE _MMIO(0x7100) >>> #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) >>> #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) >>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >>> index 2afb4f80a954..870db5a202dd 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >>> @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, >>> >>> /* Wa_14014947963:dg2 */ >>> if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || >>> - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) >>> + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) >>> wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); >>> >>> + /* Wa_18018764978:dg2 */ >>> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || >>> + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) >>> + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); >>> + >>> /* Wa_15010599737:dg2 */ >>> wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); >>> } >>> -- >>> 2.38.1 >>> > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 2023-01-18 9:54 ` Tvrtko Ursulin @ 2023-01-18 17:01 ` Rodrigo Vivi 2023-01-19 21:22 ` Matt Roper 0 siblings, 1 reply; 10+ messages in thread From: Rodrigo Vivi @ 2023-01-18 17:01 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx On Wed, Jan 18, 2023 at 09:54:56AM +0000, Tvrtko Ursulin wrote: > > On 28/11/2022 18:26, Matt Roper wrote: > > On Wed, Nov 23, 2022 at 04:45:25PM -0300, Gustavo Sousa wrote: > > > On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote: > > > > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, > > > > G11 and G12 A0+). Clean up style in function at the same time. > > > > > > > > Bspec: 66622 > > > > > > > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > > > > > > Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > > > > Both patches applied to drm-intel-gt-next. Thanks for the patches and > > review. > > Do these need to be sent to 6.2 fixes, given DG2 is out of force probe > there? Yeap, good point. I'd say in general we are not very good in cherry-picking the hw w/a to the fixes. But this one was a good catch. Let's ensure the best stability for DG2 on 6.2. pushed to drm-intel-fixes now. Thanks, Rodrigo. > > Regards, > > Tvrtko > > > > > --- > > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++++- > > > > 2 files changed, 9 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > index 80a979e6f6be..74379d3c5a4d 100644 > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > @@ -457,6 +457,9 @@ > > > > #define GEN8_L3CNTLREG _MMIO(0x7034) > > > > #define GEN8_ERRDETBCTRL (1 << 9) > > > > +#define PSS_MODE2 _MMIO(0x703c) > > > > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > > > > + > > > > #define GEN7_SC_INSTDONE _MMIO(0x7100) > > > > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > > > > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > index 2afb4f80a954..870db5a202dd 100644 > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > > > /* Wa_14014947963:dg2 */ > > > > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || > > > > - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); > > > > + /* Wa_18018764978:dg2 */ > > > > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > > > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > > > > + > > > > /* Wa_15010599737:dg2 */ > > > > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > > > > } > > > > -- > > > > 2.38.1 > > > > > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 2023-01-18 17:01 ` Rodrigo Vivi @ 2023-01-19 21:22 ` Matt Roper 2023-01-19 22:13 ` Gustavo Sousa 0 siblings, 1 reply; 10+ messages in thread From: Matt Roper @ 2023-01-19 21:22 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx On Wed, Jan 18, 2023 at 12:01:20PM -0500, Rodrigo Vivi wrote: > On Wed, Jan 18, 2023 at 09:54:56AM +0000, Tvrtko Ursulin wrote: > > > > On 28/11/2022 18:26, Matt Roper wrote: > > > On Wed, Nov 23, 2022 at 04:45:25PM -0300, Gustavo Sousa wrote: > > > > On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote: > > > > > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, > > > > > G11 and G12 A0+). Clean up style in function at the same time. > > > > > > > > > > Bspec: 66622 > > > > > > > > > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > > > > > > > > Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > > > > > > Both patches applied to drm-intel-gt-next. Thanks for the patches and > > > review. > > > > Do these need to be sent to 6.2 fixes, given DG2 is out of force probe > > there? > > Yeap, good point. I'd say in general we are not very good in cherry-picking > the hw w/a to the fixes. But this one was a good catch. Let's ensure the > best stability for DG2 on 6.2. > > pushed to drm-intel-fixes now. I don't have any concerns about putting this in drm-intel-fixes, and the patch will functionally behave as expected, but I did just notice one minor problem with the original patch that we should probably fix up on drm-intel-gt-next: the PSS_MODE2 register is in a range that has multicast behavior (GSLICE replication) on Xe_HP platforms. So the register should have been defined as MCR_REG() instead of _MMIO, and the workaround should use wa_mcr_masked_en(). As I mentioned, this oversight shouldn't cause any real problems, so no concerns about keeping this in -fixes. On DG2 we don't have to worry about steering races with external agents, so even with the 'wrong' register type definition, the steering should already be implicitly set to multicast mode at the point we're applying workarounds. The need to follow up with a correction on drm-intel-gt-next is really only important for consistency and in case this register gets used in other manners (not just workaround lists) at some point in the future. MattA/Gustavo will one of you guys send an update for that, or should I take care of it? Matt > > Thanks, > Rodrigo. > > > > > Regards, > > > > Tvrtko > > > > > > > --- > > > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++++- > > > > > 2 files changed, 9 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > > index 80a979e6f6be..74379d3c5a4d 100644 > > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > > @@ -457,6 +457,9 @@ > > > > > #define GEN8_L3CNTLREG _MMIO(0x7034) > > > > > #define GEN8_ERRDETBCTRL (1 << 9) > > > > > +#define PSS_MODE2 _MMIO(0x703c) > > > > > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > > > > > + > > > > > #define GEN7_SC_INSTDONE _MMIO(0x7100) > > > > > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > > > > > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > > index 2afb4f80a954..870db5a202dd 100644 > > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > > @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > > > > /* Wa_14014947963:dg2 */ > > > > > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || > > > > > - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > > wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); > > > > > + /* Wa_18018764978:dg2 */ > > > > > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > > > > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > > > > > + > > > > > /* Wa_15010599737:dg2 */ > > > > > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > > > > > } > > > > > -- > > > > > 2.38.1 > > > > > > > > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 2023-01-19 21:22 ` Matt Roper @ 2023-01-19 22:13 ` Gustavo Sousa 0 siblings, 0 replies; 10+ messages in thread From: Gustavo Sousa @ 2023-01-19 22:13 UTC (permalink / raw) To: Matt Roper, Rodrigo Vivi; +Cc: intel-gfx On Thu, Jan 19, 2023 at 01:22:24PM -0800, Matt Roper wrote: > On Wed, Jan 18, 2023 at 12:01:20PM -0500, Rodrigo Vivi wrote: > > On Wed, Jan 18, 2023 at 09:54:56AM +0000, Tvrtko Ursulin wrote: > > > > > > On 28/11/2022 18:26, Matt Roper wrote: > > > > On Wed, Nov 23, 2022 at 04:45:25PM -0300, Gustavo Sousa wrote: > > > > > On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote: > > > > > > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, > > > > > > G11 and G12 A0+). Clean up style in function at the same time. > > > > > > > > > > > > Bspec: 66622 > > > > > > > > > > > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > > > > > > > > > > Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > > > > > > > > Both patches applied to drm-intel-gt-next. Thanks for the patches and > > > > review. > > > > > > Do these need to be sent to 6.2 fixes, given DG2 is out of force probe > > > there? > > > > Yeap, good point. I'd say in general we are not very good in cherry-picking > > the hw w/a to the fixes. But this one was a good catch. Let's ensure the > > best stability for DG2 on 6.2. > > > > pushed to drm-intel-fixes now. > > I don't have any concerns about putting this in drm-intel-fixes, and the > patch will functionally behave as expected, but I did just notice one > minor problem with the original patch that we should probably fix up on > drm-intel-gt-next: the PSS_MODE2 register is in a range that has > multicast behavior (GSLICE replication) on Xe_HP platforms. So the > register should have been defined as MCR_REG() instead of _MMIO, and the > workaround should use wa_mcr_masked_en(). > > As I mentioned, this oversight shouldn't cause any real problems, so no > concerns about keeping this in -fixes. On DG2 we don't have to worry > about steering races with external agents, so even with the 'wrong' > register type definition, the steering should already be implicitly set > to multicast mode at the point we're applying workarounds. The need to > follow up with a correction on drm-intel-gt-next is really only > important for consistency and in case this register gets used in other > manners (not just workaround lists) at some point in the future. > > MattA/Gustavo will one of you guys send an update for that, or should I > take care of it? I'll do it. Sorry about missing that in my review. I *think* I came to learn about MCR registers only some time after that. -- Gustavo Sousa > > > Matt > > > > > Thanks, > > Rodrigo. > > > > > > > > Regards, > > > > > > Tvrtko > > > > > > > > > --- > > > > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > > > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++++- > > > > > > 2 files changed, 9 insertions(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > > > index 80a979e6f6be..74379d3c5a4d 100644 > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > > > > @@ -457,6 +457,9 @@ > > > > > > #define GEN8_L3CNTLREG _MMIO(0x7034) > > > > > > #define GEN8_ERRDETBCTRL (1 << 9) > > > > > > +#define PSS_MODE2 _MMIO(0x703c) > > > > > > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > > > > > > + > > > > > > #define GEN7_SC_INSTDONE _MMIO(0x7100) > > > > > > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > > > > > > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > > > index 2afb4f80a954..870db5a202dd 100644 > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > > > > @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > > > > > /* Wa_14014947963:dg2 */ > > > > > > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || > > > > > > - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > > > wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); > > > > > > + /* Wa_18018764978:dg2 */ > > > > > > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > > > > > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > > > > > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > > > > > > + > > > > > > /* Wa_15010599737:dg2 */ > > > > > > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > > > > > > } > > > > > > -- > > > > > > 2.38.1 > > > > > > > > > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/dg2: Introduce Wa_18018764978 2022-11-23 18:36 [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 Matt Atwood 2022-11-23 18:36 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663 Matt Atwood 2022-11-23 19:45 ` [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 Gustavo Sousa @ 2022-11-23 20:30 ` Patchwork 2 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2022-11-23 20:30 UTC (permalink / raw) To: Matt Atwood; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 12326 bytes --] == Series Details == Series: series starting with [v4,1/2] drm/i915/dg2: Introduce Wa_18018764978 URL : https://patchwork.freedesktop.org/series/111270/ State : success == Summary == CI Bug Log - changes from CI_DRM_12424 -> Patchwork_111270v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/index.html Participating hosts (37 -> 37) ------------------------------ Additional (2): fi-icl-u2 bat-dg1-6 Missing (2): fi-ctg-p8600 fi-ilk-m540 Known issues ------------ Here are the changes found in Patchwork_111270v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@debugfs_test@basic-hwmon: - fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@debugfs_test@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@gem_lmem_swapping@random-engines.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@gem_mmap@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@gem_render_tiled_blits@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@gem_tiled_fence_blits@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#7561]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@i915_pm_rps@basic-api.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][9] ([i915#146]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-bdw-gvtdvm/igt@i915_suspend@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][10] -> [INCOMPLETE][11] ([i915#4817]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4215]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_addfb_basic@tile-pitch-mismatch.html * igt@kms_chamelium@common-hpd-after-suspend: - bat-dg1-5: NOTRUN -> [SKIP][14] ([fdo#111827]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-5/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-crc-fast: - bat-dg1-6: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_chamelium@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html - fi-bdw-gvtdvm: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +7 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-bdw-gvtdvm/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-icl-u2: NOTRUN -> [SKIP][18] ([i915#4103]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html - bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html * igt@kms_flip@basic-plain-flip: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][20] ([fdo#109271]) +31 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-bdw-gvtdvm/igt@kms_flip@basic-plain-flip.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][21] ([fdo#109285]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html - bat-dg1-6: NOTRUN -> [SKIP][22] ([fdo#109285]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_psr@sprite_plane_onoff: - bat-dg1-6: NOTRUN -> [SKIP][23] ([i915#1072] / [i915#4078]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-6: NOTRUN -> [SKIP][24] ([i915#3555]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html - fi-icl-u2: NOTRUN -> [SKIP][25] ([i915#3555]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-gtt: - bat-dg1-6: NOTRUN -> [SKIP][26] ([i915#3708] / [i915#4077]) +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@prime_vgem@basic-gtt.html * igt@prime_vgem@basic-read: - bat-dg1-6: NOTRUN -> [SKIP][27] ([i915#3708]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@prime_vgem@basic-read.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][28] ([fdo#109295] / [i915#3301]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-icl-u2/igt@prime_vgem@basic-userptr.html - bat-dg1-6: NOTRUN -> [SKIP][29] ([i915#3708] / [i915#4873]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-6/igt@prime_vgem@basic-userptr.html #### Possible fixes #### * igt@gem_exec_parallel@engines@contexts: - fi-bdw-gvtdvm: [INCOMPLETE][30] ([i915#7506]) -> [PASS][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/fi-bdw-gvtdvm/igt@gem_exec_parallel@engines@contexts.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-bdw-gvtdvm/igt@gem_exec_parallel@engines@contexts.html * igt@i915_module_load@reload: - {bat-rpls-2}: [DMESG-WARN][32] ([i915#6434]) -> [PASS][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/bat-rpls-2/igt@i915_module_load@reload.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-rpls-2/igt@i915_module_load@reload.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [DMESG-FAIL][34] ([i915#5334]) -> [PASS][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_lrc: - bat-dg1-5: [INCOMPLETE][36] -> [PASS][37] [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/bat-dg1-5/igt@i915_selftest@live@gt_lrc.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-dg1-5/igt@i915_selftest@live@gt_lrc.html - {bat-rpls-1}: [INCOMPLETE][38] ([i915#4983]) -> [PASS][39] [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/bat-rpls-1/igt@i915_selftest@live@gt_lrc.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/bat-rpls-1/igt@i915_selftest@live@gt_lrc.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions: - fi-bsw-kefka: [FAIL][40] ([i915#6298]) -> [PASS][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12424/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298 [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7467]: https://gitlab.freedesktop.org/drm/intel/issues/7467 [i915#7506]: https://gitlab.freedesktop.org/drm/intel/issues/7506 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 Build changes ------------- * Linux: CI_DRM_12424 -> Patchwork_111270v1 CI-20190529: 20190529 CI_DRM_12424: c8b2ce6e20662ef30130e65f473b1ff5362765e3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7072: 69ba7163475925cdc69aebbdfa0e87453ae165c7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_111270v1: c8b2ce6e20662ef30130e65f473b1ff5362765e3 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits fe39335e058e drm/i915/dg2: Introduce Wa_18019271663 d0406972d8db drm/i915/dg2: Introduce Wa_18018764978 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111270v1/index.html [-- Attachment #2: Type: text/html, Size: 14173 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-01-19 22:14 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-23 18:36 [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 Matt Atwood 2022-11-23 18:36 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/dg2: Introduce Wa_18019271663 Matt Atwood 2022-11-23 19:47 ` Gustavo Sousa 2022-11-23 19:45 ` [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978 Gustavo Sousa 2022-11-28 18:26 ` Matt Roper 2023-01-18 9:54 ` Tvrtko Ursulin 2023-01-18 17:01 ` Rodrigo Vivi 2023-01-19 21:22 ` Matt Roper 2023-01-19 22:13 ` Gustavo Sousa 2022-11-23 20:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] " Patchwork
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