[PATCH] x86/msr: handle reads to MSR_P5_MC_ADDR

[PATCH] x86/msr: handle reads to MSR_P5_MC_ADDR

[Roger Pau Monne]

Windows Server 2019 Essentials will unconditionally attempt to read
P5_MC_ADDR MSR at boot and throw a BSOD if injected a #GP.

Fix this by adding dummy handling that returns 0 for reads of
P5_MC_ADDR.  This seems to be enough to make Windows happy.

Reported-by: Steffen Einsle <einsle@phptrix.de>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
I've added it for CENTAUR and SHANGHAI because the MSR is there since
Pentium, so likely to be implemented by those vendors also, but have
no way to check.

I wonder how long it will take for Windows to also start poking at
MSR_IA32_MC0_ADDR or other MCE related registers.  For now this seems
to be enough.
---
 xen/arch/x86/include/asm/msr-index.h |  2 ++
 xen/arch/x86/msr.c                   | 13 +++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 3e038db618..02af9dc039 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -15,6 +15,8 @@
  * abbreviated name.  Exceptions will be considered on a case-by-case basis.
  */
 
+#define MSR_P5_MC_ADDR                      0
+
 #define MSR_APIC_BASE                       0x0000001b
 #define  APIC_BASE_BSP                      (_AC(1, ULL) <<  8)
 #define  APIC_BASE_EXTD                     (_AC(1, ULL) << 10)
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index a1e268eea9..e50bbf466a 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -216,6 +216,19 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
     case MSR_AMD_PPIN:
         goto gp_fault;
 
+    case MSR_P5_MC_ADDR:
+        /*
+         * Windows Server 2019 Essentials will attempt to read the MSR and
+         * throw a BSOD if a #GP is raised, so just return 0 in order to make
+         * Windows happy.
+         */
+        if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR |
+                                 X86_VENDOR_SHANGHAI)) )
+            goto gp_fault;
+
+        *val = 0;
+        break;
+
     case MSR_IA32_FEATURE_CONTROL:
         /*
          * Architecturally, availability of this MSR is enumerated by the
-- 
2.35.1

Re: [PATCH] x86/msr: handle reads to MSR_P5_MC_ADDR

[Jan Beulich]

On 27.04.2022 17:47, Roger Pau Monne wrote:
> I've added it for CENTAUR and SHANGHAI because the MSR is there since
> Pentium, so likely to be implemented by those vendors also, but have
> no way to check.

I think that's fine.

> I wonder how long it will take for Windows to also start poking at
> MSR_IA32_MC0_ADDR or other MCE related registers.  For now this seems
> to be enough.

Those are handled by vmce_{rd,wr}msr(), aren't they? As a result I
wonder whether the MSR in question as well as its companion
P5_MC_TYPE wouldn't better also be handled (faked) there. (Even if
not, I don't think we should handle ADDR by not TYPE.)

Jan