From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com> To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: Re: [PATCH 3/3] drm/i915/gtt: ignore min_page_size for paging structures Date: Wed, 23 Jun 2021 14:44:30 +0200 [thread overview] Message-ID: <d0624cc5f8d689d325cc9ec0c5b53cfacf109fa5.camel@linux.intel.com> (raw) In-Reply-To: <dcb9729d-fd1c-900e-bb6e-38eb2cf208d2@intel.com> On Wed, 2021-06-23 at 13:25 +0100, Matthew Auld wrote: > On 23/06/2021 12:51, Thomas Hellström wrote: > > > > On 6/23/21 1:26 PM, Matthew Auld wrote: > > > The min_page_size is only needed for pages inserted into the GTT, > > > and > > > for our paging structures we only need at most 4K bytes, so > > > simply > > > ignore the min_page_size restrictions here, otherwise we might > > > see some > > > severe overallocation on some devices. > > > > > > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > > > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> > > > --- > > > drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c > > > b/drivers/gpu/drm/i915/gt/intel_gtt.c > > > index 084ea65d59c0..61e8a8c25374 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c > > > @@ -16,7 +16,7 @@ struct drm_i915_gem_object > > > *alloc_pt_lmem(struct > > > i915_address_space *vm, int sz) > > > { > > > struct drm_i915_gem_object *obj; > > > - obj = i915_gem_object_create_lmem(vm->i915, sz, 0); > > > + obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, > > > sz, 0); > > > /* > > > * Ensure all paging structures for this vm share the same > > > dma-resv > > > * object underneath, with the idea that one object_lock() > > > will > > > lock > > > > I think for this one the new gt migration code might break, because > > there we insert even PT pages into the GTT, so it might need a > > special > > interface? Ram is looking at supporter larger GPU PTE sizes with > > that > > code.. > > For DG1 at least we don't need this. But yeah we can always just pass > along the page size when allocating the stash I guess, if we need > something special for migration? > > But when we need to support huge PTEs for stuff other than DG1, then > it's still a pile of work I assume, since we still need all the > special > PTE insertion routines specifically for insert_pte() which will > differ > wildly between generations, also each has quite different > restrictions > wrt min physical alignment of lmem, whether you can mix 64K/4K PTEs > in > the same 2M va range, whether 4K PTEs are even supported for lmem > etc. > > Not sure if it's simpler to go with mapping all of lmem upfront with > the > flat-ppGTT? Maybe that sidesteps some of these issues? At least for > the > physical alignment of paging structures that would no longer be a > concern. Yes, that might be the simplest way forward. /Thomas > > > > > /Thomas > > > > > >
WARNING: multiple messages have this Message-ID (diff)
From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com> To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/gtt: ignore min_page_size for paging structures Date: Wed, 23 Jun 2021 14:44:30 +0200 [thread overview] Message-ID: <d0624cc5f8d689d325cc9ec0c5b53cfacf109fa5.camel@linux.intel.com> (raw) In-Reply-To: <dcb9729d-fd1c-900e-bb6e-38eb2cf208d2@intel.com> On Wed, 2021-06-23 at 13:25 +0100, Matthew Auld wrote: > On 23/06/2021 12:51, Thomas Hellström wrote: > > > > On 6/23/21 1:26 PM, Matthew Auld wrote: > > > The min_page_size is only needed for pages inserted into the GTT, > > > and > > > for our paging structures we only need at most 4K bytes, so > > > simply > > > ignore the min_page_size restrictions here, otherwise we might > > > see some > > > severe overallocation on some devices. > > > > > > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > > > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> > > > --- > > > drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c > > > b/drivers/gpu/drm/i915/gt/intel_gtt.c > > > index 084ea65d59c0..61e8a8c25374 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c > > > @@ -16,7 +16,7 @@ struct drm_i915_gem_object > > > *alloc_pt_lmem(struct > > > i915_address_space *vm, int sz) > > > { > > > struct drm_i915_gem_object *obj; > > > - obj = i915_gem_object_create_lmem(vm->i915, sz, 0); > > > + obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, > > > sz, 0); > > > /* > > > * Ensure all paging structures for this vm share the same > > > dma-resv > > > * object underneath, with the idea that one object_lock() > > > will > > > lock > > > > I think for this one the new gt migration code might break, because > > there we insert even PT pages into the GTT, so it might need a > > special > > interface? Ram is looking at supporter larger GPU PTE sizes with > > that > > code.. > > For DG1 at least we don't need this. But yeah we can always just pass > along the page size when allocating the stash I guess, if we need > something special for migration? > > But when we need to support huge PTEs for stuff other than DG1, then > it's still a pile of work I assume, since we still need all the > special > PTE insertion routines specifically for insert_pte() which will > differ > wildly between generations, also each has quite different > restrictions > wrt min physical alignment of lmem, whether you can mix 64K/4K PTEs > in > the same 2M va range, whether 4K PTEs are even supported for lmem > etc. > > Not sure if it's simpler to go with mapping all of lmem upfront with > the > flat-ppGTT? Maybe that sidesteps some of these issues? At least for > the > physical alignment of paging structures that would no longer be a > concern. Yes, that might be the simplest way forward. /Thomas > > > > > /Thomas > > > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-23 12:44 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-23 11:26 [PATCH 1/3] drm/i915/ttm: consider all placements for the page alignment Matthew Auld 2021-06-23 11:26 ` [Intel-gfx] " Matthew Auld 2021-06-23 11:26 ` [PATCH 2/3] drm/i915: support forcing the page size with lmem Matthew Auld 2021-06-23 11:26 ` [Intel-gfx] " Matthew Auld 2021-06-23 12:54 ` Thomas Hellström 2021-06-23 12:54 ` [Intel-gfx] " Thomas Hellström 2021-06-23 11:26 ` [PATCH 3/3] drm/i915/gtt: ignore min_page_size for paging structures Matthew Auld 2021-06-23 11:26 ` [Intel-gfx] " Matthew Auld 2021-06-23 11:51 ` Thomas Hellström 2021-06-23 11:51 ` [Intel-gfx] " Thomas Hellström 2021-06-23 12:25 ` Matthew Auld 2021-06-23 12:25 ` [Intel-gfx] " Matthew Auld 2021-06-23 12:44 ` Thomas Hellström [this message] 2021-06-23 12:44 ` Thomas Hellström 2021-06-23 13:32 ` Thomas Hellström 2021-06-23 13:32 ` [Intel-gfx] " Thomas Hellström 2021-06-23 13:38 ` Matthew Auld 2021-06-23 13:38 ` [Intel-gfx] " Matthew Auld 2021-06-23 13:39 ` Thomas Hellström 2021-06-23 13:39 ` [Intel-gfx] " Thomas Hellström 2021-06-23 12:50 ` [PATCH 1/3] drm/i915/ttm: consider all placements for the page alignment Thomas Hellström 2021-06-23 12:50 ` [Intel-gfx] " Thomas Hellström 2021-06-23 14:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] " Patchwork 2021-06-23 14:43 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=d0624cc5f8d689d325cc9ec0c5b53cfacf109fa5.camel@linux.intel.com \ --to=thomas.hellstrom@linux.intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=matthew.auld@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.