* [PATCH v3] mtd: spi-nor: Add support for N25Q256A13
@ 2017-03-02 2:42 Nobuhiro Iwamatsu
2017-03-07 22:11 ` Cyrille Pitchen
0 siblings, 1 reply; 4+ messages in thread
From: Nobuhiro Iwamatsu @ 2017-03-02 2:42 UTC (permalink / raw)
To: linux-mtd; +Cc: Nobuhiro Iwamatsu, Jagan Teki, Marek Vasut, Cyrille Pitchen
Add new Micron N25Q256A (N25Q256A13) 256Mbit NOR Flash in the list
of supported devices. This chip has the same structure as the N25Q256A
but ID and voltage (1V8) to use is different. Therefore, this adds
N25Q256A13 as n25q256ax1.
In the future, for new Micron memories we could use the patterns
"n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
CC: Jagan Teki <jagan@openedev.com>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/mtd/spi-nor/spi-nor.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 1ae872bfc3ba..2e02991d93aa 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1031,6 +1031,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
+ { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
--
2.11.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3] mtd: spi-nor: Add support for N25Q256A13
2017-03-02 2:42 [PATCH v3] mtd: spi-nor: Add support for N25Q256A13 Nobuhiro Iwamatsu
@ 2017-03-07 22:11 ` Cyrille Pitchen
2017-03-10 3:19 ` Marek Vasut
2017-03-22 5:55 ` 岩松信洋 / IWAMATSU，NOBUHIRO
0 siblings, 2 replies; 4+ messages in thread
From: Cyrille Pitchen @ 2017-03-07 22:11 UTC (permalink / raw)
To: Nobuhiro Iwamatsu, linux-mtd; +Cc: Marek Vasut, Cyrille Pitchen, Jagan Teki
Hi Nobuhiro,
Le 02/03/2017 à 03:42, Nobuhiro Iwamatsu a écrit :
> Add new Micron N25Q256A (N25Q256A13) 256Mbit NOR Flash in the list
^
You mean N25Q256A11, don't you? Otherwise it's not consistent with the
actual patch!
> of supported devices. This chip has the same structure as the N25Q256A
> but ID and voltage (1V8) to use is different. Therefore, this adds
> N25Q256A13 as n25q256ax1.
^
N25Q256A11 as n25q256ax1
>
> In the future, for new Micron memories we could use the patterns
> "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories.
>
Sound like a good idea :)
Marek, do you agree with that?
Best regards,
Cyrille
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
> CC: Jagan Teki <jagan@openedev.com>
> CC: Marek Vasut <marek.vasut@gmail.com>
> CC: Cyrille Pitchen <cyrille.pitchen@atmel.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 1ae872bfc3ba..2e02991d93aa 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1031,6 +1031,7 @@ static const struct flash_info spi_nor_ids[] = {
> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
> + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3] mtd: spi-nor: Add support for N25Q256A13
2017-03-07 22:11 ` Cyrille Pitchen
@ 2017-03-10 3:19 ` Marek Vasut
2017-03-22 5:55 ` 岩松信洋 / IWAMATSU，NOBUHIRO
1 sibling, 0 replies; 4+ messages in thread
From: Marek Vasut @ 2017-03-10 3:19 UTC (permalink / raw)
To: Cyrille Pitchen, Nobuhiro Iwamatsu, linux-mtd; +Cc: Cyrille Pitchen, Jagan Teki
On 03/07/2017 11:11 PM, Cyrille Pitchen wrote:
> Hi Nobuhiro,
>
> Le 02/03/2017 à 03:42, Nobuhiro Iwamatsu a écrit :
>> Add new Micron N25Q256A (N25Q256A13) 256Mbit NOR Flash in the list
> ^
> You mean N25Q256A11, don't you? Otherwise it's not consistent with the
> actual patch!
>
>> of supported devices. This chip has the same structure as the N25Q256A
>> but ID and voltage (1V8) to use is different. Therefore, this adds
>> N25Q256A13 as n25q256ax1.
>
> ^
> N25Q256A11 as n25q256ax1
>
>>
>> In the future, for new Micron memories we could use the patterns
>> "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories.
>>
>
> Sound like a good idea :)
> Marek, do you agree with that?
How would that work ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH v3] mtd: spi-nor: Add support for N25Q256A13
2017-03-07 22:11 ` Cyrille Pitchen
2017-03-10 3:19 ` Marek Vasut
@ 2017-03-22 5:55 ` 岩松信洋 / IWAMATSU，NOBUHIRO
1 sibling, 0 replies; 4+ messages in thread
From: 岩松信洋 / IWAMATSU，NOBUHIRO @ 2017-03-22 5:55 UTC (permalink / raw)
To: Cyrille Pitchen, linux-mtd; +Cc: Marek Vasut, Cyrille Pitchen, Jagan Teki
Hi,
> -----Original Message-----
> From: Cyrille Pitchen [mailto:cyrille.pitchen@wedev4u.fr]
> Sent: Wednesday, March 08, 2017 7:11 AM
> To: 岩松信洋 / IWAMATSU，NOBUHIRO; linux-mtd@lists.infradead.org
> Cc: Marek Vasut; Cyrille Pitchen; Jagan Teki
> Subject: Re: [PATCH v3] mtd: spi-nor: Add support for N25Q256A13
>
> Hi Nobuhiro,
>
> Le 02/03/2017 à 03:42, Nobuhiro Iwamatsu a écrit :
> > Add new Micron N25Q256A (N25Q256A13) 256Mbit NOR Flash in the list
> ^
> You mean N25Q256A11, don't you? Otherwise it's not consistent with the
> actual patch!
>
Yes, this is my bad.
> > of supported devices. This chip has the same structure as the N25Q256A
> > but ID and voltage (1V8) to use is different. Therefore, this adds
> > N25Q256A13 as n25q256ax1.
>
> ^
> N25Q256A11 as n25q256ax1
Indeed, thanks.
>
> >
> > In the future, for new Micron memories we could use the patterns
> > "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories.
> >
>
> Sound like a good idea :)
> Marek, do you agree with that?
>
> Best regards,
>
> Cyrille
>
I will send 4th patch soon.
Thanks,
Nobuhiro
> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
> > CC: Jagan Teki <jagan@openedev.com>
> > CC: Marek Vasut <marek.vasut@gmail.com>
> > CC: Cyrille Pitchen <cyrille.pitchen@atmel.com>
> > ---
> > drivers/mtd/spi-nor/spi-nor.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index 1ae872bfc3ba..2e02991d93aa
> > 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1031,6 +1031,7 @@ static const struct flash_info spi_nor_ids[] = {
> > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> > { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ) },
> > + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> > +SPI_NOR_QUAD_READ) },
> > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
> > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
> > { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
> >
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-03-22 5:55 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-02 2:42 [PATCH v3] mtd: spi-nor: Add support for N25Q256A13 Nobuhiro Iwamatsu
2017-03-07 22:11 ` Cyrille Pitchen
2017-03-10 3:19 ` Marek Vasut
2017-03-22 5:55 ` 岩松信洋 / IWAMATSU，NOBUHIRO
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.