[PATCH v2 00/22] GuC 32.0.3

[PATCH v2 00/22] GuC 32.0.3

[Michal Wajdeczko]

New GuC firmwares (for SKL, BXT, KBL, ICL) with updated ABI interface.

v2: only HuC authentication is supported

Michal Wajdeczko (20):
  drm/i915/guc: Change platform default GuC mode
  drm/i915/guc: Don't allow GuC submission
  drm/i915/guc: Simplify preparation of GuC parameter block
  drm/i915/guc: Update GuC firmware versions and names
  drm/i915/guc: Update GuC firmware CSS header
  drm/i915/guc: Update GuC boot parameters
  drm/i915/guc: Update GuC sleep status values
  drm/i915/guc: Update GuC sample-forcewake command
  drm/i915/guc: Update GuC ADS object definition
  drm/i915/guc: Always ask GuC to update power domain states
  drm/i915/guc: Reset GuC ADS during sanitize
  drm/i915/guc: Treat GuC initialization failure as -EIO
  drm/i915/guc: New GuC interrupt register for Gen11
  drm/i915/guc: New GuC scratch registers for Gen11
  drm/i915/huc: New HuC status register for Gen11
  drm/i915/guc: Update GuC CTB response definition
  drm/i915/guc: Enable GuC CTB communication on Gen11
  drm/i915/guc: Define GuC firmware version for Icelake
  drm/i915/huc: Define HuC firmware version for Icelake
  HAX: prevent CI failures on configs with forced GuC submission

Oscar Mateo (2):
  drm/i915/guc: Create vfuncs for the GuC interrupts control functions
  drm/i915/guc: Correctly handle GuC interrupts on Gen11

 drivers/gpu/drm/i915/i915_drv.h             |  28 +++-
 drivers/gpu/drm/i915/i915_gem.c             |   3 +-
 drivers/gpu/drm/i915/i915_irq.c             |  80 +++++++++-
 drivers/gpu/drm/i915/i915_pci.c             |   1 +
 drivers/gpu/drm/i915/i915_reg.h             |   1 +
 drivers/gpu/drm/i915/intel_drv.h            |   3 -
 drivers/gpu/drm/i915/intel_engine_cs.c      |   5 +
 drivers/gpu/drm/i915/intel_guc.c            |  98 +++++++-----
 drivers/gpu/drm/i915/intel_guc.h            |   3 +-
 drivers/gpu/drm/i915/intel_guc_ads.c        | 161 +++++++++++++-------
 drivers/gpu/drm/i915/intel_guc_ads.h        |   1 +
 drivers/gpu/drm/i915/intel_guc_ct.c         |   2 +-
 drivers/gpu/drm/i915/intel_guc_fw.c         |  87 ++++++-----
 drivers/gpu/drm/i915/intel_guc_fwif.h       | 161 +++++++++-----------
 drivers/gpu/drm/i915/intel_guc_reg.h        |  25 +++
 drivers/gpu/drm/i915/intel_guc_submission.c |   4 -
 drivers/gpu/drm/i915/intel_huc.c            |  56 ++++++-
 drivers/gpu/drm/i915/intel_huc_fw.c         |  12 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h     |   2 +
 drivers/gpu/drm/i915/intel_uc.c             |  43 ++++--
 drivers/gpu/drm/i915/intel_uc_fw.c          |  20 +--
 21 files changed, 525 insertions(+), 271 deletions(-)

-- 
2.19.2

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[PATCH v2 01/22] drm/i915/guc: Change platform default GuC mode

[Michal Wajdeczko]

Today our most desired GuC configuration is to only enable HuC
if it is available and we really don't care about GuC submission.
Change platform default GuC mode to match our desire.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
---
 drivers/gpu/drm/i915/intel_uc.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 25b80ffe71ad..2a56e2363888 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -57,10 +57,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *i915)
 	struct intel_uc_fw *huc_fw = &i915->huc.fw;
 	int enable_guc = 0;
 
-	/* Default is to enable GuC/HuC if we know their firmwares */
-	if (intel_uc_fw_is_selected(guc_fw))
-		enable_guc |= ENABLE_GUC_SUBMISSION;
-	if (intel_uc_fw_is_selected(huc_fw))
+	/* Default is to use HuC if we know GuC and HuC firmwares */
+	if (intel_uc_fw_is_selected(guc_fw) && intel_uc_fw_is_selected(huc_fw))
 		enable_guc |= ENABLE_GUC_LOAD_HUC;
 
 	/* Any platform specific fine-tuning can be done here */
-- 
2.19.2

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Re: [PATCH v2 01/22] drm/i915/guc: Change platform default GuC mode

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> Today our most desired GuC configuration is to only enable HuC
> if it is available and we really don't care about GuC submission.
> Change platform default GuC mode to match our desire.
> 

AFAICS GuC loading is also broken between patch 4 and patch 9 (i.e. from 
new FW defs to completion of new FW support patches). Do we want to turn 
it off entirely and turn it back on at the end of the series or are we 
ok with just having it fail in the intermediate section of the series? 
The structures are updated together with the code that uses them so it 
should fail gracefully (or at least not panic).

Daniele

> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jeff Mcgee <jeff.mcgee@intel.com>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_uc.c | 6 ++----
>   1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 25b80ffe71ad..2a56e2363888 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -57,10 +57,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *i915)
>   	struct intel_uc_fw *huc_fw = &i915->huc.fw;
>   	int enable_guc = 0;
>   
> -	/* Default is to enable GuC/HuC if we know their firmwares */
> -	if (intel_uc_fw_is_selected(guc_fw))
> -		enable_guc |= ENABLE_GUC_SUBMISSION;
> -	if (intel_uc_fw_is_selected(huc_fw))
> +	/* Default is to use HuC if we know GuC and HuC firmwares */
> +	if (intel_uc_fw_is_selected(guc_fw) && intel_uc_fw_is_selected(huc_fw))
>   		enable_guc |= ENABLE_GUC_LOAD_HUC;
>   
>   	/* Any platform specific fine-tuning can be done here */
> 
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[PATCH v2 02/22] drm/i915/guc: Don't allow GuC submission

[Michal Wajdeczko]

Due to the upcoming changes to the GuC ABI interface, we must
disable GuC submission mode until final ABI will be available
on all GuC firmwares.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
---
 drivers/gpu/drm/i915/intel_uc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2a56e2363888..21310b917ccc 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -130,6 +130,13 @@ static void sanitize_options_early(struct drm_i915_private *i915)
 					  "no HuC firmware");
 	}
 
+	/* XXX: Verify GuC submission support */
+	if (intel_uc_is_using_guc_submission(i915)) {
+		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
+			 "enable_guc", i915_modparams.enable_guc,
+			 "submission not supported");
+	}
+
 	/* A negative value means "use platform/config default" */
 	if (i915_modparams.guc_log_level < 0)
 		i915_modparams.guc_log_level =
@@ -286,6 +293,10 @@ int intel_uc_init(struct drm_i915_private *i915)
 	if (!HAS_GUC(i915))
 		return -ENODEV;
 
+	/* XXX: GuC submission is unavailable for now */
+	if (USES_GUC_SUBMISSION(i915))
+		return -EIO;
+
 	ret = intel_guc_init(guc);
 	if (ret)
 		return ret;
-- 
2.19.2

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Re: [PATCH v2 02/22] drm/i915/guc: Don't allow GuC submission

[Martin Peres]

On 11/04/2019 11:44, Michal Wajdeczko wrote:
> Due to the upcoming changes to the GuC ABI interface, we must
> disable GuC submission mode until final ABI will be available
> on all GuC firmwares.

If I understand correctly, you are disabling command submission by
returning -EIO, which leads to the GPU being marked as wedged but KMS
still working.

If I read the code correctly, this is a weak NACK from me, as even
though Linux module parameters aren't considered stable unless marked
otherwise
(https://www.kernel.org/doc/Documentation/ABI/stable/sysfs-module),
users are already relying on enable_guc=3 and after updating their
kernel they will get a non-functional GPU. See
https://www.google.de/search?q=enable_guc%3D3

My strong recommendation is to fallback to execlist and warn in the logs
that GuC command submission is not considered stable and that i915
fellback to execlists, which are tested and known to work. You can then
drop patch 22.

If you plan on going through with this plan, the least you should do is
look at new bugs in mesa and i915 every day for the next year or so for
wedged GPUs on boot, as users will have forgotten they set the option
and will think this is a regression. Are you ready to make this commitment?

Martin


> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jeff Mcgee <jeff.mcgee@intel.com>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uc.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 2a56e2363888..21310b917ccc 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -130,6 +130,13 @@ static void sanitize_options_early(struct drm_i915_private *i915)
>  					  "no HuC firmware");
>  	}
>  
> +	/* XXX: Verify GuC submission support */
> +	if (intel_uc_is_using_guc_submission(i915)) {
> +		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> +			 "enable_guc", i915_modparams.enable_guc,
> +			 "submission not supported");
> +	}
> +
>  	/* A negative value means "use platform/config default" */
>  	if (i915_modparams.guc_log_level < 0)
>  		i915_modparams.guc_log_level =
> @@ -286,6 +293,10 @@ int intel_uc_init(struct drm_i915_private *i915)
>  	if (!HAS_GUC(i915))
>  		return -ENODEV;
>  
> +	/* XXX: GuC submission is unavailable for now */
> +	if (USES_GUC_SUBMISSION(i915))
> +		return -EIO;
> +
>  	ret = intel_guc_init(guc);
>  	if (ret)
>  		return ret;
> 
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[PATCH v2 03/22] drm/i915/guc: Simplify preparation of GuC parameter block

[Michal Wajdeczko]

Definition of the parameters block passed to GuC is about to change.
Slightly refactor code now to make upcoming patch smaller.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c | 38 +++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3aabfa2d9198..c0e8b359b23a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -333,19 +333,8 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
 	return flags;
 }
 
-/*
- * Initialise the GuC parameter block before starting the firmware
- * transfer. These parameters are read by the firmware on startup
- * and cannot be changed thereafter.
- */
-void intel_guc_init_params(struct intel_guc *guc)
+static void guc_prepare_params(struct intel_guc *guc, u32 *params)
 {
-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
-	u32 params[GUC_CTL_MAX_DWORDS];
-	int i;
-
-	memset(params, 0, sizeof(params));
-
 	/*
 	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 	 * second. This ARAR is calculated by:
@@ -360,9 +349,12 @@ void intel_guc_init_params(struct intel_guc *guc)
 	params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
 	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
 	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+}
 
-	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
-		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+static void guc_write_params(struct intel_guc *guc, const u32 *params)
+{
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	int i;
 
 	/*
 	 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
@@ -373,12 +365,28 @@ void intel_guc_init_params(struct intel_guc *guc)
 
 	I915_WRITE(SOFT_SCRATCH(0), 0);
 
-	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
+	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) {
+		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
 		I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
+	}
 
 	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
 }
 
+/*
+ * Initialise the GuC parameter block before starting the firmware
+ * transfer. These parameters are read by the firmware on startup
+ * and cannot be changed thereafter.
+ */
+void intel_guc_init_params(struct intel_guc *guc)
+{
+	u32 params[GUC_CTL_MAX_DWORDS];
+
+	memset(params, 0, sizeof(params));
+	guc_prepare_params(guc, params);
+	guc_write_params(guc, params);
+}
+
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
 		       u32 *response_buf, u32 response_buf_size)
 {
-- 
2.19.2

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Re: [PATCH v2 03/22] drm/i915/guc: Simplify preparation of GuC parameter block

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> Definition of the parameters block passed to GuC is about to change.
> Slightly refactor code now to make upcoming patch smaller.

I don't think this simplifies the upcoming patch (6/22) in any way, 
since most changes in that one are concentrated in the individual 
*_flags functions, which you're not touching here. The only related 
changes are the ones that the other patch does in guc_prepare_params, 
but those looks like they would be the same without splitting the 
function out.
Personally I would just drop this an keep intel_guc_init_params() as is, 
since it is clearer to follow IMO.

Daniele

> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Reviewed-by: John Spotswood <john.a.spotswood@intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc.c | 38 +++++++++++++++++++-------------
>   1 file changed, 23 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 3aabfa2d9198..c0e8b359b23a 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -333,19 +333,8 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
>   	return flags;
>   }
>   
> -/*
> - * Initialise the GuC parameter block before starting the firmware
> - * transfer. These parameters are read by the firmware on startup
> - * and cannot be changed thereafter.
> - */
> -void intel_guc_init_params(struct intel_guc *guc)
> +static void guc_prepare_params(struct intel_guc *guc, u32 *params)
>   {
> -	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	u32 params[GUC_CTL_MAX_DWORDS];
> -	int i;
> -
> -	memset(params, 0, sizeof(params));
> -
>   	/*
>   	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
>   	 * second. This ARAR is calculated by:
> @@ -360,9 +349,12 @@ void intel_guc_init_params(struct intel_guc *guc)
>   	params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
>   	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
>   	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> +}
>   
> -	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> -		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
> +static void guc_write_params(struct intel_guc *guc, const u32 *params)
> +{
> +	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	int i;
>   
>   	/*
>   	 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
> @@ -373,12 +365,28 @@ void intel_guc_init_params(struct intel_guc *guc)
>   
>   	I915_WRITE(SOFT_SCRATCH(0), 0);
>   
> -	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> +	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) {
> +		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
>   		I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
> +	}
>   
>   	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
>   }
>   
> +/*
> + * Initialise the GuC parameter block before starting the firmware
> + * transfer. These parameters are read by the firmware on startup
> + * and cannot be changed thereafter.
> + */
> +void intel_guc_init_params(struct intel_guc *guc)
> +{
> +	u32 params[GUC_CTL_MAX_DWORDS];
> +
> +	memset(params, 0, sizeof(params));
> +	guc_prepare_params(guc, params);
> +	guc_write_params(guc, params);
> +}
> +
>   int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
>   		       u32 *response_buf, u32 response_buf_size)
>   {
> 
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[PATCH v2 04/22] drm/i915/guc: Update GuC firmware versions and names

[Michal Wajdeczko]

GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:

    <platform>_guc_<major>.<minor>.<patch>.bin

While here, reorder platform checks and start from the latest.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fw.c | 76 ++++++++++++++++-------------
 1 file changed, 42 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index 792a551450c7..c937a648c2a1 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -30,53 +30,61 @@
 #include "intel_guc_fw.h"
 #include "i915_drv.h"
 
-#define SKL_FW_MAJOR 9
-#define SKL_FW_MINOR 33
-
-#define BXT_FW_MAJOR 9
-#define BXT_FW_MINOR 29
-
-#define KBL_FW_MAJOR 9
-#define KBL_FW_MINOR 39
-
-#define GUC_FW_PATH(platform, major, minor) \
-       "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
-
-#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
-MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
-
-#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
-MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
-
-#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
-MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define __MAKE_GUC_FW_PATH(KEY) \
+	"i915/" \
+	__stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
+	__stringify(KEY##_GUC_FW_MAJOR) "." \
+	__stringify(KEY##_GUC_FW_MINOR) "." \
+	__stringify(KEY##_GUC_FW_PATCH) ".bin"
+
+#define SKL_GUC_FW_PREFIX skl
+#define SKL_GUC_FW_MAJOR 32
+#define SKL_GUC_FW_MINOR 0
+#define SKL_GUC_FW_PATCH 3
+#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
+
+#define BXT_GUC_FW_PREFIX bxt
+#define BXT_GUC_FW_MAJOR 32
+#define BXT_GUC_FW_MINOR 0
+#define BXT_GUC_FW_PATCH 3
+#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
+
+#define KBL_GUC_FW_PREFIX kbl
+#define KBL_GUC_FW_MAJOR 32
+#define KBL_GUC_FW_MINOR 0
+#define KBL_GUC_FW_PATCH 3
+#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
+
+MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
 
 static void guc_fw_select(struct intel_uc_fw *guc_fw)
 {
 	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct drm_i915_private *i915 = guc_to_i915(guc);
 
 	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
 
-	if (!HAS_GUC(dev_priv))
+	if (!HAS_GUC(i915))
 		return;
 
 	if (i915_modparams.guc_firmware_path) {
 		guc_fw->path = i915_modparams.guc_firmware_path;
 		guc_fw->major_ver_wanted = 0;
 		guc_fw->minor_ver_wanted = 0;
-	} else if (IS_SKYLAKE(dev_priv)) {
-		guc_fw->path = I915_SKL_GUC_UCODE;
-		guc_fw->major_ver_wanted = SKL_FW_MAJOR;
-		guc_fw->minor_ver_wanted = SKL_FW_MINOR;
-	} else if (IS_BROXTON(dev_priv)) {
-		guc_fw->path = I915_BXT_GUC_UCODE;
-		guc_fw->major_ver_wanted = BXT_FW_MAJOR;
-		guc_fw->minor_ver_wanted = BXT_FW_MINOR;
-	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
-		guc_fw->path = I915_KBL_GUC_UCODE;
-		guc_fw->major_ver_wanted = KBL_FW_MAJOR;
-		guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+	} else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+		guc_fw->path = KBL_GUC_FIRMWARE_PATH;
+		guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
+		guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
+	} else if (IS_BROXTON(i915)) {
+		guc_fw->path = BXT_GUC_FIRMWARE_PATH;
+		guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
+		guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
+	} else if (IS_SKYLAKE(i915)) {
+		guc_fw->path = SKL_GUC_FIRMWARE_PATH;
+		guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
+		guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
 	}
 }
 
-- 
2.19.2

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Re: [PATCH v2 04/22] drm/i915/guc: Update GuC firmware versions and names

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> GuC firmware changed its release version numbering schema and now it
> also includes patch version. Update our GuC firmware path definitions
> to match new pattern:
> 
>      <platform>_guc_<major>.<minor>.<patch>.bin
> 
> While here, reorder platform checks and start from the latest.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jeff Mcgee <jeff.mcgee@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_fw.c | 76 ++++++++++++++++-------------
>   1 file changed, 42 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> index 792a551450c7..c937a648c2a1 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -30,53 +30,61 @@
>   #include "intel_guc_fw.h"
>   #include "i915_drv.h"
>   
> -#define SKL_FW_MAJOR 9
> -#define SKL_FW_MINOR 33
> -
> -#define BXT_FW_MAJOR 9
> -#define BXT_FW_MINOR 29
> -
> -#define KBL_FW_MAJOR 9
> -#define KBL_FW_MINOR 39
> -
> -#define GUC_FW_PATH(platform, major, minor) \
> -       "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
> -
> -#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
> -MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
> -
> -#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
> -MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
> -
> -#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
> -MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
> +#define __MAKE_GUC_FW_PATH(KEY) \
> +	"i915/" \
> +	__stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
> +	__stringify(KEY##_GUC_FW_MAJOR) "." \
> +	__stringify(KEY##_GUC_FW_MINOR) "." \
> +	__stringify(KEY##_GUC_FW_PATCH) ".bin"
> +
> +#define SKL_GUC_FW_PREFIX skl
> +#define SKL_GUC_FW_MAJOR 32
> +#define SKL_GUC_FW_MINOR 0
> +#define SKL_GUC_FW_PATCH 3
> +#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
> +
> +#define BXT_GUC_FW_PREFIX bxt
> +#define BXT_GUC_FW_MAJOR 32
> +#define BXT_GUC_FW_MINOR 0
> +#define BXT_GUC_FW_PATCH 3
> +#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
> +
> +#define KBL_GUC_FW_PREFIX kbl
> +#define KBL_GUC_FW_MAJOR 32
> +#define KBL_GUC_FW_MINOR 0
> +#define KBL_GUC_FW_PATCH 3
> +#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
> +
> +MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
> +MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
> +MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);

I would put these below the respective platform defines to keep 
everything for a single platform in one block. Not a blocking issue though.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

>   
>   static void guc_fw_select(struct intel_uc_fw *guc_fw)
>   {
>   	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
> -	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
>   
>   	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
>   
> -	if (!HAS_GUC(dev_priv))
> +	if (!HAS_GUC(i915))
>   		return;
>   
>   	if (i915_modparams.guc_firmware_path) {
>   		guc_fw->path = i915_modparams.guc_firmware_path;
>   		guc_fw->major_ver_wanted = 0;
>   		guc_fw->minor_ver_wanted = 0;
> -	} else if (IS_SKYLAKE(dev_priv)) {
> -		guc_fw->path = I915_SKL_GUC_UCODE;
> -		guc_fw->major_ver_wanted = SKL_FW_MAJOR;
> -		guc_fw->minor_ver_wanted = SKL_FW_MINOR;
> -	} else if (IS_BROXTON(dev_priv)) {
> -		guc_fw->path = I915_BXT_GUC_UCODE;
> -		guc_fw->major_ver_wanted = BXT_FW_MAJOR;
> -		guc_fw->minor_ver_wanted = BXT_FW_MINOR;
> -	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
> -		guc_fw->path = I915_KBL_GUC_UCODE;
> -		guc_fw->major_ver_wanted = KBL_FW_MAJOR;
> -		guc_fw->minor_ver_wanted = KBL_FW_MINOR;
> +	} else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
> +		guc_fw->path = KBL_GUC_FIRMWARE_PATH;
> +		guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
> +		guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
> +	} else if (IS_BROXTON(i915)) {
> +		guc_fw->path = BXT_GUC_FIRMWARE_PATH;
> +		guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
> +		guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
> +	} else if (IS_SKYLAKE(i915)) {
> +		guc_fw->path = SKL_GUC_FIRMWARE_PATH;
> +		guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
> +		guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
>   	}
>   }
>   
> 
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[PATCH v2 05/22] drm/i915/guc: Update GuC firmware CSS header

[Michal Wajdeczko]

There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h | 23 ++++++++---------------
 drivers/gpu/drm/i915/intel_uc_fw.c    | 20 ++++++++++----------
 2 files changed, 18 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index b2f5148f4f17..1cb4fad2d539 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -168,11 +168,7 @@
  *    in fw. So driver will load a truncated firmware in this case.
  *
  * HuC firmware layout is same as GuC firmware.
- *
- * HuC firmware css header is different. However, the only difference is where
- * the version information is saved. The uc_css_header is unified to support
- * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
- * uc_css_header.guc_sw_version for GuC.
+ * Only HuC version information is saved in a different way.
  */
 
 struct uc_css_header {
@@ -206,16 +202,13 @@ struct uc_css_header {
 
 	char username[8];
 	char buildnumber[12];
-	union {
-		struct {
-			u32 branch_client_version;
-			u32 sw_version;
-	} guc;
-		struct {
-			u32 sw_version;
-			u32 reserved;
-	} huc;
-	};
+	u32 sw_version;
+#define CSS_SW_VERSION_GUC_MAJOR	(0xFF << 16)
+#define CSS_SW_VERSION_GUC_MINOR	(0xFF << 8)
+#define CSS_SW_VERSION_GUC_PATCH	(0xFF << 0)
+#define CSS_SW_VERSION_HUC_MAJOR	(0xFFFF << 16)
+#define CSS_SW_VERSION_HUC_MINOR	(0xFFFF << 0)
+	u32 sw_reserved;
 	u32 prod_preprod_fw;
 	u32 reserved[12];
 	u32 header_info;
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index becf05ebae4d..957c1feb30d3 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -22,6 +22,7 @@
  *
  */
 
+#include <linux/bitfield.h>
 #include <linux/firmware.h>
 #include <drm/drm_print.h>
 
@@ -119,21 +120,20 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 		goto fail;
 	}
 
-	/*
-	 * The GuC firmware image has the version number embedded at a
-	 * well-known offset within the firmware blob; note that major / minor
-	 * version are TWO bytes each (i.e. u16), although all pointers and
-	 * offsets are defined in terms of bytes (u8).
-	 */
+	/* Get version numbers from the CSS header */
 	switch (uc_fw->type) {
 	case INTEL_UC_FW_TYPE_GUC:
-		uc_fw->major_ver_found = css->guc.sw_version >> 16;
-		uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
+		uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MAJOR,
+						   css->sw_version);
+		uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MINOR,
+						   css->sw_version);
 		break;
 
 	case INTEL_UC_FW_TYPE_HUC:
-		uc_fw->major_ver_found = css->huc.sw_version >> 16;
-		uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
+		uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MAJOR,
+						   css->sw_version);
+		uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MINOR,
+						   css->sw_version);
 		break;
 
 	default:
-- 
2.19.2

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Re: [PATCH v2 05/22] drm/i915/guc: Update GuC firmware CSS header

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> There are few minor changes in the CSS header related to the version
> numbering in new GuC firmwares. Update our definition and start using
> common tools for extracting bitfields.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Jeff Mcgee <jeff.mcgee@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_fwif.h | 23 ++++++++---------------
>   drivers/gpu/drm/i915/intel_uc_fw.c    | 20 ++++++++++----------
>   2 files changed, 18 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index b2f5148f4f17..1cb4fad2d539 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -168,11 +168,7 @@
>    *    in fw. So driver will load a truncated firmware in this case.
>    *
>    * HuC firmware layout is same as GuC firmware.
> - *
> - * HuC firmware css header is different. However, the only difference is where
> - * the version information is saved. The uc_css_header is unified to support
> - * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
> - * uc_css_header.guc_sw_version for GuC.
> + * Only HuC version information is saved in a different way.
>    */
>   
>   struct uc_css_header {
> @@ -206,16 +202,13 @@ struct uc_css_header {
>   
>   	char username[8];
>   	char buildnumber[12];
> -	union {
> -		struct {
> -			u32 branch_client_version;
> -			u32 sw_version;
> -	} guc;
> -		struct {
> -			u32 sw_version;
> -			u32 reserved;
> -	} huc;
> -	};
> +	u32 sw_version;
> +#define CSS_SW_VERSION_GUC_MAJOR	(0xFF << 16)
> +#define CSS_SW_VERSION_GUC_MINOR	(0xFF << 8)
> +#define CSS_SW_VERSION_GUC_PATCH	(0xFF << 0)
> +#define CSS_SW_VERSION_HUC_MAJOR	(0xFFFF << 16)
> +#define CSS_SW_VERSION_HUC_MINOR	(0xFFFF << 0)
> +	u32 sw_reserved;
>   	u32 prod_preprod_fw;
>   	u32 reserved[12];
>   	u32 header_info;

This doesn't match guc FW headers. Over there I see

	char username[8];
	char buildnumber[12];
	u32 sw_version;
	u32 reserved[13];
	u32 private_data_size;
	u32 header_info;

While HuC headers (hoping I got the right ones since it was my first 
time looking for the HuC CSS) have:

	char username[8];
	char buildnumber[12];
	u32 sw_version;
	u32 reserved[14];
	u32 header_info;

Patch LGTM apart from this.
Daniele

> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
> index becf05ebae4d..957c1feb30d3 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
> @@ -22,6 +22,7 @@
>    *
>    */
>   
> +#include <linux/bitfield.h>
>   #include <linux/firmware.h>
>   #include <drm/drm_print.h>
>   
> @@ -119,21 +120,20 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>   		goto fail;
>   	}
>   
> -	/*
> -	 * The GuC firmware image has the version number embedded at a
> -	 * well-known offset within the firmware blob; note that major / minor
> -	 * version are TWO bytes each (i.e. u16), although all pointers and
> -	 * offsets are defined in terms of bytes (u8).
> -	 */
> +	/* Get version numbers from the CSS header */
>   	switch (uc_fw->type) {
>   	case INTEL_UC_FW_TYPE_GUC:
> -		uc_fw->major_ver_found = css->guc.sw_version >> 16;
> -		uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
> +		uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MAJOR,
> +						   css->sw_version);
> +		uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MINOR,
> +						   css->sw_version);
>   		break;
>   
>   	case INTEL_UC_FW_TYPE_HUC:
> -		uc_fw->major_ver_found = css->huc.sw_version >> 16;
> -		uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
> +		uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MAJOR,
> +						   css->sw_version);
> +		uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MINOR,
> +						   css->sw_version);
>   		break;
>   
>   	default:
> 
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[PATCH v2 06/22] drm/i915/guc: Update GuC boot parameters

[Michal Wajdeczko]

New GuC firmwares require updated boot parameters.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c      | 36 +++++++++----------------
 drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++++++--------------------
 2 files changed, 22 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index c0e8b359b23a..483c7019f817 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -243,14 +243,7 @@ void intel_guc_fini(struct intel_guc *guc)
 static u32 guc_ctl_debug_flags(struct intel_guc *guc)
 {
 	u32 level = intel_guc_log_get_level(&guc->log);
-	u32 flags;
-	u32 ads;
-
-	ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
-	flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
-
-	if (!GUC_LOG_LEVEL_IS_ENABLED(level))
-		flags |= GUC_LOG_DEFAULT_DISABLED;
+	u32 flags = 0;
 
 	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
 		flags |= GUC_LOG_DISABLED;
@@ -265,11 +258,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
 {
 	u32 flags = 0;
 
-	flags |=  GUC_CTL_VCS2_ENABLED;
-
-	if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
-		flags |= GUC_CTL_KERNEL_SUBMISSIONS;
-	else
+	if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
 		flags |= GUC_CTL_DISABLE_SCHEDULER;
 
 	return flags;
@@ -333,22 +322,21 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
 	return flags;
 }
 
-static void guc_prepare_params(struct intel_guc *guc, u32 *params)
+static u32 guc_ctl_ads_flags(struct intel_guc *guc)
 {
-	/*
-	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
-	 * second. This ARAR is calculated by:
-	 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
-	 */
-	params[GUC_CTL_ARAT_HIGH] = 0;
-	params[GUC_CTL_ARAT_LOW] = 100000000;
+	u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
+	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
 
-	params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
+	return flags;
+}
 
+static void guc_prepare_params(struct intel_guc *guc, u32 *params)
+{
+	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
 	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
-	params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
 	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
-	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
 }
 
 static void guc_write_params(struct intel_guc *guc, const u32 *params)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 1cb4fad2d539..64b56da9775c 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -73,44 +73,28 @@
 #define GUC_STAGE_DESC_ATTR_PCH		BIT(6)
 #define GUC_STAGE_DESC_ATTR_TERMINATED	BIT(7)
 
-/* The guc control data is 10 DWORDs */
+/* New GuC control data */
 #define GUC_CTL_CTXINFO			0
 #define   GUC_CTL_CTXNUM_IN16_SHIFT	0
 #define   GUC_CTL_BASE_ADDR_SHIFT	12
 
-#define GUC_CTL_ARAT_HIGH		1
-#define GUC_CTL_ARAT_LOW		2
-
-#define GUC_CTL_DEVICE_INFO		3
-
-#define GUC_CTL_LOG_PARAMS		4
+#define GUC_CTL_LOG_PARAMS		1
 #define   GUC_LOG_VALID			(1 << 0)
 #define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
 #define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
 #define   GUC_LOG_CRASH_SHIFT		4
-#define   GUC_LOG_CRASH_MASK		(0x1 << GUC_LOG_CRASH_SHIFT)
+#define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
 #define   GUC_LOG_DPC_SHIFT		6
 #define   GUC_LOG_DPC_MASK	        (0x7 << GUC_LOG_DPC_SHIFT)
 #define   GUC_LOG_ISR_SHIFT		9
 #define   GUC_LOG_ISR_MASK	        (0x7 << GUC_LOG_ISR_SHIFT)
 #define   GUC_LOG_BUF_ADDR_SHIFT	12
 
-#define GUC_CTL_PAGE_FAULT_CONTROL	5
-
-#define GUC_CTL_WA			6
-#define   GUC_CTL_WA_UK_BY_DRIVER	(1 << 3)
-
-#define GUC_CTL_FEATURE			7
-#define   GUC_CTL_VCS2_ENABLED		(1 << 0)
-#define   GUC_CTL_KERNEL_SUBMISSIONS	(1 << 1)
-#define   GUC_CTL_FEATURE2		(1 << 2)
-#define   GUC_CTL_POWER_GATING		(1 << 3)
-#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 4)
-#define   GUC_CTL_PREEMPTION_LOG	(1 << 5)
-#define   GUC_CTL_ENABLE_SLPC		(1 << 7)
-#define   GUC_CTL_RESET_ON_PREMPT_FAILURE	(1 << 8)
+#define GUC_CTL_WA			2
+#define GUC_CTL_FEATURE			3
+#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 14)
 
-#define GUC_CTL_DEBUG			8
+#define GUC_CTL_DEBUG			4
 #define   GUC_LOG_VERBOSITY_SHIFT	0
 #define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
 #define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
@@ -123,13 +107,10 @@
 #define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
 #define   GUC_LOG_DISABLED		(1 << 6)
 #define   GUC_PROFILE_ENABLED		(1 << 7)
-#define   GUC_WQ_TRACK_ENABLED		(1 << 8)
-#define   GUC_ADS_ENABLED		(1 << 9)
-#define   GUC_LOG_DEFAULT_DISABLED	(1 << 10)
-#define   GUC_ADS_ADDR_SHIFT		11
-#define   GUC_ADS_ADDR_MASK		0xfffff800
 
-#define GUC_CTL_RSRVD			9
+#define GUC_CTL_ADS			5
+#define   GUC_ADS_ADDR_SHIFT		1
+#define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
 
 #define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */
 
-- 
2.19.2

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Re: [PATCH v2 06/22] drm/i915/guc: Update GuC boot parameters

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> New GuC firmwares require updated boot parameters.
> 

Matches the FW headers.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc.c      | 36 +++++++++----------------
>   drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++++++--------------------
>   2 files changed, 22 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index c0e8b359b23a..483c7019f817 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -243,14 +243,7 @@ void intel_guc_fini(struct intel_guc *guc)
>   static u32 guc_ctl_debug_flags(struct intel_guc *guc)
>   {
>   	u32 level = intel_guc_log_get_level(&guc->log);
> -	u32 flags;
> -	u32 ads;
> -
> -	ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
> -	flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
> -
> -	if (!GUC_LOG_LEVEL_IS_ENABLED(level))
> -		flags |= GUC_LOG_DEFAULT_DISABLED;
> +	u32 flags = 0;
>   
>   	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
>   		flags |= GUC_LOG_DISABLED;
> @@ -265,11 +258,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
>   {
>   	u32 flags = 0;
>   
> -	flags |=  GUC_CTL_VCS2_ENABLED;
> -
> -	if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
> -		flags |= GUC_CTL_KERNEL_SUBMISSIONS;
> -	else
> +	if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
>   		flags |= GUC_CTL_DISABLE_SCHEDULER;
>   
>   	return flags;
> @@ -333,22 +322,21 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
>   	return flags;
>   }
>   
> -static void guc_prepare_params(struct intel_guc *guc, u32 *params)
> +static u32 guc_ctl_ads_flags(struct intel_guc *guc)
>   {
> -	/*
> -	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
> -	 * second. This ARAR is calculated by:
> -	 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
> -	 */
> -	params[GUC_CTL_ARAT_HIGH] = 0;
> -	params[GUC_CTL_ARAT_LOW] = 100000000;
> +	u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
> +	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
>   
> -	params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
> +	return flags;
> +}
>   
> +static void guc_prepare_params(struct intel_guc *guc, u32 *params)
> +{
> +	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> +	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
>   	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
> -	params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
>   	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
> -	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> +	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
>   }
>   
>   static void guc_write_params(struct intel_guc *guc, const u32 *params)
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 1cb4fad2d539..64b56da9775c 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -73,44 +73,28 @@
>   #define GUC_STAGE_DESC_ATTR_PCH		BIT(6)
>   #define GUC_STAGE_DESC_ATTR_TERMINATED	BIT(7)
>   
> -/* The guc control data is 10 DWORDs */
> +/* New GuC control data */
>   #define GUC_CTL_CTXINFO			0
>   #define   GUC_CTL_CTXNUM_IN16_SHIFT	0
>   #define   GUC_CTL_BASE_ADDR_SHIFT	12
>   
> -#define GUC_CTL_ARAT_HIGH		1
> -#define GUC_CTL_ARAT_LOW		2
> -
> -#define GUC_CTL_DEVICE_INFO		3
> -
> -#define GUC_CTL_LOG_PARAMS		4
> +#define GUC_CTL_LOG_PARAMS		1
>   #define   GUC_LOG_VALID			(1 << 0)
>   #define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
>   #define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
>   #define   GUC_LOG_CRASH_SHIFT		4
> -#define   GUC_LOG_CRASH_MASK		(0x1 << GUC_LOG_CRASH_SHIFT)
> +#define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
>   #define   GUC_LOG_DPC_SHIFT		6
>   #define   GUC_LOG_DPC_MASK	        (0x7 << GUC_LOG_DPC_SHIFT)
>   #define   GUC_LOG_ISR_SHIFT		9
>   #define   GUC_LOG_ISR_MASK	        (0x7 << GUC_LOG_ISR_SHIFT)
>   #define   GUC_LOG_BUF_ADDR_SHIFT	12
>   
> -#define GUC_CTL_PAGE_FAULT_CONTROL	5
> -
> -#define GUC_CTL_WA			6
> -#define   GUC_CTL_WA_UK_BY_DRIVER	(1 << 3)
> -
> -#define GUC_CTL_FEATURE			7
> -#define   GUC_CTL_VCS2_ENABLED		(1 << 0)
> -#define   GUC_CTL_KERNEL_SUBMISSIONS	(1 << 1)
> -#define   GUC_CTL_FEATURE2		(1 << 2)
> -#define   GUC_CTL_POWER_GATING		(1 << 3)
> -#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 4)
> -#define   GUC_CTL_PREEMPTION_LOG	(1 << 5)
> -#define   GUC_CTL_ENABLE_SLPC		(1 << 7)
> -#define   GUC_CTL_RESET_ON_PREMPT_FAILURE	(1 << 8)
> +#define GUC_CTL_WA			2
> +#define GUC_CTL_FEATURE			3
> +#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 14)
>   
> -#define GUC_CTL_DEBUG			8
> +#define GUC_CTL_DEBUG			4
>   #define   GUC_LOG_VERBOSITY_SHIFT	0
>   #define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
>   #define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
> @@ -123,13 +107,10 @@
>   #define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
>   #define   GUC_LOG_DISABLED		(1 << 6)
>   #define   GUC_PROFILE_ENABLED		(1 << 7)
> -#define   GUC_WQ_TRACK_ENABLED		(1 << 8)
> -#define   GUC_ADS_ENABLED		(1 << 9)
> -#define   GUC_LOG_DEFAULT_DISABLED	(1 << 10)
> -#define   GUC_ADS_ADDR_SHIFT		11
> -#define   GUC_ADS_ADDR_MASK		0xfffff800
>   
> -#define GUC_CTL_RSRVD			9
> +#define GUC_CTL_ADS			5
> +#define   GUC_ADS_ADDR_SHIFT		1
> +#define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
>   
>   #define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */
>   
> 
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[PATCH v2 07/22] drm/i915/guc: Update GuC sleep status values

[Michal Wajdeczko]

New GuC firmwares use updated sleep status definitions.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 64b56da9775c..25d57c819e3f 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -648,9 +648,9 @@ enum intel_guc_report_status {
 };
 
 enum intel_guc_sleep_state_status {
-	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
-	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
-	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
+	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
+	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
+	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
 };
 
-- 
2.19.2

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Re: [PATCH v2 07/22] drm/i915/guc: Update GuC sleep status values

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> New GuC firmwares use updated sleep status definitions.
> 

There is also no need to poll on resume anymore. We're not failing on it 
in CI because the wait timeout comes out as a debug message and the guc 
is obviously still fine and responsive since we waited for nothing.

I think I had sent you a patch for this already, let me see if I can 
find it again and send it in reply to this one (if I do find it, I'm 
going to re-compile test it only).

Daniele

> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 64b56da9775c..25d57c819e3f 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -648,9 +648,9 @@ enum intel_guc_report_status {
>   };
>   
>   enum intel_guc_sleep_state_status {
> -	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
> -	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
> -	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
> +	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
> +	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
> +	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
>   #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
>   };
>   
> 
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Re: [PATCH v2 07/22] drm/i915/guc: Update GuC sleep status values

[Daniele Ceraolo Spurio]

On 4/12/19 5:06 PM, Daniele Ceraolo Spurio wrote:
> 
> 
> On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
>> New GuC firmwares use updated sleep status definitions.
>>
> 
> There is also no need to poll on resume anymore. We're not failing on it 
> in CI because the wait timeout comes out as a debug message and the guc 
> is obviously still fine and responsive since we waited for nothing.
> 
> I think I had sent you a patch for this already, let me see if I can 
> find it again and send it in reply to this one (if I do find it, I'm 
> going to re-compile test it only).
> 
> Daniele
> 

One more thing: John S had mentioned that the guc suspend/resume 
protocol mainly handles submission-related data, so it should be 
possible to skip it when in huc-only mode. Not something that needs to 
be included here, but a possible follow up optimization.

John, can you confirm this?

Thanks,
Daniele

>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: John Spotswood <john.a.spotswood@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index 64b56da9775c..25d57c819e3f 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -648,9 +648,9 @@ enum intel_guc_report_status {
>>   };
>>   enum intel_guc_sleep_state_status {
>> -    INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
>> -    INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
>> -    INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
>> +    INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
>> +    INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
>> +    INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
>>   #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
>>   };
>>
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Re: [PATCH v2 07/22] drm/i915/guc: Update GuC sleep status values

[John Spotswood]

On Fri, 2019-04-12 at 17:24 -0700, Ceraolo Spurio, Daniele wrote:
> 
> On 4/12/19 5:06 PM, Daniele Ceraolo Spurio wrote:
> > 
> > 
> > 
> > On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> > > 
> > > New GuC firmwares use updated sleep status definitions.
> > > 
> > There is also no need to poll on resume anymore. We're not failing
> > on it 
> > in CI because the wait timeout comes out as a debug message and the
> > guc 
> > is obviously still fine and responsive since we waited for nothing.
> > 
> > I think I had sent you a patch for this already, let me see if I
> > can 
> > find it again and send it in reply to this one (if I do find it,
> > I'm 
> > going to re-compile test it only).
> > 
> > Daniele
> > 
> One more thing: John S had mentioned that the guc suspend/resume 
> protocol mainly handles submission-related data, so it should be 
> possible to skip it when in huc-only mode. Not something that needs
> to 
> be included here, but a possible follow up optimization.
> 
> John, can you confirm this?
> 
> Thanks,
> Daniele
> 

If running with HuC authentication only, the GuC will have nothing to
do once authentication is completed, so GuC will go to sleep on its
own.  The driver can remove those suspend/resume calls if GuC
submission is disabled.

John


> > 
> > > 
> > > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: John Spotswood <john.a.spotswood@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++---
> > >   1 file changed, 3 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
> > > b/drivers/gpu/drm/i915/intel_guc_fwif.h
> > > index 64b56da9775c..25d57c819e3f 100644
> > > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> > > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> > > @@ -648,9 +648,9 @@ enum intel_guc_report_status {
> > >   };
> > >   enum intel_guc_sleep_state_status {
> > > -    INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
> > > -    INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
> > > -    INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
> > > +    INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
> > > +    INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
> > > +    INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
> > >   #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
> > >   };
> > > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH v2] drm/i915/guc: updated suspend/resume protocol

[Daniele Ceraolo Spurio]

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

New GuC firmwares use updated sleep status definitions.
The polling on scratch register 14 is also now required only on suspend
and there is no need to provide the shared page.

v2: include changes for polling and shared page

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c      | 50 +++++++++++----------------
 drivers/gpu/drm/i915/intel_guc_fwif.h |  6 ++--
 2 files changed, 24 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 483c7019f817..cf943eb7537c 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -539,25 +539,33 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
 	return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
 
-/*
- * The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC FW and
- * then return, so waiting on the H2G is not enough to guarantee GuC is done.
- * When all the processing is done, GuC writes INTEL_GUC_SLEEP_STATE_SUCCESS to
- * scratch register 14, so we can poll on that. Note that GuC does not ensure
- * that the value in the register is different from
- * INTEL_GUC_SLEEP_STATE_SUCCESS while the action is in progress so we need to
- * take care of that ourselves as well.
+/**
+ * intel_guc_suspend() - notify GuC entering suspend state
+ * @guc:	the guc
  */
-static int guc_sleep_state_action(struct intel_guc *guc,
-				  const u32 *action, u32 len)
+int intel_guc_suspend(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	int ret;
 	u32 status;
+	u32 action[] = {
+		INTEL_GUC_ACTION_ENTER_S_STATE,
+		GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
+	};
+
+	/*
+	 * The ENTER_S_STATE action queues the save/restore operation in GuC FW
+	 * and then returns, so waiting on the H2G is not enough to guarantee
+	 * GuC is done. When all the processing is done, GuC writes
+	 * INTEL_GUC_SLEEP_STATE_SUCCESS to scratch register 14, so we can poll
+	 * on that. Note that GuC does not ensure that the value in the register
+	 * is different from INTEL_GUC_SLEEP_STATE_SUCCESS while the action is
+	 * in progress so we need to take care of that ourselves as well.
+	 */
 
 	I915_WRITE(SOFT_SCRATCH(14), INTEL_GUC_SLEEP_STATE_INVALID_MASK);
 
-	ret = intel_guc_send(guc, action, len);
+	ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
 	if (ret)
 		return ret;
 
@@ -577,21 +585,6 @@ static int guc_sleep_state_action(struct intel_guc *guc,
 	return 0;
 }
 
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @guc:	the guc
- */
-int intel_guc_suspend(struct intel_guc *guc)
-{
-	u32 data[] = {
-		INTEL_GUC_ACTION_ENTER_S_STATE,
-		GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
-		intel_guc_ggtt_offset(guc, guc->shared_data)
-	};
-
-	return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
-}
-
 /**
  * intel_guc_reset_engine() - ask GuC to reset an engine
  * @guc:	intel_guc structure
@@ -621,13 +614,12 @@ int intel_guc_reset_engine(struct intel_guc *guc,
  */
 int intel_guc_resume(struct intel_guc *guc)
 {
-	u32 data[] = {
+	u32 action[] = {
 		INTEL_GUC_ACTION_EXIT_S_STATE,
 		GUC_POWER_D0,
-		intel_guc_ggtt_offset(guc, guc->shared_data)
 	};
 
-	return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 64b56da9775c..25d57c819e3f 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -648,9 +648,9 @@ enum intel_guc_report_status {
 };
 
 enum intel_guc_sleep_state_status {
-	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
-	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
-	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
+	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
+	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
+	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
 };
 
-- 
2.20.1

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Re: [PATCH v2] drm/i915/guc: updated suspend/resume protocol

[John Spotswood]

On Fri, 2019-04-12 at 17:20 -0700, Ceraolo Spurio, Daniele wrote:
> From: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> New GuC firmwares use updated sleep status definitions.
> The polling on scratch register 14 is also now required only on
> suspend
> and there is no need to provide the shared page.
> 
> v2: include changes for polling and shared page
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.co
> m>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>

Reviewed-by: John Spotswood <john.a.spotswood@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_guc.c      | 50 +++++++++++------------
> ----
>  drivers/gpu/drm/i915/intel_guc_fwif.h |  6 ++--
>  2 files changed, 24 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> index 483c7019f817..cf943eb7537c 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -539,25 +539,33 @@ int intel_guc_auth_huc(struct intel_guc *guc,
> u32 rsa_offset)
>  	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>  }
>  
> -/*
> - * The ENTER/EXIT_S_STATE actions queue the save/restore operation
> in GuC FW and
> - * then return, so waiting on the H2G is not enough to guarantee GuC
> is done.
> - * When all the processing is done, GuC writes
> INTEL_GUC_SLEEP_STATE_SUCCESS to
> - * scratch register 14, so we can poll on that. Note that GuC does
> not ensure
> - * that the value in the register is different from
> - * INTEL_GUC_SLEEP_STATE_SUCCESS while the action is in progress so
> we need to
> - * take care of that ourselves as well.
> +/**
> + * intel_guc_suspend() - notify GuC entering suspend state
> + * @guc:	the guc
>   */
> -static int guc_sleep_state_action(struct intel_guc *guc,
> -				  const u32 *action, u32 len)
> +int intel_guc_suspend(struct intel_guc *guc)
>  {
>  	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>  	int ret;
>  	u32 status;
> +	u32 action[] = {
> +		INTEL_GUC_ACTION_ENTER_S_STATE,
> +		GUC_POWER_D1, /* any value greater than GUC_POWER_D0
> */
> +	};
> +
> +	/*
> +	 * The ENTER_S_STATE action queues the save/restore
> operation in GuC FW
> +	 * and then returns, so waiting on the H2G is not enough to
> guarantee
> +	 * GuC is done. When all the processing is done, GuC writes
> +	 * INTEL_GUC_SLEEP_STATE_SUCCESS to scratch register 14, so
> we can poll
> +	 * on that. Note that GuC does not ensure that the value in
> the register
> +	 * is different from INTEL_GUC_SLEEP_STATE_SUCCESS while the
> action is
> +	 * in progress so we need to take care of that ourselves as
> well.
> +	 */
>  
>  	I915_WRITE(SOFT_SCRATCH(14),
> INTEL_GUC_SLEEP_STATE_INVALID_MASK);
>  
> -	ret = intel_guc_send(guc, action, len);
> +	ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
>  	if (ret)
>  		return ret;
>  
> @@ -577,21 +585,6 @@ static int guc_sleep_state_action(struct
> intel_guc *guc,
>  	return 0;
>  }
>  
> -/**
> - * intel_guc_suspend() - notify GuC entering suspend state
> - * @guc:	the guc
> - */
> -int intel_guc_suspend(struct intel_guc *guc)
> -{
> -	u32 data[] = {
> -		INTEL_GUC_ACTION_ENTER_S_STATE,
> -		GUC_POWER_D1, /* any value greater than GUC_POWER_D0
> */
> -		intel_guc_ggtt_offset(guc, guc->shared_data)
> -	};
> -
> -	return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
> -}
> -
>  /**
>   * intel_guc_reset_engine() - ask GuC to reset an engine
>   * @guc:	intel_guc structure
> @@ -621,13 +614,12 @@ int intel_guc_reset_engine(struct intel_guc
> *guc,
>   */
>  int intel_guc_resume(struct intel_guc *guc)
>  {
> -	u32 data[] = {
> +	u32 action[] = {
>  		INTEL_GUC_ACTION_EXIT_S_STATE,
>  		GUC_POWER_D0,
> -		intel_guc_ggtt_offset(guc, guc->shared_data)
>  	};
>  
> -	return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
> +	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 64b56da9775c..25d57c819e3f 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -648,9 +648,9 @@ enum intel_guc_report_status {
>  };
>  
>  enum intel_guc_sleep_state_status {
> -	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
> -	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
> -	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
> +	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
> +	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
> +	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
>  #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
>  };
>  
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[PATCH v2 08/22] drm/i915/guc: Update GuC sample-forcewake command

[Michal Wajdeczko]

New GuC firmwares use different action code value for this command.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 25d57c819e3f..dd9d99dc2aca 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -620,7 +620,6 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_DEFAULT = 0x0,
 	INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
 	INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
-	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
 	INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
 	INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
 	INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
@@ -628,6 +627,7 @@ enum intel_guc_action {
 	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
 	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 	INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
 	INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
-- 
2.19.2

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Re: [PATCH v2 08/22] drm/i915/guc: Update GuC sample-forcewake command

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> New GuC firmwares use different action code value for this command.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 25d57c819e3f..dd9d99dc2aca 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -620,7 +620,6 @@ enum intel_guc_action {
>   	INTEL_GUC_ACTION_DEFAULT = 0x0,
>   	INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
>   	INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
> -	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
>   	INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
>   	INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
>   	INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
> @@ -628,6 +627,7 @@ enum intel_guc_action {
>   	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
>   	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>   	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> +	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
>   	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>   	INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
>   	INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
> 
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Re: [PATCH v2 08/22] drm/i915/guc: Update GuC sample-forcewake command

[John Spotswood]

On Fri, 2019-04-12 at 17:10 -0700, Ceraolo Spurio, Daniele wrote:
> 
> On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> > 
> > New GuC firmwares use different action code value for this command.
> > 
> > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > Cc: John Spotswood <john.a.spotswood@intel.com>
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Reviewed-by: John Spotswood <john.a.spotswood@intel.com>

> 
> > 
> > ---
> >   drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> > b/drivers/gpu/drm/i915/intel_guc_fwif.h
> > index 25d57c819e3f..dd9d99dc2aca 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> > @@ -620,7 +620,6 @@ enum intel_guc_action {
> >   	INTEL_GUC_ACTION_DEFAULT = 0x0,
> >   	INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
> >   	INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
> > -	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
> >   	INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
> >   	INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
> >   	INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
> > @@ -628,6 +627,7 @@ enum intel_guc_action {
> >   	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
> >   	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
> >   	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> > +	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
> >   	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> >   	INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER =
> > 0x4505,
> >   	INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER =
> > 0x4506,
> > 
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[PATCH v2 09/22] drm/i915/guc: Update GuC ADS object definition

[Michal Wajdeczko]

New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Fernando Pacheco <fernando.pacheco@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  5 ++
 drivers/gpu/drm/i915/intel_guc_ads.c    | 94 +++++++++++++++----------
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 89 +++++++++++++----------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +
 4 files changed, 117 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index eea9bec04f1b..2a4d1527e171 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -231,6 +231,11 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
 	}
 }
 
+u32 intel_class_context_size(struct drm_i915_private *dev_priv, u8 class)
+{
+	return __intel_engine_context_size(dev_priv, class);
+}
+
 static u32 __engine_mmio_base(struct drm_i915_private *i915,
 			      const struct engine_mmio_base *bases)
 {
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
index bec62f34b15a..abab5cb6909a 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -51,7 +51,7 @@ static void guc_policies_init(struct guc_policies *policies)
 	policies->max_num_work_items = POLICY_MAX_NUM_WI;
 
 	for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
-		for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
+		for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
 			policy = &policies->policy[p][i];
 
 			guc_policy_init(policy);
@@ -61,6 +61,11 @@ static void guc_policies_init(struct guc_policies *policies)
 	policies->is_valid = 1;
 }
 
+static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
+{
+	memset(pool, 0, num * sizeof(*pool));
+}
+
 /*
  * The first 80 dwords of the register state context, containing the
  * execlists and ppgtt registers.
@@ -75,20 +80,21 @@ static void guc_policies_init(struct guc_policies *policies)
 int intel_guc_ads_create(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
-	struct i915_vma *vma, *kernel_ctx_vma;
-	struct page *page;
+	struct i915_vma *vma;
 	/* The ads obj includes the struct itself and buffers passed to GuC */
 	struct {
 		struct guc_ads ads;
 		struct guc_policies policies;
 		struct guc_mmio_reg_state reg_state;
+		struct guc_gt_system_info system_info;
+		struct guc_clients_info clients_info;
+		struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
 		u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
 	} __packed *blob;
-	struct intel_engine_cs *engine;
-	enum intel_engine_id id;
-	const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
 	const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
 	u32 base;
+	u8 engine_class;
+	int ret;
 
 	GEM_BUG_ON(guc->ads_vma);
 
@@ -98,51 +104,67 @@ int intel_guc_ads_create(struct intel_guc *guc)
 
 	guc->ads_vma = vma;
 
-	page = i915_vma_first_page(vma);
-	blob = kmap(page);
+	blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
+	if (IS_ERR(blob)) {
+		ret = PTR_ERR(blob);
+		goto err_vma;
+	}
 
 	/* GuC scheduling policies */
 	guc_policies_init(&blob->policies);
 
-	/* MMIO reg state */
-	for_each_engine(engine, dev_priv, id) {
-		blob->reg_state.white_list[engine->guc_id].mmio_start =
-			engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
-		/* Nothing to be saved or restored for now. */
-		blob->reg_state.white_list[engine->guc_id].count = 0;
-	}
-
 	/*
-	 * The GuC requires a "Golden Context" when it reinitialises
-	 * engines after a reset. Here we use the Render ring default
-	 * context, which must already exist and be pinned in the GGTT,
-	 * so its address won't change after we've told the GuC where
-	 * to find it. Note that we have to skip our header (1 page),
-	 * because our GuC shared data is there.
+	 * GuC expects a per-engine-class context image and size
+	 * (minus hwsp and ring context). The context image will be
+	 * used to reinitialize engines after a reset. It must exist
+	 * and be pinned in the GGTT, so that the address won't change after
+	 * we have told GuC where to find it. The context size will be used
+	 * to validate that the LRC base + size fall within allowed GGTT.
 	 */
-	kernel_ctx_vma = dev_priv->engine[RCS0]->kernel_context->state;
-	blob->ads.golden_context_lrca =
-		intel_guc_ggtt_offset(guc, kernel_ctx_vma) + skipped_offset;
+	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
+		if (engine_class == OTHER_CLASS)
+			continue;
+		/*
+		 * TODO: Set context pointer to default state to allow
+		 * GuC to re-init guilty contexts after internal reset.
+		 */
+		blob->ads.golden_context_lrca[engine_class] = 0;
+		blob->ads.eng_state_size[engine_class] =
+			intel_class_context_size(dev_priv, engine_class) - skipped_size;
+	}
 
-	/*
-	 * The GuC expects us to exclude the portion of the context image that
-	 * it skips from the size it is to read. It starts reading from after
-	 * the execlist context (so skipping the first page [PPHWSP] and 80
-	 * dwords). Weird guc is weird.
-	 */
-	for_each_engine(engine, dev_priv, id)
-		blob->ads.eng_state_size[engine->guc_id] =
-			engine->context_size - skipped_size;
+	/* System info */
+	blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
+	blob->system_info.rcs_enabled = 1;
+	blob->system_info.bcs_enabled = 1;
+
+	blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);
+	blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
+	blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
 
 	base = intel_guc_ggtt_offset(guc, vma);
+
+	/* Clients info  */
+	guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
+
+	blob->clients_info.clients_num = 1;
+	blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
+	blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
+
+	/* ADS */
 	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
 	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
 	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
+	blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
+	blob->ads.clients_info = base + ptr_offset(blob, clients_info);
 
-	kunmap(page);
+	i915_gem_object_unpin_map(guc->ads_vma->obj);
 
 	return 0;
+
+err_vma:
+	i915_vma_unpin_and_release(&guc->ads_vma, 0);
+	return ret;
 }
 
 void intel_guc_ads_destroy(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index dd9d99dc2aca..68dfeecf7b26 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -39,6 +39,9 @@
 #define GUC_VIDEO_ENGINE2		4
 #define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)
 
+#define GUC_MAX_ENGINE_CLASSES		5
+#define GUC_MAX_INSTANCES_PER_CLASS	4
+
 #define GUC_DOORBELL_INVALID		256
 
 #define GUC_DB_SIZE			(PAGE_SIZE)
@@ -397,23 +400,19 @@ struct guc_ct_buffer_desc {
 struct guc_policy {
 	/* Time for one workload to execute. (in micro seconds) */
 	u32 execution_quantum;
-	u32 reserved1;
-
 	/* Time to wait for a preemption request to completed before issuing a
 	 * reset. (in micro seconds). */
 	u32 preemption_time;
-
 	/* How much time to allow to run after the first fault is observed.
 	 * Then preempt afterwards. (in micro seconds) */
 	u32 fault_time;
-
 	u32 policy_flags;
-	u32 reserved[2];
+	u32 reserved[8];
 } __packed;
 
 struct guc_policies {
-	struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
-
+	struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
+	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
 	/* In micro seconds. How much time to allow before DPC processing is
 	 * called back via interrupt (to prevent DPC queue drain starving).
 	 * Typically 1000s of micro seconds (example only, not granularity). */
@@ -426,57 +425,73 @@ struct guc_policies {
 	 * idle. */
 	u32 max_num_work_items;
 
-	u32 reserved[19];
+	u32 reserved[4];
 } __packed;
 
 /* GuC MMIO reg state struct */
 
-#define GUC_REGSET_FLAGS_NONE		0x0
-#define GUC_REGSET_POWERCYCLE		0x1
-#define GUC_REGSET_MASKED		0x2
-#define GUC_REGSET_ENGINERESET		0x4
-#define GUC_REGSET_SAVE_DEFAULT_VALUE	0x8
-#define GUC_REGSET_SAVE_CURRENT_VALUE	0x10
 
-#define GUC_REGSET_MAX_REGISTERS	25
-#define GUC_MMIO_WHITE_LIST_START	0x24d0
-#define GUC_MMIO_WHITE_LIST_MAX		12
+#define GUC_REGSET_MAX_REGISTERS	64
 #define GUC_S3_SAVE_SPACE_PAGES		10
 
-struct guc_mmio_regset {
-	struct __packed {
-		u32 offset;
-		u32 value;
-		u32 flags;
-	} registers[GUC_REGSET_MAX_REGISTERS];
+struct guc_mmio_reg {
+	u32 offset;
+	u32 value;
+	u32 flags;
+#define GUC_REGSET_MASKED		(1 << 0)
+} __packed;
 
+struct guc_mmio_regset {
+	struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS];
 	u32 values_valid;
 	u32 number_of_registers;
 } __packed;
 
-/* MMIO registers that are set as non privileged */
-struct mmio_white_list {
-	u32 mmio_start;
-	u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
-	u32 count;
+/* GuC register sets */
+struct guc_mmio_reg_state {
+	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
+	u32 reserved[98];
 } __packed;
 
-struct guc_mmio_reg_state {
-	struct guc_mmio_regset global_reg;
-	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
-	struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];
+/* HW info */
+struct guc_gt_system_info {
+	u32 slice_enabled;
+	u32 rcs_enabled;
+	u32 reserved0;
+	u32 bcs_enabled;
+	u32 vdbox_enable_mask;
+	u32 vdbox_sfc_support_mask;
+	u32 vebox_enable_mask;
+	u32 reserved[9];
 } __packed;
 
-/* GuC Additional Data Struct */
+/* Clients info */
+struct guc_ct_pool_entry {
+	struct guc_ct_buffer_desc desc;
+	u32 reserved[7];
+} __packed;
 
+#define GUC_CT_POOL_SIZE	2
+
+struct guc_clients_info {
+	u32 clients_num;
+	u32 reserved0[13];
+	u32 ct_pool_addr;
+	u32 ct_pool_count;
+	u32 reserved[4];
+} __packed;
+
+/* GuC Additional Data Struct */
 struct guc_ads {
 	u32 reg_state_addr;
 	u32 reg_state_buffer;
-	u32 golden_context_lrca;
 	u32 scheduler_policies;
-	u32 reserved0[3];
-	u32 eng_state_size[GUC_MAX_ENGINES_NUM];
-	u32 reserved2[4];
+	u32 gt_system_info;
+	u32 clients_info;
+	u32 control_data;
+	u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
+	u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
+	u32 reserved[16];
 } __packed;
 
 /* GuC logging structures */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 0dea6c7fd438..584eec348412 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -547,6 +547,8 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
 struct i915_request *
 intel_engine_find_active_request(struct intel_engine_cs *engine);
 
+u32 intel_class_context_size(struct drm_i915_private *dev_priv, u8 class);
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 
 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 09/22] drm/i915/guc: Update GuC ADS object definition

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> New GuC firmwares use updated definitions for the Additional Data
> Structures (ADS).
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Fernando Pacheco <fernando.pacheco@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_engine_cs.c  |  5 ++
>   drivers/gpu/drm/i915/intel_guc_ads.c    | 94 +++++++++++++++----------
>   drivers/gpu/drm/i915/intel_guc_fwif.h   | 89 +++++++++++++----------
>   drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +
>   4 files changed, 117 insertions(+), 73 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index eea9bec04f1b..2a4d1527e171 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -231,6 +231,11 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
>   	}
>   }
>   
> +u32 intel_class_context_size(struct drm_i915_private *dev_priv, u8 class)
> +{
> +	return __intel_engine_context_size(dev_priv, class);
> +}
> +

Any reason not to just rename __intel_engine_context_size to 
intel_class_context_size?

>   static u32 __engine_mmio_base(struct drm_i915_private *i915,
>   			      const struct engine_mmio_base *bases)
>   {
> diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
> index bec62f34b15a..abab5cb6909a 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ads.c
> @@ -51,7 +51,7 @@ static void guc_policies_init(struct guc_policies *policies)

Possible future improvement: the defs say that the policies page doesn't 
need to be kept in memory because it is copied during load, so we could 
release it after load. It also says that the default values (which I 
believe are what we're setting) are automatically used if the page is 
not set, so we could just get rid of this until we need a customized 
value, but I'm not sure we want to go trough the churn.

>   	policies->max_num_work_items = POLICY_MAX_NUM_WI;
>   
>   	for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
> -		for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
> +		for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
>   			policy = &policies->policy[p][i];
>   
>   			guc_policy_init(policy);
> @@ -61,6 +61,11 @@ static void guc_policies_init(struct guc_policies *policies)
>   	policies->is_valid = 1;
>   }
>   
> +static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
> +{
> +	memset(pool, 0, num * sizeof(*pool));
> +}
> +
>   /*
>    * The first 80 dwords of the register state context, containing the
>    * execlists and ppgtt registers.
> @@ -75,20 +80,21 @@ static void guc_policies_init(struct guc_policies *policies)
>   int intel_guc_ads_create(struct intel_guc *guc)
>   {
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	struct i915_vma *vma, *kernel_ctx_vma;
> -	struct page *page;
> +	struct i915_vma *vma;
>   	/* The ads obj includes the struct itself and buffers passed to GuC */
>   	struct {
>   		struct guc_ads ads;
>   		struct guc_policies policies;
>   		struct guc_mmio_reg_state reg_state;
> +		struct guc_gt_system_info system_info;
> +		struct guc_clients_info clients_info;
> +		struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
>   		u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
>   	} __packed *blob;
> -	struct intel_engine_cs *engine;
> -	enum intel_engine_id id;
> -	const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
>   	const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
>   	u32 base;
> +	u8 engine_class;
> +	int ret;
>   
>   	GEM_BUG_ON(guc->ads_vma);
>   
> @@ -98,51 +104,67 @@ int intel_guc_ads_create(struct intel_guc *guc)
>   
>   	guc->ads_vma = vma;
>   
> -	page = i915_vma_first_page(vma);
> -	blob = kmap(page);
> +	blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
> +	if (IS_ERR(blob)) {
> +		ret = PTR_ERR(blob);
> +		goto err_vma;
> +	}
>   
>   	/* GuC scheduling policies */
>   	guc_policies_init(&blob->policies);
>   
> -	/* MMIO reg state */
> -	for_each_engine(engine, dev_priv, id) {
> -		blob->reg_state.white_list[engine->guc_id].mmio_start =
> -			engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
> -
> -		/* Nothing to be saved or restored for now. */
> -		blob->reg_state.white_list[engine->guc_id].count = 0;
> -	}
> -
>   	/*
> -	 * The GuC requires a "Golden Context" when it reinitialises
> -	 * engines after a reset. Here we use the Render ring default
> -	 * context, which must already exist and be pinned in the GGTT,
> -	 * so its address won't change after we've told the GuC where
> -	 * to find it. Note that we have to skip our header (1 page),
> -	 * because our GuC shared data is there.
> +	 * GuC expects a per-engine-class context image and size
> +	 * (minus hwsp and ring context). The context image will be
> +	 * used to reinitialize engines after a reset. It must exist
> +	 * and be pinned in the GGTT, so that the address won't change after
> +	 * we have told GuC where to find it. The context size will be used
> +	 * to validate that the LRC base + size fall within allowed GGTT.
>   	 */
> -	kernel_ctx_vma = dev_priv->engine[RCS0]->kernel_context->state;
> -	blob->ads.golden_context_lrca =
> -		intel_guc_ggtt_offset(guc, kernel_ctx_vma) + skipped_offset;
> +	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
> +		if (engine_class == OTHER_CLASS)
> +			continue;
> +		/*
> +		 * TODO: Set context pointer to default state to allow
> +		 * GuC to re-init guilty contexts after internal reset.
> +		 */
> +		blob->ads.golden_context_lrca[engine_class] = 0;
> +		blob->ads.eng_state_size[engine_class] =
> +			intel_class_context_size(dev_priv, engine_class) - skipped_size;
> +	}
>   
> -	/*
> -	 * The GuC expects us to exclude the portion of the context image that
> -	 * it skips from the size it is to read. It starts reading from after
> -	 * the execlist context (so skipping the first page [PPHWSP] and 80
> -	 * dwords). Weird guc is weird.
> -	 */
> -	for_each_engine(engine, dev_priv, id)
> -		blob->ads.eng_state_size[engine->guc_id] =
> -			engine->context_size - skipped_size;
> +	/* System info */
> +	blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
> +	blob->system_info.rcs_enabled = 1;
> +	blob->system_info.bcs_enabled = 1;
> +
> +	blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);
> +	blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
> +	blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
>   
>   	base = intel_guc_ggtt_offset(guc, vma);
> +
> +	/* Clients info  */
> +	guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
> +
> +	blob->clients_info.clients_num = 1;
> +	blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
> +	blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
> +
> +	/* ADS */
>   	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
>   	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
>   	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
> +	blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
> +	blob->ads.clients_info = base + ptr_offset(blob, clients_info);
>   
> -	kunmap(page);
> +	i915_gem_object_unpin_map(guc->ads_vma->obj);
>   
>   	return 0;
> +
> +err_vma:
> +	i915_vma_unpin_and_release(&guc->ads_vma, 0);
> +	return ret;
>   }
>   
>   void intel_guc_ads_destroy(struct intel_guc *guc)
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index dd9d99dc2aca..68dfeecf7b26 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -39,6 +39,9 @@
>   #define GUC_VIDEO_ENGINE2		4
>   #define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)
>   
> +#define GUC_MAX_ENGINE_CLASSES		5
> +#define GUC_MAX_INSTANCES_PER_CLASS	4

mmm, inside of guc this is defined as

#if GEN9
#define GUC_MAX_INSTANCES_PER_CLASS 1
#else
#define GUC_MAX_INSTANCES_PER_CLASS 4
#endif

Now, this is only used for the regset, which only matters if guc is 
doing engine resets. Since we're never going to enable guc submission on 
gen9 with the new interface we should be ok, but we should at least add 
a comment.
I've mentioned it to the guc team and they say it is on their list of 
things to fix so the FW should move to a unified define soon-ish.

Daniele

> +
>   #define GUC_DOORBELL_INVALID		256
>   
>   #define GUC_DB_SIZE			(PAGE_SIZE)
> @@ -397,23 +400,19 @@ struct guc_ct_buffer_desc {
>   struct guc_policy {
>   	/* Time for one workload to execute. (in micro seconds) */
>   	u32 execution_quantum;
> -	u32 reserved1;
> -
>   	/* Time to wait for a preemption request to completed before issuing a
>   	 * reset. (in micro seconds). */
>   	u32 preemption_time;
> -
>   	/* How much time to allow to run after the first fault is observed.
>   	 * Then preempt afterwards. (in micro seconds) */
>   	u32 fault_time;
> -
>   	u32 policy_flags;
> -	u32 reserved[2];
> +	u32 reserved[8];
>   } __packed;
>   
>   struct guc_policies {
> -	struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
> -
> +	struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
> +	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
>   	/* In micro seconds. How much time to allow before DPC processing is
>   	 * called back via interrupt (to prevent DPC queue drain starving).
>   	 * Typically 1000s of micro seconds (example only, not granularity). */
> @@ -426,57 +425,73 @@ struct guc_policies {
>   	 * idle. */
>   	u32 max_num_work_items;
>   
> -	u32 reserved[19];
> +	u32 reserved[4];
>   } __packed;
>   
>   /* GuC MMIO reg state struct */
>   
> -#define GUC_REGSET_FLAGS_NONE		0x0
> -#define GUC_REGSET_POWERCYCLE		0x1
> -#define GUC_REGSET_MASKED		0x2
> -#define GUC_REGSET_ENGINERESET		0x4
> -#define GUC_REGSET_SAVE_DEFAULT_VALUE	0x8
> -#define GUC_REGSET_SAVE_CURRENT_VALUE	0x10
>   
> -#define GUC_REGSET_MAX_REGISTERS	25
> -#define GUC_MMIO_WHITE_LIST_START	0x24d0
> -#define GUC_MMIO_WHITE_LIST_MAX		12
> +#define GUC_REGSET_MAX_REGISTERS	64
>   #define GUC_S3_SAVE_SPACE_PAGES		10
>   
> -struct guc_mmio_regset {
> -	struct __packed {
> -		u32 offset;
> -		u32 value;
> -		u32 flags;
> -	} registers[GUC_REGSET_MAX_REGISTERS];
> +struct guc_mmio_reg {
> +	u32 offset;
> +	u32 value;
> +	u32 flags;
> +#define GUC_REGSET_MASKED		(1 << 0)
> +} __packed;
>   
> +struct guc_mmio_regset {
> +	struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS];
>   	u32 values_valid;
>   	u32 number_of_registers;
>   } __packed;
>   
> -/* MMIO registers that are set as non privileged */
> -struct mmio_white_list {
> -	u32 mmio_start;
> -	u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
> -	u32 count;
> +/* GuC register sets */
> +struct guc_mmio_reg_state {
> +	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
> +	u32 reserved[98];
>   } __packed;
>   
> -struct guc_mmio_reg_state {
> -	struct guc_mmio_regset global_reg;
> -	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
> -	struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];
> +/* HW info */
> +struct guc_gt_system_info {
> +	u32 slice_enabled;
> +	u32 rcs_enabled;
> +	u32 reserved0;
> +	u32 bcs_enabled;
> +	u32 vdbox_enable_mask;
> +	u32 vdbox_sfc_support_mask;
> +	u32 vebox_enable_mask;
> +	u32 reserved[9];
>   } __packed;
>   
> -/* GuC Additional Data Struct */
> +/* Clients info */
> +struct guc_ct_pool_entry {
> +	struct guc_ct_buffer_desc desc;
> +	u32 reserved[7];
> +} __packed;
>   
> +#define GUC_CT_POOL_SIZE	2
> +
> +struct guc_clients_info {
> +	u32 clients_num;
> +	u32 reserved0[13];
> +	u32 ct_pool_addr;
> +	u32 ct_pool_count;
> +	u32 reserved[4];
> +} __packed;
> +
> +/* GuC Additional Data Struct */
>   struct guc_ads {
>   	u32 reg_state_addr;
>   	u32 reg_state_buffer;
> -	u32 golden_context_lrca;
>   	u32 scheduler_policies;
> -	u32 reserved0[3];
> -	u32 eng_state_size[GUC_MAX_ENGINES_NUM];
> -	u32 reserved2[4];
> +	u32 gt_system_info;
> +	u32 clients_info;
> +	u32 control_data;
> +	u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
> +	u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
> +	u32 reserved[16];
>   } __packed;
>   
>   /* GuC logging structures */
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 0dea6c7fd438..584eec348412 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -547,6 +547,8 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
>   struct i915_request *
>   intel_engine_find_active_request(struct intel_engine_cs *engine);
>   
> +u32 intel_class_context_size(struct drm_i915_private *dev_priv, u8 class);
> +
>   #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>   
>   static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
> 
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[PATCH v2 10/22] drm/i915/guc: Always ask GuC to update power domain states

[Michal Wajdeczko]

With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 4 ----
 drivers/gpu/drm/i915/intel_uc.c             | 8 ++++----
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index dea87253d141..856505dbbe91 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1319,10 +1319,6 @@ int intel_guc_submission_enable(struct intel_guc *guc)
 
 	GEM_BUG_ON(!guc->execbuf_client);
 
-	err = intel_guc_sample_forcewake(guc);
-	if (err)
-		return err;
-
 	err = guc_clients_enable(guc);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 21310b917ccc..8e5e4226df53 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -405,14 +405,14 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
 			goto err_communication;
 	}
 
+	ret = intel_guc_sample_forcewake(guc);
+	if (ret)
+		goto err_communication;
+
 	if (USES_GUC_SUBMISSION(i915)) {
 		ret = intel_guc_submission_enable(guc);
 		if (ret)
 			goto err_communication;
-	} else if (INTEL_GEN(i915) < 11) {
-		ret = intel_guc_sample_forcewake(guc);
-		if (ret)
-			goto err_communication;
 	}
 
 	dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
-- 
2.19.2

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Re: [PATCH v2 10/22] drm/i915/guc: Always ask GuC to update power domain states

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> With newer GuC firmware it is always ok to ask GuC to update power
> domain states. Make it an unconditional initialization step.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/i915/intel_guc_submission.c | 4 ----
>   drivers/gpu/drm/i915/intel_uc.c             | 8 ++++----
>   2 files changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index dea87253d141..856505dbbe91 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -1319,10 +1319,6 @@ int intel_guc_submission_enable(struct intel_guc *guc)
>   
>   	GEM_BUG_ON(!guc->execbuf_client);
>   
> -	err = intel_guc_sample_forcewake(guc);
> -	if (err)
> -		return err;
> -
>   	err = guc_clients_enable(guc);
>   	if (err)
>   		return err;
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 21310b917ccc..8e5e4226df53 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -405,14 +405,14 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
>   			goto err_communication;
>   	}
>   
> +	ret = intel_guc_sample_forcewake(guc);
> +	if (ret)
> +		goto err_communication;
> +
>   	if (USES_GUC_SUBMISSION(i915)) {
>   		ret = intel_guc_submission_enable(guc);
>   		if (ret)
>   			goto err_communication;
> -	} else if (INTEL_GEN(i915) < 11) {
> -		ret = intel_guc_sample_forcewake(guc);
> -		if (ret)
> -			goto err_communication;
>   	}
>   
>   	dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
> 
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Re: [PATCH v2 10/22] drm/i915/guc: Always ask GuC to update power domain states

[John Spotswood]

On Mon, 2019-04-15 at 13:46 -0700, Ceraolo Spurio, Daniele wrote:
> 
> On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> > 
> > With newer GuC firmware it is always ok to ask GuC to update power
> > domain states. Make it an unconditional initialization step.
> > 
> > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: John Spotswood <john.a.spotswood@intel.com>
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> Daniele

Reviewed-by: John Spotswood <john.a.spotswood@intel.com>

> 
> > 
> > ---
> >   drivers/gpu/drm/i915/intel_guc_submission.c | 4 ----
> >   drivers/gpu/drm/i915/intel_uc.c             | 8 ++++----
> >   2 files changed, 4 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/intel_guc_submission.c
> > index dea87253d141..856505dbbe91 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> > @@ -1319,10 +1319,6 @@ int intel_guc_submission_enable(struct
> > intel_guc *guc)
> >   
> >   	GEM_BUG_ON(!guc->execbuf_client);
> >   
> > -	err = intel_guc_sample_forcewake(guc);
> > -	if (err)
> > -		return err;
> > -
> >   	err = guc_clients_enable(guc);
> >   	if (err)
> >   		return err;
> > diff --git a/drivers/gpu/drm/i915/intel_uc.c
> > b/drivers/gpu/drm/i915/intel_uc.c
> > index 21310b917ccc..8e5e4226df53 100644
> > --- a/drivers/gpu/drm/i915/intel_uc.c
> > +++ b/drivers/gpu/drm/i915/intel_uc.c
> > @@ -405,14 +405,14 @@ int intel_uc_init_hw(struct drm_i915_private
> > *i915)
> >   			goto err_communication;
> >   	}
> >   
> > +	ret = intel_guc_sample_forcewake(guc);
> > +	if (ret)
> > +		goto err_communication;
> > +
> >   	if (USES_GUC_SUBMISSION(i915)) {
> >   		ret = intel_guc_submission_enable(guc);
> >   		if (ret)
> >   			goto err_communication;
> > -	} else if (INTEL_GEN(i915) < 11) {
> > -		ret = intel_guc_sample_forcewake(guc);
> > -		if (ret)
> > -			goto err_communication;
> >   	}
> >   
> >   	dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
> > 
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[PATCH v2 11/22] drm/i915/guc: Reset GuC ADS during sanitize

[Michal Wajdeczko]

GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: MichaĹ Winiarski <michal.winiarski@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.h     |  2 +
 drivers/gpu/drm/i915/intel_guc_ads.c | 85 ++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_guc_ads.h |  1 +
 3 files changed, 57 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 2c59ff8d9f39..4f3cf8eddfe6 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -26,6 +26,7 @@
 #define _INTEL_GUC_H_
 
 #include "intel_uncore.h"
+#include "intel_guc_ads.h"
 #include "intel_guc_fw.h"
 #include "intel_guc_fwif.h"
 #include "intel_guc_ct.h"
@@ -177,6 +178,7 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
 static inline int intel_guc_sanitize(struct intel_guc *guc)
 {
 	intel_uc_fw_sanitize(&guc->fw);
+	intel_guc_ads_reset(guc);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
index abab5cb6909a..97926effb944 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -72,43 +72,28 @@ static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
  */
 #define LR_HW_CONTEXT_SIZE	(80 * sizeof(u32))
 
-/**
- * intel_guc_ads_create() - creates GuC ADS
- * @guc: intel_guc struct
- *
- */
-int intel_guc_ads_create(struct intel_guc *guc)
+/* The ads obj includes the struct itself and buffers passed to GuC */
+struct __guc_ads_blob {
+	struct guc_ads ads;
+	struct guc_policies policies;
+	struct guc_mmio_reg_state reg_state;
+	struct guc_gt_system_info system_info;
+	struct guc_clients_info clients_info;
+	struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
+	u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
+} __packed;
+
+static int __guc_ads_reinit(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
-	struct i915_vma *vma;
-	/* The ads obj includes the struct itself and buffers passed to GuC */
-	struct {
-		struct guc_ads ads;
-		struct guc_policies policies;
-		struct guc_mmio_reg_state reg_state;
-		struct guc_gt_system_info system_info;
-		struct guc_clients_info clients_info;
-		struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
-		u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
-	} __packed *blob;
+	struct __guc_ads_blob *blob;
 	const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
 	u32 base;
 	u8 engine_class;
-	int ret;
-
-	GEM_BUG_ON(guc->ads_vma);
-
-	vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
-	if (IS_ERR(vma))
-		return PTR_ERR(vma);
-
-	guc->ads_vma = vma;
 
 	blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
-	if (IS_ERR(blob)) {
-		ret = PTR_ERR(blob);
-		goto err_vma;
-	}
+	if (IS_ERR(blob))
+		return PTR_ERR(blob);
 
 	/* GuC scheduling policies */
 	guc_policies_init(&blob->policies);
@@ -142,7 +127,7 @@ int intel_guc_ads_create(struct intel_guc *guc)
 	blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
 	blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
 
-	base = intel_guc_ggtt_offset(guc, vma);
+	base = intel_guc_ggtt_offset(guc, guc->ads_vma);
 
 	/* Clients info  */
 	guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
@@ -161,6 +146,32 @@ int intel_guc_ads_create(struct intel_guc *guc)
 	i915_gem_object_unpin_map(guc->ads_vma->obj);
 
 	return 0;
+}
+
+/**
+ * intel_guc_ads_create() - creates GuC ADS
+ * @guc: intel_guc struct
+ *
+ */
+int intel_guc_ads_create(struct intel_guc *guc)
+{
+	const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob));
+	struct i915_vma *vma;
+	int ret;
+
+	GEM_BUG_ON(guc->ads_vma);
+
+	vma = intel_guc_allocate_vma(guc, size);
+	if (IS_ERR(vma))
+		return PTR_ERR(vma);
+
+	guc->ads_vma = vma;
+
+	ret = __guc_ads_reinit(guc);
+	if (ret)
+		goto err_vma;
+
+	return 0;
 
 err_vma:
 	i915_vma_unpin_and_release(&guc->ads_vma, 0);
@@ -171,3 +182,15 @@ void intel_guc_ads_destroy(struct intel_guc *guc)
 {
 	i915_vma_unpin_and_release(&guc->ads_vma, 0);
 }
+
+/**
+ * intel_guc_ads_reset() - resets GuC ADS
+ * @guc: intel_guc struct
+ *
+ */
+void intel_guc_ads_reset(struct intel_guc *guc)
+{
+	if (!guc->ads_vma)
+		return;
+	__guc_ads_reinit(guc);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.h b/drivers/gpu/drm/i915/intel_guc_ads.h
index c4735742c564..7f40f9cd5fb9 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.h
+++ b/drivers/gpu/drm/i915/intel_guc_ads.h
@@ -29,5 +29,6 @@ struct intel_guc;
 
 int intel_guc_ads_create(struct intel_guc *guc);
 void intel_guc_ads_destroy(struct intel_guc *guc);
+void intel_guc_ads_reset(struct intel_guc *guc);
 
 #endif
-- 
2.19.2

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Re: [PATCH v2 11/22] drm/i915/guc: Reset GuC ADS during sanitize

[Lis, Tomasz]

Only comment issues. Besides these:

Reviewed-by: Tomasz Lis <tomasz.lis@intel.com>

On 2019-04-11 10:44, Michal Wajdeczko wrote:
> GuC stores some data in there, which might be stale after a reset.
> Reinitialize whole ADS in case any part of it was corrupted during
> previous GuC run.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: MichaĹ Winiarski <michal.winiarski@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc.h     |  2 +
>   drivers/gpu/drm/i915/intel_guc_ads.c | 85 ++++++++++++++++++----------
>   drivers/gpu/drm/i915/intel_guc_ads.h |  1 +
>   3 files changed, 57 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 2c59ff8d9f39..4f3cf8eddfe6 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -26,6 +26,7 @@
>   #define _INTEL_GUC_H_
>   
>   #include "intel_uncore.h"
> +#include "intel_guc_ads.h"
>   #include "intel_guc_fw.h"
>   #include "intel_guc_fwif.h"
>   #include "intel_guc_ct.h"
> @@ -177,6 +178,7 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
>   static inline int intel_guc_sanitize(struct intel_guc *guc)
>   {
>   	intel_uc_fw_sanitize(&guc->fw);
> +	intel_guc_ads_reset(guc);
>   	return 0;
>   }
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
> index abab5cb6909a..97926effb944 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ads.c
> @@ -72,43 +72,28 @@ static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
>    */
>   #define LR_HW_CONTEXT_SIZE	(80 * sizeof(u32))
>   
> -/**
> - * intel_guc_ads_create() - creates GuC ADS
> - * @guc: intel_guc struct
> - *
> - */
> -int intel_guc_ads_create(struct intel_guc *guc)
> +/* The ads obj includes the struct itself and buffers passed to GuC */
> +struct __guc_ads_blob {
> +	struct guc_ads ads;
> +	struct guc_policies policies;
> +	struct guc_mmio_reg_state reg_state;
> +	struct guc_gt_system_info system_info;
> +	struct guc_clients_info clients_info;
> +	struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
> +	u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
> +} __packed;
> +
> +static int __guc_ads_reinit(struct intel_guc *guc)
>   {
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	struct i915_vma *vma;
> -	/* The ads obj includes the struct itself and buffers passed to GuC */
> -	struct {
> -		struct guc_ads ads;
> -		struct guc_policies policies;
> -		struct guc_mmio_reg_state reg_state;
> -		struct guc_gt_system_info system_info;
> -		struct guc_clients_info clients_info;
> -		struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
> -		u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
> -	} __packed *blob;
> +	struct __guc_ads_blob *blob;
>   	const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
>   	u32 base;
>   	u8 engine_class;
> -	int ret;
> -
> -	GEM_BUG_ON(guc->ads_vma);
> -
> -	vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
> -	if (IS_ERR(vma))
> -		return PTR_ERR(vma);
> -
> -	guc->ads_vma = vma;
>   
>   	blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
> -	if (IS_ERR(blob)) {
> -		ret = PTR_ERR(blob);
> -		goto err_vma;
> -	}
> +	if (IS_ERR(blob))
> +		return PTR_ERR(blob);
>   
>   	/* GuC scheduling policies */
>   	guc_policies_init(&blob->policies);
> @@ -142,7 +127,7 @@ int intel_guc_ads_create(struct intel_guc *guc)
>   	blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
>   	blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
>   
> -	base = intel_guc_ggtt_offset(guc, vma);
> +	base = intel_guc_ggtt_offset(guc, guc->ads_vma);
>   
>   	/* Clients info  */
>   	guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
> @@ -161,6 +146,32 @@ int intel_guc_ads_create(struct intel_guc *guc)
>   	i915_gem_object_unpin_map(guc->ads_vma->obj);
>   
>   	return 0;
> +}
> +
> +/**
> + * intel_guc_ads_create() - creates GuC ADS
> + * @guc: intel_guc struct
Are we really ok with documentation which just reads names with spaces 
instead of underscores?
I believe the description should go deeper, or at least use different 
words to describe the thing.
ie. here:

intel_guc_ads_create() - allocates and initializes GuC Additional Data Struct

@guc: instance of intel_guc which will own the ADS
> + *
> + */
> +int intel_guc_ads_create(struct intel_guc *guc)
> +{
> +	const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob));
> +	struct i915_vma *vma;
> +	int ret;
> +
> +	GEM_BUG_ON(guc->ads_vma);
> +
> +	vma = intel_guc_allocate_vma(guc, size);
> +	if (IS_ERR(vma))
> +		return PTR_ERR(vma);
> +
> +	guc->ads_vma = vma;
> +
> +	ret = __guc_ads_reinit(guc);
> +	if (ret)
> +		goto err_vma;
> +
> +	return 0;
>   
>   err_vma:
>   	i915_vma_unpin_and_release(&guc->ads_vma, 0);
> @@ -171,3 +182,15 @@ void intel_guc_ads_destroy(struct intel_guc *guc)
>   {
>   	i915_vma_unpin_and_release(&guc->ads_vma, 0);
>   }
> +
> +/**
> + * intel_guc_ads_reset() - resets GuC ADS
Again:

intel_guc_ads_reset() - prepares GuC Additional Data Struct for reuse

-Tomasz

> + * @guc: intel_guc struct
> + *
> + */
> +void intel_guc_ads_reset(struct intel_guc *guc)
> +{
> +	if (!guc->ads_vma)
> +		return;
> +	__guc_ads_reinit(guc);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_ads.h b/drivers/gpu/drm/i915/intel_guc_ads.h
> index c4735742c564..7f40f9cd5fb9 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ads.h
> +++ b/drivers/gpu/drm/i915/intel_guc_ads.h
> @@ -29,5 +29,6 @@ struct intel_guc;
>   
>   int intel_guc_ads_create(struct intel_guc *guc);
>   void intel_guc_ads_destroy(struct intel_guc *guc);
> +void intel_guc_ads_reset(struct intel_guc *guc);
>   
>   #endif

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[PATCH v2 12/22] drm/i915/guc: Treat GuC initialization failure as -EIO

[Michal Wajdeczko]

There is no fallback to execlists, but instead of aborting whole
driver load, just mark it as wedged.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c | 3 ++-
 drivers/gpu/drm/i915/intel_uc.c | 6 ++----
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0a818a60ad31..ac64a6fd9b91 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4963,7 +4963,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	intel_uc_fini_hw(dev_priv);
 err_uc_init:
-	intel_uc_fini(dev_priv);
+	if (ret != -EIO)
+		intel_uc_fini(dev_priv);
 err_pm:
 	if (ret != -EIO) {
 		intel_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8e5e4226df53..03bc2a0ee34b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -435,12 +435,10 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
 	/*
 	 * Note that there is no fallback as either user explicitly asked for
 	 * the GuC or driver default option was to run with the GuC enabled.
+	 * Return -EIO to just disable GPU submission but keep KMS alive.
 	 */
-	if (GEM_WARN_ON(ret == -EIO))
-		ret = -EINVAL;
-
 	dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
-	return ret;
+	return -EIO;
 }
 
 void intel_uc_fini_hw(struct drm_i915_private *i915)
-- 
2.19.2

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Re: [PATCH v2 12/22] drm/i915/guc: Treat GuC initialization failure as -EIO

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> There is no fallback to execlists, but instead of aborting whole
> driver load, just mark it as wedged.
> 

I don't see any inject_load_failure() in the guc paths (WOPCM aside). 
Can you sprinkle a few of them around to make sure this is solid?

Thanks,
Daniele

> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/i915_gem.c | 3 ++-
>   drivers/gpu/drm/i915/intel_uc.c | 6 ++----
>   2 files changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 0a818a60ad31..ac64a6fd9b91 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4963,7 +4963,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>   	mutex_lock(&dev_priv->drm.struct_mutex);
>   	intel_uc_fini_hw(dev_priv);
>   err_uc_init:
> -	intel_uc_fini(dev_priv);
> +	if (ret != -EIO)
> +		intel_uc_fini(dev_priv);
>   err_pm:
>   	if (ret != -EIO) {
>   		intel_cleanup_gt_powersave(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 8e5e4226df53..03bc2a0ee34b 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -435,12 +435,10 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
>   	/*
>   	 * Note that there is no fallback as either user explicitly asked for
>   	 * the GuC or driver default option was to run with the GuC enabled.
> +	 * Return -EIO to just disable GPU submission but keep KMS alive.
>   	 */
> -	if (GEM_WARN_ON(ret == -EIO))
> -		ret = -EINVAL;
> -
>   	dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
> -	return ret;
> +	return -EIO;
>   }
>   
>   void intel_uc_fini_hw(struct drm_i915_private *i915)
> 
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[PATCH v2 13/22] drm/i915/guc: New GuC interrupt register for Gen11

[Michal Wajdeczko]

Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.

Bspec: 21043

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c     | 14 +++++++++++++-
 drivers/gpu/drm/i915/intel_guc_reg.h |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 483c7019f817..5bc9bc7c956a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -34,6 +34,13 @@ static void gen8_guc_raise_irq(struct intel_guc *guc)
 	I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
 }
 
+static void gen11_guc_raise_irq(struct intel_guc *guc)
+{
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+	I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
+}
+
 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
 {
 	GEM_BUG_ON(!guc->send_regs.base);
@@ -63,6 +70,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
 
 void intel_guc_init_early(struct intel_guc *guc)
 {
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
 	intel_guc_fw_init_early(guc);
 	intel_guc_ct_init_early(&guc->ct);
 	intel_guc_log_init_early(&guc->log);
@@ -71,7 +80,10 @@ void intel_guc_init_early(struct intel_guc *guc)
 	spin_lock_init(&guc->irq_lock);
 	guc->send = intel_guc_send_nop;
 	guc->handler = intel_guc_to_host_event_handler_nop;
-	guc->notify = gen8_guc_raise_irq;
+	if (INTEL_GEN(i915) >= 11)
+		guc->notify = gen11_guc_raise_irq;
+	else
+		guc->notify = gen8_guc_raise_irq;
 }
 
 static int guc_init_wq(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 57e7ad522c2f..aec02eddbaed 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -103,6 +103,7 @@
 
 #define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)
 #define   GUC_SEND_TRIGGER		  (1<<0)
+#define GEN11_GUC_HOST_INTERRUPT	_MMIO(0x1901f0)
 
 #define GUC_NUM_DOORBELLS		256
 
-- 
2.19.2

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Re: [PATCH v2 13/22] drm/i915/guc: New GuC interrupt register for Gen11

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> Gen11 defines new more flexible Host-to-GuC interrupt register.
> Now the host can write any 32-bit payload to trigger an interrupt
> and GuC can additionally read this payload from the register.
> Current GuC firmware ignores the payload so we just write 0.
> 
> Bspec: 21043
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

matches the specs.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

As a possible simplification, instead of using a function pointer we 
could also just save the interrupt register in guc->send_regs and always 
use GUC_SEND_TRIGGER (the gen11 payload is ignored anyway), or save the 
trigger/payload value as well.

Daniele

> ---
>   drivers/gpu/drm/i915/intel_guc.c     | 14 +++++++++++++-
>   drivers/gpu/drm/i915/intel_guc_reg.h |  1 +
>   2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 483c7019f817..5bc9bc7c956a 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -34,6 +34,13 @@ static void gen8_guc_raise_irq(struct intel_guc *guc)
>   	I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
>   }
>   
> +static void gen11_guc_raise_irq(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> +	I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
> +}
> +
>   static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
>   {
>   	GEM_BUG_ON(!guc->send_regs.base);
> @@ -63,6 +70,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
>   
>   void intel_guc_init_early(struct intel_guc *guc)
>   {
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
> +
>   	intel_guc_fw_init_early(guc);
>   	intel_guc_ct_init_early(&guc->ct);
>   	intel_guc_log_init_early(&guc->log);
> @@ -71,7 +80,10 @@ void intel_guc_init_early(struct intel_guc *guc)
>   	spin_lock_init(&guc->irq_lock);
>   	guc->send = intel_guc_send_nop;
>   	guc->handler = intel_guc_to_host_event_handler_nop;
> -	guc->notify = gen8_guc_raise_irq;
> +	if (INTEL_GEN(i915) >= 11)
> +		guc->notify = gen11_guc_raise_irq;
> +	else
> +		guc->notify = gen8_guc_raise_irq;
>   }
>   
>   static int guc_init_wq(struct intel_guc *guc)
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index 57e7ad522c2f..aec02eddbaed 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -103,6 +103,7 @@
>   
>   #define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)
>   #define   GUC_SEND_TRIGGER		  (1<<0)
> +#define GEN11_GUC_HOST_INTERRUPT	_MMIO(0x1901f0)
>   
>   #define GUC_NUM_DOORBELLS		256
>   
> 
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[PATCH v2 14/22] drm/i915/guc: New GuC scratch registers for Gen11

[Michal Wajdeczko]

Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.

Bspec: 21044

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c     | 12 +++++++++---
 drivers/gpu/drm/i915/intel_guc_reg.h |  3 +++
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 5bc9bc7c956a..e54de551b567 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -56,9 +56,15 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
 	enum forcewake_domains fw_domains = 0;
 	unsigned int i;
 
-	guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
-	guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
-	BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
+	if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) {
+		guc->send_regs.base =
+				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
+		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
+	} else {
+		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
+		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
+	}
 
 	for (i = 0; i < guc->send_regs.count; i++) {
 		fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index aec02eddbaed..d26de5193568 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -51,6 +51,9 @@
 #define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
 #define SOFT_SCRATCH_COUNT		16
 
+#define GEN11_SOFT_SCRATCH(n)		_MMIO(0x190240 + (n) * 4)
+#define GEN11_SOFT_SCRATCH_COUNT	4
+
 #define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
 #define UOS_RSA_SCRATCH_COUNT		64
 
-- 
2.19.2

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Re: [PATCH v2 14/22] drm/i915/guc: New GuC scratch registers for Gen11

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> Gen11 adds new set of scratch registers that can be used for MMIO
> based Host-to-Guc communication. Due to limited number of these
> registers it is expected that host will use them only for command
> transport buffers (CTB) communication setup if one is available.
> 
> Bspec: 21044
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/i915/intel_guc.c     | 12 +++++++++---
>   drivers/gpu/drm/i915/intel_guc_reg.h |  3 +++
>   2 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 5bc9bc7c956a..e54de551b567 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -56,9 +56,15 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
>   	enum forcewake_domains fw_domains = 0;
>   	unsigned int i;
>   
> -	guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> -	guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
> -	BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
> +	if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) {
> +		guc->send_regs.base =
> +				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
> +		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
> +	} else {
> +		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> +		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
> +		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
> +	}
>   
>   	for (i = 0; i < guc->send_regs.count; i++) {
>   		fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index aec02eddbaed..d26de5193568 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -51,6 +51,9 @@
>   #define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
>   #define SOFT_SCRATCH_COUNT		16
>   
> +#define GEN11_SOFT_SCRATCH(n)		_MMIO(0x190240 + (n) * 4)
> +#define GEN11_SOFT_SCRATCH_COUNT	4
> +
>   #define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
>   #define UOS_RSA_SCRATCH_COUNT		64
>   
> 
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[PATCH v2 15/22] drm/i915/huc: New HuC status register for Gen11

[Michal Wajdeczko]

Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.

BSpec: 19686

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_reg.h |  3 ++
 drivers/gpu/drm/i915/intel_huc.c     | 56 ++++++++++++++++++++++++----
 2 files changed, 51 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index d26de5193568..7eba65795b58 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -79,6 +79,9 @@
 #define HUC_STATUS2             _MMIO(0xD3B0)
 #define   HUC_FW_VERIFIED       (1<<7)
 
+#define GEN11_HUC_KERNEL_LOAD_INFO	_MMIO(0xC1DC)
+#define   HUC_LOAD_SUCCESSFUL		  (1 << 0)
+
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
 #define   GUC_WOPCM_SIZE_LOCKED		  (1<<0)
 #define   GUC_WOPCM_SIZE_SHIFT		12
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 94c04f16a2ad..708a4b387259 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -40,6 +40,47 @@ int intel_huc_init_misc(struct intel_huc *huc)
 	return 0;
 }
 
+static int gen8_huc_wait_verified(struct intel_huc *huc)
+{
+	struct drm_i915_private *i915 = huc_to_i915(huc);
+	u32 status;
+	int ret;
+
+	ret = __intel_wait_for_register(&i915->uncore,
+					HUC_STATUS2,
+					HUC_FW_VERIFIED,
+					HUC_FW_VERIFIED,
+					2, 50, &status);
+	if (ret)
+		DRM_ERROR("HuC: status %#x\n", status);
+	return ret;
+}
+
+static int gen11_huc_wait_verified(struct intel_huc *huc)
+{
+	struct drm_i915_private *i915 = huc_to_i915(huc);
+	int ret;
+
+	ret = __intel_wait_for_register(&i915->uncore,
+					GEN11_HUC_KERNEL_LOAD_INFO,
+					HUC_LOAD_SUCCESSFUL,
+					HUC_LOAD_SUCCESSFUL,
+					2, 50, NULL);
+	return ret;
+}
+
+static int huc_wait_verified(struct intel_huc *huc)
+{
+	struct drm_i915_private *i915 = huc_to_i915(huc);
+	int ret;
+
+	if (INTEL_GEN(i915) >= 11)
+		ret = gen11_huc_wait_verified(huc);
+	else
+		ret = gen8_huc_wait_verified(huc);
+	return ret;
+}
+
 /**
  * intel_huc_auth() - Authenticate HuC uCode
  * @huc: intel_huc structure
@@ -56,7 +97,6 @@ int intel_huc_auth(struct intel_huc *huc)
 	struct drm_i915_private *i915 = huc_to_i915(huc);
 	struct intel_guc *guc = &i915->guc;
 	struct i915_vma *vma;
-	u32 status;
 	int ret;
 
 	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
@@ -79,13 +119,9 @@ int intel_huc_auth(struct intel_huc *huc)
 	}
 
 	/* Check authentication status, it should be done by now */
-	ret = __intel_wait_for_register(&i915->uncore,
-					HUC_STATUS2,
-					HUC_FW_VERIFIED,
-					HUC_FW_VERIFIED,
-					2, 50, &status);
+	ret = huc_wait_verified(huc);
 	if (ret) {
-		DRM_ERROR("HuC: Firmware not verified %#x\n", status);
+		DRM_ERROR("HuC: Firmware not verified %d\n", ret);
 		goto fail_unpin;
 	}
 
@@ -122,7 +158,11 @@ int intel_huc_check_status(struct intel_huc *huc)
 		return -ENODEV;
 
 	with_intel_runtime_pm(dev_priv, wakeref)
-		status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+		if (INTEL_GEN(dev_priv) >= 11)
+			status = I915_READ(GEN11_HUC_KERNEL_LOAD_INFO) &
+				HUC_LOAD_SUCCESSFUL;
+		else
+			status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 
 	return status;
 }
-- 
2.19.2

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Re: [PATCH v2 15/22] drm/i915/huc: New HuC status register for Gen11

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> Gen11 defines new register for checking HuC authentication status.
> Look into the right register and bit.
> 
> BSpec: 19686
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_reg.h |  3 ++
>   drivers/gpu/drm/i915/intel_huc.c     | 56 ++++++++++++++++++++++++----
>   2 files changed, 51 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index d26de5193568..7eba65795b58 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -79,6 +79,9 @@
>   #define HUC_STATUS2             _MMIO(0xD3B0)
>   #define   HUC_FW_VERIFIED       (1<<7)
>   
> +#define GEN11_HUC_KERNEL_LOAD_INFO	_MMIO(0xC1DC)
> +#define   HUC_LOAD_SUCCESSFUL		  (1 << 0)
> +
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
>   #define   GUC_WOPCM_SIZE_LOCKED		  (1<<0)
>   #define   GUC_WOPCM_SIZE_SHIFT		12
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index 94c04f16a2ad..708a4b387259 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -40,6 +40,47 @@ int intel_huc_init_misc(struct intel_huc *huc)
>   	return 0;
>   }
>   
> +static int gen8_huc_wait_verified(struct intel_huc *huc)

why gen8?

> +{
> +	struct drm_i915_private *i915 = huc_to_i915(huc);
> +	u32 status;
> +	int ret;
> +
> +	ret = __intel_wait_for_register(&i915->uncore,
> +					HUC_STATUS2,
> +					HUC_FW_VERIFIED,
> +					HUC_FW_VERIFIED,
> +					2, 50, &status);
> +	if (ret)
> +		DRM_ERROR("HuC: status %#x\n", status);
> +	return ret;
> +}
> +
> +static int gen11_huc_wait_verified(struct intel_huc *huc)
> +{
> +	struct drm_i915_private *i915 = huc_to_i915(huc);
> +	int ret;
> +
> +	ret = __intel_wait_for_register(&i915->uncore,
> +					GEN11_HUC_KERNEL_LOAD_INFO,
> +					HUC_LOAD_SUCCESSFUL,
> +					HUC_LOAD_SUCCESSFUL,
> +					2, 50, NULL);
> +	return ret;
> +}
> +
> +static int huc_wait_verified(struct intel_huc *huc)

We do call this only once, so maybe we can just avoid having a separate 
function and just have it directly in intel_huc_auth? the code is simple 
enough. Otherwise, to avoid 2 identical functions which diff only in the 
register details, we could save the register and the expected value in 
the huc struct during init_early and just wait on (huc->auth.reg & 
huc->auth.mask), which we could also use in intel_huc_check_status().

Apart from this, register values do match the FW and the specs.

Daniele

> +{
> +	struct drm_i915_private *i915 = huc_to_i915(huc);
> +	int ret;
> +
> +	if (INTEL_GEN(i915) >= 11)
> +		ret = gen11_huc_wait_verified(huc);
> +	else
> +		ret = gen8_huc_wait_verified(huc);
> +	return ret;
> +}
> +
>   /**
>    * intel_huc_auth() - Authenticate HuC uCode
>    * @huc: intel_huc structure
> @@ -56,7 +97,6 @@ int intel_huc_auth(struct intel_huc *huc)
>   	struct drm_i915_private *i915 = huc_to_i915(huc);
>   	struct intel_guc *guc = &i915->guc;
>   	struct i915_vma *vma;
> -	u32 status;
>   	int ret;
>   
>   	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
> @@ -79,13 +119,9 @@ int intel_huc_auth(struct intel_huc *huc)
>   	}
>   
>   	/* Check authentication status, it should be done by now */
> -	ret = __intel_wait_for_register(&i915->uncore,
> -					HUC_STATUS2,
> -					HUC_FW_VERIFIED,
> -					HUC_FW_VERIFIED,
> -					2, 50, &status);
> +	ret = huc_wait_verified(huc);
>   	if (ret) {
> -		DRM_ERROR("HuC: Firmware not verified %#x\n", status);
> +		DRM_ERROR("HuC: Firmware not verified %d\n", ret);
>   		goto fail_unpin;
>   	}
>   
> @@ -122,7 +158,11 @@ int intel_huc_check_status(struct intel_huc *huc)
>   		return -ENODEV;
>   
>   	with_intel_runtime_pm(dev_priv, wakeref)
> -		status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> +		if (INTEL_GEN(dev_priv) >= 11)
> +			status = I915_READ(GEN11_HUC_KERNEL_LOAD_INFO) &
> +				HUC_LOAD_SUCCESSFUL;
> +		else
> +			status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
>   
>   	return status;
>   }
> 
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Re: [PATCH v2 15/22] drm/i915/huc: New HuC status register for Gen11

[Michal Wajdeczko]

On Mon, 15 Apr 2019 23:19:40 +0200, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

>
>
> On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
>> Gen11 defines new register for checking HuC authentication status.
>> Look into the right register and bit.
>>  BSpec: 19686
>>  Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Tony Ye <tony.ye@intel.com>
>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> Cc: John Spotswood <john.a.spotswood@intel.com>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_guc_reg.h |  3 ++
>>   drivers/gpu/drm/i915/intel_huc.c     | 56 ++++++++++++++++++++++++----
>>   2 files changed, 51 insertions(+), 8 deletions(-)
>>  diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h  
>> b/drivers/gpu/drm/i915/intel_guc_reg.h
>> index d26de5193568..7eba65795b58 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
>> @@ -79,6 +79,9 @@
>>   #define HUC_STATUS2             _MMIO(0xD3B0)
>>   #define   HUC_FW_VERIFIED       (1<<7)
>>   +#define GEN11_HUC_KERNEL_LOAD_INFO	_MMIO(0xC1DC)
>> +#define   HUC_LOAD_SUCCESSFUL		  (1 << 0)
>> +
>>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
>>   #define   GUC_WOPCM_SIZE_LOCKED		  (1<<0)
>>   #define   GUC_WOPCM_SIZE_SHIFT		12
>> diff --git a/drivers/gpu/drm/i915/intel_huc.c  
>> b/drivers/gpu/drm/i915/intel_huc.c
>> index 94c04f16a2ad..708a4b387259 100644
>> --- a/drivers/gpu/drm/i915/intel_huc.c
>> +++ b/drivers/gpu/drm/i915/intel_huc.c
>> @@ -40,6 +40,47 @@ int intel_huc_init_misc(struct intel_huc *huc)
>>   	return 0;
>>   }
>>   +static int gen8_huc_wait_verified(struct intel_huc *huc)
>
> why gen8?
>
>> +{
>> +	struct drm_i915_private *i915 = huc_to_i915(huc);
>> +	u32 status;
>> +	int ret;
>> +
>> +	ret = __intel_wait_for_register(&i915->uncore,
>> +					HUC_STATUS2,
>> +					HUC_FW_VERIFIED,
>> +					HUC_FW_VERIFIED,
>> +					2, 50, &status);
>> +	if (ret)
>> +		DRM_ERROR("HuC: status %#x\n", status);
>> +	return ret;
>> +}
>> +
>> +static int gen11_huc_wait_verified(struct intel_huc *huc)
>> +{
>> +	struct drm_i915_private *i915 = huc_to_i915(huc);
>> +	int ret;
>> +
>> +	ret = __intel_wait_for_register(&i915->uncore,
>> +					GEN11_HUC_KERNEL_LOAD_INFO,
>> +					HUC_LOAD_SUCCESSFUL,
>> +					HUC_LOAD_SUCCESSFUL,
>> +					2, 50, NULL);
>> +	return ret;
>> +}
>> +
>> +static int huc_wait_verified(struct intel_huc *huc)
>
> We do call this only once, so maybe we can just avoid having a separate  
> function and just have it directly in intel_huc_auth? the code is simple  
> enough. Otherwise, to avoid 2 identical functions which diff only in the  
> register details,

There was one small diff: in case of timeout, pre-gen11 variant was  
printing
whole HuC status value. But maybe we don't care any more...

> we could save the register and the expected value in the huc struct  
> during init_early and just wait on (huc->auth.reg & huc->auth.mask),  
> which we could also use in intel_huc_check_status().

To be more future ready, we should store reg/mask/value tuple.

Btw, is it ok that intel_huc_check_status() will now return different
values depending on gen (was 1<<7, now 1<<0) for status ?

Note that intel_huc_check_status() is used directly in  
I915_PARAM_HUC_STATUS.
Maybe we should try to unify these and always return just 0 and fixed 1 ?
Does it count as uABI change ?

>
> Apart from this, register values do match the FW and the specs.
>
> Daniele
>
>> +{
>> +	struct drm_i915_private *i915 = huc_to_i915(huc);
>> +	int ret;
>> +
>> +	if (INTEL_GEN(i915) >= 11)
>> +		ret = gen11_huc_wait_verified(huc);
>> +	else
>> +		ret = gen8_huc_wait_verified(huc);
>> +	return ret;
>> +}
>> +
>>   /**
>>    * intel_huc_auth() - Authenticate HuC uCode
>>    * @huc: intel_huc structure
>> @@ -56,7 +97,6 @@ int intel_huc_auth(struct intel_huc *huc)
>>   	struct drm_i915_private *i915 = huc_to_i915(huc);
>>   	struct intel_guc *guc = &i915->guc;
>>   	struct i915_vma *vma;
>> -	u32 status;
>>   	int ret;
>>     	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>> @@ -79,13 +119,9 @@ int intel_huc_auth(struct intel_huc *huc)
>>   	}
>>     	/* Check authentication status, it should be done by now */
>> -	ret = __intel_wait_for_register(&i915->uncore,
>> -					HUC_STATUS2,
>> -					HUC_FW_VERIFIED,
>> -					HUC_FW_VERIFIED,
>> -					2, 50, &status);
>> +	ret = huc_wait_verified(huc);
>>   	if (ret) {
>> -		DRM_ERROR("HuC: Firmware not verified %#x\n", status);
>> +		DRM_ERROR("HuC: Firmware not verified %d\n", ret);
>>   		goto fail_unpin;
>>   	}
>>   @@ -122,7 +158,11 @@ int intel_huc_check_status(struct intel_huc *huc)
>>   		return -ENODEV;
>>     	with_intel_runtime_pm(dev_priv, wakeref)
>> -		status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
>> +		if (INTEL_GEN(dev_priv) >= 11)
>> +			status = I915_READ(GEN11_HUC_KERNEL_LOAD_INFO) &
>> +				HUC_LOAD_SUCCESSFUL;
>> +		else
>> +			status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
>>     	return status;
>>   }
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Re: [PATCH v2 15/22] drm/i915/huc: New HuC status register for Gen11

[Daniele Ceraolo Spurio]

On 4/15/19 2:44 PM, Michal Wajdeczko wrote:
> On Mon, 15 Apr 2019 23:19:40 +0200, Daniele Ceraolo Spurio 
> <daniele.ceraolospurio@intel.com> wrote:
> 
>>
>>
>> On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
>>> Gen11 defines new register for checking HuC authentication status.
>>> Look into the right register and bit.
>>>  BSpec: 19686
>>>  Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Cc: Tony Ye <tony.ye@intel.com>
>>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>> Cc: John Spotswood <john.a.spotswood@intel.com>
>>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_guc_reg.h |  3 ++
>>>   drivers/gpu/drm/i915/intel_huc.c     | 56 ++++++++++++++++++++++++----
>>>   2 files changed, 51 insertions(+), 8 deletions(-)
>>>  diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h 
>>> b/drivers/gpu/drm/i915/intel_guc_reg.h
>>> index d26de5193568..7eba65795b58 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
>>> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
>>> @@ -79,6 +79,9 @@
>>>   #define HUC_STATUS2             _MMIO(0xD3B0)
>>>   #define   HUC_FW_VERIFIED       (1<<7)
>>>   +#define GEN11_HUC_KERNEL_LOAD_INFO    _MMIO(0xC1DC)
>>> +#define   HUC_LOAD_SUCCESSFUL          (1 << 0)
>>> +
>>>   #define GUC_WOPCM_SIZE            _MMIO(0xc050)
>>>   #define   GUC_WOPCM_SIZE_LOCKED          (1<<0)
>>>   #define   GUC_WOPCM_SIZE_SHIFT        12
>>> diff --git a/drivers/gpu/drm/i915/intel_huc.c 
>>> b/drivers/gpu/drm/i915/intel_huc.c
>>> index 94c04f16a2ad..708a4b387259 100644
>>> --- a/drivers/gpu/drm/i915/intel_huc.c
>>> +++ b/drivers/gpu/drm/i915/intel_huc.c
>>> @@ -40,6 +40,47 @@ int intel_huc_init_misc(struct intel_huc *huc)
>>>       return 0;
>>>   }
>>>   +static int gen8_huc_wait_verified(struct intel_huc *huc)
>>
>> why gen8?
>>
>>> +{
>>> +    struct drm_i915_private *i915 = huc_to_i915(huc);
>>> +    u32 status;
>>> +    int ret;
>>> +
>>> +    ret = __intel_wait_for_register(&i915->uncore,
>>> +                    HUC_STATUS2,
>>> +                    HUC_FW_VERIFIED,
>>> +                    HUC_FW_VERIFIED,
>>> +                    2, 50, &status);
>>> +    if (ret)
>>> +        DRM_ERROR("HuC: status %#x\n", status);
>>> +    return ret;
>>> +}
>>> +
>>> +static int gen11_huc_wait_verified(struct intel_huc *huc)
>>> +{
>>> +    struct drm_i915_private *i915 = huc_to_i915(huc);
>>> +    int ret;
>>> +
>>> +    ret = __intel_wait_for_register(&i915->uncore,
>>> +                    GEN11_HUC_KERNEL_LOAD_INFO,
>>> +                    HUC_LOAD_SUCCESSFUL,
>>> +                    HUC_LOAD_SUCCESSFUL,
>>> +                    2, 50, NULL);
>>> +    return ret;
>>> +}
>>> +
>>> +static int huc_wait_verified(struct intel_huc *huc)
>>
>> We do call this only once, so maybe we can just avoid having a 
>> separate function and just have it directly in intel_huc_auth? the 
>> code is simple enough. Otherwise, to avoid 2 identical functions which 
>> diff only in the register details,
> 
> There was one small diff: in case of timeout, pre-gen11 variant was 
> printing
> whole HuC status value. But maybe we don't care any more...

AFAICS the other bits in the pre-gen11 register are unrelated to 
authentication, so there isn't really any value in printing that on an 
auth fail. Some of the bits are loading failure related, so we could 
think about printing the register if the dma fails.

> 
>> we could save the register and the expected value in the huc struct 
>> during init_early and just wait on (huc->auth.reg & huc->auth.mask), 
>> which we could also use in intel_huc_check_status().
> 
> To be more future ready, we should store reg/mask/value tuple.
> 
> Btw, is it ok that intel_huc_check_status() will now return different
> values depending on gen (was 1<<7, now 1<<0) for status ?
> 
> Note that intel_huc_check_status() is used directly in 
> I915_PARAM_HUC_STATUS.
> Maybe we should try to unify these and always return just 0 and fixed 1 ?
> Does it count as uABI change ?
> 

It is in theory an ABI change, but the documentation above 
intel_huc_check_status says:

  * Returns: 1 if HuC firmware is loaded and verified,
  * 0 if HuC firmware is not loaded and -ENODEV if HuC
  * is not present on this platform.

So I'm guessing there is already a disconnect between expectation and 
actual returned value. I doubt anyone is using the parameter as 
something different than a bool so we should be able to get away with 
"fixing" the ABI like we did with other calls in the past, but we should 
double-check with the user the call was added for.

Daniele

>>
>> Apart from this, register values do match the FW and the specs.
>>
>> Daniele
>>
>>> +{
>>> +    struct drm_i915_private *i915 = huc_to_i915(huc);
>>> +    int ret;
>>> +
>>> +    if (INTEL_GEN(i915) >= 11)
>>> +        ret = gen11_huc_wait_verified(huc);
>>> +    else
>>> +        ret = gen8_huc_wait_verified(huc);
>>> +    return ret;
>>> +}
>>> +
>>>   /**
>>>    * intel_huc_auth() - Authenticate HuC uCode
>>>    * @huc: intel_huc structure
>>> @@ -56,7 +97,6 @@ int intel_huc_auth(struct intel_huc *huc)
>>>       struct drm_i915_private *i915 = huc_to_i915(huc);
>>>       struct intel_guc *guc = &i915->guc;
>>>       struct i915_vma *vma;
>>> -    u32 status;
>>>       int ret;
>>>         if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>>> @@ -79,13 +119,9 @@ int intel_huc_auth(struct intel_huc *huc)
>>>       }
>>>         /* Check authentication status, it should be done by now */
>>> -    ret = __intel_wait_for_register(&i915->uncore,
>>> -                    HUC_STATUS2,
>>> -                    HUC_FW_VERIFIED,
>>> -                    HUC_FW_VERIFIED,
>>> -                    2, 50, &status);
>>> +    ret = huc_wait_verified(huc);
>>>       if (ret) {
>>> -        DRM_ERROR("HuC: Firmware not verified %#x\n", status);
>>> +        DRM_ERROR("HuC: Firmware not verified %d\n", ret);
>>>           goto fail_unpin;
>>>       }
>>>   @@ -122,7 +158,11 @@ int intel_huc_check_status(struct intel_huc *huc)
>>>           return -ENODEV;
>>>         with_intel_runtime_pm(dev_priv, wakeref)
>>> -        status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
>>> +        if (INTEL_GEN(dev_priv) >= 11)
>>> +            status = I915_READ(GEN11_HUC_KERNEL_LOAD_INFO) &
>>> +                HUC_LOAD_SUCCESSFUL;
>>> +        else
>>> +            status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
>>>         return status;
>>>   }
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Re: [PATCH v2 15/22] drm/i915/huc: New HuC status register for Gen11

[Daniele Ceraolo Spurio]

On 4/15/19 3:10 PM, Daniele Ceraolo Spurio wrote:
> 
> 
> On 4/15/19 2:44 PM, Michal Wajdeczko wrote:
>> On Mon, 15 Apr 2019 23:19:40 +0200, Daniele Ceraolo Spurio 
>> <daniele.ceraolospurio@intel.com> wrote:
>>
>>>
>>>
>>> On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
>>>> Gen11 defines new register for checking HuC authentication status.
>>>> Look into the right register and bit.
>>>>  BSpec: 19686
>>>>  Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> Cc: Tony Ye <tony.ye@intel.com>
>>>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>>> Cc: John Spotswood <john.a.spotswood@intel.com>
>>>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/intel_guc_reg.h |  3 ++
>>>>   drivers/gpu/drm/i915/intel_huc.c     | 56 
>>>> ++++++++++++++++++++++++----
>>>>   2 files changed, 51 insertions(+), 8 deletions(-)
>>>>  diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h 
>>>> b/drivers/gpu/drm/i915/intel_guc_reg.h
>>>> index d26de5193568..7eba65795b58 100644
>>>> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
>>>> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
>>>> @@ -79,6 +79,9 @@
>>>>   #define HUC_STATUS2             _MMIO(0xD3B0)
>>>>   #define   HUC_FW_VERIFIED       (1<<7)
>>>>   +#define GEN11_HUC_KERNEL_LOAD_INFO    _MMIO(0xC1DC)
>>>> +#define   HUC_LOAD_SUCCESSFUL          (1 << 0)
>>>> +
>>>>   #define GUC_WOPCM_SIZE            _MMIO(0xc050)
>>>>   #define   GUC_WOPCM_SIZE_LOCKED          (1<<0)
>>>>   #define   GUC_WOPCM_SIZE_SHIFT        12
>>>> diff --git a/drivers/gpu/drm/i915/intel_huc.c 
>>>> b/drivers/gpu/drm/i915/intel_huc.c
>>>> index 94c04f16a2ad..708a4b387259 100644
>>>> --- a/drivers/gpu/drm/i915/intel_huc.c
>>>> +++ b/drivers/gpu/drm/i915/intel_huc.c
>>>> @@ -40,6 +40,47 @@ int intel_huc_init_misc(struct intel_huc *huc)
>>>>       return 0;
>>>>   }
>>>>   +static int gen8_huc_wait_verified(struct intel_huc *huc)
>>>
>>> why gen8?
>>>
>>>> +{
>>>> +    struct drm_i915_private *i915 = huc_to_i915(huc);
>>>> +    u32 status;
>>>> +    int ret;
>>>> +
>>>> +    ret = __intel_wait_for_register(&i915->uncore,
>>>> +                    HUC_STATUS2,
>>>> +                    HUC_FW_VERIFIED,
>>>> +                    HUC_FW_VERIFIED,
>>>> +                    2, 50, &status);
>>>> +    if (ret)
>>>> +        DRM_ERROR("HuC: status %#x\n", status);
>>>> +    return ret;
>>>> +}
>>>> +
>>>> +static int gen11_huc_wait_verified(struct intel_huc *huc)
>>>> +{
>>>> +    struct drm_i915_private *i915 = huc_to_i915(huc);
>>>> +    int ret;
>>>> +
>>>> +    ret = __intel_wait_for_register(&i915->uncore,
>>>> +                    GEN11_HUC_KERNEL_LOAD_INFO,
>>>> +                    HUC_LOAD_SUCCESSFUL,
>>>> +                    HUC_LOAD_SUCCESSFUL,
>>>> +                    2, 50, NULL);
>>>> +    return ret;
>>>> +}
>>>> +
>>>> +static int huc_wait_verified(struct intel_huc *huc)
>>>
>>> We do call this only once, so maybe we can just avoid having a 
>>> separate function and just have it directly in intel_huc_auth? the 
>>> code is simple enough. Otherwise, to avoid 2 identical functions 
>>> which diff only in the register details,
>>
>> There was one small diff: in case of timeout, pre-gen11 variant was 
>> printing
>> whole HuC status value. But maybe we don't care any more...
> 
> AFAICS the other bits in the pre-gen11 register are unrelated to 
> authentication, so there isn't really any value in printing that on an 
> auth fail. Some of the bits are loading failure related, so we could 
> think about printing the register if the dma fails.
> 
>>
>>> we could save the register and the expected value in the huc struct 
>>> during init_early and just wait on (huc->auth.reg & huc->auth.mask), 
>>> which we could also use in intel_huc_check_status().
>>
>> To be more future ready, we should store reg/mask/value tuple.
>>
>> Btw, is it ok that intel_huc_check_status() will now return different
>> values depending on gen (was 1<<7, now 1<<0) for status ?
>>
>> Note that intel_huc_check_status() is used directly in 
>> I915_PARAM_HUC_STATUS.
>> Maybe we should try to unify these and always return just 0 and fixed 1 ?
>> Does it count as uABI change ?
>>
> 
> It is in theory an ABI change, but the documentation above 
> intel_huc_check_status says:
> 
>   * Returns: 1 if HuC firmware is loaded and verified,
>   * 0 if HuC firmware is not loaded and -ENODEV if HuC
>   * is not present on this platform.
> 
> So I'm guessing there is already a disconnect between expectation and 
> actual returned value. I doubt anyone is using the parameter as 
> something different than a bool so we should be able to get away with 
> "fixing" the ABI like we did with other calls in the past, but we should 
> double-check with the user the call was added for.
> 

Scratch this, the status variable that we return is a bool, so the 
result should already be  automatically casted to the appropriate value 
(0 or 1).

Daniele

> Daniele
> 
>>>
>>> Apart from this, register values do match the FW and the specs.
>>>
>>> Daniele
>>>
>>>> +{
>>>> +    struct drm_i915_private *i915 = huc_to_i915(huc);
>>>> +    int ret;
>>>> +
>>>> +    if (INTEL_GEN(i915) >= 11)
>>>> +        ret = gen11_huc_wait_verified(huc);
>>>> +    else
>>>> +        ret = gen8_huc_wait_verified(huc);
>>>> +    return ret;
>>>> +}
>>>> +
>>>>   /**
>>>>    * intel_huc_auth() - Authenticate HuC uCode
>>>>    * @huc: intel_huc structure
>>>> @@ -56,7 +97,6 @@ int intel_huc_auth(struct intel_huc *huc)
>>>>       struct drm_i915_private *i915 = huc_to_i915(huc);
>>>>       struct intel_guc *guc = &i915->guc;
>>>>       struct i915_vma *vma;
>>>> -    u32 status;
>>>>       int ret;
>>>>         if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>>>> @@ -79,13 +119,9 @@ int intel_huc_auth(struct intel_huc *huc)
>>>>       }
>>>>         /* Check authentication status, it should be done by now */
>>>> -    ret = __intel_wait_for_register(&i915->uncore,
>>>> -                    HUC_STATUS2,
>>>> -                    HUC_FW_VERIFIED,
>>>> -                    HUC_FW_VERIFIED,
>>>> -                    2, 50, &status);
>>>> +    ret = huc_wait_verified(huc);
>>>>       if (ret) {
>>>> -        DRM_ERROR("HuC: Firmware not verified %#x\n", status);
>>>> +        DRM_ERROR("HuC: Firmware not verified %d\n", ret);
>>>>           goto fail_unpin;
>>>>       }
>>>>   @@ -122,7 +158,11 @@ int intel_huc_check_status(struct intel_huc 
>>>> *huc)
>>>>           return -ENODEV;
>>>>         with_intel_runtime_pm(dev_priv, wakeref)
>>>> -        status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
>>>> +        if (INTEL_GEN(dev_priv) >= 11)
>>>> +            status = I915_READ(GEN11_HUC_KERNEL_LOAD_INFO) &
>>>> +                HUC_LOAD_SUCCESSFUL;
>>>> +        else
>>>> +            status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
>>>>         return status;
>>>>   }
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[PATCH v2 16/22] drm/i915/guc: Create vfuncs for the GuC interrupts control functions

[Michal Wajdeczko]

From: Oscar Mateo <oscar.mateo@intel.com>

Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_irq.c  | 18 ++++++++++++------
 drivers/gpu/drm/i915/intel_drv.h |  3 ---
 drivers/gpu/drm/i915/intel_guc.h |  1 -
 drivers/gpu/drm/i915/intel_uc.c  |  6 +++---
 5 files changed, 37 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 35d0782c077e..6c5260d91bc1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1574,6 +1574,13 @@ struct drm_i915_private {
 	u32 pm_guc_events;
 	u32 pipestat_irq_mask[I915_MAX_PIPES];
 
+	struct {
+		bool enabled;
+		void (*reset)(struct drm_i915_private *i915);
+		void (*enable)(struct drm_i915_private *i915);
+		void (*disable)(struct drm_i915_private *i915);
+	} guc_interrupts;
+
 	struct i915_hotplug hotplug;
 	struct intel_fbc fbc;
 	struct i915_drrs drrs;
@@ -2753,6 +2760,21 @@ extern void intel_irq_fini(struct drm_i915_private *dev_priv);
 int intel_irq_install(struct drm_i915_private *dev_priv);
 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
 
+static inline void intel_reset_guc_interrupts(struct drm_i915_private *i915)
+{
+	i915->guc_interrupts.reset(i915);
+}
+
+static inline void intel_enable_guc_interrupts(struct drm_i915_private *i915)
+{
+	i915->guc_interrupts.enable(i915);
+}
+
+static inline void intel_disable_guc_interrupts(struct drm_i915_private *i915)
+{
+	i915->guc_interrupts.disable(i915);
+}
+
 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
 {
 	return dev_priv->gvt;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d934545445e1..e2f0cbee9345 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -554,7 +554,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 		gen6_reset_rps_interrupts(dev_priv);
 }
 
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	assert_rpm_wakelock_held(dev_priv);
 
@@ -563,26 +563,26 @@ void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	assert_rpm_wakelock_held(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	if (!dev_priv->guc.interrupts_enabled) {
+	if (!dev_priv->guc_interrupts.enabled) {
 		WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 				       dev_priv->pm_guc_events);
-		dev_priv->guc.interrupts_enabled = true;
+		dev_priv->guc_interrupts.enabled = true;
 		gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 	}
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	assert_rpm_wakelock_held(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	dev_priv->guc.interrupts_enabled = false;
+	dev_priv->guc_interrupts.enabled = false;
 
 	gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 
@@ -4673,6 +4673,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 8)
 		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
+	if (INTEL_GEN(dev_priv) >= 9) {
+		dev_priv->guc_interrupts.reset = gen9_reset_guc_interrupts;
+		dev_priv->guc_interrupts.enable = gen9_enable_guc_interrupts;
+		dev_priv->guc_interrupts.disable = gen9_disable_guc_interrupts;
+	}
+
 	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
 		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
 	else if (INTEL_GEN(dev_priv) >= 3)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a38b9cff5cd0..9b6cac90e891 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1627,9 +1627,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
 
 /* intel_display.c */
 void intel_plane_destroy(struct drm_plane *plane);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4f3cf8eddfe6..0371b8f30930 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -56,7 +56,6 @@ struct intel_guc {
 
 	/* intel_guc_recv interrupt related state */
 	spinlock_t irq_lock;
-	bool interrupts_enabled;
 	unsigned int msg_enabled_mask;
 
 	struct i915_vma *ads_vma;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 03bc2a0ee34b..a1a068511fd9 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -219,7 +219,7 @@ static int guc_enable_communication(struct intel_guc *guc)
 {
 	struct drm_i915_private *i915 = guc_to_i915(guc);
 
-	gen9_enable_guc_interrupts(i915);
+	intel_enable_guc_interrupts(i915);
 
 	if (HAS_GUC_CT(i915))
 		return intel_guc_ct_enable(&guc->ct);
@@ -236,7 +236,7 @@ static void guc_disable_communication(struct intel_guc *guc)
 	if (HAS_GUC_CT(i915))
 		intel_guc_ct_disable(&guc->ct);
 
-	gen9_disable_guc_interrupts(i915);
+	intel_disable_guc_interrupts(i915);
 
 	guc->send = intel_guc_send_nop;
 	guc->handler = intel_guc_to_host_event_handler_nop;
@@ -358,7 +358,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
 
 	GEM_BUG_ON(!HAS_GUC(i915));
 
-	gen9_reset_guc_interrupts(i915);
+	intel_reset_guc_interrupts(i915);
 
 	/* WaEnableuKernelHeaderValidFix:skl */
 	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
-- 
2.19.2

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Re: [PATCH v2 16/22] drm/i915/guc: Create vfuncs for the GuC interrupts control functions

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> From: Oscar Mateo <oscar.mateo@intel.com>
> 
> Controlling and handling of the GuC interrupts is Gen specific.
> Create virtual functions to avoid redundant runtime Gen checks.
> Gen-specific versions of these functions will follow.
> 
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h  | 22 ++++++++++++++++++++++
>   drivers/gpu/drm/i915/i915_irq.c  | 18 ++++++++++++------
>   drivers/gpu/drm/i915/intel_drv.h |  3 ---
>   drivers/gpu/drm/i915/intel_guc.h |  1 -
>   drivers/gpu/drm/i915/intel_uc.c  |  6 +++---
>   5 files changed, 37 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 35d0782c077e..6c5260d91bc1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1574,6 +1574,13 @@ struct drm_i915_private {
>   	u32 pm_guc_events;
>   	u32 pipestat_irq_mask[I915_MAX_PIPES];
>   
> +	struct {
> +		bool enabled;
> +		void (*reset)(struct drm_i915_private *i915);
> +		void (*enable)(struct drm_i915_private *i915);
> +		void (*disable)(struct drm_i915_private *i915);
> +	} guc_interrupts;
> +

I would put those under the guc structure since they're guc-specific 
functions. With that:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

>   	struct i915_hotplug hotplug;
>   	struct intel_fbc fbc;
>   	struct i915_drrs drrs;
> @@ -2753,6 +2760,21 @@ extern void intel_irq_fini(struct drm_i915_private *dev_priv);
>   int intel_irq_install(struct drm_i915_private *dev_priv);
>   void intel_irq_uninstall(struct drm_i915_private *dev_priv);
>   
> +static inline void intel_reset_guc_interrupts(struct drm_i915_private *i915)
> +{
> +	i915->guc_interrupts.reset(i915);
> +}
> +
> +static inline void intel_enable_guc_interrupts(struct drm_i915_private *i915)
> +{
> +	i915->guc_interrupts.enable(i915);
> +}
> +
> +static inline void intel_disable_guc_interrupts(struct drm_i915_private *i915)
> +{
> +	i915->guc_interrupts.disable(i915);
> +}
> +
>   static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
>   {
>   	return dev_priv->gvt;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d934545445e1..e2f0cbee9345 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -554,7 +554,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
>   		gen6_reset_rps_interrupts(dev_priv);
>   }
>   
> -void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
> +static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
>   {
>   	assert_rpm_wakelock_held(dev_priv);
>   
> @@ -563,26 +563,26 @@ void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
>   	spin_unlock_irq(&dev_priv->irq_lock);
>   }
>   
> -void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
> +static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
>   {
>   	assert_rpm_wakelock_held(dev_priv);
>   
>   	spin_lock_irq(&dev_priv->irq_lock);
> -	if (!dev_priv->guc.interrupts_enabled) {
> +	if (!dev_priv->guc_interrupts.enabled) {
>   		WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
>   				       dev_priv->pm_guc_events);
> -		dev_priv->guc.interrupts_enabled = true;
> +		dev_priv->guc_interrupts.enabled = true;
>   		gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
>   	}
>   	spin_unlock_irq(&dev_priv->irq_lock);
>   }
>   
> -void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
> +static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
>   {
>   	assert_rpm_wakelock_held(dev_priv);
>   
>   	spin_lock_irq(&dev_priv->irq_lock);
> -	dev_priv->guc.interrupts_enabled = false;
> +	dev_priv->guc_interrupts.enabled = false;
>   
>   	gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
>   
> @@ -4673,6 +4673,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>   	if (INTEL_GEN(dev_priv) >= 8)
>   		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>   
> +	if (INTEL_GEN(dev_priv) >= 9) {
> +		dev_priv->guc_interrupts.reset = gen9_reset_guc_interrupts;
> +		dev_priv->guc_interrupts.enable = gen9_enable_guc_interrupts;
> +		dev_priv->guc_interrupts.disable = gen9_disable_guc_interrupts;
> +	}
> +
>   	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
>   		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
>   	else if (INTEL_GEN(dev_priv) >= 3)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a38b9cff5cd0..9b6cac90e891 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1627,9 +1627,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>   				     u8 pipe_mask);
>   void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
>   				     u8 pipe_mask);
> -void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
> -void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
> -void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
>   
>   /* intel_display.c */
>   void intel_plane_destroy(struct drm_plane *plane);
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 4f3cf8eddfe6..0371b8f30930 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -56,7 +56,6 @@ struct intel_guc {
>   
>   	/* intel_guc_recv interrupt related state */
>   	spinlock_t irq_lock;
> -	bool interrupts_enabled;
>   	unsigned int msg_enabled_mask;
>   
>   	struct i915_vma *ads_vma;
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 03bc2a0ee34b..a1a068511fd9 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -219,7 +219,7 @@ static int guc_enable_communication(struct intel_guc *guc)
>   {
>   	struct drm_i915_private *i915 = guc_to_i915(guc);
>   
> -	gen9_enable_guc_interrupts(i915);
> +	intel_enable_guc_interrupts(i915);
>   
>   	if (HAS_GUC_CT(i915))
>   		return intel_guc_ct_enable(&guc->ct);
> @@ -236,7 +236,7 @@ static void guc_disable_communication(struct intel_guc *guc)
>   	if (HAS_GUC_CT(i915))
>   		intel_guc_ct_disable(&guc->ct);
>   
> -	gen9_disable_guc_interrupts(i915);
> +	intel_disable_guc_interrupts(i915);
>   
>   	guc->send = intel_guc_send_nop;
>   	guc->handler = intel_guc_to_host_event_handler_nop;
> @@ -358,7 +358,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
>   
>   	GEM_BUG_ON(!HAS_GUC(i915));
>   
> -	gen9_reset_guc_interrupts(i915);
> +	intel_reset_guc_interrupts(i915);
>   
>   	/* WaEnableuKernelHeaderValidFix:skl */
>   	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
> 
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[PATCH v2 17/22] drm/i915/guc: Correctly handle GuC interrupts on Gen11

[Michal Wajdeczko]

From: Oscar Mateo <oscar.mateo@intel.com>

The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.

v2: (Chris)
v3: rebased (Michal)
Bspec: 19820

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  6 ++-
 drivers/gpu/drm/i915/i915_irq.c      | 64 ++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_guc_reg.h | 18 ++++++++
 4 files changed, 85 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6c5260d91bc1..973f6c724c36 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1571,7 +1571,11 @@ struct drm_i915_private {
 	u32 pm_imr;
 	u32 pm_ier;
 	u32 pm_rps_events;
-	u32 pm_guc_events;
+	union {
+		/* RPS and GuC share a register pre-Gen11 */
+		u32 pm_guc_events;
+		u32 guc_events;
+	};
 	u32 pipestat_irq_mask[I915_MAX_PIPES];
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2f0cbee9345..5580f00a3d28 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -592,6 +592,41 @@ static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 	gen9_reset_guc_interrupts(dev_priv);
 }
 
+static void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
+{
+	spin_lock_irq(&i915->irq_lock);
+	gen11_reset_one_iir(i915, 0, GEN11_GUC);
+	spin_unlock_irq(&i915->irq_lock);
+}
+
+static void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+	spin_lock_irq(&dev_priv->irq_lock);
+	if (!dev_priv->guc_interrupts.enabled) {
+		u32 guc_events = dev_priv->guc_events << 16;
+
+		WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GUC));
+		I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, guc_events);
+		I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~guc_events);
+		dev_priv->guc_interrupts.enabled = true;
+	}
+	spin_unlock_irq(&dev_priv->irq_lock);
+}
+
+static void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+	spin_lock_irq(&dev_priv->irq_lock);
+	dev_priv->guc_interrupts.enabled = false;
+
+	I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
+	I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+
+	spin_unlock_irq(&dev_priv->irq_lock);
+	synchronize_irq(dev_priv->drm.irq);
+
+	gen11_reset_guc_interrupts(dev_priv);
+}
+
 /**
  * bdw_update_port_irq - update DE port interrupt
  * @dev_priv: driver private
@@ -1861,6 +1896,12 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
 		intel_guc_to_host_event_handler(&dev_priv->guc);
 }
 
+static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
+{
+	if (iir & GEN11_GUC_INTR_GUC2HOST)
+		intel_guc_to_host_event_handler(&i915->guc);
+}
+
 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
 {
 	enum pipe pipe;
@@ -2983,6 +3024,9 @@ static void
 gen11_other_irq_handler(struct drm_i915_private * const i915,
 			const u8 instance, const u16 iir)
 {
+	if (instance == OTHER_GUC_INSTANCE)
+		return gen11_guc_irq_handler(i915, iir);
+
 	if (instance == OTHER_GTPM_INSTANCE)
 		return gen11_rps_irq_handler(i915, iir);
 
@@ -3501,6 +3545,8 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
 
 	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
 	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
+	I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+	I915_WRITE(GEN11_GUC_SG_INTR_MASK,  ~0);
 }
 
 static void gen11_irq_reset(struct drm_device *dev)
@@ -4143,6 +4189,10 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
 	dev_priv->pm_imr = ~dev_priv->pm_ier;
 	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
 	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
+
+	/* Same thing for GuC interrupts */
+	I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+	I915_WRITE(GEN11_GUC_SG_INTR_MASK,  ~0);
 }
 
 static void icp_irq_postinstall(struct drm_device *dev)
@@ -4643,8 +4693,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	for (i = 0; i < MAX_L3_SLICES; ++i)
 		dev_priv->l3_parity.remap_info[i] = NULL;
 
-	if (HAS_GUC_SCHED(dev_priv))
-		dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+	if (HAS_GUC_SCHED(dev_priv)) {
+		if (INTEL_GEN(dev_priv) < 11)
+			dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+		else
+			dev_priv->guc_events = GEN11_GUC_INTR_GUC2HOST;
+	}
 
 	/* Let's track the enabled rps events */
 	if (IS_VALLEYVIEW(dev_priv))
@@ -4673,7 +4727,11 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 8)
 		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (INTEL_GEN(dev_priv) >= 11) {
+		dev_priv->guc_interrupts.reset = gen11_reset_guc_interrupts;
+		dev_priv->guc_interrupts.enable = gen11_enable_guc_interrupts;
+		dev_priv->guc_interrupts.disable = gen11_disable_guc_interrupts;
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		dev_priv->guc_interrupts.reset = gen9_reset_guc_interrupts;
 		dev_priv->guc_interrupts.enable = gen9_enable_guc_interrupts;
 		dev_priv->guc_interrupts.disable = gen9_disable_guc_interrupts;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ad2f0a03f28..26a3ce86dbcf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -290,6 +290,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define OTHER_CLASS		4
 #define MAX_ENGINE_CLASS	4
 
+#define OTHER_GUC_INSTANCE	0
 #define OTHER_GTPM_INSTANCE	1
 #define MAX_ENGINE_INSTANCE    3
 
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 7eba65795b58..a214f8b71929 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -134,4 +134,22 @@ struct guc_doorbell_info {
 #define GUC_WD_VECS_IER			_MMIO(0xC558)
 #define GUC_PM_P24C_IER			_MMIO(0xC55C)
 
+/* GuC Interrupt Vector */
+#define GEN11_GUC_INTR_GUC2HOST		(1 << 15)
+#define GEN11_GUC_INTR_EXEC_ERROR	(1 << 14)
+#define GEN11_GUC_INTR_DISPLAY_EVENT	(1 << 13)
+#define GEN11_GUC_INTR_SEM_SIG		(1 << 12)
+#define GEN11_GUC_INTR_IOMMU2GUC	(1 << 11)
+#define GEN11_GUC_INTR_DOORBELL_RANG	(1 << 10)
+#define GEN11_GUC_INTR_DMA_DONE		(1 <<  9)
+#define GEN11_GUC_INTR_FATAL_ERROR	(1 <<  8)
+#define GEN11_GUC_INTR_NOTIF_ERROR	(1 <<  7)
+#define GEN11_GUC_INTR_SW_INT_6		(1 <<  6)
+#define GEN11_GUC_INTR_SW_INT_5		(1 <<  5)
+#define GEN11_GUC_INTR_SW_INT_4		(1 <<  4)
+#define GEN11_GUC_INTR_SW_INT_3		(1 <<  3)
+#define GEN11_GUC_INTR_SW_INT_2		(1 <<  2)
+#define GEN11_GUC_INTR_SW_INT_1		(1 <<  1)
+#define GEN11_GUC_INTR_SW_INT_0		(1 <<  0)
+
 #endif
-- 
2.19.2

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[PATCH v2 18/22] drm/i915/guc: Update GuC CTB response definition

[Michal Wajdeczko]

Current GuC firmwares identify response message in a different way.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_ct.c   | 2 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index dde1dc0d6e69..2d5dc2aa22a7 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -565,7 +565,7 @@ static inline unsigned int ct_header_get_action(u32 header)
 
 static inline bool ct_header_is_response(u32 header)
 {
-	return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT;
+	return !!(header & GUC_CT_MSG_IS_RESPONSE);
 }
 
 static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 68dfeecf7b26..115c693daf8e 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -361,6 +361,7 @@ struct guc_ct_buffer_desc {
  *
  * bit[4..0]	message len (in dwords)
  * bit[7..5]	reserved
+ * bit[8]	response (G2H only)
  * bit[8]	write fence to desc
  * bit[9]	write status to H2G buff
  * bit[10]	send status (via G2H)
@@ -369,6 +370,7 @@ struct guc_ct_buffer_desc {
  */
 #define GUC_CT_MSG_LEN_SHIFT			0
 #define GUC_CT_MSG_LEN_MASK			0x1F
+#define GUC_CT_MSG_IS_RESPONSE			(1 << 8)
 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC		(1 << 8)
 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF		(1 << 9)
 #define GUC_CT_MSG_SEND_STATUS			(1 << 10)
-- 
2.19.2

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Re: [PATCH v2 18/22] drm/i915/guc: Update GuC CTB response definition

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> Current GuC firmwares identify response message in a different way.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_ct.c   | 2 +-
>   drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
>   2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
> index dde1dc0d6e69..2d5dc2aa22a7 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ct.c
> @@ -565,7 +565,7 @@ static inline unsigned int ct_header_get_action(u32 header)
>   
>   static inline bool ct_header_is_response(u32 header)
>   {
> -	return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT;
> +	return !!(header & GUC_CT_MSG_IS_RESPONSE);
>   }
>   
>   static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 68dfeecf7b26..115c693daf8e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -361,6 +361,7 @@ struct guc_ct_buffer_desc {
>    *
>    * bit[4..0]	message len (in dwords)
>    * bit[7..5]	reserved
> + * bit[8]	response (G2H only)
>    * bit[8]	write fence to desc
>    * bit[9]	write status to H2G buff
>    * bit[10]	send status (via G2H)

The other definition of bit 8 and the defs of bits 9-10 are H2G only, we 
could update this comment to reflect that. With or without the change:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> @@ -369,6 +370,7 @@ struct guc_ct_buffer_desc {
>    */
>   #define GUC_CT_MSG_LEN_SHIFT			0
>   #define GUC_CT_MSG_LEN_MASK			0x1F
> +#define GUC_CT_MSG_IS_RESPONSE			(1 << 8)
>   #define GUC_CT_MSG_WRITE_FENCE_TO_DESC		(1 << 8)
>   #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF		(1 << 9)
>   #define GUC_CT_MSG_SEND_STATUS			(1 << 10)
> 
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[PATCH v2 19/22] drm/i915/guc: Enable GuC CTB communication on Gen11

[Michal Wajdeczko]

Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f893c2cbce15..8af8820b3df8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -743,6 +743,7 @@ static const struct intel_device_info intel_cannonlake_info = {
 	}, \
 	GEN(11), \
 	.ddb_size = 2048, \
+	.has_guc_ct = 1, \
 	.has_logical_ring_elsq = 1, \
 	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
 
-- 
2.19.2

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Re: [PATCH v2 19/22] drm/i915/guc: Enable GuC CTB communication on Gen11

[Daniele Ceraolo Spurio]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> Gen11 GuC firmware expects H2G command messages to be sent over CTB
> (command transport buffers).
> 

Even gen9 blobs can now use CTB, so we can just make the whole CTB 
handling unconditional. I'm ok with doing that as a follow up as this 
series already changes enough things as is.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_pci.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f893c2cbce15..8af8820b3df8 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -743,6 +743,7 @@ static const struct intel_device_info intel_cannonlake_info = {
>   	}, \
>   	GEN(11), \
>   	.ddb_size = 2048, \
> +	.has_guc_ct = 1, \
>   	.has_logical_ring_elsq = 1, \
>   	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
>   
> 
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[PATCH v2 20/22] drm/i915/guc: Define GuC firmware version for Icelake

[Michal Wajdeczko]

Define GuC firmware version for Icelake.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index c937a648c2a1..c88a089885a0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -55,9 +55,16 @@
 #define KBL_GUC_FW_PATCH 3
 #define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
 
+#define ICL_GUC_FW_PREFIX icl
+#define ICL_GUC_FW_MAJOR 32
+#define ICL_GUC_FW_MINOR 0
+#define ICL_GUC_FW_PATCH 3
+#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
+
 MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
 MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
 MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
 
 static void guc_fw_select(struct intel_uc_fw *guc_fw)
 {
@@ -73,6 +80,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
 		guc_fw->path = i915_modparams.guc_firmware_path;
 		guc_fw->major_ver_wanted = 0;
 		guc_fw->minor_ver_wanted = 0;
+	} else if (IS_ICELAKE(i915)) {
+		guc_fw->path = ICL_GUC_FIRMWARE_PATH;
+		guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
+		guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
 	} else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
 		guc_fw->path = KBL_GUC_FIRMWARE_PATH;
 		guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
-- 
2.19.2

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Re: [PATCH v2 20/22] drm/i915/guc: Define GuC firmware version for Icelake

[Srivatsa, Anusha]

>-----Original Message-----
>From: Wajdeczko, Michal
>Sent: Thursday, April 11, 2019 1:45 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Wajdeczko, Michal <Michal.Wajdeczko@intel.com>; Ceraolo Spurio, Daniele
><daniele.ceraolospurio@intel.com>; Joonas Lahtinen
><joonas.lahtinen@linux.intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Subject: [PATCH v2 20/22] drm/i915/guc: Define GuC firmware version for Icelake
>
>Define GuC firmware version for Icelake.
>
>Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Looks good. 
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

>---
> drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
>b/drivers/gpu/drm/i915/intel_guc_fw.c
>index c937a648c2a1..c88a089885a0 100644
>--- a/drivers/gpu/drm/i915/intel_guc_fw.c
>+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
>@@ -55,9 +55,16 @@
> #define KBL_GUC_FW_PATCH 3
> #define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
>
>+#define ICL_GUC_FW_PREFIX icl
>+#define ICL_GUC_FW_MAJOR 32
>+#define ICL_GUC_FW_MINOR 0
>+#define ICL_GUC_FW_PATCH 3
>+#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
>+
> MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
> MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
> MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
>+MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
>
> static void guc_fw_select(struct intel_uc_fw *guc_fw)  { @@ -73,6 +80,10 @@
>static void guc_fw_select(struct intel_uc_fw *guc_fw)
> 		guc_fw->path = i915_modparams.guc_firmware_path;
> 		guc_fw->major_ver_wanted = 0;
> 		guc_fw->minor_ver_wanted = 0;
>+	} else if (IS_ICELAKE(i915)) {
>+		guc_fw->path = ICL_GUC_FIRMWARE_PATH;
>+		guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
>+		guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
> 	} else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
> 		guc_fw->path = KBL_GUC_FIRMWARE_PATH;
> 		guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
>--
>2.19.2

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[PATCH v2 21/22] drm/i915/huc: Define HuC firmware version for Icelake

[Michal Wajdeczko]

This patch adds the support to load HuC on ICL.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
---
 drivers/gpu/drm/i915/intel_huc_fw.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
index 68d47c105939..b8e160dc4621 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
 #define KBL_HUC_FW_MINOR 00
 #define KBL_BLD_NUM 1810
 
+#define ICL_HUC_FW_MAJOR 8
+#define ICL_HUC_FW_MINOR 4
+#define ICL_BLD_NUM 3132
+
 #define HUC_FW_PATH(platform, major, minor, bld_num) \
 	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
 	__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
 	KBL_HUC_FW_MINOR, KBL_BLD_NUM)
 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
 
+#define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
+	ICL_HUC_FW_MINOR, ICL_BLD_NUM)
+MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
+
 static void huc_fw_select(struct intel_uc_fw *huc_fw)
 {
 	struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
 		huc_fw->path = I915_KBL_HUC_UCODE;
 		huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
 		huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+	} else if (IS_ICELAKE(dev_priv)) {
+		huc_fw->path = I915_ICL_HUC_UCODE;
+		huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
+		huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
 	}
 }
 
-- 
2.19.2

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Re: [PATCH v2 21/22] drm/i915/huc: Define HuC firmware version for Icelake

[Ye, Tony]

On 4/11/2019 4:44 PM, Michal Wajdeczko wrote:
> This patch adds the support to load HuC on ICL.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_huc_fw.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
> index 68d47c105939..b8e160dc4621 100644
> --- a/drivers/gpu/drm/i915/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_huc_fw.c
> @@ -34,6 +34,10 @@
>   #define KBL_HUC_FW_MINOR 00
>   #define KBL_BLD_NUM 1810
>   
> +#define ICL_HUC_FW_MAJOR 8
> +#define ICL_HUC_FW_MINOR 4
> +#define ICL_BLD_NUM 3132

There is a new build of ICL HuC FW, icl_huc_ver8_4_3238.bin. Can we 
update with that build?

Regards,

Tony

> +
>   #define HUC_FW_PATH(platform, major, minor, bld_num) \
>   	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
>   	__stringify(minor) "_" __stringify(bld_num) ".bin"
> @@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
>   	KBL_HUC_FW_MINOR, KBL_BLD_NUM)
>   MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
>   
> +#define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
> +	ICL_HUC_FW_MINOR, ICL_BLD_NUM)
> +MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
> +
>   static void huc_fw_select(struct intel_uc_fw *huc_fw)
>   {
>   	struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
> @@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
>   		huc_fw->path = I915_KBL_HUC_UCODE;
>   		huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
>   		huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
> +	} else if (IS_ICELAKE(dev_priv)) {
> +		huc_fw->path = I915_ICL_HUC_UCODE;
> +		huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
> +		huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
>   	}
>   }
>   
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[PATCH v2 22/22] HAX: prevent CI failures on configs with forced GuC submission

[Michal Wajdeczko]

Some CI systems might be configured to run with no longer supported
configuration "enable_guc=3" or "enable_guc=1". Hack that ;)

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/intel_uc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index a1a068511fd9..c40c8e6e6cd9 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -105,6 +105,12 @@ static void sanitize_options_early(struct drm_i915_private *i915)
 	struct intel_uc_fw *guc_fw = &i915->guc.fw;
 	struct intel_uc_fw *huc_fw = &i915->huc.fw;
 
+	/* HAX: prevent CI failures on configs with forced GuC */
+	if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION) {
+		DRM_DEBUG_DRIVER("turning off ENABLE_GUC_SUBMISSION\n");
+		i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
+	}
+
 	/* A negative value means "use platform default" */
 	if (i915_modparams.enable_guc < 0)
 		i915_modparams.enable_guc = __get_platform_enable_guc(i915);
-- 
2.19.2

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Re: [PATCH v2 22/22] HAX: prevent CI failures on configs with forced GuC submission

[Martin Peres]

On 11/04/2019 11:44, Michal Wajdeczko wrote:
> Some CI systems might be configured to run with no longer supported
> configuration "enable_guc=3" or "enable_guc=1". Hack that ;)

This is not a hack, this is what we need to do: Users put parameters in
their command line and forget about them, myself included.

GUC Command submission does not work / is not validated on any released
platform, so force-disable it. If someone starts working on enabling
that, then it is easy to make a HAX patch to force-enable it ;)

Anyways, thanks a lot, seems like there is good progress!

Martin

> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uc.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index a1a068511fd9..c40c8e6e6cd9 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -105,6 +105,12 @@ static void sanitize_options_early(struct drm_i915_private *i915)
>  	struct intel_uc_fw *guc_fw = &i915->guc.fw;
>  	struct intel_uc_fw *huc_fw = &i915->huc.fw;
>  
> +	/* HAX: prevent CI failures on configs with forced GuC */
> +	if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION) {
> +		DRM_DEBUG_DRIVER("turning off ENABLE_GUC_SUBMISSION\n");
> +		i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
> +	}
> +
>  	/* A negative value means "use platform default" */
>  	if (i915_modparams.enable_guc < 0)
>  		i915_modparams.enable_guc = __get_platform_enable_guc(i915);
> 
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Re: [PATCH v2 22/22] HAX: prevent CI failures on configs with forced GuC submission

[Michal Wajdeczko]

On Fri, 12 Apr 2019 13:30:47 +0200, Martin Peres  
<martin.peres@linux.intel.com> wrote:

> On 11/04/2019 11:44, Michal Wajdeczko wrote:
>> Some CI systems might be configured to run with no longer supported
>> configuration "enable_guc=3" or "enable_guc=1". Hack that ;)
>
> This is not a hack, this is what we need to do: Users put parameters in
> their command line and forget about them, myself included.
>
> GUC Command submission does not work / is not validated on any released
> platform, so force-disable it.

We don't want to silently switch to execlist submission. We stopped doing
that from commit 121981fafe69 ("drm/i915/guc: Combine enable_guc_loading|
submission modparams").

Patch [2/22] will take care to WARN user and stop GPU submission if this
modparam was configured to use GuC submission.

Michal

[2/22] https://patchwork.freedesktop.org/patch/298018/?series=58760&rev=2

> If someone starts working on enabling
> that, then it is easy to make a HAX patch to force-enable it ;)
>
>
> Anyways, thanks a lot, seems like there is good progress!
>
> Martin
>
>>
>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_uc.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c  
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index a1a068511fd9..c40c8e6e6cd9 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -105,6 +105,12 @@ static void sanitize_options_early(struct  
>> drm_i915_private *i915)
>>  	struct intel_uc_fw *guc_fw = &i915->guc.fw;
>>  	struct intel_uc_fw *huc_fw = &i915->huc.fw;
>>
>> +	/* HAX: prevent CI failures on configs with forced GuC */
>> +	if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION) {
>> +		DRM_DEBUG_DRIVER("turning off ENABLE_GUC_SUBMISSION\n");
>> +		i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
>> +	}
>> +
>>  	/* A negative value means "use platform default" */
>>  	if (i915_modparams.enable_guc < 0)
>>  		i915_modparams.enable_guc = __get_platform_enable_guc(i915);
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✗ Fi.CI.SPARSE: warning for GuC 32.0.3 (rev2)

[Patchwork]

== Series Details ==

Series: GuC 32.0.3 (rev2)
URL   : https://patchwork.freedesktop.org/series/58760/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/guc: Change platform default GuC mode
Okay!

Commit: drm/i915/guc: Don't allow GuC submission
Okay!

Commit: drm/i915/guc: Simplify preparation of GuC parameter block
Okay!

Commit: drm/i915/guc: Update GuC firmware versions and names
Okay!

Commit: drm/i915/guc: Update GuC firmware CSS header
Okay!

Commit: drm/i915/guc: Update GuC boot parameters
Okay!

Commit: drm/i915/guc: Update GuC sleep status values
Okay!

Commit: drm/i915/guc: Update GuC sample-forcewake command
Okay!

Commit: drm/i915/guc: Update GuC ADS object definition
Okay!

Commit: drm/i915/guc: Always ask GuC to update power domain states
Okay!

Commit: drm/i915/guc: Reset GuC ADS during sanitize
Okay!

Commit: drm/i915/guc: Treat GuC initialization failure as -EIO
Okay!

Commit: drm/i915/guc: New GuC interrupt register for Gen11
Okay!

Commit: drm/i915/guc: New GuC scratch registers for Gen11
Okay!

Commit: drm/i915/huc: New HuC status register for Gen11
Okay!

Commit: drm/i915/guc: Create vfuncs for the GuC interrupts control functions
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3616:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3638:16: warning: expression using sizeof(void)

Commit: drm/i915/guc: Correctly handle GuC interrupts on Gen11
+drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3638:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3642:16: warning: expression using sizeof(void)

Commit: drm/i915/guc: Update GuC CTB response definition
Okay!

Commit: drm/i915/guc: Enable GuC CTB communication on Gen11
Okay!

Commit: drm/i915/guc: Define GuC firmware version for Icelake
Okay!

Commit: drm/i915/huc: Define HuC firmware version for Icelake
Okay!

Commit: HAX: prevent CI failures on configs with forced GuC submission
Okay!

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for GuC 32.0.3 (rev2)

[Patchwork]

== Series Details ==

Series: GuC 32.0.3 (rev2)
URL   : https://patchwork.freedesktop.org/series/58760/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5913 -> Patchwork_12762
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58760/revisions/2/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12762 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@fork-compute0:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] +18

  * igt@i915_selftest@live_contexts:
    - fi-bdw-gvtdvm:      PASS -> DMESG-FAIL [fdo#110235 ]

  * igt@i915_selftest@live_evict:
    - fi-bsw-kefka:       PASS -> DMESG-WARN [fdo#107709]

  * igt@kms_force_connector_basic@force-edid:
    - fi-glk-dsi:         NOTRUN -> SKIP [fdo#109271] +26

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-bxt-j4205:       NOTRUN -> SKIP [fdo#109271] +47

  * igt@kms_frontbuffer_tracking@basic:
    - fi-glk-dsi:         NOTRUN -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
    - fi-glk-dsi:         NOTRUN -> FAIL [fdo#103191]

  * igt@kms_psr@primary_page_flip:
    - fi-apl-guc:         NOTRUN -> SKIP [fdo#109271] +50

  * igt@runner@aborted:
    - fi-bsw-kefka:       NOTRUN -> FAIL [fdo#107709]

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@i915_selftest@live_hangcheck:
    - fi-bxt-dsi:         INCOMPLETE [fdo#103927] -> PASS

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - fi-glk-dsi:         INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] -> PASS

  
#### Warnings ####

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       DMESG-WARN [fdo#103841] -> DMESG-FAIL [fdo#109627]

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109627]: https://bugs.freedesktop.org/show_bug.cgi?id=109627
  [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (47 -> 43)
------------------------------

  Additional (2): fi-bxt-j4205 fi-apl-guc 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5913 -> Patchwork_12762

  CI_DRM_5913: 67eef5880fe95727f01e0ae2233218951bbf251a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4943: 5941f371b0fe25084d4b1c49882faa8d41d44c9f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12762: 8bd9521867836937549a4d4b72f735d385bb0087 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8bd952186783 HAX: prevent CI failures on configs with forced GuC submission
edd687854841 drm/i915/huc: Define HuC firmware version for Icelake
bf1a92842ba2 drm/i915/guc: Define GuC firmware version for Icelake
c61df035872b drm/i915/guc: Enable GuC CTB communication on Gen11
75a2791cf5bb drm/i915/guc: Update GuC CTB response definition
57a4e4be8218 drm/i915/guc: Correctly handle GuC interrupts on Gen11
0ea3f7c5f1b5 drm/i915/guc: Create vfuncs for the GuC interrupts control functions
2e43a34be819 drm/i915/huc: New HuC status register for Gen11
32c33ce38ca9 drm/i915/guc: New GuC scratch registers for Gen11
ef7df7d843dd drm/i915/guc: New GuC interrupt register for Gen11
c46cc04b9b27 drm/i915/guc: Treat GuC initialization failure as -EIO
cf9605715387 drm/i915/guc: Reset GuC ADS during sanitize
f91d28b80f67 drm/i915/guc: Always ask GuC to update power domain states
df04e5f15c1f drm/i915/guc: Update GuC ADS object definition
63112cd315b7 drm/i915/guc: Update GuC sample-forcewake command
0f4ccf8cdc79 drm/i915/guc: Update GuC sleep status values
6250e65c0ecd drm/i915/guc: Update GuC boot parameters
69f77dbb1de2 drm/i915/guc: Update GuC firmware CSS header
67b80c97ecfd drm/i915/guc: Update GuC firmware versions and names
87fb28b4c504 drm/i915/guc: Simplify preparation of GuC parameter block
5c9246394466 drm/i915/guc: Don't allow GuC submission
c9aa87194114 drm/i915/guc: Change platform default GuC mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12762/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 00/22] GuC 32.0.3

[Chris Wilson]

Quoting Michal Wajdeczko (2019-04-11 09:44:14)
> New GuC firmwares (for SKL, BXT, KBL, ICL) with updated ABI interface.

It is worth mentioning the trybot run with i915.enable_guc=-1 turned up
no problems. Looks like this series is ready, as is the fw release.
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4129/
-Chris
_______________________________________________
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✓ Fi.CI.IGT: success for GuC 32.0.3 (rev2)

[Patchwork]

== Series Details ==

Series: GuC 32.0.3 (rev2)
URL   : https://patchwork.freedesktop.org/series/58760/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5913_full -> Patchwork_12762_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12762_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109283]

  * igt@gem_pwrite@stolen-uncached:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109277]

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          PASS -> SKIP [fdo#109271]

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109308]

  * igt@i915_suspend@debugfs-reader:
    - shard-apl:          PASS -> DMESG-WARN [fdo#108566] +3

  * igt@kms_addfb_basic@size-max:
    - shard-apl:          PASS -> INCOMPLETE [fdo#103927]

  * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
    - shard-apl:          PASS -> FAIL [fdo#109660]

  * igt@kms_busy@extended-modeset-hang-oldfb-render-f:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +15

  * igt@kms_chamelium@hdmi-cmp-nv21:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109284] +1

  * igt@kms_content_protection@legacy:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109300]

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
    - shard-skl:          NOTRUN -> FAIL [fdo#103184]

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +2

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#108566] +2

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +7

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +151

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
    - shard-snb:          PASS -> SKIP [fdo#109271]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
    - shard-iclb:         PASS -> FAIL [fdo#109247] +9
    - shard-skl:          NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +5

  * igt@kms_lease@atomic_implicit_crtc:
    - shard-skl:          NOTRUN -> FAIL [fdo#110279]

  * igt@kms_lease@cursor_implicit_plane:
    - shard-skl:          NOTRUN -> FAIL [fdo#110278]

  * igt@kms_lease@setcrtc_implicit_plane:
    - shard-skl:          NOTRUN -> FAIL [fdo#110281]
    - shard-iclb:         NOTRUN -> FAIL [fdo#110281]

  * igt@kms_plane@pixel-format-pipe-a-planes:
    - shard-glk:          PASS -> SKIP [fdo#109271]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          NOTRUN -> FAIL [fdo#110403]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          PASS -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#110403]

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         PASS -> FAIL [fdo#103166]

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
    - shard-glk:          PASS -> SKIP [fdo#109271] / [fdo#109278]
    - shard-iclb:         NOTRUN -> FAIL [fdo#109052]

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         PASS -> SKIP [fdo#109642]

  * igt@kms_psr@no_drrs:
    - shard-iclb:         PASS -> FAIL [fdo#108341]

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         PASS -> SKIP [fdo#109441] +2

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109441] +1

  * igt@kms_setmode@basic:
    - shard-skl:          NOTRUN -> FAIL [fdo#99912]

  * igt@kms_universal_plane@cursor-fb-leak-pipe-e:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +3

  * igt@prime_busy@wait-after-bsd2:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +2

  * igt@prime_nv_api@nv_self_import_to_different_fd:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109291]

  * igt@prime_vgem@fence-flip-hang:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109295]

  * igt@v3d_mmap@mmap-bad-handle:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109315]

  
#### Possible fixes ####

  * igt@gem_eio@reset-stress:
    - shard-snb:          FAIL [fdo#109661] -> PASS

  * igt@gem_softpin@noreloc-s3:
    - shard-kbl:          DMESG-WARN [fdo#108566] -> PASS +3

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          DMESG-WARN [fdo#108566] -> PASS +4

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         SKIP [fdo#109349] -> PASS

  * igt@kms_fbcon_fbt@fbc:
    - shard-iclb:         DMESG-WARN [fdo#109593] -> PASS

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          FAIL [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-glk:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +3

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         FAIL [fdo#109247] -> PASS +4

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-glk:          SKIP [fdo#109271] -> PASS

  * igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
    - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> PASS

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         SKIP [fdo#109441] -> PASS +3

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          FAIL [fdo#109016] -> PASS

  * igt@kms_setmode@basic:
    - shard-apl:          FAIL [fdo#99912] -> PASS

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-skl:          INCOMPLETE [fdo#104108] -> PASS

  
#### Warnings ####

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-skl:          SKIP [fdo#109271] -> INCOMPLETE [fdo#107807]

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         INCOMPLETE -> SKIP [fdo#109280] +1

  
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
  [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109593]: https://bugs.freedesktop.org/show_bug.cgi?id=109593
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109660]: https://bugs.freedesktop.org/show_bug.cgi?id=109660
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110278]: https://bugs.freedesktop.org/show_bug.cgi?id=110278
  [fdo#110279]: https://bugs.freedesktop.org/show_bug.cgi?id=110279
  [fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 9)
------------------------------

  Missing    (1): shard-hsw 


Build changes
-------------

    * Linux: CI_DRM_5913 -> Patchwork_12762

  CI_DRM_5913: 67eef5880fe95727f01e0ae2233218951bbf251a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4943: 5941f371b0fe25084d4b1c49882faa8d41d44c9f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12762: 8bd9521867836937549a4d4b72f735d385bb0087 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12762/
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✗ Fi.CI.SPARSE: warning for GuC 32.0.3 (rev3)

[Patchwork]

== Series Details ==

Series: GuC 32.0.3 (rev3)
URL   : https://patchwork.freedesktop.org/series/58760/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/guc: Change platform default GuC mode
Okay!

Commit: drm/i915/guc: Don't allow GuC submission
Okay!

Commit: drm/i915/guc: Simplify preparation of GuC parameter block
Okay!

Commit: drm/i915/guc: Update GuC firmware versions and names
Okay!

Commit: drm/i915/guc: Update GuC firmware CSS header
Okay!

Commit: drm/i915/guc: Update GuC boot parameters
Okay!

Commit: drm/i915/guc: updated suspend/resume protocol
Okay!

Commit: drm/i915/guc: Update GuC sample-forcewake command
Okay!

Commit: drm/i915/guc: Update GuC ADS object definition
Okay!

Commit: drm/i915/guc: Always ask GuC to update power domain states
Okay!

Commit: drm/i915/guc: Reset GuC ADS during sanitize
Okay!

Commit: drm/i915/guc: Treat GuC initialization failure as -EIO
Okay!

Commit: drm/i915/guc: New GuC interrupt register for Gen11
Okay!

Commit: drm/i915/guc: New GuC scratch registers for Gen11
Okay!

Commit: drm/i915/huc: New HuC status register for Gen11
Okay!

Commit: drm/i915/guc: Create vfuncs for the GuC interrupts control functions
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3616:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3638:16: warning: expression using sizeof(void)

Commit: drm/i915/guc: Correctly handle GuC interrupts on Gen11
+drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3638:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3642:16: warning: expression using sizeof(void)

Commit: drm/i915/guc: Update GuC CTB response definition
Okay!

Commit: drm/i915/guc: Enable GuC CTB communication on Gen11
Okay!

Commit: drm/i915/guc: Define GuC firmware version for Icelake
Okay!

Commit: drm/i915/huc: Define HuC firmware version for Icelake
Okay!

Commit: HAX: prevent CI failures on configs with forced GuC submission
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for GuC 32.0.3 (rev3)

[Patchwork]

== Series Details ==

Series: GuC 32.0.3 (rev3)
URL   : https://patchwork.freedesktop.org/series/58760/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5926 -> Patchwork_12789
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58760/revisions/3/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12789 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_basic@basic-bsd2:
    - fi-icl-guc:         NOTRUN -> SKIP [fdo#109276] +7

  * igt@gem_exec_parse@basic-rejected:
    - fi-icl-guc:         NOTRUN -> SKIP [fdo#109289] +1

  * igt@gem_exec_suspend@basic-s3:
    - fi-icl-guc:         NOTRUN -> INCOMPLETE [fdo#107713] / [fdo#108743]

  * igt@i915_selftest@live_contexts:
    - fi-bdw-gvtdvm:      PASS -> DMESG-FAIL [fdo#110235 ]

  * igt@kms_force_connector_basic@force-edid:
    - fi-glk-dsi:         NOTRUN -> SKIP [fdo#109271] +26

  * igt@kms_frontbuffer_tracking@basic:
    - fi-glk-dsi:         NOTRUN -> FAIL [fdo#103167]

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - fi-glk-dsi:         INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          FAIL [fdo#103167] -> PASS
    - fi-byt-clapper:     FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] -> PASS +1

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108743]: https://bugs.freedesktop.org/show_bug.cgi?id=108743
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
  [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (48 -> 45)
------------------------------

  Additional (1): fi-icl-guc 
  Missing    (4): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5926 -> Patchwork_12789

  CI_DRM_5926: 2ab8e3b23618f04e84a03ecb53685e14cd2a5346 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12789: d84a3bc94aae570e01af6f7a2d437819017888f2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d84a3bc94aae HAX: prevent CI failures on configs with forced GuC submission
f881170bc4f4 drm/i915/huc: Define HuC firmware version for Icelake
e960b886ffdc drm/i915/guc: Define GuC firmware version for Icelake
20c69c285110 drm/i915/guc: Enable GuC CTB communication on Gen11
328a52f90fb7 drm/i915/guc: Update GuC CTB response definition
4dd5256ddaf1 drm/i915/guc: Correctly handle GuC interrupts on Gen11
243c6405e47c drm/i915/guc: Create vfuncs for the GuC interrupts control functions
5cd11f9afe37 drm/i915/huc: New HuC status register for Gen11
1685d7ddf6df drm/i915/guc: New GuC scratch registers for Gen11
99b3811b3b40 drm/i915/guc: New GuC interrupt register for Gen11
a659a551bfde drm/i915/guc: Treat GuC initialization failure as -EIO
eef812801d7d drm/i915/guc: Reset GuC ADS during sanitize
21fac6f414be drm/i915/guc: Always ask GuC to update power domain states
53c52dd4f6c0 drm/i915/guc: Update GuC ADS object definition
7faf86f4f2c0 drm/i915/guc: Update GuC sample-forcewake command
34291caa1ffd drm/i915/guc: updated suspend/resume protocol
3a9c93b435cc drm/i915/guc: Update GuC boot parameters
05000eb6a162 drm/i915/guc: Update GuC firmware CSS header
3ba3aed8cc3d drm/i915/guc: Update GuC firmware versions and names
4d98515d1e03 drm/i915/guc: Simplify preparation of GuC parameter block
3f69cda4475b drm/i915/guc: Don't allow GuC submission
50a78dc98ac8 drm/i915/guc: Change platform default GuC mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12789/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for GuC 32.0.3 (rev3)

[Patchwork]

== Series Details ==

Series: GuC 32.0.3 (rev3)
URL   : https://patchwork.freedesktop.org/series/58760/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5926_full -> Patchwork_12789_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12789_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109313]

  * igt@gem_exec_nop@basic-series:
    - shard-apl:          PASS -> INCOMPLETE [fdo#103927] +2

  * igt@gem_mocs_settings@mocs-settings-dirty-render:
    - shard-iclb:         NOTRUN -> SKIP [fdo#110206] +1

  * igt@gem_pread@stolen-normal:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109277] +2

  * igt@gem_softpin@noreloc-s3:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#108566]

  * igt@i915_pm_lpsp@screens-disabled:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109301]

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109308]

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109506]
    - shard-skl:          NOTRUN -> INCOMPLETE [fdo#107807]

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-iclb:         NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-pageflip-hang-oldfb-render-d:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +4

  * igt@kms_chamelium@dp-crc-single:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109284] +3

  * igt@kms_crtc_background_color:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109305]

  * igt@kms_cursor_crc@cursor-512x512-onscreen:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109279]

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          PASS -> FAIL [fdo#106509] / [fdo#107409]

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - shard-snb:          PASS -> INCOMPLETE [fdo#105411]

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          NOTRUN -> FAIL [fdo#103833]

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +63

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +7

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          PASS -> INCOMPLETE [fdo#107773] / [fdo#109507]

  * igt@kms_force_connector_basic@force-connector-state:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109285]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-skl:          NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
    - shard-iclb:         PASS -> FAIL [fdo#109247] +16

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +4

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +25

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
    - shard-iclb:         NOTRUN -> FAIL [fdo#109247] +2

  * igt@kms_invalid_dotclock:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109310]

  * igt@kms_lease@cursor_implicit_plane:
    - shard-iclb:         NOTRUN -> FAIL [fdo#110278]

  * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109289]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          PASS -> FAIL [fdo#108145]

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
    - shard-iclb:         NOTRUN -> FAIL [fdo#109052]

  * igt@kms_psr@no_drrs:
    - shard-iclb:         PASS -> FAIL [fdo#108341]

  * igt@kms_psr@primary_mmap_cpu:
    - shard-iclb:         NOTRUN -> FAIL [fdo#107383] / [fdo#110215]

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109441] +1

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         PASS -> SKIP [fdo#109441]

  * igt@kms_psr@sprite_render:
    - shard-iclb:         PASS -> FAIL [fdo#107383] / [fdo#110215] +2

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#105763]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> FAIL [fdo#109016]

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-f:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-apl:          PASS -> DMESG-WARN [fdo#108566] +4

  * igt@perf_pmu@busy-no-semaphores-vcs1:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +20

  * igt@perf_pmu@rc6:
    - shard-kbl:          PASS -> SKIP [fdo#109271]

  * igt@prime_nv_api@i915_self_import:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109291] +3

  * igt@tools_test@sysfs_l3_parity:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109307]

  
#### Possible fixes ####

  * igt@gem_tiled_swapping@non-threaded:
    - shard-iclb:         FAIL [fdo#108686] -> PASS

  * igt@i915_pm_rpm@gem-idle:
    - shard-skl:          INCOMPLETE [fdo#107807] -> PASS

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          DMESG-WARN [fdo#108566] -> PASS +3

  * igt@kms_cursor_crc@cursor-128x128-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-kbl:          DMESG-WARN [fdo#108566] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-iclb:         FAIL [fdo#109247] -> PASS +9

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-glk:          SKIP [fdo#109271] -> PASS +1

  * igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
    - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> PASS

  * igt@kms_psr@cursor_mmap_gtt:
    - shard-iclb:         FAIL [fdo#107383] / [fdo#110215] -> PASS +5

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         SKIP [fdo#109441] -> PASS +3

  
#### Warnings ####

  * igt@tools_test@sysfs_l3_parity:
    - shard-apl:          SKIP [fdo#109271] -> INCOMPLETE [fdo#103927]

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
  [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109301]: https://bugs.freedesktop.org/show_bug.cgi?id=109301
  [fdo#109305]: https://bugs.freedesktop.org/show_bug.cgi?id=109305
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109310]: https://bugs.freedesktop.org/show_bug.cgi?id=109310
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110206]: https://bugs.freedesktop.org/show_bug.cgi?id=110206
  [fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
  [fdo#110278]: https://bugs.freedesktop.org/show_bug.cgi?id=110278


Participating hosts (10 -> 9)
------------------------------

  Missing    (1): shard-hsw 


Build changes
-------------

    * Linux: CI_DRM_5926 -> Patchwork_12789

  CI_DRM_5926: 2ab8e3b23618f04e84a03ecb53685e14cd2a5346 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12789: d84a3bc94aae570e01af6f7a2d437819017888f2 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12789/
_______________________________________________
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