From: Florian Fainelli <f.fainelli@gmail.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
hauke@hauke-m.de, netdev@vger.kernel.org
Cc: andrew@lunn.ch, vivien.didelot@gmail.com, olteanv@gmail.com,
davem@davemloft.net, kuba@kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH 2/2] net: dsa: lantiq_gswip: Fix GSWIP_MII_CFG(p) register access
Date: Mon, 4 Jan 2021 11:58:10 -0800 [thread overview]
Message-ID: <d1a79b89-4a85-49c7-b1f1-dc3c7b8a77eb@gmail.com> (raw)
In-Reply-To: <20210103012544.3259029-3-martin.blumenstingl@googlemail.com>
On 1/2/21 5:25 PM, Martin Blumenstingl wrote:
> There is one GSWIP_MII_CFG register for each switch-port except the CPU
> port. The register offset for the first port is 0x0, 0x02 for the
> second, 0x04 for the third and so on.
>
> Update the driver to not only restrict the GSWIP_MII_CFG registers to
> ports 0, 1 and 5. Handle ports 0..5 instead but skip the CPU port. This
> means we are not overwriting the configuration for the third port (port
> two since we start counting from zero) with the settings for the sixth
> port (with number five) anymore.
>
> The GSWIP_MII_PCDU(p) registers are not updated because there's really
> only three (one for each of the following ports: 0, 1, 5).
>
> Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> Cc: stable@vger.kernel.org
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
prev parent reply other threads:[~2021-01-04 19:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-03 1:25 [PATCH 0/2] net: dsa: lantiq_gswip: two fixes for -net/-stable Martin Blumenstingl
2021-01-03 1:25 ` [PATCH 1/2] net: dsa: lantiq_gswip: Enable GSWIP_MII_CFG_EN also for internal PHYs Martin Blumenstingl
2021-01-03 1:35 ` Hauke Mehrtens
2021-01-03 2:09 ` Andrew Lunn
2021-01-03 2:12 ` Martin Blumenstingl
2021-01-04 21:52 ` Jakub Kicinski
2021-01-04 23:54 ` Martin Blumenstingl
2021-01-04 19:53 ` Florian Fainelli
2021-01-03 1:25 ` [PATCH 2/2] net: dsa: lantiq_gswip: Fix GSWIP_MII_CFG(p) register access Martin Blumenstingl
2021-01-03 1:36 ` Hauke Mehrtens
2021-01-04 19:58 ` Florian Fainelli [this message]
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