* [PATCH v4 1/2] MIPS: io: prevent compiler reordering on the default writeX() implementation
@ 2018-04-13 2:30 ` Sinan Kaya
0 siblings, 0 replies; 8+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:30 UTC (permalink / raw)
To: linux-mips, arnd, timur, sulrich
Cc: linux-arm-msm, linux-arm-kernel, Sinan Kaya, Ralf Baechle,
James Hogan, Paul Burton, linux-kernel
writeX() has a strong ordering semantics with respect to memory updates.
In the abscence of a write barrier or a compiler barrier, commpiler can
reorder register and memory update instructions. This breaks the writeX()
API.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
arch/mips/include/asm/io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 0cbf3af..fd00ddaf 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -307,7 +307,7 @@ static inline void iounmap(const volatile void __iomem *addr)
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
#define war_io_reorder_wmb() wmb()
#else
-#define war_io_reorder_wmb() do { } while (0)
+#define war_io_reorder_wmb() barrier()
#endif
#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 1/2] MIPS: io: prevent compiler reordering on the default writeX() implementation
@ 2018-04-13 2:30 ` Sinan Kaya
0 siblings, 0 replies; 8+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:30 UTC (permalink / raw)
To: linux-arm-kernel
writeX() has a strong ordering semantics with respect to memory updates.
In the abscence of a write barrier or a compiler barrier, commpiler can
reorder register and memory update instructions. This breaks the writeX()
API.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
arch/mips/include/asm/io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 0cbf3af..fd00ddaf 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -307,7 +307,7 @@ static inline void iounmap(const volatile void __iomem *addr)
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
#define war_io_reorder_wmb() wmb()
#else
-#define war_io_reorder_wmb() do { } while (0)
+#define war_io_reorder_wmb() barrier()
#endif
#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()
2018-04-13 2:30 ` Sinan Kaya
@ 2018-04-13 2:30 ` Sinan Kaya
-1 siblings, 0 replies; 8+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:30 UTC (permalink / raw)
To: linux-mips, arnd, timur, sulrich
Cc: linux-arm-msm, linux-arm-kernel, Sinan Kaya, Ralf Baechle,
James Hogan, Paul Burton, linux-kernel
While a barrier is present in writeX() function before the register write,
a similar barrier is missing in the readX() function after the register
read. This could allow memory accesses following readX() to observe
stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
---
arch/mips/include/asm/io.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index fd00ddaf..d96af41 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
BUG(); \
} \
\
+ /* prevent prefetching of coherent DMA dma prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()
@ 2018-04-13 2:30 ` Sinan Kaya
0 siblings, 0 replies; 8+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:30 UTC (permalink / raw)
To: linux-arm-kernel
While a barrier is present in writeX() function before the register write,
a similar barrier is missing in the readX() function after the register
read. This could allow memory accesses following readX() to observe
stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
---
arch/mips/include/asm/io.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index fd00ddaf..d96af41 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
BUG(); \
} \
\
+ /* prevent prefetching of coherent DMA dma prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()
2018-04-13 2:30 ` Sinan Kaya
@ 2018-04-13 2:33 ` Sinan Kaya
-1 siblings, 0 replies; 8+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:33 UTC (permalink / raw)
To: linux-mips, arnd, timur, sulrich
Cc: linux-arm-msm, linux-arm-kernel, Ralf Baechle, James Hogan,
Paul Burton, linux-kernel
On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> + /* prevent prefetching of coherent DMA dma prematurely */ \
I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
posting another version until I hear back from you for wmb().
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()
@ 2018-04-13 2:33 ` Sinan Kaya
0 siblings, 0 replies; 8+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:33 UTC (permalink / raw)
To: linux-arm-kernel
On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> + /* prevent prefetching of coherent DMA dma prematurely */ \
I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
posting another version until I hear back from you for wmb().
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()
2018-04-13 2:33 ` Sinan Kaya
@ 2018-04-13 23:52 ` James Hogan
-1 siblings, 0 replies; 8+ messages in thread
From: James Hogan @ 2018-04-13 23:52 UTC (permalink / raw)
To: Sinan Kaya
Cc: linux-mips, arnd, timur, sulrich, linux-arm-msm,
linux-arm-kernel, Ralf Baechle, Paul Burton, linux-kernel
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On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote:
> On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> > + /* prevent prefetching of coherent DMA dma prematurely */ \
>
> I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
> posting another version until I hear back from you for wmb().
No problem, I've applied both for 4.17 and tweaked the comment.
Thanks
James
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()
@ 2018-04-13 23:52 ` James Hogan
0 siblings, 0 replies; 8+ messages in thread
From: James Hogan @ 2018-04-13 23:52 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote:
> On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> > + /* prevent prefetching of coherent DMA dma prematurely */ \
>
> I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
> posting another version until I hear back from you for wmb().
No problem, I've applied both for 4.17 and tweaked the comment.
Thanks
James
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end of thread, other threads:[~2018-04-13 23:52 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-13 2:30 [PATCH v4 1/2] MIPS: io: prevent compiler reordering on the default writeX() implementation Sinan Kaya
2018-04-13 2:30 ` Sinan Kaya
2018-04-13 2:30 ` [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX() Sinan Kaya
2018-04-13 2:30 ` Sinan Kaya
2018-04-13 2:33 ` Sinan Kaya
2018-04-13 2:33 ` Sinan Kaya
2018-04-13 23:52 ` James Hogan
2018-04-13 23:52 ` James Hogan
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