* [PATCH 0/5] drm: use core pcie functionality for pcie gen/width
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx, dri-devel, airlied, linux-pci, bhelgaas; +Cc: Alex Deucher
This series exports some pcie helper functions for use by drivers and
fixes up the amdgpu and radeon drivers to use this core functionality
rather than the duplicated functionality in the drm. Finally we remove
the drm helpers since the duplicate the pcie functionality of the core.
This also adds proper pcie gen4 detection for amdgpu.
Alex Deucher (5):
pci: export pcie_get_speed_cap and pcie_get_width_cap
drm/amdgpu: update amd_pcie.h to include gen4 speeds
drm/amdgpu: use pcie functions for link width and speed
drm/radeon: use pcie functions for link width
drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
drivers/gpu/drm/amd/include/amd_pcie.h | 2 +
drivers/gpu/drm/drm_pci.c | 58 ---------------------
drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++--
drivers/gpu/drm/radeon/cik.c | 22 ++++----
drivers/gpu/drm/radeon/r600_dpm.c | 4 +-
drivers/gpu/drm/radeon/radeon.h | 4 ++
drivers/gpu/drm/radeon/si.c | 22 ++++----
drivers/gpu/drm/radeon/si_dpm.c | 20 +++++--
drivers/pci/pci.c | 2 +
include/drm/drm_pci.h | 7 ---
include/linux/pci.h | 3 ++
15 files changed, 132 insertions(+), 128 deletions(-)
--
2.13.6
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 0/5] drm: use core pcie functionality for pcie gen/width
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
airlied-Re5JQEeQqe8AvxtiuMwx3w, linux-pci-u79uwXL29TY76Z2rM5mHXA,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA
Cc: Alex Deucher
This series exports some pcie helper functions for use by drivers and
fixes up the amdgpu and radeon drivers to use this core functionality
rather than the duplicated functionality in the drm. Finally we remove
the drm helpers since the duplicate the pcie functionality of the core.
This also adds proper pcie gen4 detection for amdgpu.
Alex Deucher (5):
pci: export pcie_get_speed_cap and pcie_get_width_cap
drm/amdgpu: update amd_pcie.h to include gen4 speeds
drm/amdgpu: use pcie functions for link width and speed
drm/radeon: use pcie functions for link width
drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
drivers/gpu/drm/amd/include/amd_pcie.h | 2 +
drivers/gpu/drm/drm_pci.c | 58 ---------------------
drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++--
drivers/gpu/drm/radeon/cik.c | 22 ++++----
drivers/gpu/drm/radeon/r600_dpm.c | 4 +-
drivers/gpu/drm/radeon/radeon.h | 4 ++
drivers/gpu/drm/radeon/si.c | 22 ++++----
drivers/gpu/drm/radeon/si_dpm.c | 20 +++++--
drivers/pci/pci.c | 2 +
include/drm/drm_pci.h | 7 ---
include/linux/pci.h | 3 ++
15 files changed, 132 insertions(+), 128 deletions(-)
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx, dri-devel, airlied, linux-pci, bhelgaas; +Cc: Alex Deucher
So drivers can use them. This can be used to replace
duplicate code in the drm subsystem.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/pci/pci.c | 2 ++
include/linux/pci.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 97acba712e4e..22adaf35b136 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5222,6 +5222,7 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
return PCI_SPEED_UNKNOWN;
}
+EXPORT_SYMBOL(pcie_get_speed_cap);
/**
* pcie_get_width_cap - query for the PCI device's link width capability
@@ -5240,6 +5241,7 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
return PCIE_LNK_WIDTH_UNKNOWN;
}
+EXPORT_SYMBOL(pcie_get_width_cap);
/**
* pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 340029b2fb38..6e0c0803b241 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -261,6 +261,9 @@ enum pci_bus_speed {
PCI_SPEED_UNKNOWN = 0xff,
};
+enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
+enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
+
struct pci_cap_saved_data {
u16 cap_nr;
bool cap_extended;
--
2.13.6
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
airlied-Re5JQEeQqe8AvxtiuMwx3w, linux-pci-u79uwXL29TY76Z2rM5mHXA,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA
Cc: Alex Deucher
So drivers can use them. This can be used to replace
duplicate code in the drm subsystem.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/pci/pci.c | 2 ++
include/linux/pci.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 97acba712e4e..22adaf35b136 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5222,6 +5222,7 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
return PCI_SPEED_UNKNOWN;
}
+EXPORT_SYMBOL(pcie_get_speed_cap);
/**
* pcie_get_width_cap - query for the PCI device's link width capability
@@ -5240,6 +5241,7 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
return PCIE_LNK_WIDTH_UNKNOWN;
}
+EXPORT_SYMBOL(pcie_get_width_cap);
/**
* pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 340029b2fb38..6e0c0803b241 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -261,6 +261,9 @@ enum pci_bus_speed {
PCI_SPEED_UNKNOWN = 0xff,
};
+enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
+enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
+
struct pci_cap_saved_data {
u16 cap_nr;
bool cap_extended;
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx, dri-devel, airlied, linux-pci, bhelgaas; +Cc: Alex Deucher
Internal header used by the driver to specify pcie gen
speeds of the asic and chipset.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/amd_pcie.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
index 5eb895fd98bf..9cb9ceb4d74d 100644
--- a/drivers/gpu/drm/amd/include/amd_pcie.h
+++ b/drivers/gpu/drm/amd/include/amd_pcie.h
@@ -27,6 +27,7 @@
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
@@ -34,6 +35,7 @@
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
--
2.13.6
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
airlied-Re5JQEeQqe8AvxtiuMwx3w, linux-pci-u79uwXL29TY76Z2rM5mHXA,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA
Cc: Alex Deucher
Internal header used by the driver to specify pcie gen
speeds of the asic and chipset.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/amd_pcie.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
index 5eb895fd98bf..9cb9ceb4d74d 100644
--- a/drivers/gpu/drm/amd/include/amd_pcie.h
+++ b/drivers/gpu/drm/amd/include/amd_pcie.h
@@ -27,6 +27,7 @@
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
@@ -34,6 +35,7 @@
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 3/5] drm/amdgpu: use pcie functions for link width and speed
2018-06-25 21:06 ` Alex Deucher
@ 2018-06-25 21:06 ` Alex Deucher
-1 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx, dri-devel, airlied, linux-pci, bhelgaas; +Cc: Alex Deucher
Use the newly exported pci functions to get the link width
and speed rather than using the drm duplicated versions.
Also query the GPU link caps directly rather than hardcoding
them.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
4 files changed, 65 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6e5284e6c028..b70f44022813 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3290,8 +3290,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
*/
static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
{
- u32 mask;
- int ret;
+ struct pci_dev *pdev;
+ enum pci_bus_speed speed_cap;
+ enum pcie_link_width link_width;
if (amdgpu_pcie_gen_cap)
adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@@ -3309,27 +3310,61 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
}
if (adev->pm.pcie_gen_mask == 0) {
- ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
- if (!ret) {
- adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ /* asic caps */
+ pdev = adev->pdev;
+ speed_cap = pcie_get_speed_cap(pdev);
+ if (speed_cap == PCI_SPEED_UNKNOWN) {
+ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
-
- if (mask & DRM_PCIE_SPEED_25)
- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
- if (mask & DRM_PCIE_SPEED_50)
- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
- if (mask & DRM_PCIE_SPEED_80)
- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
} else {
- adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
+ if (speed_cap == PCIE_SPEED_16_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
+ else if (speed_cap == PCIE_SPEED_8_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
+ else if (speed_cap == PCIE_SPEED_5_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
+ else
+ adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
+ }
+ /* platform caps */
+ pdev = adev->ddev->pdev->bus->self;
+ speed_cap = pcie_get_speed_cap(pdev);
+ if (speed_cap == PCI_SPEED_UNKNOWN) {
+ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
+ } else {
+ if (speed_cap == PCIE_SPEED_16_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
+ else if (speed_cap == PCIE_SPEED_8_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
+ else if (speed_cap == PCIE_SPEED_5_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
+ else
+ adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
+
}
}
if (adev->pm.pcie_mlw_mask == 0) {
- ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
- if (!ret) {
- switch (mask) {
- case 32:
+ pdev = adev->ddev->pdev->bus->self;
+ link_width = pcie_get_width_cap(pdev);
+ if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
+ adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
+ } else {
+ switch (link_width) {
+ case PCIE_LNK_X32:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
@@ -3338,7 +3373,7 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 16:
+ case PCIE_LNK_X16:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
@@ -3346,36 +3381,34 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 12:
+ case PCIE_LNK_X12:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 8:
+ case PCIE_LNK_X8:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 4:
+ case PCIE_LNK_X4:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 2:
+ case PCIE_LNK_X2:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 1:
+ case PCIE_LNK_X1:
adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
break;
default:
break;
}
- } else {
- adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
}
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 77ad59ade85c..1c4595562f8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -28,6 +28,7 @@
#include "amdgpu_i2c.h"
#include "amdgpu_dpm.h"
#include "atom.h"
+#include "amd_pcie.h"
void amdgpu_dpm_print_class_info(u32 class, u32 class2)
{
@@ -936,9 +937,11 @@ enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
case AMDGPU_PCIE_GEN3:
return AMDGPU_PCIE_GEN3;
default:
- if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
+ if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) &&
+ (default_gen == AMDGPU_PCIE_GEN3))
return AMDGPU_PCIE_GEN3;
- else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
+ else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) &&
+ (default_gen == AMDGPU_PCIE_GEN2))
return AMDGPU_PCIE_GEN2;
else
return AMDGPU_PCIE_GEN1;
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 7fbad2f5f0bd..a3641778a813 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -5846,8 +5846,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
adev->pm.dpm.priv = pi;
pi->sys_pcie_mask =
- (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
- CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
+ adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 5c97a3671726..0243899ff0d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7318,8 +7318,7 @@ static int si_dpm_init(struct amdgpu_device *adev)
pi = &eg_pi->rv7xx;
si_pi->sys_pcie_mask =
- (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
- CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
+ adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
--
2.13.6
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 3/5] drm/amdgpu: use pcie functions for link width and speed
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx, dri-devel, airlied, linux-pci, bhelgaas; +Cc: Alex Deucher
Use the newly exported pci functions to get the link width
and speed rather than using the drm duplicated versions.
Also query the GPU link caps directly rather than hardcoding
them.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
4 files changed, 65 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6e5284e6c028..b70f44022813 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3290,8 +3290,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
*/
static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
{
- u32 mask;
- int ret;
+ struct pci_dev *pdev;
+ enum pci_bus_speed speed_cap;
+ enum pcie_link_width link_width;
if (amdgpu_pcie_gen_cap)
adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@@ -3309,27 +3310,61 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
}
if (adev->pm.pcie_gen_mask == 0) {
- ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
- if (!ret) {
- adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ /* asic caps */
+ pdev = adev->pdev;
+ speed_cap = pcie_get_speed_cap(pdev);
+ if (speed_cap == PCI_SPEED_UNKNOWN) {
+ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
-
- if (mask & DRM_PCIE_SPEED_25)
- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
- if (mask & DRM_PCIE_SPEED_50)
- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
- if (mask & DRM_PCIE_SPEED_80)
- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
} else {
- adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
+ if (speed_cap == PCIE_SPEED_16_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
+ else if (speed_cap == PCIE_SPEED_8_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
+ else if (speed_cap == PCIE_SPEED_5_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
+ else
+ adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
+ }
+ /* platform caps */
+ pdev = adev->ddev->pdev->bus->self;
+ speed_cap = pcie_get_speed_cap(pdev);
+ if (speed_cap == PCI_SPEED_UNKNOWN) {
+ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
+ } else {
+ if (speed_cap == PCIE_SPEED_16_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
+ else if (speed_cap == PCIE_SPEED_8_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
+ else if (speed_cap == PCIE_SPEED_5_0GT)
+ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
+ else
+ adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
+
}
}
if (adev->pm.pcie_mlw_mask == 0) {
- ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
- if (!ret) {
- switch (mask) {
- case 32:
+ pdev = adev->ddev->pdev->bus->self;
+ link_width = pcie_get_width_cap(pdev);
+ if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
+ adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
+ } else {
+ switch (link_width) {
+ case PCIE_LNK_X32:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
@@ -3338,7 +3373,7 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 16:
+ case PCIE_LNK_X16:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
@@ -3346,36 +3381,34 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 12:
+ case PCIE_LNK_X12:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 8:
+ case PCIE_LNK_X8:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 4:
+ case PCIE_LNK_X4:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 2:
+ case PCIE_LNK_X2:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
- case 1:
+ case PCIE_LNK_X1:
adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
break;
default:
break;
}
- } else {
- adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
}
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 77ad59ade85c..1c4595562f8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -28,6 +28,7 @@
#include "amdgpu_i2c.h"
#include "amdgpu_dpm.h"
#include "atom.h"
+#include "amd_pcie.h"
void amdgpu_dpm_print_class_info(u32 class, u32 class2)
{
@@ -936,9 +937,11 @@ enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
case AMDGPU_PCIE_GEN3:
return AMDGPU_PCIE_GEN3;
default:
- if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
+ if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) &&
+ (default_gen == AMDGPU_PCIE_GEN3))
return AMDGPU_PCIE_GEN3;
- else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
+ else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) &&
+ (default_gen == AMDGPU_PCIE_GEN2))
return AMDGPU_PCIE_GEN2;
else
return AMDGPU_PCIE_GEN1;
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 7fbad2f5f0bd..a3641778a813 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -5846,8 +5846,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
adev->pm.dpm.priv = pi;
pi->sys_pcie_mask =
- (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
- CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
+ adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 5c97a3671726..0243899ff0d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7318,8 +7318,7 @@ static int si_dpm_init(struct amdgpu_device *adev)
pi = &eg_pi->rv7xx;
si_pi->sys_pcie_mask =
- (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
- CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
+ adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
--
2.13.6
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 4/5] drm/radeon: use pcie functions for link width
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx, dri-devel, airlied, linux-pci, bhelgaas; +Cc: Alex Deucher
This is the last user of drm_pcie_get_speed_cap_mask. Use the pci
version so we can drop drm_pcie_get_speed_cap_mask.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++++++++++++-----
drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++----------
drivers/gpu/drm/radeon/r600_dpm.c | 4 ++--
drivers/gpu/drm/radeon/radeon.h | 4 ++++
drivers/gpu/drm/radeon/si.c | 22 ++++++++++++----------
drivers/gpu/drm/radeon/si_dpm.c | 20 +++++++++++++++-----
6 files changed, 60 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index b9302c918271..d587779a80b4 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -5676,19 +5676,29 @@ int ci_dpm_init(struct radeon_device *rdev)
u16 data_offset, size;
u8 frev, crev;
struct ci_power_info *pi;
+ enum pci_bus_speed speed_cap;
+ struct pci_dev *root = rdev->pdev->bus->self;
int ret;
- u32 mask;
pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
if (pi == NULL)
return -ENOMEM;
rdev->pm.dpm.priv = pi;
- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
- if (ret)
+ speed_cap = pcie_get_speed_cap(root);
+ if (speed_cap == PCI_SPEED_UNKNOWN) {
pi->sys_pcie_mask = 0;
- else
- pi->sys_pcie_mask = mask;
+ } else {
+ if (speed_cap == PCIE_SPEED_8_0GT)
+ pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
+ RADEON_PCIE_SPEED_50 |
+ RADEON_PCIE_SPEED_80;
+ else if (speed_cap == PCIE_SPEED_5_0GT)
+ pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
+ RADEON_PCIE_SPEED_50;
+ else
+ pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
+ }
pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 7c73bc7e2f85..ebce4601a305 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9499,9 +9499,10 @@ int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
static void cik_pcie_gen3_enable(struct radeon_device *rdev)
{
struct pci_dev *root = rdev->pdev->bus->self;
+ enum pci_bus_speed speed_cap;
int bridge_pos, gpu_pos;
- u32 speed_cntl, mask, current_data_rate;
- int ret, i;
+ u32 speed_cntl, current_data_rate;
+ int i;
u16 tmp16;
if (pci_is_root_bus(rdev->pdev->bus))
@@ -9516,23 +9517,24 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
if (!(rdev->flags & RADEON_IS_PCIE))
return;
- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
- if (ret != 0)
+ speed_cap = pcie_get_speed_cap(root);
+ if (speed_cap == PCI_SPEED_UNKNOWN)
return;
- if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
+ if ((speed_cap != PCIE_SPEED_8_0GT) &&
+ (speed_cap != PCIE_SPEED_5_0GT))
return;
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
LC_CURRENT_DATA_RATE_SHIFT;
- if (mask & DRM_PCIE_SPEED_80) {
+ if (speed_cap == PCIE_SPEED_8_0GT) {
if (current_data_rate == 2) {
DRM_INFO("PCIE gen 3 link speeds already enabled\n");
return;
}
DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
- } else if (mask & DRM_PCIE_SPEED_50) {
+ } else if (speed_cap == PCIE_SPEED_5_0GT) {
if (current_data_rate == 1) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return;
@@ -9548,7 +9550,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
if (!gpu_pos)
return;
- if (mask & DRM_PCIE_SPEED_80) {
+ if (speed_cap == PCIE_SPEED_8_0GT) {
/* re-try equalization if gen3 is not already enabled */
if (current_data_rate != 2) {
u16 bridge_cfg, gpu_cfg;
@@ -9636,9 +9638,9 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf;
- if (mask & DRM_PCIE_SPEED_80)
+ if (speed_cap == PCIE_SPEED_8_0GT)
tmp16 |= 3; /* gen3 */
- else if (mask & DRM_PCIE_SPEED_50)
+ else if (speed_cap == PCIE_SPEED_5_0GT)
tmp16 |= 2; /* gen2 */
else
tmp16 |= 1; /* gen1 */
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index 73d4c5348116..5e044c98fca2 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -1327,9 +1327,9 @@ enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
case RADEON_PCIE_GEN3:
return RADEON_PCIE_GEN3;
default:
- if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3))
+ if ((sys_mask & RADEON_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3))
return RADEON_PCIE_GEN3;
- else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2))
+ else if ((sys_mask & RADEON_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2))
return RADEON_PCIE_GEN2;
else
return RADEON_PCIE_GEN1;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 4a2eb409aacc..1a6f6edb3515 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1653,6 +1653,10 @@ struct radeon_pm {
struct radeon_dpm dpm;
};
+#define RADEON_PCIE_SPEED_25 1
+#define RADEON_PCIE_SPEED_50 2
+#define RADEON_PCIE_SPEED_80 4
+
int radeon_pm_get_type_index(struct radeon_device *rdev,
enum radeon_pm_state_type ps_type,
int instance);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 1907c950d76f..85c604d29235 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7082,9 +7082,10 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
static void si_pcie_gen3_enable(struct radeon_device *rdev)
{
struct pci_dev *root = rdev->pdev->bus->self;
+ enum pci_bus_speed speed_cap;
int bridge_pos, gpu_pos;
- u32 speed_cntl, mask, current_data_rate;
- int ret, i;
+ u32 speed_cntl, current_data_rate;
+ int i;
u16 tmp16;
if (pci_is_root_bus(rdev->pdev->bus))
@@ -7099,23 +7100,24 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
if (!(rdev->flags & RADEON_IS_PCIE))
return;
- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
- if (ret != 0)
+ speed_cap = pcie_get_speed_cap(root);
+ if (speed_cap == PCI_SPEED_UNKNOWN)
return;
- if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
+ if ((speed_cap != PCIE_SPEED_8_0GT) &&
+ (speed_cap != PCIE_SPEED_5_0GT))
return;
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
LC_CURRENT_DATA_RATE_SHIFT;
- if (mask & DRM_PCIE_SPEED_80) {
+ if (speed_cap == PCIE_SPEED_8_0GT) {
if (current_data_rate == 2) {
DRM_INFO("PCIE gen 3 link speeds already enabled\n");
return;
}
DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
- } else if (mask & DRM_PCIE_SPEED_50) {
+ } else if (speed_cap == PCIE_SPEED_5_0GT) {
if (current_data_rate == 1) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return;
@@ -7131,7 +7133,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
if (!gpu_pos)
return;
- if (mask & DRM_PCIE_SPEED_80) {
+ if (speed_cap == PCIE_SPEED_8_0GT) {
/* re-try equalization if gen3 is not already enabled */
if (current_data_rate != 2) {
u16 bridge_cfg, gpu_cfg;
@@ -7219,9 +7221,9 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf;
- if (mask & DRM_PCIE_SPEED_80)
+ if (speed_cap == PCIE_SPEED_8_0GT)
tmp16 |= 3; /* gen3 */
- else if (mask & DRM_PCIE_SPEED_50)
+ else if (speed_cap == PCIE_SPEED_5_0GT)
tmp16 |= 2; /* gen2 */
else
tmp16 |= 1; /* gen1 */
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index fea88078cf8e..8fb60b3af015 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -6899,8 +6899,9 @@ int si_dpm_init(struct radeon_device *rdev)
struct ni_power_info *ni_pi;
struct si_power_info *si_pi;
struct atom_clock_dividers dividers;
+ enum pci_bus_speed speed_cap;
+ struct pci_dev *root = rdev->pdev->bus->self;
int ret;
- u32 mask;
si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
if (si_pi == NULL)
@@ -6910,11 +6911,20 @@ int si_dpm_init(struct radeon_device *rdev)
eg_pi = &ni_pi->eg;
pi = &eg_pi->rv7xx;
- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
- if (ret)
+ speed_cap = pcie_get_speed_cap(root);
+ if (speed_cap == PCI_SPEED_UNKNOWN) {
si_pi->sys_pcie_mask = 0;
- else
- si_pi->sys_pcie_mask = mask;
+ } else {
+ if (speed_cap == PCIE_SPEED_8_0GT)
+ si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
+ RADEON_PCIE_SPEED_50 |
+ RADEON_PCIE_SPEED_80;
+ else if (speed_cap == PCIE_SPEED_5_0GT)
+ si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
+ RADEON_PCIE_SPEED_50;
+ else
+ si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
+ }
si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
--
2.13.6
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 4/5] drm/radeon: use pcie functions for link width
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
airlied-Re5JQEeQqe8AvxtiuMwx3w, linux-pci-u79uwXL29TY76Z2rM5mHXA,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA
Cc: Alex Deucher
This is the last user of drm_pcie_get_speed_cap_mask. Use the pci
version so we can drop drm_pcie_get_speed_cap_mask.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++++++++++++-----
drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++----------
drivers/gpu/drm/radeon/r600_dpm.c | 4 ++--
drivers/gpu/drm/radeon/radeon.h | 4 ++++
drivers/gpu/drm/radeon/si.c | 22 ++++++++++++----------
drivers/gpu/drm/radeon/si_dpm.c | 20 +++++++++++++++-----
6 files changed, 60 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index b9302c918271..d587779a80b4 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -5676,19 +5676,29 @@ int ci_dpm_init(struct radeon_device *rdev)
u16 data_offset, size;
u8 frev, crev;
struct ci_power_info *pi;
+ enum pci_bus_speed speed_cap;
+ struct pci_dev *root = rdev->pdev->bus->self;
int ret;
- u32 mask;
pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
if (pi == NULL)
return -ENOMEM;
rdev->pm.dpm.priv = pi;
- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
- if (ret)
+ speed_cap = pcie_get_speed_cap(root);
+ if (speed_cap == PCI_SPEED_UNKNOWN) {
pi->sys_pcie_mask = 0;
- else
- pi->sys_pcie_mask = mask;
+ } else {
+ if (speed_cap == PCIE_SPEED_8_0GT)
+ pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
+ RADEON_PCIE_SPEED_50 |
+ RADEON_PCIE_SPEED_80;
+ else if (speed_cap == PCIE_SPEED_5_0GT)
+ pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
+ RADEON_PCIE_SPEED_50;
+ else
+ pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
+ }
pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 7c73bc7e2f85..ebce4601a305 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9499,9 +9499,10 @@ int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
static void cik_pcie_gen3_enable(struct radeon_device *rdev)
{
struct pci_dev *root = rdev->pdev->bus->self;
+ enum pci_bus_speed speed_cap;
int bridge_pos, gpu_pos;
- u32 speed_cntl, mask, current_data_rate;
- int ret, i;
+ u32 speed_cntl, current_data_rate;
+ int i;
u16 tmp16;
if (pci_is_root_bus(rdev->pdev->bus))
@@ -9516,23 +9517,24 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
if (!(rdev->flags & RADEON_IS_PCIE))
return;
- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
- if (ret != 0)
+ speed_cap = pcie_get_speed_cap(root);
+ if (speed_cap == PCI_SPEED_UNKNOWN)
return;
- if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
+ if ((speed_cap != PCIE_SPEED_8_0GT) &&
+ (speed_cap != PCIE_SPEED_5_0GT))
return;
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
LC_CURRENT_DATA_RATE_SHIFT;
- if (mask & DRM_PCIE_SPEED_80) {
+ if (speed_cap == PCIE_SPEED_8_0GT) {
if (current_data_rate == 2) {
DRM_INFO("PCIE gen 3 link speeds already enabled\n");
return;
}
DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
- } else if (mask & DRM_PCIE_SPEED_50) {
+ } else if (speed_cap == PCIE_SPEED_5_0GT) {
if (current_data_rate == 1) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return;
@@ -9548,7 +9550,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
if (!gpu_pos)
return;
- if (mask & DRM_PCIE_SPEED_80) {
+ if (speed_cap == PCIE_SPEED_8_0GT) {
/* re-try equalization if gen3 is not already enabled */
if (current_data_rate != 2) {
u16 bridge_cfg, gpu_cfg;
@@ -9636,9 +9638,9 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf;
- if (mask & DRM_PCIE_SPEED_80)
+ if (speed_cap == PCIE_SPEED_8_0GT)
tmp16 |= 3; /* gen3 */
- else if (mask & DRM_PCIE_SPEED_50)
+ else if (speed_cap == PCIE_SPEED_5_0GT)
tmp16 |= 2; /* gen2 */
else
tmp16 |= 1; /* gen1 */
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index 73d4c5348116..5e044c98fca2 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -1327,9 +1327,9 @@ enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
case RADEON_PCIE_GEN3:
return RADEON_PCIE_GEN3;
default:
- if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3))
+ if ((sys_mask & RADEON_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3))
return RADEON_PCIE_GEN3;
- else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2))
+ else if ((sys_mask & RADEON_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2))
return RADEON_PCIE_GEN2;
else
return RADEON_PCIE_GEN1;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 4a2eb409aacc..1a6f6edb3515 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1653,6 +1653,10 @@ struct radeon_pm {
struct radeon_dpm dpm;
};
+#define RADEON_PCIE_SPEED_25 1
+#define RADEON_PCIE_SPEED_50 2
+#define RADEON_PCIE_SPEED_80 4
+
int radeon_pm_get_type_index(struct radeon_device *rdev,
enum radeon_pm_state_type ps_type,
int instance);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 1907c950d76f..85c604d29235 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7082,9 +7082,10 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
static void si_pcie_gen3_enable(struct radeon_device *rdev)
{
struct pci_dev *root = rdev->pdev->bus->self;
+ enum pci_bus_speed speed_cap;
int bridge_pos, gpu_pos;
- u32 speed_cntl, mask, current_data_rate;
- int ret, i;
+ u32 speed_cntl, current_data_rate;
+ int i;
u16 tmp16;
if (pci_is_root_bus(rdev->pdev->bus))
@@ -7099,23 +7100,24 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
if (!(rdev->flags & RADEON_IS_PCIE))
return;
- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
- if (ret != 0)
+ speed_cap = pcie_get_speed_cap(root);
+ if (speed_cap == PCI_SPEED_UNKNOWN)
return;
- if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
+ if ((speed_cap != PCIE_SPEED_8_0GT) &&
+ (speed_cap != PCIE_SPEED_5_0GT))
return;
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
LC_CURRENT_DATA_RATE_SHIFT;
- if (mask & DRM_PCIE_SPEED_80) {
+ if (speed_cap == PCIE_SPEED_8_0GT) {
if (current_data_rate == 2) {
DRM_INFO("PCIE gen 3 link speeds already enabled\n");
return;
}
DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
- } else if (mask & DRM_PCIE_SPEED_50) {
+ } else if (speed_cap == PCIE_SPEED_5_0GT) {
if (current_data_rate == 1) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return;
@@ -7131,7 +7133,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
if (!gpu_pos)
return;
- if (mask & DRM_PCIE_SPEED_80) {
+ if (speed_cap == PCIE_SPEED_8_0GT) {
/* re-try equalization if gen3 is not already enabled */
if (current_data_rate != 2) {
u16 bridge_cfg, gpu_cfg;
@@ -7219,9 +7221,9 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf;
- if (mask & DRM_PCIE_SPEED_80)
+ if (speed_cap == PCIE_SPEED_8_0GT)
tmp16 |= 3; /* gen3 */
- else if (mask & DRM_PCIE_SPEED_50)
+ else if (speed_cap == PCIE_SPEED_5_0GT)
tmp16 |= 2; /* gen2 */
else
tmp16 |= 1; /* gen1 */
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index fea88078cf8e..8fb60b3af015 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -6899,8 +6899,9 @@ int si_dpm_init(struct radeon_device *rdev)
struct ni_power_info *ni_pi;
struct si_power_info *si_pi;
struct atom_clock_dividers dividers;
+ enum pci_bus_speed speed_cap;
+ struct pci_dev *root = rdev->pdev->bus->self;
int ret;
- u32 mask;
si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
if (si_pi == NULL)
@@ -6910,11 +6911,20 @@ int si_dpm_init(struct radeon_device *rdev)
eg_pi = &ni_pi->eg;
pi = &eg_pi->rv7xx;
- ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
- if (ret)
+ speed_cap = pcie_get_speed_cap(root);
+ if (speed_cap == PCI_SPEED_UNKNOWN) {
si_pi->sys_pcie_mask = 0;
- else
- si_pi->sys_pcie_mask = mask;
+ } else {
+ if (speed_cap == PCIE_SPEED_8_0GT)
+ si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
+ RADEON_PCIE_SPEED_50 |
+ RADEON_PCIE_SPEED_80;
+ else if (speed_cap == PCIE_SPEED_5_0GT)
+ si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
+ RADEON_PCIE_SPEED_50;
+ else
+ si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
+ }
si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 5/5] drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx, dri-devel, airlied, linux-pci, bhelgaas; +Cc: Alex Deucher
These functions duplicated functionality which was ultimately added
to the pci core.
All users of these functions have been ported to using the newly
exposed pci functionality. These functions are no longer used,
so drop them.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/drm_pci.c | 58 -----------------------------------------------
include/drm/drm_pci.h | 7 ------
2 files changed, 65 deletions(-)
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index 4db9c515b74f..896e42a34895 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -326,64 +326,6 @@ int drm_legacy_pci_init(struct drm_driver *driver, struct pci_driver *pdriver)
}
EXPORT_SYMBOL(drm_legacy_pci_init);
-int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *mask)
-{
- struct pci_dev *root;
- u32 lnkcap, lnkcap2;
-
- *mask = 0;
- if (!dev->pdev)
- return -EINVAL;
-
- root = dev->pdev->bus->self;
-
- /* we've been informed via and serverworks don't make the cut */
- if (root->vendor == PCI_VENDOR_ID_VIA ||
- root->vendor == PCI_VENDOR_ID_SERVERWORKS)
- return -EINVAL;
-
- pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
- pcie_capability_read_dword(root, PCI_EXP_LNKCAP2, &lnkcap2);
-
- if (lnkcap2) { /* PCIe r3.0-compliant */
- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
- *mask |= DRM_PCIE_SPEED_25;
- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
- *mask |= DRM_PCIE_SPEED_50;
- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
- *mask |= DRM_PCIE_SPEED_80;
- } else { /* pre-r3.0 */
- if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
- *mask |= DRM_PCIE_SPEED_25;
- if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
- *mask |= (DRM_PCIE_SPEED_25 | DRM_PCIE_SPEED_50);
- }
-
- DRM_INFO("probing gen 2 caps for device %x:%x = %x/%x\n", root->vendor, root->device, lnkcap, lnkcap2);
- return 0;
-}
-EXPORT_SYMBOL(drm_pcie_get_speed_cap_mask);
-
-int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw)
-{
- struct pci_dev *root;
- u32 lnkcap;
-
- *mlw = 0;
- if (!dev->pdev)
- return -EINVAL;
-
- root = dev->pdev->bus->self;
-
- pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
-
- *mlw = (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
-
- DRM_INFO("probing mlw for device %x:%x = %x\n", root->vendor, root->device, lnkcap);
- return 0;
-}
-EXPORT_SYMBOL(drm_pcie_get_max_link_width);
-
#else
void drm_pci_agp_destroy(struct drm_device *dev) {}
diff --git a/include/drm/drm_pci.h b/include/drm/drm_pci.h
index 674599025d7d..8181e9e7cf1d 100644
--- a/include/drm/drm_pci.h
+++ b/include/drm/drm_pci.h
@@ -58,11 +58,4 @@ static inline int drm_get_pci_dev(struct pci_dev *pdev,
}
#endif
-#define DRM_PCIE_SPEED_25 1
-#define DRM_PCIE_SPEED_50 2
-#define DRM_PCIE_SPEED_80 4
-
-int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask);
-int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw);
-
#endif /* _DRM_PCI_H_ */
--
2.13.6
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 5/5] drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
@ 2018-06-25 21:06 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-25 21:06 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
airlied-Re5JQEeQqe8AvxtiuMwx3w, linux-pci-u79uwXL29TY76Z2rM5mHXA,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA
Cc: Alex Deucher
These functions duplicated functionality which was ultimately added
to the pci core.
All users of these functions have been ported to using the newly
exposed pci functionality. These functions are no longer used,
so drop them.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/drm_pci.c | 58 -----------------------------------------------
include/drm/drm_pci.h | 7 ------
2 files changed, 65 deletions(-)
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index 4db9c515b74f..896e42a34895 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -326,64 +326,6 @@ int drm_legacy_pci_init(struct drm_driver *driver, struct pci_driver *pdriver)
}
EXPORT_SYMBOL(drm_legacy_pci_init);
-int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *mask)
-{
- struct pci_dev *root;
- u32 lnkcap, lnkcap2;
-
- *mask = 0;
- if (!dev->pdev)
- return -EINVAL;
-
- root = dev->pdev->bus->self;
-
- /* we've been informed via and serverworks don't make the cut */
- if (root->vendor == PCI_VENDOR_ID_VIA ||
- root->vendor == PCI_VENDOR_ID_SERVERWORKS)
- return -EINVAL;
-
- pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
- pcie_capability_read_dword(root, PCI_EXP_LNKCAP2, &lnkcap2);
-
- if (lnkcap2) { /* PCIe r3.0-compliant */
- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
- *mask |= DRM_PCIE_SPEED_25;
- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
- *mask |= DRM_PCIE_SPEED_50;
- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
- *mask |= DRM_PCIE_SPEED_80;
- } else { /* pre-r3.0 */
- if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
- *mask |= DRM_PCIE_SPEED_25;
- if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
- *mask |= (DRM_PCIE_SPEED_25 | DRM_PCIE_SPEED_50);
- }
-
- DRM_INFO("probing gen 2 caps for device %x:%x = %x/%x\n", root->vendor, root->device, lnkcap, lnkcap2);
- return 0;
-}
-EXPORT_SYMBOL(drm_pcie_get_speed_cap_mask);
-
-int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw)
-{
- struct pci_dev *root;
- u32 lnkcap;
-
- *mlw = 0;
- if (!dev->pdev)
- return -EINVAL;
-
- root = dev->pdev->bus->self;
-
- pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
-
- *mlw = (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
-
- DRM_INFO("probing mlw for device %x:%x = %x\n", root->vendor, root->device, lnkcap);
- return 0;
-}
-EXPORT_SYMBOL(drm_pcie_get_max_link_width);
-
#else
void drm_pci_agp_destroy(struct drm_device *dev) {}
diff --git a/include/drm/drm_pci.h b/include/drm/drm_pci.h
index 674599025d7d..8181e9e7cf1d 100644
--- a/include/drm/drm_pci.h
+++ b/include/drm/drm_pci.h
@@ -58,11 +58,4 @@ static inline int drm_get_pci_dev(struct pci_dev *pdev,
}
#endif
-#define DRM_PCIE_SPEED_25 1
-#define DRM_PCIE_SPEED_50 2
-#define DRM_PCIE_SPEED_80 4
-
-int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask);
-int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw);
-
#endif /* _DRM_PCI_H_ */
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap
2018-06-25 21:06 ` Alex Deucher
@ 2018-06-28 13:42 ` Bjorn Helgaas
-1 siblings, 0 replies; 26+ messages in thread
From: Bjorn Helgaas @ 2018-06-28 13:42 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx, dri-devel, airlied, linux-pci, bhelgaas, Alex Deucher
On Mon, Jun 25, 2018 at 04:06:02PM -0500, Alex Deucher wrote:
> So drivers can use them. This can be used to replace
> duplicate code in the drm subsystem.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Thanks a lot for doing this!
If you haven't applied these yet, please
s/pci: export/PCI: Export/
in the subject.
> ---
> drivers/pci/pci.c | 2 ++
> include/linux/pci.h | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 97acba712e4e..22adaf35b136 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5222,6 +5222,7 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
>
> return PCI_SPEED_UNKNOWN;
> }
> +EXPORT_SYMBOL(pcie_get_speed_cap);
>
> /**
> * pcie_get_width_cap - query for the PCI device's link width capability
> @@ -5240,6 +5241,7 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
>
> return PCIE_LNK_WIDTH_UNKNOWN;
> }
> +EXPORT_SYMBOL(pcie_get_width_cap);
>
> /**
> * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 340029b2fb38..6e0c0803b241 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -261,6 +261,9 @@ enum pci_bus_speed {
> PCI_SPEED_UNKNOWN = 0xff,
> };
>
> +enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
> +enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
> +
> struct pci_cap_saved_data {
> u16 cap_nr;
> bool cap_extended;
> --
> 2.13.6
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap
@ 2018-06-28 13:42 ` Bjorn Helgaas
0 siblings, 0 replies; 26+ messages in thread
From: Bjorn Helgaas @ 2018-06-28 13:42 UTC (permalink / raw)
To: Alex Deucher; +Cc: linux-pci, dri-devel, Alex Deucher, amd-gfx, bhelgaas
On Mon, Jun 25, 2018 at 04:06:02PM -0500, Alex Deucher wrote:
> So drivers can use them. This can be used to replace
> duplicate code in the drm subsystem.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Thanks a lot for doing this!
If you haven't applied these yet, please
s/pci: export/PCI: Export/
in the subject.
> ---
> drivers/pci/pci.c | 2 ++
> include/linux/pci.h | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 97acba712e4e..22adaf35b136 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5222,6 +5222,7 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
>
> return PCI_SPEED_UNKNOWN;
> }
> +EXPORT_SYMBOL(pcie_get_speed_cap);
>
> /**
> * pcie_get_width_cap - query for the PCI device's link width capability
> @@ -5240,6 +5241,7 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
>
> return PCIE_LNK_WIDTH_UNKNOWN;
> }
> +EXPORT_SYMBOL(pcie_get_width_cap);
>
> /**
> * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 340029b2fb38..6e0c0803b241 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -261,6 +261,9 @@ enum pci_bus_speed {
> PCI_SPEED_UNKNOWN = 0xff,
> };
>
> +enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
> +enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
> +
> struct pci_cap_saved_data {
> u16 cap_nr;
> bool cap_extended;
> --
> 2.13.6
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap
@ 2018-06-28 14:19 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-28 14:19 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: amd-gfx list, Maling list - DRI developers, Dave Airlie,
Linux PCI, Bjorn Helgaas, Alex Deucher
On Thu, Jun 28, 2018 at 9:42 AM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Mon, Jun 25, 2018 at 04:06:02PM -0500, Alex Deucher wrote:
>> So drivers can use them. This can be used to replace
>> duplicate code in the drm subsystem.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>
> Thanks a lot for doing this!
>
> If you haven't applied these yet, please
>
> s/pci: export/PCI: Export/
>
> in the subject.
Will fix. Any objections to taking this via the drm tree?
Thanks,
Alex
>
>> ---
>> drivers/pci/pci.c | 2 ++
>> include/linux/pci.h | 3 +++
>> 2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
>> index 97acba712e4e..22adaf35b136 100644
>> --- a/drivers/pci/pci.c
>> +++ b/drivers/pci/pci.c
>> @@ -5222,6 +5222,7 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
>>
>> return PCI_SPEED_UNKNOWN;
>> }
>> +EXPORT_SYMBOL(pcie_get_speed_cap);
>>
>> /**
>> * pcie_get_width_cap - query for the PCI device's link width capability
>> @@ -5240,6 +5241,7 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
>>
>> return PCIE_LNK_WIDTH_UNKNOWN;
>> }
>> +EXPORT_SYMBOL(pcie_get_width_cap);
>>
>> /**
>> * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
>> diff --git a/include/linux/pci.h b/include/linux/pci.h
>> index 340029b2fb38..6e0c0803b241 100644
>> --- a/include/linux/pci.h
>> +++ b/include/linux/pci.h
>> @@ -261,6 +261,9 @@ enum pci_bus_speed {
>> PCI_SPEED_UNKNOWN = 0xff,
>> };
>>
>> +enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
>> +enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
>> +
>> struct pci_cap_saved_data {
>> u16 cap_nr;
>> bool cap_extended;
>> --
>> 2.13.6
>>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap
@ 2018-06-28 14:19 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-28 14:19 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Linux PCI, Maling list - DRI developers, Alex Deucher,
amd-gfx list, Bjorn Helgaas, Dave Airlie
On Thu, Jun 28, 2018 at 9:42 AM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Mon, Jun 25, 2018 at 04:06:02PM -0500, Alex Deucher wrote:
>> So drivers can use them. This can be used to replace
>> duplicate code in the drm subsystem.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>
> Thanks a lot for doing this!
>
> If you haven't applied these yet, please
>
> s/pci: export/PCI: Export/
>
> in the subject.
Will fix. Any objections to taking this via the drm tree?
Thanks,
Alex
>
>> ---
>> drivers/pci/pci.c | 2 ++
>> include/linux/pci.h | 3 +++
>> 2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
>> index 97acba712e4e..22adaf35b136 100644
>> --- a/drivers/pci/pci.c
>> +++ b/drivers/pci/pci.c
>> @@ -5222,6 +5222,7 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
>>
>> return PCI_SPEED_UNKNOWN;
>> }
>> +EXPORT_SYMBOL(pcie_get_speed_cap);
>>
>> /**
>> * pcie_get_width_cap - query for the PCI device's link width capability
>> @@ -5240,6 +5241,7 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
>>
>> return PCIE_LNK_WIDTH_UNKNOWN;
>> }
>> +EXPORT_SYMBOL(pcie_get_width_cap);
>>
>> /**
>> * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
>> diff --git a/include/linux/pci.h b/include/linux/pci.h
>> index 340029b2fb38..6e0c0803b241 100644
>> --- a/include/linux/pci.h
>> +++ b/include/linux/pci.h
>> @@ -261,6 +261,9 @@ enum pci_bus_speed {
>> PCI_SPEED_UNKNOWN = 0xff,
>> };
>>
>> +enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
>> +enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
>> +
>> struct pci_cap_saved_data {
>> u16 cap_nr;
>> bool cap_extended;
>> --
>> 2.13.6
>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap
@ 2018-06-28 16:53 ` Bjorn Helgaas
0 siblings, 0 replies; 26+ messages in thread
From: Bjorn Helgaas @ 2018-06-28 16:53 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx list, Maling list - DRI developers, Dave Airlie,
Linux PCI, Bjorn Helgaas, Alex Deucher
On Thu, Jun 28, 2018 at 10:19:41AM -0400, Alex Deucher wrote:
> On Thu, Jun 28, 2018 at 9:42 AM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Mon, Jun 25, 2018 at 04:06:02PM -0500, Alex Deucher wrote:
> >> So drivers can use them. This can be used to replace
> >> duplicate code in the drm subsystem.
> >>
> >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >
> > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> >
> > Thanks a lot for doing this!
> >
> > If you haven't applied these yet, please
> >
> > s/pci: export/PCI: Export/
> >
> > in the subject.
>
>
> Will fix. Any objections to taking this via the drm tree?
Nope, I acked it because I assumed you would merge it along with the rest
of the series via some non-PCI tree, so the drm tree would be great.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap
@ 2018-06-28 16:53 ` Bjorn Helgaas
0 siblings, 0 replies; 26+ messages in thread
From: Bjorn Helgaas @ 2018-06-28 16:53 UTC (permalink / raw)
To: Alex Deucher
Cc: Linux PCI, Maling list - DRI developers, Alex Deucher,
amd-gfx list, Bjorn Helgaas, Dave Airlie
On Thu, Jun 28, 2018 at 10:19:41AM -0400, Alex Deucher wrote:
> On Thu, Jun 28, 2018 at 9:42 AM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Mon, Jun 25, 2018 at 04:06:02PM -0500, Alex Deucher wrote:
> >> So drivers can use them. This can be used to replace
> >> duplicate code in the drm subsystem.
> >>
> >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >
> > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> >
> > Thanks a lot for doing this!
> >
> > If you haven't applied these yet, please
> >
> > s/pci: export/PCI: Export/
> >
> > in the subject.
>
>
> Will fix. Any objections to taking this via the drm tree?
Nope, I acked it because I assumed you would merge it along with the rest
of the series via some non-PCI tree, so the drm tree would be great.
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 0/5] drm: use core pcie functionality for pcie gen/width
2018-06-25 21:06 ` Alex Deucher
@ 2018-06-29 14:59 ` Alex Deucher
-1 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-29 14:59 UTC (permalink / raw)
To: amd-gfx list, Maling list - DRI developers, Dave Airlie,
Linux PCI, Bjorn Helgaas
Cc: Alex Deucher
Ping on the drm and amdgpu patches.
Alex
On Mon, Jun 25, 2018 at 5:06 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> This series exports some pcie helper functions for use by drivers and
> fixes up the amdgpu and radeon drivers to use this core functionality
> rather than the duplicated functionality in the drm. Finally we remove
> the drm helpers since the duplicate the pcie functionality of the core.
> This also adds proper pcie gen4 detection for amdgpu.
>
> Alex Deucher (5):
> pci: export pcie_get_speed_cap and pcie_get_width_cap
> drm/amdgpu: update amd_pcie.h to include gen4 speeds
> drm/amdgpu: use pcie functions for link width and speed
> drm/radeon: use pcie functions for link width
> drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
> drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
> drivers/gpu/drm/amd/include/amd_pcie.h | 2 +
> drivers/gpu/drm/drm_pci.c | 58 ---------------------
> drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++--
> drivers/gpu/drm/radeon/cik.c | 22 ++++----
> drivers/gpu/drm/radeon/r600_dpm.c | 4 +-
> drivers/gpu/drm/radeon/radeon.h | 4 ++
> drivers/gpu/drm/radeon/si.c | 22 ++++----
> drivers/gpu/drm/radeon/si_dpm.c | 20 +++++--
> drivers/pci/pci.c | 2 +
> include/drm/drm_pci.h | 7 ---
> include/linux/pci.h | 3 ++
> 15 files changed, 132 insertions(+), 128 deletions(-)
>
> --
> 2.13.6
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 0/5] drm: use core pcie functionality for pcie gen/width
@ 2018-06-29 14:59 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-06-29 14:59 UTC (permalink / raw)
To: amd-gfx list, Maling list - DRI developers, Dave Airlie,
Linux PCI, Bjorn Helgaas
Cc: Alex Deucher
Ping on the drm and amdgpu patches.
Alex
On Mon, Jun 25, 2018 at 5:06 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> This series exports some pcie helper functions for use by drivers and
> fixes up the amdgpu and radeon drivers to use this core functionality
> rather than the duplicated functionality in the drm. Finally we remove
> the drm helpers since the duplicate the pcie functionality of the core.
> This also adds proper pcie gen4 detection for amdgpu.
>
> Alex Deucher (5):
> pci: export pcie_get_speed_cap and pcie_get_width_cap
> drm/amdgpu: update amd_pcie.h to include gen4 speeds
> drm/amdgpu: use pcie functions for link width and speed
> drm/radeon: use pcie functions for link width
> drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
> drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
> drivers/gpu/drm/amd/include/amd_pcie.h | 2 +
> drivers/gpu/drm/drm_pci.c | 58 ---------------------
> drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++--
> drivers/gpu/drm/radeon/cik.c | 22 ++++----
> drivers/gpu/drm/radeon/r600_dpm.c | 4 +-
> drivers/gpu/drm/radeon/radeon.h | 4 ++
> drivers/gpu/drm/radeon/si.c | 22 ++++----
> drivers/gpu/drm/radeon/si_dpm.c | 20 +++++--
> drivers/pci/pci.c | 2 +
> include/drm/drm_pci.h | 7 ---
> include/linux/pci.h | 3 ++
> 15 files changed, 132 insertions(+), 128 deletions(-)
>
> --
> 2.13.6
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/5] drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
@ 2018-06-29 19:40 ` Dave Airlie
0 siblings, 0 replies; 26+ messages in thread
From: Dave Airlie @ 2018-06-29 19:40 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx mailing list, dri-devel, Linux PCI, Bjorn Helgaas, Alex Deucher
On 26 June 2018 at 07:06, Alex Deucher <alexdeucher@gmail.com> wrote:
> These functions duplicated functionality which was ultimately added
> to the pci core.
>
> All users of these functions have been ported to using the newly
> exposed pci functionality. These functions are no longer used,
> so drop them.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/5] drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
@ 2018-06-29 19:40 ` Dave Airlie
0 siblings, 0 replies; 26+ messages in thread
From: Dave Airlie @ 2018-06-29 19:40 UTC (permalink / raw)
To: Alex Deucher
Cc: Bjorn Helgaas, Linux PCI, Alex Deucher, dri-devel, amd-gfx mailing list
On 26 June 2018 at 07:06, Alex Deucher <alexdeucher@gmail.com> wrote:
> These functions duplicated functionality which was ultimately added
> to the pci core.
>
> All users of these functions have been ported to using the newly
> exposed pci functionality. These functions are no longer used,
> so drop them.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave.
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds
@ 2018-07-04 7:14 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-07-04 7:14 UTC (permalink / raw)
To: amd-gfx list, Maling list - DRI developers, Dave Airlie,
Linux PCI, Bjorn Helgaas
Cc: Alex Deucher
On Mon, Jun 25, 2018 at 5:06 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Internal header used by the driver to specify pcie gen
> speeds of the asic and chipset.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anyone care to review patches 2,3,4?
> ---
> drivers/gpu/drm/amd/include/amd_pcie.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
> index 5eb895fd98bf..9cb9ceb4d74d 100644
> --- a/drivers/gpu/drm/amd/include/amd_pcie.h
> +++ b/drivers/gpu/drm/amd/include/amd_pcie.h
> @@ -27,6 +27,7 @@
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
> +#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
>
> @@ -34,6 +35,7 @@
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
> +#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
>
> --
> 2.13.6
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds
@ 2018-07-04 7:14 ` Alex Deucher
0 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2018-07-04 7:14 UTC (permalink / raw)
To: amd-gfx list, Maling list - DRI developers, Dave Airlie,
Linux PCI, Bjorn Helgaas
Cc: Alex Deucher
On Mon, Jun 25, 2018 at 5:06 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Internal header used by the driver to specify pcie gen
> speeds of the asic and chipset.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anyone care to review patches 2,3,4?
> ---
> drivers/gpu/drm/amd/include/amd_pcie.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
> index 5eb895fd98bf..9cb9ceb4d74d 100644
> --- a/drivers/gpu/drm/amd/include/amd_pcie.h
> +++ b/drivers/gpu/drm/amd/include/amd_pcie.h
> @@ -27,6 +27,7 @@
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
> +#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
>
> @@ -34,6 +35,7 @@
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
> +#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
>
> --
> 2.13.6
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 0/5] drm: use core pcie functionality for pcie gen/width
@ 2018-07-04 8:38 ` Christian König
0 siblings, 0 replies; 26+ messages in thread
From: Christian König @ 2018-07-04 8:38 UTC (permalink / raw)
To: Alex Deucher, amd-gfx, dri-devel, airlied, linux-pci, bhelgaas
Cc: Alex Deucher
Whole series is Acked-by: Christian König <christian.koenig@amd.com>.
BTW: With patch #2 you created quite some noise in the news:
https://www.tomshardware.com/news/amd-vega-20-pcie-4.0,37389.html
Cheers,
Christian.
Am 25.06.2018 um 23:06 schrieb Alex Deucher:
> This series exports some pcie helper functions for use by drivers and
> fixes up the amdgpu and radeon drivers to use this core functionality
> rather than the duplicated functionality in the drm. Finally we remove
> the drm helpers since the duplicate the pcie functionality of the core.
> This also adds proper pcie gen4 detection for amdgpu.
>
> Alex Deucher (5):
> pci: export pcie_get_speed_cap and pcie_get_width_cap
> drm/amdgpu: update amd_pcie.h to include gen4 speeds
> drm/amdgpu: use pcie functions for link width and speed
> drm/radeon: use pcie functions for link width
> drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
> drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
> drivers/gpu/drm/amd/include/amd_pcie.h | 2 +
> drivers/gpu/drm/drm_pci.c | 58 ---------------------
> drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++--
> drivers/gpu/drm/radeon/cik.c | 22 ++++----
> drivers/gpu/drm/radeon/r600_dpm.c | 4 +-
> drivers/gpu/drm/radeon/radeon.h | 4 ++
> drivers/gpu/drm/radeon/si.c | 22 ++++----
> drivers/gpu/drm/radeon/si_dpm.c | 20 +++++--
> drivers/pci/pci.c | 2 +
> include/drm/drm_pci.h | 7 ---
> include/linux/pci.h | 3 ++
> 15 files changed, 132 insertions(+), 128 deletions(-)
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 0/5] drm: use core pcie functionality for pcie gen/width
@ 2018-07-04 8:38 ` Christian König
0 siblings, 0 replies; 26+ messages in thread
From: Christian König @ 2018-07-04 8:38 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
airlied-Re5JQEeQqe8AvxtiuMwx3w, linux-pci-u79uwXL29TY76Z2rM5mHXA,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA
Cc: Alex Deucher
Whole series is Acked-by: Christian König <christian.koenig@amd.com>.
BTW: With patch #2 you created quite some noise in the news:
https://www.tomshardware.com/news/amd-vega-20-pcie-4.0,37389.html
Cheers,
Christian.
Am 25.06.2018 um 23:06 schrieb Alex Deucher:
> This series exports some pcie helper functions for use by drivers and
> fixes up the amdgpu and radeon drivers to use this core functionality
> rather than the duplicated functionality in the drm. Finally we remove
> the drm helpers since the duplicate the pcie functionality of the core.
> This also adds proper pcie gen4 detection for amdgpu.
>
> Alex Deucher (5):
> pci: export pcie_get_speed_cap and pcie_get_width_cap
> drm/amdgpu: update amd_pcie.h to include gen4 speeds
> drm/amdgpu: use pcie functions for link width and speed
> drm/radeon: use pcie functions for link width
> drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
> drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
> drivers/gpu/drm/amd/include/amd_pcie.h | 2 +
> drivers/gpu/drm/drm_pci.c | 58 ---------------------
> drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++--
> drivers/gpu/drm/radeon/cik.c | 22 ++++----
> drivers/gpu/drm/radeon/r600_dpm.c | 4 +-
> drivers/gpu/drm/radeon/radeon.h | 4 ++
> drivers/gpu/drm/radeon/si.c | 22 ++++----
> drivers/gpu/drm/radeon/si_dpm.c | 20 +++++--
> drivers/pci/pci.c | 2 +
> include/drm/drm_pci.h | 7 ---
> include/linux/pci.h | 3 ++
> 15 files changed, 132 insertions(+), 128 deletions(-)
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2018-07-04 8:38 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-25 21:06 [PATCH 0/5] drm: use core pcie functionality for pcie gen/width Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-25 21:06 ` [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-28 13:42 ` Bjorn Helgaas
2018-06-28 13:42 ` Bjorn Helgaas
2018-06-28 14:19 ` Alex Deucher
2018-06-28 14:19 ` Alex Deucher
2018-06-28 16:53 ` Bjorn Helgaas
2018-06-28 16:53 ` Bjorn Helgaas
2018-06-25 21:06 ` [PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-07-04 7:14 ` Alex Deucher
2018-07-04 7:14 ` Alex Deucher
2018-06-25 21:06 ` [PATCH 3/5] drm/amdgpu: use pcie functions for link width and speed Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-25 21:06 ` [PATCH 4/5] drm/radeon: use pcie functions for link width Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-25 21:06 ` [PATCH 5/5] drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-29 19:40 ` Dave Airlie
2018-06-29 19:40 ` Dave Airlie
2018-06-29 14:59 ` [PATCH 0/5] drm: use core pcie functionality for pcie gen/width Alex Deucher
2018-06-29 14:59 ` Alex Deucher
2018-07-04 8:38 ` Christian König
2018-07-04 8:38 ` Christian König
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